feat(cpufeat): add support for FEAT_FGWTE3
Enable write traps for key EL3 system registers as per FEAT_FGWTE3,
ensuring their values remain unchanged after boot.
Excluded Registers:
MDCR_EL3 and MPAM3_EL3: Not trapped as they are part of the EL3 context.
SCTLR_EL3: Not trapped since it is overwritten during
powerdown sequence(Included when HW_ASSISTED_COHERENCY=1)
TPIDR_EL3: Excluded due to its use in crash reporting(It is included
when CRASH_REPORTING=0)
Reference:
https://developer.arm.com/documentation/ddi0601/2025-06/AArch64-Registers/FGWTE3-EL3--Fine-Grained-Write-Traps-EL3
Change-Id: Idcb32aaac7d65a0b0e5c90571af00e01a4e9edb1
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
diff --git a/common/feat_detect.c b/common/feat_detect.c
index fa817d9..d7adae6 100644
--- a/common/feat_detect.c
+++ b/common/feat_detect.c
@@ -297,6 +297,12 @@
ID_AA64ISAR2_EL1_MOPS_MASK);
}
+static unsigned int read_feat_fgwte3_id_field(void)
+{
+ return ISOLATE_FIELD(read_id_aa64mmfr4_el1(), ID_AA64MMFR4_EL1_FGWTE3_SHIFT,
+ ID_AA64MMFR4_EL1_FGWTE3_MASK);
+}
+
/***********************************************************************************
* TF-A supports many Arm architectural features starting from arch version
* (8.0 till 8.7+). These features are mostly enabled through build flags. This
@@ -437,6 +443,8 @@
check_feature(ENABLE_FEAT_GCS, read_feat_gcs_id_field(), "GCS", 1, 1);
check_feature(ENABLE_RME, read_feat_rme_id_field(), "RME", 1, 1);
check_feature(ENABLE_FEAT_PAUTH_LR, is_feat_pauth_lr_present(), "PAUTH_LR", 1, 1);
+ check_feature(ENABLE_FEAT_FGWTE3, read_feat_fgwte3_id_field(),
+ "FGWTE3", 1, 1);
if (tainted) {
panic();