tree 782fb94f2b6bbc49740979daa7c87fa71baf1343
parent 3d80b71fdef9aec613114bbe1df980341957ecba
author Soren Brinkmann <soren.brinkmann@xilinx.com> 1457324187 -0800
committer Soren Brinkmann <soren.brinkmann@xilinx.com> 1459964667 -0700

Add support for Xilinx Zynq UltraScale+ MPSOC

The Xilinx Zynq UltraScale+ MPSOC containes a quad A53 cluster. This
patch adds the platform port for that SoC.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>