Merge "fix(plat/marvell/a3720/uart): fix UART parent clock rate determination" into integration
diff --git a/Makefile b/Makefile
index 2376b9a..017fc65 100644
--- a/Makefile
+++ b/Makefile
@@ -521,6 +521,10 @@
ifeq ($(findstring optee_sp,$(ARM_SPMC_MANIFEST_DTS)),optee_sp)
DTC_CPPFLAGS += -DOPTEE_SP_FW_CONFIG
endif
+
+ ifeq ($(TS_SP_FW_CONFIG),1)
+ DTC_CPPFLAGS += -DTS_SP_FW_CONFIG
+ endif
else
# All other SPDs in spd directory
SPD_DIR := spd
diff --git a/bl31/bl31.mk b/bl31/bl31.mk
index 2088533..1fdf545 100644
--- a/bl31/bl31.mk
+++ b/bl31/bl31.mk
@@ -95,6 +95,10 @@
lib/cpus/aarch64/wa_cve_2017_5715_mmu.S
endif
+ifeq ($(SMC_PCI_SUPPORT),1)
+BL31_SOURCES += services/std_svc/pci_svc.c
+endif
+
BL31_LINKERFILE := bl31/bl31.ld.S
# Flag used to indicate if Crash reporting via console should be included
diff --git a/common/hw_crc32.c b/common/hw_crc32.c
new file mode 100644
index 0000000..a8731da
--- /dev/null
+++ b/common/hw_crc32.c
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdarg.h>
+#include <assert.h>
+
+#include <arm_acle.h>
+#include <common/debug.h>
+
+/* hw_crc32 - compute CRC using Arm intrinsic function
+ *
+ * This function is useful for the platforms with the CPU ARMv8.0
+ * (with CRC instructions supported), and onwards.
+ * Platforms with CPU ARMv8.0 should make sure to add a compile switch
+ * '-march=armv8-a+crc" for successful compilation of this file.
+ *
+ * @crc: previous accumulated CRC
+ * @buf: buffer base address
+ * @size: the size of the buffer
+ *
+ * Return calculated CRC value
+ */
+uint32_t hw_crc32(uint32_t crc, const unsigned char *buf, size_t size)
+{
+ assert(buf != NULL);
+
+ uint32_t calc_crc = ~crc;
+ const unsigned char *local_buf = buf;
+ size_t local_size = size;
+
+ /*
+ * calculate CRC over byte data
+ */
+ while (local_size != 0UL) {
+ calc_crc = __crc32b(calc_crc, *local_buf);
+ local_buf++;
+ local_size--;
+ }
+
+ return ~calc_crc;
+}
diff --git a/docs/about/maintainers.rst b/docs/about/maintainers.rst
index 30b2ab2..9cb5aa7 100644
--- a/docs/about/maintainers.rst
+++ b/docs/about/maintainers.rst
@@ -681,6 +681,20 @@
:|F|: Makefile
:|F|: make_helpers/
+Threat Model
+~~~~~~~~~~~~~
+:|M|: Zelalem Aweke <Zelalem.Aweke@arm.com>
+:|G|: `zelalem-aweke`_
+:|M|: Sandrine Bailleux <sandrine.bailleux@arm.com>
+:|G|: `sandrine-bailleux-arm`_
+:|M|: Joanna Farley <joanna.farley@arm.com>
+:|G|: `joannafarley-arm`_
+:|M|: Raghu Krishnamurthy <raghu.ncstate@icloud.com>
+:|G|: `raghuncstate`_
+:|M|: Varun Wadekar <vwadekar@nvidia.com>
+:|G|: `vwadekar`_
+:|F|: docs/threat_model/
+
.. _AlexeiFedorov: https://github.com/AlexeiFedorov
.. _Andre-ARM: https://github.com/Andre-ARM
.. _Anson-Huang: https://github.com/Anson-Huang
diff --git a/docs/change-log.rst b/docs/change-log.rst
index 4e7c96f..9c47568 100644
--- a/docs/change-log.rst
+++ b/docs/change-log.rst
@@ -107,7 +107,7 @@
- Cortex_A78C CPU
- Makalu ELP CPU
- Makalu CPU
- - Matterhorn CPU
+ - Matterhorn ELP CPU
- Neoverse-N2 CPU
- CPU Errata
diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst
index 2c3cd6b..99fc21d 100644
--- a/docs/getting_started/build-options.rst
+++ b/docs/getting_started/build-options.rst
@@ -579,6 +579,11 @@
``BL31_NOBITS_LIMIT``. When the option is ``0`` (the default), NOBITS
sections are placed in RAM immediately following the loaded firmware image.
+- ``SMC_PCI_SUPPORT``: This option allows platforms to handle PCI configuration
+ access requests via a standard SMCCC defined in `DEN0115`_. When combined with
+ UEFI+ACPI this can provide a certain amount of OS forward compatibility
+ with newer platforms that aren't ECAM compliant.
+
- ``SPD``: Choose a Secure Payload Dispatcher component to be built into TF-A.
This build option is only valid if ``ARCH=aarch64``. The value should be
the path to the directory containing the SPD source, relative to
@@ -849,3 +854,6 @@
--------------
*Copyright (c) 2019-2021, Arm Limited. All rights reserved.*
+
+.. _DEN0115: https://developer.arm.com/docs/den0115/latest
+
diff --git a/docs/getting_started/prerequisites.rst b/docs/getting_started/prerequisites.rst
index d116ce1..7eea22f 100644
--- a/docs/getting_started/prerequisites.rst
+++ b/docs/getting_started/prerequisites.rst
@@ -26,7 +26,7 @@
|TF-A| can be built with any of the following *cross-compiler* toolchains that
target the Armv7-A or Armv8-A architectures:
-- GCC >= 9.2-2019.12 (from the `Arm Developer website`_)
+- GCC >= 10.2-2020.11 (from the `Arm Developer website`_)
- Clang >= 4.0
- Arm Compiler >= 6.0
diff --git a/docs/plat/arm/arm-build-options.rst b/docs/plat/arm/arm-build-options.rst
index db8d945..d4fa98d 100644
--- a/docs/plat/arm/arm-build-options.rst
+++ b/docs/plat/arm/arm-build-options.rst
@@ -104,6 +104,9 @@
device tree. This flag is defined only when ``ARM_SPMC_MANIFEST_DTS`` manifest
file name contains pattern optee_sp.
+- ``TS_SP_FW_CONFIG``: DTC build flag to include Trusted Services (Crypto and
+ secure-storage) as SP in tb_fw_config device tree.
+
- ``ARM_GPT_SUPPORT``: Enable GPT parser to get the entry address and length of
the various partitions present in the GPT image. This support is available
only for the BL2 component, and it is disabled by default.
diff --git a/include/common/hw_crc32.h b/include/common/hw_crc32.h
new file mode 100644
index 0000000..0d14d57
--- /dev/null
+++ b/include/common/hw_crc32.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef HW_CRC32_H
+#define HW_CRC32_H
+
+#include <stddef.h>
+#include <stdint.h>
+
+/* compute CRC using Arm intrinsic function */
+uint32_t hw_crc32(uint32_t crc, const unsigned char *buf, size_t size);
+
+#endif /* HW_CRC32_H */
diff --git a/include/lib/cpus/aarch64/cortex_a510.h b/include/lib/cpus/aarch64/cortex_a510.h
new file mode 100644
index 0000000..6a4cfdf
--- /dev/null
+++ b/include/lib/cpus/aarch64/cortex_a510.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2021, ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CORTEX_A510_H
+#define CORTEX_A510_H
+
+#define CORTEX_A510_MIDR U(0x410FD460)
+
+/*******************************************************************************
+ * CPU Extended Control register specific definitions
+ ******************************************************************************/
+#define CORTEX_A510_CPUECTLR_EL1 S3_0_C15_C1_4
+
+/*******************************************************************************
+ * CPU Power Control register specific definitions
+ ******************************************************************************/
+#define CORTEX_A510_CPUPWRCTLR_EL1 S3_0_C15_C2_7
+#define CORTEX_A510_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
+
+#endif /* CORTEX_A510_H */
diff --git a/include/lib/cpus/aarch64/cortex_a710.h b/include/lib/cpus/aarch64/cortex_a710.h
new file mode 100644
index 0000000..44c540c
--- /dev/null
+++ b/include/lib/cpus/aarch64/cortex_a710.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CORTEX_A710_H
+#define CORTEX_A710_H
+
+#define CORTEX_A710_MIDR U(0x410FD470)
+
+/*******************************************************************************
+ * CPU Extended Control register specific definitions
+ ******************************************************************************/
+#define CORTEX_A710_CPUECTLR_EL1 S3_0_C15_C1_4
+
+/*******************************************************************************
+ * CPU Power Control register specific definitions
+ ******************************************************************************/
+#define CORTEX_A710_CPUPWRCTLR_EL1 S3_0_C15_C2_7
+#define CORTEX_A710_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
+
+#endif /* CORTEX_A710_H */
diff --git a/include/lib/cpus/aarch64/cortex_klein.h b/include/lib/cpus/aarch64/cortex_klein.h
deleted file mode 100644
index 729b3bf..0000000
--- a/include/lib/cpus/aarch64/cortex_klein.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * Copyright (c) 2020, ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef CORTEX_KLEIN_H
-#define CORTEX_KLEIN_H
-
-#define CORTEX_KLEIN_MIDR U(0x410FD460)
-
-/*******************************************************************************
- * CPU Extended Control register specific definitions
- ******************************************************************************/
-#define CORTEX_KLEIN_CPUECTLR_EL1 S3_0_C15_C1_4
-
-/*******************************************************************************
- * CPU Power Control register specific definitions
- ******************************************************************************/
-#define CORTEX_KLEIN_CPUPWRCTLR_EL1 S3_0_C15_C2_7
-#define CORTEX_KLEIN_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
-
-#endif /* CORTEX_KLEIN_H */
diff --git a/include/lib/cpus/aarch64/cortex_matterhorn.h b/include/lib/cpus/aarch64/cortex_matterhorn.h
deleted file mode 100644
index 0185533..0000000
--- a/include/lib/cpus/aarch64/cortex_matterhorn.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * Copyright (c) 2020, ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef CORTEX_MATTERHORN_H
-#define CORTEX_MATTERHORN_H
-
-#define CORTEX_MATTERHORN_MIDR U(0x410FD470)
-
-/*******************************************************************************
- * CPU Extended Control register specific definitions
- ******************************************************************************/
-#define CORTEX_MATTERHORN_CPUECTLR_EL1 S3_0_C15_C1_4
-
-/*******************************************************************************
- * CPU Power Control register specific definitions
- ******************************************************************************/
-#define CORTEX_MATTERHORN_CPUPWRCTLR_EL1 S3_0_C15_C2_7
-#define CORTEX_MATTERHORN_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
-
-#endif /* CORTEX_MATTERHORN_H */
diff --git a/include/lib/cpus/aarch64/cortex_matterhorn_elp_arm.h b/include/lib/cpus/aarch64/cortex_matterhorn_elp_arm.h
deleted file mode 100644
index 309578e..0000000
--- a/include/lib/cpus/aarch64/cortex_matterhorn_elp_arm.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * Copyright (c) 2021, ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef CORTEX_MATTERHORN_ELP_ARM_H
-#define CORTEX_MATTERHORN_ELP_ARM_H
-
-#define CORTEX_MATTERHORN_ELP_ARM_MIDR U(0x410FD480)
-
-/*******************************************************************************
- * CPU Extended Control register specific definitions
- ******************************************************************************/
-#define CORTEX_MATTERHORN_ELP_ARM_CPUECTLR_EL1 S3_0_C15_C1_4
-
-/*******************************************************************************
- * CPU Power Control register specific definitions
- ******************************************************************************/
-#define CORTEX_MATTERHORN_ELP_ARM_CPUPWRCTLR_EL1 S3_0_C15_C2_7
-#define CORTEX_MATTERHORN_ELP_ARM_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
-
-#endif /* CORTEX_MATTERHORN_ELP_ARM_H */
diff --git a/include/lib/cpus/aarch64/cortex_x2.h b/include/lib/cpus/aarch64/cortex_x2.h
new file mode 100644
index 0000000..9ce1223
--- /dev/null
+++ b/include/lib/cpus/aarch64/cortex_x2.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CORTEX_X2_H
+#define CORTEX_X2_H
+
+#define CORTEX_X2_MIDR U(0x410FD480)
+
+/*******************************************************************************
+ * CPU Extended Control register specific definitions
+ ******************************************************************************/
+#define CORTEX_X2_CPUECTLR_EL1 S3_0_C15_C1_4
+
+/*******************************************************************************
+ * CPU Power Control register specific definitions
+ ******************************************************************************/
+#define CORTEX_X2_CPUPWRCTLR_EL1 S3_0_C15_C2_7
+#define CORTEX_X2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
+
+#endif /* CORTEX_X2_H */
diff --git a/include/lib/libc/arm_acle.h b/include/lib/libc/arm_acle.h
index 953933f..eb08552 100644
--- a/include/lib/libc/arm_acle.h
+++ b/include/lib/libc/arm_acle.h
@@ -14,8 +14,10 @@
#define ARM_ACLE_H
#if !defined(__aarch64__) || defined(__clang__)
+# define __crc32b __builtin_arm_crc32b
# define __crc32w __builtin_arm_crc32w
#else
+# define __crc32b __builtin_aarch64_crc32b
# define __crc32w __builtin_aarch64_crc32w
#endif
diff --git a/include/plat/arm/css/common/css_def.h b/include/plat/arm/css/common/css_def.h
index d599352..dde174c 100644
--- a/include/plat/arm/css/common/css_def.h
+++ b/include/plat/arm/css/common/css_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -137,6 +137,8 @@
#define SSC_DBGCFG_SET 0x14
#define SSC_DBGCFG_CLR 0x18
+#define SPNIDEN_INT_CLR_SHIFT 4
+#define SPNIDEN_SEL_SET_SHIFT 5
#define SPIDEN_INT_CLR_SHIFT 6
#define SPIDEN_SEL_SET_SHIFT 7
diff --git a/include/services/pci_svc.h b/include/services/pci_svc.h
new file mode 100644
index 0000000..664a742
--- /dev/null
+++ b/include/services/pci_svc.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PCI_SVC_H
+#define PCI_SVC_H
+
+#include <lib/utils_def.h>
+
+/* SMCCC PCI platform functions */
+#define SMC_PCI_VERSION U(0x84000130)
+#define SMC_PCI_FEATURES U(0x84000131)
+#define SMC_PCI_READ U(0x84000132)
+#define SMC_PCI_WRITE U(0x84000133)
+#define SMC_PCI_SEG_INFO U(0x84000134)
+
+#define is_pci_fid(_fid) (((_fid) >= SMC_PCI_VERSION) && \
+ ((_fid) <= SMC_PCI_SEG_INFO))
+
+uint64_t pci_smc_handler(uint32_t smc_fid, u_register_t x1, u_register_t x2,
+ u_register_t x3, u_register_t x4, void *cookie,
+ void *handle, u_register_t flags);
+
+#define PCI_ADDR_FUN(dev) ((dev) & U(0x7))
+#define PCI_ADDR_DEV(dev) (((dev) >> U(3)) & U(0x001F))
+#define PCI_ADDR_BUS(dev) (((dev) >> U(8)) & U(0x00FF))
+#define PCI_ADDR_SEG(dev) (((dev) >> U(16)) & U(0xFFFF))
+#define PCI_OFFSET_MASK U(0xFFF)
+typedef union {
+ struct {
+ uint16_t minor;
+ uint16_t major;
+ } __packed;
+ uint32_t val;
+} pcie_version;
+
+/*
+ * platforms are responsible for providing implementations of these
+ * three functions in a manner which conforms to the Arm PCI Configuration
+ * Space Access Firmware Interface (DEN0115) and the PCIe specification's
+ * sections on PCI configuration access. See the rpi4_pci_svc.c example.
+ */
+uint32_t pci_read_config(uint32_t addr, uint32_t off, uint32_t sz, uint32_t *val);
+uint32_t pci_write_config(uint32_t addr, uint32_t off, uint32_t sz, uint32_t val);
+uint32_t pci_get_bus_for_seg(uint32_t seg, uint32_t *bus_range, uint32_t *nseg);
+
+/* Return codes for Arm PCI Config Space Access Firmware SMC calls */
+#define SMC_PCI_CALL_SUCCESS U(0)
+#define SMC_PCI_CALL_NOT_SUPPORTED -1
+#define SMC_PCI_CALL_INVAL_PARAM -2
+#define SMC_PCI_CALL_NOT_IMPL -3
+
+#define SMC_PCI_SZ_8BIT U(1)
+#define SMC_PCI_SZ_16BIT U(2)
+#define SMC_PCI_SZ_32BIT U(4)
+
+#endif /* PCI_SVC_H */
diff --git a/lib/cpus/aarch64/cortex_a510.S b/lib/cpus/aarch64/cortex_a510.S
new file mode 100644
index 0000000..3310322
--- /dev/null
+++ b/lib/cpus/aarch64/cortex_a510.S
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2021, ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <common/bl_common.h>
+#include <cortex_a510.h>
+#include <cpu_macros.S>
+#include <plat_macros.S>
+
+/* Hardware handled coherency */
+#if HW_ASSISTED_COHERENCY == 0
+#error "Cortex A510 must be compiled with HW_ASSISTED_COHERENCY enabled"
+#endif
+
+/* 64-bit only core */
+#if CTX_INCLUDE_AARCH32_REGS == 1
+#error "Cortex A510 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
+#endif
+
+ /* ----------------------------------------------------
+ * HW will do the cache maintenance while powering down
+ * ----------------------------------------------------
+ */
+func cortex_a510_core_pwr_dwn
+ /* ---------------------------------------------------
+ * Enable CPU power down bit in power control register
+ * ---------------------------------------------------
+ */
+ mrs x0, CORTEX_A510_CPUPWRCTLR_EL1
+ orr x0, x0, #CORTEX_A510_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
+ msr CORTEX_A510_CPUPWRCTLR_EL1, x0
+ isb
+ ret
+endfunc cortex_a510_core_pwr_dwn
+
+ /*
+ * Errata printing function for Cortex A510. Must follow AAPCS.
+ */
+#if REPORT_ERRATA
+func cortex_a510_errata_report
+ ret
+endfunc cortex_a510_errata_report
+#endif
+
+func cortex_a510_reset_func
+ /* Disable speculative loads */
+ msr SSBS, xzr
+ isb
+ ret
+endfunc cortex_a510_reset_func
+
+ /* ---------------------------------------------
+ * This function provides Cortex-A510 specific
+ * register information for crash reporting.
+ * It needs to return with x6 pointing to
+ * a list of register names in ascii and
+ * x8 - x15 having values of registers to be
+ * reported.
+ * ---------------------------------------------
+ */
+.section .rodata.cortex_a510_regs, "aS"
+cortex_a510_regs: /* The ascii list of register names to be reported */
+ .asciz "cpuectlr_el1", ""
+
+func cortex_a510_cpu_reg_dump
+ adr x6, cortex_a510_regs
+ mrs x8, CORTEX_A510_CPUECTLR_EL1
+ ret
+endfunc cortex_a510_cpu_reg_dump
+
+declare_cpu_ops cortex_a510, CORTEX_A510_MIDR, \
+ cortex_a510_reset_func, \
+ cortex_a510_core_pwr_dwn
diff --git a/lib/cpus/aarch64/cortex_a710.S b/lib/cpus/aarch64/cortex_a710.S
new file mode 100644
index 0000000..4f979f8
--- /dev/null
+++ b/lib/cpus/aarch64/cortex_a710.S
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <common/bl_common.h>
+#include <cortex_a710.h>
+#include <cpu_macros.S>
+#include <plat_macros.S>
+
+/* Hardware handled coherency */
+#if HW_ASSISTED_COHERENCY == 0
+#error "Cortex A710 must be compiled with HW_ASSISTED_COHERENCY enabled"
+#endif
+
+/* 64-bit only core */
+#if CTX_INCLUDE_AARCH32_REGS == 1
+#error "Cortex A710 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
+#endif
+
+ /* ----------------------------------------------------
+ * HW will do the cache maintenance while powering down
+ * ----------------------------------------------------
+ */
+func cortex_a710_core_pwr_dwn
+ /* ---------------------------------------------------
+ * Enable CPU power down bit in power control register
+ * ---------------------------------------------------
+ */
+ mrs x0, CORTEX_A710_CPUPWRCTLR_EL1
+ orr x0, x0, #CORTEX_A710_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
+ msr CORTEX_A710_CPUPWRCTLR_EL1, x0
+ isb
+ ret
+endfunc cortex_a710_core_pwr_dwn
+
+ /*
+ * Errata printing function for Cortex A710. Must follow AAPCS.
+ */
+#if REPORT_ERRATA
+func cortex_a710_errata_report
+ ret
+endfunc cortex_a710_errata_report
+#endif
+
+func cortex_a710_reset_func
+ /* Disable speculative loads */
+ msr SSBS, xzr
+ isb
+ ret
+endfunc cortex_a710_reset_func
+
+ /* ---------------------------------------------
+ * This function provides Cortex-A710 specific
+ * register information for crash reporting.
+ * It needs to return with x6 pointing to
+ * a list of register names in ascii and
+ * x8 - x15 having values of registers to be
+ * reported.
+ * ---------------------------------------------
+ */
+.section .rodata.cortex_a710_regs, "aS"
+cortex_a710_regs: /* The ascii list of register names to be reported */
+ .asciz "cpuectlr_el1", ""
+
+func cortex_a710_cpu_reg_dump
+ adr x6, cortex_a710_regs
+ mrs x8, CORTEX_A710_CPUECTLR_EL1
+ ret
+endfunc cortex_a710_cpu_reg_dump
+
+declare_cpu_ops cortex_a710, CORTEX_A710_MIDR, \
+ cortex_a710_reset_func, \
+ cortex_a710_core_pwr_dwn
diff --git a/lib/cpus/aarch64/cortex_klein.S b/lib/cpus/aarch64/cortex_klein.S
deleted file mode 100644
index d3a8ab4..0000000
--- a/lib/cpus/aarch64/cortex_klein.S
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * Copyright (c) 2020, ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch.h>
-#include <asm_macros.S>
-#include <common/bl_common.h>
-#include <cortex_klein.h>
-#include <cpu_macros.S>
-#include <plat_macros.S>
-
-/* Hardware handled coherency */
-#if HW_ASSISTED_COHERENCY == 0
-#error "Cortex Klein must be compiled with HW_ASSISTED_COHERENCY enabled"
-#endif
-
-/* 64-bit only core */
-#if CTX_INCLUDE_AARCH32_REGS == 1
-#error "Cortex Klein supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
-#endif
-
- /* ----------------------------------------------------
- * HW will do the cache maintenance while powering down
- * ----------------------------------------------------
- */
-func cortex_klein_core_pwr_dwn
- /* ---------------------------------------------------
- * Enable CPU power down bit in power control register
- * ---------------------------------------------------
- */
- mrs x0, CORTEX_KLEIN_CPUPWRCTLR_EL1
- orr x0, x0, #CORTEX_KLEIN_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
- msr CORTEX_KLEIN_CPUPWRCTLR_EL1, x0
- isb
- ret
-endfunc cortex_klein_core_pwr_dwn
-
- /*
- * Errata printing function for Cortex Klein. Must follow AAPCS.
- */
-#if REPORT_ERRATA
-func cortex_klein_errata_report
- ret
-endfunc cortex_klein_errata_report
-#endif
-
-func cortex_klein_reset_func
- /* Disable speculative loads */
- msr SSBS, xzr
- isb
- ret
-endfunc cortex_klein_reset_func
-
- /* ---------------------------------------------
- * This function provides Cortex-Klein specific
- * register information for crash reporting.
- * It needs to return with x6 pointing to
- * a list of register names in ascii and
- * x8 - x15 having values of registers to be
- * reported.
- * ---------------------------------------------
- */
-.section .rodata.cortex_klein_regs, "aS"
-cortex_klein_regs: /* The ascii list of register names to be reported */
- .asciz "cpuectlr_el1", ""
-
-func cortex_klein_cpu_reg_dump
- adr x6, cortex_klein_regs
- mrs x8, CORTEX_KLEIN_CPUECTLR_EL1
- ret
-endfunc cortex_klein_cpu_reg_dump
-
-declare_cpu_ops cortex_klein, CORTEX_KLEIN_MIDR, \
- cortex_klein_reset_func, \
- cortex_klein_core_pwr_dwn
diff --git a/lib/cpus/aarch64/cortex_matterhorn.S b/lib/cpus/aarch64/cortex_matterhorn.S
deleted file mode 100644
index 4156f3c..0000000
--- a/lib/cpus/aarch64/cortex_matterhorn.S
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * Copyright (c) 2020, ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch.h>
-#include <asm_macros.S>
-#include <common/bl_common.h>
-#include <cortex_matterhorn.h>
-#include <cpu_macros.S>
-#include <plat_macros.S>
-
-/* Hardware handled coherency */
-#if HW_ASSISTED_COHERENCY == 0
-#error "Cortex Matterhorn must be compiled with HW_ASSISTED_COHERENCY enabled"
-#endif
-
-/* 64-bit only core */
-#if CTX_INCLUDE_AARCH32_REGS == 1
-#error "Cortex Matterhorn supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
-#endif
-
- /* ----------------------------------------------------
- * HW will do the cache maintenance while powering down
- * ----------------------------------------------------
- */
-func cortex_matterhorn_core_pwr_dwn
- /* ---------------------------------------------------
- * Enable CPU power down bit in power control register
- * ---------------------------------------------------
- */
- mrs x0, CORTEX_MATTERHORN_CPUPWRCTLR_EL1
- orr x0, x0, #CORTEX_MATTERHORN_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
- msr CORTEX_MATTERHORN_CPUPWRCTLR_EL1, x0
- isb
- ret
-endfunc cortex_matterhorn_core_pwr_dwn
-
- /*
- * Errata printing function for Cortex Matterhorn. Must follow AAPCS.
- */
-#if REPORT_ERRATA
-func cortex_matterhorn_errata_report
- ret
-endfunc cortex_matterhorn_errata_report
-#endif
-
-func cortex_matterhorn_reset_func
- /* Disable speculative loads */
- msr SSBS, xzr
- isb
- ret
-endfunc cortex_matterhorn_reset_func
-
- /* ---------------------------------------------
- * This function provides Cortex-Matterhorn specific
- * register information for crash reporting.
- * It needs to return with x6 pointing to
- * a list of register names in ascii and
- * x8 - x15 having values of registers to be
- * reported.
- * ---------------------------------------------
- */
-.section .rodata.cortex_matterhorn_regs, "aS"
-cortex_matterhorn_regs: /* The ascii list of register names to be reported */
- .asciz "cpuectlr_el1", ""
-
-func cortex_matterhorn_cpu_reg_dump
- adr x6, cortex_matterhorn_regs
- mrs x8, CORTEX_MATTERHORN_CPUECTLR_EL1
- ret
-endfunc cortex_matterhorn_cpu_reg_dump
-
-declare_cpu_ops cortex_matterhorn, CORTEX_MATTERHORN_MIDR, \
- cortex_matterhorn_reset_func, \
- cortex_matterhorn_core_pwr_dwn
diff --git a/lib/cpus/aarch64/cortex_matterhorn_elp_arm.S b/lib/cpus/aarch64/cortex_matterhorn_elp_arm.S
deleted file mode 100644
index b0f81a2..0000000
--- a/lib/cpus/aarch64/cortex_matterhorn_elp_arm.S
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * Copyright (c) 2021, ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch.h>
-#include <asm_macros.S>
-#include <common/bl_common.h>
-#include <cortex_matterhorn_elp_arm.h>
-#include <cpu_macros.S>
-#include <plat_macros.S>
-
-/* Hardware handled coherency */
-#if HW_ASSISTED_COHERENCY == 0
-#error "Cortex Matterhorn ELP ARM must be compiled with HW_ASSISTED_COHERENCY enabled"
-#endif
-
-/* 64-bit only core */
-#if CTX_INCLUDE_AARCH32_REGS == 1
-#error "Cortex Matterhorn ELP ARM supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
-#endif
-
- /* ----------------------------------------------------
- * HW will do the cache maintenance while powering down
- * ----------------------------------------------------
- */
-func cortex_matterhorn_elp_arm_core_pwr_dwn
- /* ---------------------------------------------------
- * Enable CPU power down bit in power control register
- * ---------------------------------------------------
- */
- mrs x0, CORTEX_MATTERHORN_ELP_ARM_CPUPWRCTLR_EL1
- orr x0, x0, #CORTEX_MATTERHORN_ELP_ARM_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
- msr CORTEX_MATTERHORN_ELP_ARM_CPUPWRCTLR_EL1, x0
- isb
- ret
-endfunc cortex_matterhorn_elp_arm_core_pwr_dwn
-
- /*
- * Errata printing function for Cortex Matterhorn_elp_arm. Must follow AAPCS.
- */
-#if REPORT_ERRATA
-func cortex_matterhorn_elp_arm_errata_report
- ret
-endfunc cortex_matterhorn_elp_arm_errata_report
-#endif
-
-func cortex_matterhorn_elp_arm_reset_func
- /* Disable speculative loads */
- msr SSBS, xzr
- isb
- ret
-endfunc cortex_matterhorn_elp_arm_reset_func
-
- /* ---------------------------------------------
- * This function provides Cortex-Matterhorn_elp_arm specific
- * register information for crash reporting.
- * It needs to return with x6 pointing to
- * a list of register names in ascii and
- * x8 - x15 having values of registers to be
- * reported.
- * ---------------------------------------------
- */
-.section .rodata.cortex_matterhorn_elp_arm_regs, "aS"
-cortex_matterhorn_elp_arm_regs: /* The ascii list of register names to be reported */
- .asciz "cpuectlr_el1", ""
-
-func cortex_matterhorn_elp_arm_cpu_reg_dump
- adr x6, cortex_matterhorn_elp_arm_regs
- mrs x8, CORTEX_MATTERHORN_ELP_ARM_CPUECTLR_EL1
- ret
-endfunc cortex_matterhorn_elp_arm_cpu_reg_dump
-
-declare_cpu_ops cortex_matterhorn_elp_arm, CORTEX_MATTERHORN_ELP_ARM_MIDR, \
- cortex_matterhorn_elp_arm_reset_func, \
- cortex_matterhorn_elp_arm_core_pwr_dwn
diff --git a/lib/cpus/aarch64/cortex_x2.S b/lib/cpus/aarch64/cortex_x2.S
new file mode 100644
index 0000000..87a9bdf
--- /dev/null
+++ b/lib/cpus/aarch64/cortex_x2.S
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <common/bl_common.h>
+#include <cortex_x2.h>
+#include <cpu_macros.S>
+#include <plat_macros.S>
+
+/* Hardware handled coherency */
+#if HW_ASSISTED_COHERENCY == 0
+#error "Cortex X2 must be compiled with HW_ASSISTED_COHERENCY enabled"
+#endif
+
+/* 64-bit only core */
+#if CTX_INCLUDE_AARCH32_REGS == 1
+#error "Cortex X2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
+#endif
+
+ /* ----------------------------------------------------
+ * HW will do the cache maintenance while powering down
+ * ----------------------------------------------------
+ */
+func cortex_x2_core_pwr_dwn
+ /* ---------------------------------------------------
+ * Enable CPU power down bit in power control register
+ * ---------------------------------------------------
+ */
+ mrs x0, CORTEX_X2_CPUPWRCTLR_EL1
+ orr x0, x0, #CORTEX_X2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
+ msr CORTEX_X2_CPUPWRCTLR_EL1, x0
+ isb
+ ret
+endfunc cortex_x2_core_pwr_dwn
+
+ /*
+ * Errata printing function for Cortex X2. Must follow AAPCS.
+ */
+#if REPORT_ERRATA
+func cortex_x2_errata_report
+ ret
+endfunc cortex_x2_errata_report
+#endif
+
+func cortex_x2_reset_func
+ /* Disable speculative loads */
+ msr SSBS, xzr
+ isb
+ ret
+endfunc cortex_x2_reset_func
+
+ /* ---------------------------------------------
+ * This function provides Cortex X2 specific
+ * register information for crash reporting.
+ * It needs to return with x6 pointing to
+ * a list of register names in ascii and
+ * x8 - x15 having values of registers to be
+ * reported.
+ * ---------------------------------------------
+ */
+.section .rodata.cortex_x2_regs, "aS"
+cortex_x2_regs: /* The ascii list of register names to be reported */
+ .asciz "cpuectlr_el1", ""
+
+func cortex_x2_cpu_reg_dump
+ adr x6, cortex_x2_regs
+ mrs x8, CORTEX_X2_CPUECTLR_EL1
+ ret
+endfunc cortex_x2_cpu_reg_dump
+
+declare_cpu_ops cortex_x2, CORTEX_X2_MIDR, \
+ cortex_x2_reset_func, \
+ cortex_x2_core_pwr_dwn
diff --git a/lib/cpus/aarch64/cpu_helpers.S b/lib/cpus/aarch64/cpu_helpers.S
index 730b09b..bd8f85f 100644
--- a/lib/cpus/aarch64/cpu_helpers.S
+++ b/lib/cpus/aarch64/cpu_helpers.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2020, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2021, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -144,7 +144,7 @@
* If cpu_ops for the MIDR_EL1 cannot be found and
* SUPPORT_UNKNOWN_MPID is enabled, it will try to look for a
* default cpu_ops with an MIDR value of 0.
- * (Implementation number 0x0 should be reseverd for software use
+ * (Implementation number 0x0 should be reserved for software use
* and therefore no clashes should happen with that default value).
*
* Return :
diff --git a/lib/el3_runtime/aarch32/context_mgmt.c b/lib/el3_runtime/aarch32/context_mgmt.c
index 2443001..81d793b 100644
--- a/lib/el3_runtime/aarch32/context_mgmt.c
+++ b/lib/el3_runtime/aarch32/context_mgmt.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -49,7 +49,7 @@
*
* To prepare the register state for entry call cm_prepare_el3_exit() and
* el3_exit(). For Secure-EL1 cm_prepare_el3_exit() is equivalent to
- * cm_e1_sysreg_context_restore().
+ * cm_el1_sysregs_context_restore().
******************************************************************************/
void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep)
{
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index e0e4298..96023b6 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -60,7 +60,7 @@
*
* To prepare the register state for entry call cm_prepare_el3_exit() and
* el3_exit(). For Secure-EL1 cm_prepare_el3_exit() is equivalent to
- * cm_e1_sysreg_context_restore().
+ * cm_el1_sysregs_context_restore().
******************************************************************************/
void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep)
{
@@ -286,7 +286,7 @@
/*
* Store the initialised SCTLR_EL1 value in the cpu_context - SCTLR_EL2
- * and other EL2 registers are set up by cm_prepare_ns_entry() as they
+ * and other EL2 registers are set up by cm_prepare_el3_exit() as they
* are not part of the stored cpu_context.
*/
write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx);
diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk
index 8d0cd04..0433123 100644
--- a/make_helpers/defaults.mk
+++ b/make_helpers/defaults.mk
@@ -212,6 +212,9 @@
# True Random Number firmware Interface
TRNG_SUPPORT := 0
+# SMCCC PCI support
+SMC_PCI_SUPPORT := 0
+
# Whether code and read-only data should be put on separate memory pages. The
# platform Makefile is free to override this value.
SEPARATE_CODE_AND_RODATA := 0
diff --git a/plat/arm/board/arm_fpga/platform.mk b/plat/arm/board/arm_fpga/platform.mk
index 4e38751..f1fd777 100644
--- a/plat/arm/board/arm_fpga/platform.mk
+++ b/plat/arm/board/arm_fpga/platform.mk
@@ -67,8 +67,8 @@
lib/cpus/aarch64/cortex_a78_ae.S \
lib/cpus/aarch64/cortex_a65.S \
lib/cpus/aarch64/cortex_a65ae.S \
- lib/cpus/aarch64/cortex_klein.S \
- lib/cpus/aarch64/cortex_matterhorn.S \
+ lib/cpus/aarch64/cortex_a510.S \
+ lib/cpus/aarch64/cortex_a710.S \
lib/cpus/aarch64/cortex_makalu.S \
lib/cpus/aarch64/cortex_makalu_elp_arm.S \
lib/cpus/aarch64/cortex_a78c.S
diff --git a/plat/arm/board/fvp/fdts/fvp_spmc_optee_sp_manifest.dts b/plat/arm/board/fvp/fdts/fvp_spmc_optee_sp_manifest.dts
index 57d6792..088179b 100644
--- a/plat/arm/board/fvp/fdts/fvp_spmc_optee_sp_manifest.dts
+++ b/plat/arm/board/fvp/fdts/fvp_spmc_optee_sp_manifest.dts
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020, Arm Limited. All rights reserved.
+ * Copyright (c) 2020-2021, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -33,7 +33,6 @@
is_ffa_partition;
debug_name = "op-tee";
load_address = <0x6280000>;
- smc_whitelist = <0xbe000000>;
vcpu_count = <8>;
mem_size = <1048576>;
};
diff --git a/plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts b/plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts
index 14ad5f5..8ea6ba3 100644
--- a/plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts
+++ b/plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts
@@ -51,14 +51,14 @@
scp_bl2_uuid = "9766fd3d-89be-e849-ae5d-78a140608213";
bl31_uuid = "47d4086d-4cfe-9846-9b95-2950cbbd5a00";
bl32_uuid = "05d0e189-53dc-1347-8d2b-500a4b7a3e38";
- bl32_extra1_uuid = "0b70c28b-2a5a-7840-9f65-0a5682738288";
+ bl32_extra1_uuid = "0b70c29b-2a5a-7840-9f65-0a5682738288";
bl32_extra2_uuid = "8ea87bb1-cfa2-3f4d-85fd-e7bba50220d9";
bl33_uuid = "d6d0eea7-fcea-d54b-9782-9934f234b6e4";
hw_cfg_uuid = "08b8f1d9-c9cf-9349-a962-6fbc6b7265cc";
soc_fw_cfg_uuid = "9979814b-0376-fb46-8c8e-8d267f7859e0";
tos_fw_cfg_uuid = "26257c1a-dbc6-7f47-8d96-c4c4b0248021";
nt_fw_cfg_uuid = "28da9815-93e8-7e44-ac66-1aaf801550f9";
- t_key_cert_uuid = "827ee890-f860-e411-a1b4-77a721b4f94c";
+ t_key_cert_uuid = "827ee890-f860-e411-a1b4-777a21b4f94c";
scp_fw_key_uuid = "024221a1-f860-e411-8d9b-f33c0e15a014";
soc_fw_key_uuid = "8ab8becc-f960-e411-9ad0-eb4822d8dcf8";
tos_fw_key_cert_uuid = "9477d603-fb60-e411-85dd-b7105b8cee04";
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index b58a0d2..10258ad 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -131,8 +131,8 @@
lib/cpus/aarch64/neoverse_e1.S \
lib/cpus/aarch64/neoverse_v1.S \
lib/cpus/aarch64/cortex_a78_ae.S \
- lib/cpus/aarch64/cortex_klein.S \
- lib/cpus/aarch64/cortex_matterhorn.S \
+ lib/cpus/aarch64/cortex_a510.S \
+ lib/cpus/aarch64/cortex_a710.S \
lib/cpus/aarch64/cortex_makalu.S \
lib/cpus/aarch64/cortex_makalu_elp_arm.S \
lib/cpus/aarch64/cortex_a65.S \
diff --git a/plat/arm/board/juno/juno_security.c b/plat/arm/board/juno/juno_security.c
index 1e64c02..654a7f1 100644
--- a/plat/arm/board/juno/juno_security.c
+++ b/plat/arm/board/juno/juno_security.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -115,6 +115,14 @@
/* Drive SPIDEN LOW to disable invasive debug of secure state. */
mmio_write_32(SSC_REG_BASE + SSC_DBGCFG_CLR,
1U << SPIDEN_INT_CLR_SHIFT);
+
+ /* Set internal drive selection for SPNIDEN. */
+ mmio_write_32(SSC_REG_BASE + SSC_DBGCFG_SET,
+ 1U << SPNIDEN_SEL_SET_SHIFT);
+
+ /* Drive SPNIDEN LOW to disable non-invasive debug of secure state. */
+ mmio_write_32(SSC_REG_BASE + SSC_DBGCFG_CLR,
+ 1U << SPNIDEN_INT_CLR_SHIFT);
#endif
}
diff --git a/plat/arm/board/rdv1mc/platform.mk b/plat/arm/board/rdv1mc/platform.mk
index 06a2047..df0b09a 100644
--- a/plat/arm/board/rdv1mc/platform.mk
+++ b/plat/arm/board/rdv1mc/platform.mk
@@ -68,6 +68,7 @@
$(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config,${NT_FW_CONFIG}))
override CTX_INCLUDE_AARCH32_REGS := 0
+override ENABLE_AMU := 1
ifneq ($(CSS_SGI_PLATFORM_VARIANT),0)
$(error "CSS_SGI_PLATFORM_VARIANT for RD-V1-MC should always be 0, \
diff --git a/plat/arm/board/tc0/fdts/tc0_spmc_optee_sp_manifest.dts b/plat/arm/board/tc0/fdts/tc0_spmc_optee_sp_manifest.dts
index 221039c..0830d5c 100644
--- a/plat/arm/board/tc0/fdts/tc0_spmc_optee_sp_manifest.dts
+++ b/plat/arm/board/tc0/fdts/tc0_spmc_optee_sp_manifest.dts
@@ -27,8 +27,28 @@
debug_name = "op-tee";
load_address = <0xfd280000>;
vcpu_count = <8>;
- mem_size = <30928896>; /* 32MB TZC DRAM - SPMC region */
+#ifdef TS_SP_FW_CONFIG
+ mem_size = <26738688>; /* 25MB TZC DRAM */
+#else
+ mem_size = <30928896>; /* 29MB TZC DRAM */
+#endif
+ };
+#ifdef TS_SP_FW_CONFIG
+ vm2 {
+ is_ffa_partition;
+ debug_name = "secure-storage";
+ load_address = <0xfee00000>;
+ vcpu_count = <1>;
+ mem_size = <2097152>; /* 2MB TZC DRAM */
+ };
+ vm3 {
+ is_ffa_partition;
+ debug_name = "crypto";
+ load_address = <0xfec00000>;
+ vcpu_count = <1>;
+ mem_size = <2097152>; /* 2MB TZC DRAM */
};
+#endif
};
cpus {
diff --git a/plat/arm/board/tc0/fdts/tc0_tb_fw_config.dts b/plat/arm/board/tc0/fdts/tc0_tb_fw_config.dts
index de5f95d..38fd0e0 100644
--- a/plat/arm/board/tc0/fdts/tc0_tb_fw_config.dts
+++ b/plat/arm/board/tc0/fdts/tc0_tb_fw_config.dts
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020, Arm Limited. All rights reserved.
+ * Copyright (c) 2020-2021, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -27,6 +27,16 @@
secure-partitions {
compatible = "arm,sp";
+#ifdef TS_SP_FW_CONFIG
+ secure-storage {
+ uuid = "dc1eef48-b17a-4ccf-ac8b-dfcff7711b14";
+ load-address = <0xfee00000>;
+ };
+ crypto {
+ uuid = "d9df52d5-16a2-4bb2-9aa4-d26d3b84e8c0";
+ load-address = <0xfec00000>;
+ };
+#endif
#if OPTEE_SP_FW_CONFIG
op-tee {
uuid = <0x486178e0 0xe7f811e3 0xbc5e0002 0xa5d5c51b>;
diff --git a/plat/arm/board/tc0/platform.mk b/plat/arm/board/tc0/platform.mk
index 20ea6e3..814ccd3 100644
--- a/plat/arm/board/tc0/platform.mk
+++ b/plat/arm/board/tc0/platform.mk
@@ -43,9 +43,9 @@
PLAT_INCLUDES += -I${TC0_BASE}/include/
-TC0_CPU_SOURCES := lib/cpus/aarch64/cortex_klein.S \
- lib/cpus/aarch64/cortex_matterhorn.S \
- lib/cpus/aarch64/cortex_matterhorn_elp_arm.S
+TC0_CPU_SOURCES := lib/cpus/aarch64/cortex_a510.S \
+ lib/cpus/aarch64/cortex_a710.S \
+ lib/cpus/aarch64/cortex_x2.S
INTERCONNECT_SOURCES := ${TC0_BASE}/tc0_interconnect.c
diff --git a/plat/arm/common/arm_common.c b/plat/arm/common/arm_common.c
index 7d9fd6c..946b732 100644
--- a/plat/arm/common/arm_common.c
+++ b/plat/arm/common/arm_common.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -151,10 +151,10 @@
*/
mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTCTLBASE_CNTFRQ, freq_val);
-#if defined(PLAT_juno) || defined(PLAT_n1sdp)
+#if defined(PLAT_juno) || defined(PLAT_n1sdp) || defined(PLAT_morello)
/*
* Initialize CNTFRQ register in Non-secure CNTBase frame.
- * This is only required for Juno and N1SDP, because they do not
+ * This is required for Juno, N1SDP and Morello because they do not
* follow ARM ARM in that the value updated in CNTFRQ is not
* reflected in CNTBASEN_CNTFRQ. Hence update the value manually.
*/
diff --git a/plat/arm/common/arm_common.mk b/plat/arm/common/arm_common.mk
index fff1294..5faf9f9 100644
--- a/plat/arm/common/arm_common.mk
+++ b/plat/arm/common/arm_common.mk
@@ -178,6 +178,13 @@
drivers/partition/partition.c
endif
+# Enable CRC instructions via extension for ARMv8-A CPUs.
+# For ARMv8.1-A, and onwards CRC instructions are default enabled.
+# Enable HW computed CRC support unconditionally in BL2 component.
+ifeq (${ARM_ARCH_MINOR},0)
+ BL2_CPPFLAGS += -march=armv8-a+crc
+endif
+
ifeq (${ARCH}, aarch64)
PLAT_INCLUDES += -Iinclude/plat/arm/common/aarch64
endif
@@ -223,6 +230,7 @@
drivers/io/io_storage.c \
plat/arm/common/arm_bl2_setup.c \
plat/arm/common/arm_err.c \
+ common/hw_crc32.c \
${ARM_IO_SOURCES}
# Firmware Configuration Framework sources
diff --git a/plat/arm/css/sgi/sgi-common.mk b/plat/arm/css/sgi/sgi-common.mk
index 1e2054f..8baf4ee 100644
--- a/plat/arm/css/sgi/sgi-common.mk
+++ b/plat/arm/css/sgi/sgi-common.mk
@@ -65,6 +65,8 @@
override NEED_BL2U := no
override ARM_BL31_IN_DRAM := 1
override ARM_PLAT_MT := 1
+override PSCI_EXTENDED_STATE_ID := 1
+override ARM_RECOM_STATE_ID_ENC := 1
# System coherency is managed in hardware
HW_ASSISTED_COHERENCY := 1
diff --git a/plat/imx/common/imx_sip_handler.c b/plat/imx/common/imx_sip_handler.c
index f9f5577..d4b3425 100644
--- a/plat/imx/common/imx_sip_handler.c
+++ b/plat/imx/common/imx_sip_handler.c
@@ -14,6 +14,7 @@
#include <common/runtime_svc.h>
#include <imx_sip_svc.h>
#include <lib/el3_runtime/context_mgmt.h>
+#include <lib/mmio.h>
#include <sci/sci.h>
#if defined(PLAT_imx8qm) || defined(PLAT_imx8qx)
@@ -145,6 +146,37 @@
#endif /* defined(PLAT_imx8qm) || defined(PLAT_imx8qx) */
+#if defined(PLAT_imx8mm) || defined(PLAT_imx8mq)
+int imx_src_handler(uint32_t smc_fid,
+ u_register_t x1,
+ u_register_t x2,
+ u_register_t x3,
+ void *handle)
+{
+ uint32_t val;
+
+ switch (x1) {
+ case IMX_SIP_SRC_SET_SECONDARY_BOOT:
+ if (x2 != 0U) {
+ mmio_setbits_32(IMX_SRC_BASE + SRC_GPR10_OFFSET,
+ SRC_GPR10_PERSIST_SECONDARY_BOOT);
+ } else {
+ mmio_clrbits_32(IMX_SRC_BASE + SRC_GPR10_OFFSET,
+ SRC_GPR10_PERSIST_SECONDARY_BOOT);
+ }
+ break;
+ case IMX_SIP_SRC_IS_SECONDARY_BOOT:
+ val = mmio_read_32(IMX_SRC_BASE + SRC_GPR10_OFFSET);
+ return !!(val & SRC_GPR10_PERSIST_SECONDARY_BOOT);
+ default:
+ return SMC_UNK;
+
+ };
+
+ return 0;
+}
+#endif /* defined(PLAT_imx8mm) || defined(PLAT_imx8mq) */
+
static uint64_t imx_get_commit_hash(u_register_t x2,
u_register_t x3,
u_register_t x4)
diff --git a/plat/imx/common/imx_sip_svc.c b/plat/imx/common/imx_sip_svc.c
index 20e1479..fd54820 100644
--- a/plat/imx/common/imx_sip_svc.c
+++ b/plat/imx/common/imx_sip_svc.c
@@ -48,6 +48,11 @@
case IMX_SIP_MISC_SET_TEMP:
SMC_RET1(handle, imx_misc_set_temp_handler(smc_fid, x1, x2, x3, x4));
#endif
+#if defined(PLAT_imx8mm) || defined(PLAT_imx8mq)
+ case IMX_SIP_SRC:
+ SMC_RET1(handle, imx_src_handler(smc_fid, x1, x2, x3, handle));
+ break;
+#endif
case IMX_SIP_BUILDINFO:
SMC_RET1(handle, imx_buildinfo_handler(smc_fid, x1, x2, x3, x4));
default:
diff --git a/plat/imx/common/include/imx_sip_svc.h b/plat/imx/common/include/imx_sip_svc.h
index 0a2d750..6c7a760 100644
--- a/plat/imx/common/include/imx_sip_svc.h
+++ b/plat/imx/common/include/imx_sip_svc.h
@@ -17,6 +17,10 @@
#define IMX_SIP_BUILDINFO 0xC2000003
#define IMX_SIP_BUILDINFO_GET_COMMITHASH 0x00
+#define IMX_SIP_SRC 0xC2000005
+#define IMX_SIP_SRC_SET_SECONDARY_BOOT 0x10
+#define IMX_SIP_SRC_IS_SECONDARY_BOOT 0x11
+
#define IMX_SIP_GET_SOC_INFO 0xC2000006
#define IMX_SIP_WAKEUP_SRC 0xC2000009
@@ -38,6 +42,11 @@
u_register_t x2, u_register_t x3);
#endif
+#if defined(PLAT_imx8mm) || defined(PLAT_imx8mq)
+int imx_src_handler(uint32_t smc_fid, u_register_t x1,
+ u_register_t x2, u_register_t x3, void *handle);
+#endif
+
#if (defined(PLAT_imx8qm) || defined(PLAT_imx8qx))
int imx_cpufreq_handler(uint32_t smc_fid, u_register_t x1,
u_register_t x2, u_register_t x3);
diff --git a/plat/imx/imx8m/imx8mm/include/platform_def.h b/plat/imx/imx8m/imx8mm/include/platform_def.h
index ec915ad..f8efa56 100644
--- a/plat/imx/imx8m/imx8mm/include/platform_def.h
+++ b/plat/imx/imx8m/imx8mm/include/platform_def.h
@@ -124,6 +124,8 @@
#define SRC_OTG1PHY_SCR U(0x20)
#define SRC_OTG2PHY_SCR U(0x24)
#define SRC_GPR1_OFFSET U(0x74)
+#define SRC_GPR10_OFFSET U(0x98)
+#define SRC_GPR10_PERSIST_SECONDARY_BOOT BIT(30)
#define SNVS_LPCR U(0x38)
#define SNVS_LPCR_SRTC_ENV BIT(0)
diff --git a/plat/imx/imx8m/imx8mq/include/platform_def.h b/plat/imx/imx8m/imx8mq/include/platform_def.h
index 9db3a13..6d6a865 100644
--- a/plat/imx/imx8m/imx8mq/include/platform_def.h
+++ b/plat/imx/imx8m/imx8mq/include/platform_def.h
@@ -103,6 +103,8 @@
#define SRC_OTG1PHY_SCR U(0x20)
#define SRC_OTG2PHY_SCR U(0x24)
#define SRC_GPR1_OFFSET U(0x74)
+#define SRC_GPR10_OFFSET U(0x98)
+#define SRC_GPR10_PERSIST_SECONDARY_BOOT BIT(30)
#define SNVS_LPCR U(0x38)
#define SNVS_LPCR_SRTC_ENV BIT(0)
diff --git a/plat/mediatek/common/drivers/pmic_wrap/pmic_wrap_init_v2.c b/plat/mediatek/common/drivers/pmic_wrap/pmic_wrap_init_v2.c
index fca6913..d9a79c4 100644
--- a/plat/mediatek/common/drivers/pmic_wrap/pmic_wrap_init_v2.c
+++ b/plat/mediatek/common/drivers/pmic_wrap/pmic_wrap_init_v2.c
@@ -26,12 +26,30 @@
while (retry != 0) {
udelay(WAIT_IDLE_POLLING_DELAY_US);
reg_rdata = mmio_read_32((uintptr_t)wacs_register);
- if (GET_WACS_FSM(reg_rdata) == SWINF_FSM_IDLE) {
+ /* if last read command timeout,clear vldclr bit
+ * read command state machine:FSM_REQ-->wfdle-->WFVLDCLR;
+ * write:FSM_REQ-->idle
+ */
+ switch (GET_WACS_FSM(reg_rdata)) {
+ case SWINF_FSM_WFVLDCLR:
+ mmio_write_32((uintptr_t)&mtk_pwrap->wacs2_vldclr, 0x1);
+ INFO("WACS_FSM = SWINF_FSM_WFVLDCLR\n");
+ break;
+ case SWINF_FSM_WFDLE:
+ INFO("WACS_FSM = SWINF_FSM_WFDLE\n");
+ break;
+ case SWINF_FSM_REQ:
+ INFO("WACS_FSM = SWINF_FSM_REQ\n");
+ break;
+ case SWINF_FSM_IDLE:
+ goto done;
+ default:
break;
}
retry--;
};
+done:
if (retry == 0) {
/* timeout */
return E_PWR_WAIT_IDLE_TIMEOUT;
diff --git a/plat/mediatek/common/mtk_sip_svc.h b/plat/mediatek/common/mtk_sip_svc.h
index 45ce281..74b17b6 100644
--- a/plat/mediatek/common/mtk_sip_svc.h
+++ b/plat/mediatek/common/mtk_sip_svc.h
@@ -35,6 +35,10 @@
#define MTK_SIP_VCORE_CONTROL_ARCH32 0x82000506
#define MTK_SIP_VCORE_CONTROL_ARCH64 0xC2000506
+/* APUSYS SMC call */
+#define MTK_SIP_APUSYS_CONTROL_AARCH32 0x8200051E
+#define MTK_SIP_APUSYS_CONTROL_AARCH64 0xC200051E
+
/* Mediatek SiP Calls error code */
enum {
MTK_SIP_E_SUCCESS = 0,
diff --git a/plat/mediatek/mt8192/aarch64/platform_common.c b/plat/mediatek/mt8192/aarch64/platform_common.c
index ffa10fe..fc98871 100644
--- a/plat/mediatek/mt8192/aarch64/platform_common.c
+++ b/plat/mediatek/mt8192/aarch64/platform_common.c
@@ -21,6 +21,14 @@
MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(MTK_MCDI_SRAM_BASE, MTK_MCDI_SRAM_MAP_SIZE,
MT_DEVICE | MT_RW | MT_SECURE),
+ MAP_REGION_FLAT(APUSYS_SCTRL_REVISER_BASE, APUSYS_SCTRL_REVISER_SIZE,
+ MT_DEVICE | MT_RW | MT_SECURE),
+ MAP_REGION_FLAT(APUSYS_APU_S_S_4_BASE, APUSYS_APU_S_S_4_SIZE,
+ MT_DEVICE | MT_RW | MT_SECURE),
+ MAP_REGION_FLAT(APUSYS_APC_AO_WRAPPER_BASE, APUSYS_APC_AO_WRAPPER_SIZE,
+ MT_DEVICE | MT_RW | MT_SECURE),
+ MAP_REGION_FLAT(APUSYS_NOC_DAPC_AO_BASE, APUSYS_NOC_DAPC_AO_SIZE,
+ MT_DEVICE | MT_RW | MT_SECURE),
{ 0 }
};
diff --git a/plat/mediatek/mt8192/drivers/apusys/mtk_apusys.c b/plat/mediatek/mt8192/drivers/apusys/mtk_apusys.c
new file mode 100644
index 0000000..782aa5f
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/apusys/mtk_apusys.c
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <drivers/console.h>
+#include <lib/mmio.h>
+#include <mtk_apusys.h>
+#include <plat/common/platform.h>
+
+uint64_t apusys_kernel_ctrl(uint64_t x1, uint64_t x2, uint64_t x3, uint64_t x4,
+ uint32_t *ret1)
+{
+ uint32_t request_ops;
+
+ request_ops = (uint32_t)x1;
+ INFO("[APUSYS] ops=0x%x\n", request_ops);
+
+ switch (request_ops) {
+ case MTK_SIP_APU_START_MCU:
+ /* setup addr[33:32] in reviser */
+ mmio_write_32(REVISER_SECUREFW_CTXT, 0U);
+ mmio_write_32(REVISER_USDRFW_CTXT, 0U);
+
+ /* setup secure sideband */
+ mmio_write_32(AO_SEC_FW,
+ (SEC_FW_NON_SECURE << SEC_FW_SHIFT_NS) |
+ (0U << SEC_FW_DOMAIN_SHIFT));
+
+ /* setup boot address */
+ mmio_write_32(AO_MD32_BOOT_CTRL, 0U);
+
+ /* setup pre-define region */
+ mmio_write_32(AO_MD32_PRE_DEFINE,
+ (PRE_DEFINE_CACHE_TCM << PRE_DEFINE_SHIFT_0G) |
+ (PRE_DEFINE_CACHE << PRE_DEFINE_SHIFT_1G) |
+ (PRE_DEFINE_CACHE << PRE_DEFINE_SHIFT_2G) |
+ (PRE_DEFINE_CACHE << PRE_DEFINE_SHIFT_3G));
+
+ /* release runstall */
+ mmio_write_32(AO_MD32_SYS_CTRL, SYS_CTRL_RUN);
+
+ INFO("[APUSYS] reviser_ctxt=%x,%x\n",
+ mmio_read_32(REVISER_SECUREFW_CTXT),
+ mmio_read_32(REVISER_USDRFW_CTXT));
+ INFO("[APUSYS]fw=0x%08x,boot=0x%08x,def=0x%08x,sys=0x%08x\n",
+ mmio_read_32(AO_SEC_FW),
+ mmio_read_32(AO_MD32_BOOT_CTRL),
+ mmio_read_32(AO_MD32_PRE_DEFINE),
+ mmio_read_32(AO_MD32_SYS_CTRL));
+ break;
+ case MTK_SIP_APU_STOP_MCU:
+ /* hold runstall */
+ mmio_write_32(AO_MD32_SYS_CTRL, SYS_CTRL_STALL);
+
+ INFO("[APUSYS] md32_boot_ctrl=0x%08x,runstall=0x%08x\n",
+ mmio_read_32(AO_MD32_BOOT_CTRL),
+ mmio_read_32(AO_MD32_SYS_CTRL));
+ break;
+ default:
+ ERROR("%s, unknown request_ops = %x\n", __func__, request_ops);
+ break;
+ }
+
+ return 0UL;
+}
diff --git a/plat/mediatek/mt8192/drivers/apusys/mtk_apusys.h b/plat/mediatek/mt8192/drivers/apusys/mtk_apusys.h
new file mode 100644
index 0000000..95fac4a
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/apusys/mtk_apusys.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __MTK_APUSYS_H__
+#define __MTK_APUSYS_H__
+
+#include <stdint.h>
+
+/* setup the SMC command ops */
+#define MTK_SIP_APU_START_MCU 0x00U
+#define MTK_SIP_APU_STOP_MCU 0x01U
+
+/* AO Register */
+#define AO_MD32_PRE_DEFINE (APUSYS_APU_S_S_4_BASE + 0x00)
+#define AO_MD32_BOOT_CTRL (APUSYS_APU_S_S_4_BASE + 0x04)
+#define AO_MD32_SYS_CTRL (APUSYS_APU_S_S_4_BASE + 0x08)
+#define AO_SEC_FW (APUSYS_APU_S_S_4_BASE + 0x10)
+
+#define PRE_DEFINE_CACHE_TCM 0x3U
+#define PRE_DEFINE_CACHE 0x2U
+#define PRE_DEFINE_SHIFT_0G 0U
+#define PRE_DEFINE_SHIFT_1G 2U
+#define PRE_DEFINE_SHIFT_2G 4U
+#define PRE_DEFINE_SHIFT_3G 6U
+
+#define SEC_FW_NON_SECURE 1U
+#define SEC_FW_SHIFT_NS 4U
+#define SEC_FW_DOMAIN_SHIFT 0U
+
+#define SYS_CTRL_RUN 0U
+#define SYS_CTRL_STALL 1U
+
+/* Reviser Register */
+#define REVISER_SECUREFW_CTXT (APUSYS_SCTRL_REVISER_BASE + 0x300)
+#define REVISER_USDRFW_CTXT (APUSYS_SCTRL_REVISER_BASE + 0x304)
+
+uint64_t apusys_kernel_ctrl(uint64_t x1, uint64_t x2, uint64_t x3, uint64_t x4,
+ uint32_t *ret1);
+#endif /* __MTK_APUSYS_H__ */
diff --git a/plat/mediatek/mt8192/drivers/apusys/mtk_apusys_apc.c b/plat/mediatek/mt8192/drivers/apusys/mtk_apusys_apc.c
new file mode 100644
index 0000000..245d512
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/apusys/mtk_apusys_apc.c
@@ -0,0 +1,571 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <mtk_apusys_apc.h>
+#include <mtk_apusys_apc_def.h>
+#include <mtk_plat_common.h>
+#include <platform_def.h>
+
+static const struct APC_DOM_16 APUSYS_NOC_DAPC_AO[] = {
+/* 0~3 */
+APUSYS_APC_AO_ATTR("slv07-0",
+ NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+ NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+ NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+ NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION),
+APUSYS_APC_AO_ATTR("slv07-1",
+ NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+ NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+ NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+ NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION),
+APUSYS_APC_AO_ATTR("slv07-2",
+ NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+ NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+ NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+ NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION),
+APUSYS_APC_AO_ATTR("slv07-3",
+ NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+ NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+ NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+ NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION),
+
+/* 16~18 */
+APUSYS_APC_AO_ATTR("slv01-0",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("slv01-1",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("slv01-2",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+/* 19~21 */
+APUSYS_APC_AO_ATTR("slv00-0",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("slv00-1",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("slv00-2",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+/* 22~26 */
+APUSYS_APC_AO_ATTR("slv02-0",
+ NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+ NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+ NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+ NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION),
+APUSYS_APC_AO_ATTR("slv02-1",
+ NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+ NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+ NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+ NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION),
+APUSYS_APC_AO_ATTR("slv02-2",
+ NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+ NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+ NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+ NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION),
+APUSYS_APC_AO_ATTR("slv02-3",
+ NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+ NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+ NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+ NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION),
+APUSYS_APC_AO_ATTR("slv02-4",
+ NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+ NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+ NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+ NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION),
+};
+
+static int32_t set_slave_noc_dapc(uint32_t slave,
+ enum APUSYS_APC_DOMAIN_ID domain_id,
+ enum APUSYS_APC_PERM_TYPE perm)
+{
+ uint32_t apc_register_index;
+ uint32_t apc_set_index;
+ uintptr_t base;
+ uint32_t clr_bit;
+ uint32_t set_bit;
+ int32_t ret;
+
+ if (perm >= PERM_NUM) {
+ ERROR("[NOC_DAPC] perm type:0x%x is not supported!\n", perm);
+ ret = APUSYS_APC_ERR_PERMISSION_NOT_SUPPORTED;
+ goto exit;
+ }
+
+ apc_register_index = slave / APUSYS_NOC_DAPC_AO_SLAVE_NUM_IN_1_DOM;
+ apc_set_index = slave % APUSYS_NOC_DAPC_AO_SLAVE_NUM_IN_1_DOM;
+
+ clr_bit = 0xFFFFFFFF ^ (0x3U << (apc_set_index * 2));
+ set_bit = perm << (apc_set_index * 2);
+
+ if ((slave < APUSYS_NOC_DAPC_AO_SLAVE_NUM) &&
+ (domain_id < APUSYS_NOC_DAPC_AO_DOM_NUM)) {
+ base = APUSYS_NOC_DAPC_AO_BASE +
+ (domain_id * 0x40) + (apc_register_index * 4);
+ apuapc_writel(apuapc_readl(base) & clr_bit, base);
+ apuapc_writel(apuapc_readl(base) | set_bit, base);
+ ret = APUSYS_APC_OK;
+ } else {
+ ERROR("[NOC_DAPC] %s: %s, %s:0x%x, %s:0x%x\n",
+ __func__, "out of boundary",
+ "slave", slave,
+ "domain_id", domain_id);
+ ret = APUSYS_APC_ERR_OUT_OF_BOUNDARY;
+ }
+
+exit:
+ return ret;
+}
+
+static void dump_apusys_noc_dapc(void)
+{
+ uint32_t reg_num;
+ uint32_t d, i;
+
+ reg_num = APUSYS_NOC_DAPC_AO_SLAVE_NUM /
+ APUSYS_NOC_DAPC_AO_SLAVE_NUM_IN_1_DOM;
+ for (d = 0U; d < APUSYS_NOC_DAPC_AO_DOM_NUM; d++) {
+ for (i = 0U; i <= reg_num; i++) {
+ INFO("[NOCDAPC] D%d_APC_%d: 0x%x\n", d, i,
+ apuapc_readl(APUSYS_NOC_DAPC_AO_BASE +
+ (d * 0x40) + (i * 4)));
+ }
+ }
+
+ INFO("[NOCDAPC] APC_CON: 0x%x\n", apuapc_readl(APUSYS_NOC_DAPC_CON));
+}
+
+static const struct APC_DOM_16 APUSYS_AO_Devices[] = {
+
+/* 0 */
+APUSYS_APC_AO_ATTR("apusys_ao-0",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("apusys_ao-1",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("apusys_ao-2",
+ SEC_RW_ONLY, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("apusys_ao-3",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("apusys_ao-4",
+ SEC_RW_ONLY, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("apusys_ao-5",
+ SEC_RW_ONLY, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("md32_apb_s-0",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("md32_apb_s-1",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("md32_apb_s-2",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("md32_debug_apb",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+/* 10 */
+APUSYS_APC_AO_ATTR("apu_conn_config",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("apu_sctrl_reviser",
+ SEC_RW_ONLY, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("apu_sema_stimer",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("apu_emi_config",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("apu_adl",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("apu_edma_lite0",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("apu_edma_lite1",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("apu_edma0",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("apu_edma0",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("apu_dapc_ao",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+/* 20 */
+APUSYS_APC_AO_ATTR("apu_dapc",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("infra_bcrm",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("apb_dbg_ctl",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("noc_dapc",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("apu_noc_bcrm",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("apu_noc_config",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("vpu_core0_config-0",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("vpu_core0_config-1",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("vpu_core1_config-0",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("vpu_core1_config-1",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+/* 30 */
+APUSYS_APC_AO_ATTR("mdla0_apb-0",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("mdla0_apb-1",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("mdla0_apb-2",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("mdla0_apb-3",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("apu_iommu0_r0",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("apu_iommu0_r1",
+ SEC_RW_ONLY, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("apu_iommu0_r2",
+ SEC_RW_ONLY, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("apu_iommu0_r3",
+ SEC_RW_ONLY, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("apu_iommu0_r4",
+ SEC_RW_ONLY, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("apu_rsi2_config",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+/* 40 */
+APUSYS_APC_AO_ATTR("apu_ssc2_config",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("vp6_core0_debug_apb",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("vp6_core1_debug_apb",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+};
+
+static int32_t set_slave_apc(uint32_t slave,
+ enum APUSYS_APC_DOMAIN_ID domain_id,
+ enum APUSYS_APC_PERM_TYPE perm)
+{
+ uint32_t apc_register_index;
+ uint32_t apc_set_index;
+ uintptr_t base;
+ uint32_t clr_bit;
+ uint32_t set_bit;
+ int32_t ret;
+
+ if (perm >= PERM_NUM) {
+ ERROR("[APUAPC] perm type:0x%x is not supported!\n", perm);
+ ret = APUSYS_APC_ERR_PERMISSION_NOT_SUPPORTED;
+ goto exit;
+ }
+
+ apc_register_index = slave / APUSYS_APC_SYS0_AO_SLAVE_NUM_IN_1_DOM;
+ apc_set_index = slave % APUSYS_APC_SYS0_AO_SLAVE_NUM_IN_1_DOM;
+
+ clr_bit = 0xFFFFFFFF ^ (0x3U << (apc_set_index * 2));
+ set_bit = perm << (apc_set_index * 2);
+
+ if ((slave < APUSYS_APC_SYS0_AO_SLAVE_NUM) &&
+ (domain_id < APUSYS_APC_SYS0_AO_DOM_NUM)) {
+ base = APUSYS_APC_AO_BASE +
+ (domain_id * 0x40) + (apc_register_index * 4);
+ apuapc_writel(apuapc_readl(base) & clr_bit, base);
+ apuapc_writel(apuapc_readl(base) | set_bit, base);
+ ret = APUSYS_APC_OK;
+ } else {
+ ERROR("[APUAPC] %s: %s, %s:0x%x, %s:0x%x\n",
+ __func__, "out of boundary",
+ "slave", slave,
+ "domain_id", domain_id);
+ ret = APUSYS_APC_ERR_OUT_OF_BOUNDARY;
+ }
+
+exit:
+ return ret;
+}
+
+static void dump_apusys_ao_apc(void)
+{
+ uint32_t reg_num;
+ uint32_t d, i;
+
+ reg_num = APUSYS_APC_SYS0_AO_SLAVE_NUM /
+ APUSYS_APC_SYS0_AO_SLAVE_NUM_IN_1_DOM;
+ for (d = 0U; d < APUSYS_APC_SYS0_AO_DOM_NUM; d++) {
+ for (i = 0U; i <= reg_num; i++) {
+ INFO("[APUAPC] D%d_APC_%d: 0x%x\n", d, i,
+ apuapc_readl(APUSYS_APC_AO_BASE +
+ (d * 0x40) + (i * 4)));
+ }
+ }
+ INFO("[APUAPC] APC_CON: 0x%x\n", apuapc_readl(APUSYS_APC_CON));
+}
+
+static int32_t set_apusys_noc_dapc(void)
+{
+ int32_t ret = 0;
+ uint32_t i;
+ uint32_t index;
+
+ for (i = 0U; i < ARRAY_SIZE(APUSYS_NOC_DAPC_AO); i++) {
+ if (i < APUSYS_NOC_DAPC_GAP_BOUNDARY) {
+ index = i;
+ } else {
+ index = i + APUSYS_NOC_DAPC_JUMP_GAP;
+ }
+ ret += set_slave_noc_dapc(index, DOMAIN_0,
+ APUSYS_NOC_DAPC_AO[i].d0_permission);
+ ret += set_slave_noc_dapc(index, DOMAIN_1,
+ APUSYS_NOC_DAPC_AO[i].d1_permission);
+ ret += set_slave_noc_dapc(index, DOMAIN_2,
+ APUSYS_NOC_DAPC_AO[i].d2_permission);
+ ret += set_slave_noc_dapc(index, DOMAIN_3,
+ APUSYS_NOC_DAPC_AO[i].d3_permission);
+ ret += set_slave_noc_dapc(index, DOMAIN_4,
+ APUSYS_NOC_DAPC_AO[i].d4_permission);
+ ret += set_slave_noc_dapc(index, DOMAIN_5,
+ APUSYS_NOC_DAPC_AO[i].d5_permission);
+ ret += set_slave_noc_dapc(index, DOMAIN_6,
+ APUSYS_NOC_DAPC_AO[i].d6_permission);
+ ret += set_slave_noc_dapc(index, DOMAIN_7,
+ APUSYS_NOC_DAPC_AO[i].d7_permission);
+ ret += set_slave_noc_dapc(index, DOMAIN_8,
+ APUSYS_NOC_DAPC_AO[i].d8_permission);
+ ret += set_slave_noc_dapc(index, DOMAIN_9,
+ APUSYS_NOC_DAPC_AO[i].d9_permission);
+ ret += set_slave_noc_dapc(index, DOMAIN_10,
+ APUSYS_NOC_DAPC_AO[i].d10_permission);
+ ret += set_slave_noc_dapc(index, DOMAIN_11,
+ APUSYS_NOC_DAPC_AO[i].d11_permission);
+ ret += set_slave_noc_dapc(index, DOMAIN_12,
+ APUSYS_NOC_DAPC_AO[i].d12_permission);
+ ret += set_slave_noc_dapc(index, DOMAIN_13,
+ APUSYS_NOC_DAPC_AO[i].d13_permission);
+ ret += set_slave_noc_dapc(index, DOMAIN_14,
+ APUSYS_NOC_DAPC_AO[i].d14_permission);
+ ret += set_slave_noc_dapc(index, DOMAIN_15,
+ APUSYS_NOC_DAPC_AO[i].d15_permission);
+ }
+
+ return ret;
+}
+
+static int32_t set_apusys_ao_apc(void)
+{
+ int32_t ret = 0;
+ uint32_t i;
+
+ for (i = 0U; i < ARRAY_SIZE(APUSYS_AO_Devices); i++) {
+ ret += set_slave_apc(i, DOMAIN_0,
+ APUSYS_AO_Devices[i].d0_permission);
+ ret += set_slave_apc(i, DOMAIN_1,
+ APUSYS_AO_Devices[i].d1_permission);
+ ret += set_slave_apc(i, DOMAIN_2,
+ APUSYS_AO_Devices[i].d2_permission);
+ ret += set_slave_apc(i, DOMAIN_3,
+ APUSYS_AO_Devices[i].d3_permission);
+ ret += set_slave_apc(i, DOMAIN_4,
+ APUSYS_AO_Devices[i].d4_permission);
+ ret += set_slave_apc(i, DOMAIN_5,
+ APUSYS_AO_Devices[i].d5_permission);
+ ret += set_slave_apc(i, DOMAIN_6,
+ APUSYS_AO_Devices[i].d6_permission);
+ ret += set_slave_apc(i, DOMAIN_7,
+ APUSYS_AO_Devices[i].d7_permission);
+ ret += set_slave_apc(i, DOMAIN_8,
+ APUSYS_AO_Devices[i].d8_permission);
+ ret += set_slave_apc(i, DOMAIN_9,
+ APUSYS_AO_Devices[i].d9_permission);
+ ret += set_slave_apc(i, DOMAIN_10,
+ APUSYS_AO_Devices[i].d10_permission);
+ ret += set_slave_apc(i, DOMAIN_11,
+ APUSYS_AO_Devices[i].d11_permission);
+ ret += set_slave_apc(i, DOMAIN_12,
+ APUSYS_AO_Devices[i].d12_permission);
+ ret += set_slave_apc(i, DOMAIN_13,
+ APUSYS_AO_Devices[i].d13_permission);
+ ret += set_slave_apc(i, DOMAIN_14,
+ APUSYS_AO_Devices[i].d14_permission);
+ ret += set_slave_apc(i, DOMAIN_15,
+ APUSYS_AO_Devices[i].d15_permission);
+ }
+
+ return ret;
+}
+
+static void set_apusys_apc_lock(void)
+{
+ uint32_t set_bit = 1U << APUSYS_APC_SYS0_LOCK_BIT_APU_SCTRL_REVISER;
+
+ /* Lock apu_sctrl_reviser */
+ set_bit = set_bit | (1U << APUSYS_APC_SYS0_LOCK_BIT_APUSYS_AO_5);
+ apuapc_writel(set_bit, APUSYS_SYS0_APC_LOCK_0);
+}
+
+void set_apusys_apc(void)
+{
+ int32_t ret = 0;
+
+ /* Check violation status */
+ INFO("[APUAPC] vio %d\n", apuapc_readl(APUSYS_APC_CON) & 0x80000000);
+
+ /* Initial Permission */
+ ret = set_apusys_ao_apc();
+ INFO("[APUAPC] %s - %s!\n", "set_apusys_ao_apc",
+ ret ? "FAILED" : "SUCCESS");
+
+ /* Lock */
+ set_apusys_apc_lock();
+
+ /* Initial NoC Permission */
+ ret = set_apusys_noc_dapc();
+ INFO("[APUAPC] %s - %s!\n", "set_apusys_noc_dapc",
+ ret ? "FAILED" : "SUCCESS");
+
+ /* Dump Permission */
+ dump_apusys_ao_apc();
+ dump_apusys_noc_dapc();
+
+ INFO("[APUAPC] %s done\n", __func__);
+}
diff --git a/plat/mediatek/mt8192/drivers/apusys/mtk_apusys_apc.h b/plat/mediatek/mt8192/drivers/apusys/mtk_apusys_apc.h
new file mode 100644
index 0000000..ff7a9fa
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/apusys/mtk_apusys_apc.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __MTK_APUSYS_APC_H__
+#define __MTK_APUSYS_APC_H__
+
+void set_apusys_apc(void);
+
+#endif /* __MTK_APUSYS_APC_H__ */
diff --git a/plat/mediatek/mt8192/drivers/apusys/mtk_apusys_apc_def.h b/plat/mediatek/mt8192/drivers/apusys/mtk_apusys_apc_def.h
new file mode 100644
index 0000000..b392d6a
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/apusys/mtk_apusys_apc_def.h
@@ -0,0 +1,110 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __MTK_APUSYS_APC_DEF_H__
+#define __MTK_APUSYS_APC_DEF_H__
+
+#include <lib/mmio.h>
+
+enum APUSYS_APC_ERR_STATUS {
+ APUSYS_APC_OK = 0x0,
+
+ APUSYS_APC_ERR_GENERIC = 0x1000,
+ APUSYS_APC_ERR_INVALID_CMD = 0x1001,
+ APUSYS_APC_ERR_SLAVE_TYPE_NOT_SUPPORTED = 0x1002,
+ APUSYS_APC_ERR_SLAVE_IDX_NOT_SUPPORTED = 0x1003,
+ APUSYS_APC_ERR_DOMAIN_NOT_SUPPORTED = 0x1004,
+ APUSYS_APC_ERR_PERMISSION_NOT_SUPPORTED = 0x1005,
+ APUSYS_APC_ERR_OUT_OF_BOUNDARY = 0x1006,
+ APUSYS_APC_ERR_REQ_TYPE_NOT_SUPPORTED = 0x1007,
+};
+
+enum APUSYS_APC_PERM_TYPE {
+ NO_PROTECTION = 0U,
+ SEC_RW_ONLY = 1U,
+ SEC_RW_NS_R = 2U,
+ FORBIDDEN = 3U,
+ PERM_NUM = 4U,
+};
+
+enum APUSYS_APC_DOMAIN_ID {
+ DOMAIN_0 = 0U,
+ DOMAIN_1 = 1U,
+ DOMAIN_2 = 2U,
+ DOMAIN_3 = 3U,
+ DOMAIN_4 = 4U,
+ DOMAIN_5 = 5U,
+ DOMAIN_6 = 6U,
+ DOMAIN_7 = 7U,
+ DOMAIN_8 = 8U,
+ DOMAIN_9 = 9U,
+ DOMAIN_10 = 10U,
+ DOMAIN_11 = 11U,
+ DOMAIN_12 = 12U,
+ DOMAIN_13 = 13U,
+ DOMAIN_14 = 14U,
+ DOMAIN_15 = 15U,
+};
+
+struct APC_DOM_16 {
+ unsigned char d0_permission;
+ unsigned char d1_permission;
+ unsigned char d2_permission;
+ unsigned char d3_permission;
+ unsigned char d4_permission;
+ unsigned char d5_permission;
+ unsigned char d6_permission;
+ unsigned char d7_permission;
+ unsigned char d8_permission;
+ unsigned char d9_permission;
+ unsigned char d10_permission;
+ unsigned char d11_permission;
+ unsigned char d12_permission;
+ unsigned char d13_permission;
+ unsigned char d14_permission;
+ unsigned char d15_permission;
+};
+
+#define APUSYS_APC_AO_ATTR(DEV_NAME, PERM_ATTR0, PERM_ATTR1, \
+ PERM_ATTR2, PERM_ATTR3, PERM_ATTR4, PERM_ATTR5, \
+ PERM_ATTR6, PERM_ATTR7, PERM_ATTR8, PERM_ATTR9, \
+ PERM_ATTR10, PERM_ATTR11, PERM_ATTR12, PERM_ATTR13, \
+ PERM_ATTR14, PERM_ATTR15) \
+ {(unsigned char)PERM_ATTR0, (unsigned char)PERM_ATTR1, \
+ (unsigned char)PERM_ATTR2, (unsigned char)PERM_ATTR3, \
+ (unsigned char)PERM_ATTR4, (unsigned char)PERM_ATTR5, \
+ (unsigned char)PERM_ATTR6, (unsigned char)PERM_ATTR7, \
+ (unsigned char)PERM_ATTR8, (unsigned char)PERM_ATTR9, \
+ (unsigned char)PERM_ATTR10, (unsigned char)PERM_ATTR11, \
+ (unsigned char)PERM_ATTR12, (unsigned char)PERM_ATTR13, \
+ (unsigned char)PERM_ATTR14, (unsigned char)PERM_ATTR15}
+
+#define apuapc_writel(VAL, REG) mmio_write_32((uintptr_t)REG, VAL)
+#define apuapc_readl(REG) mmio_read_32((uintptr_t)REG)
+
+/* APUSYS APC AO Registers */
+#define APUSYS_APC_AO_BASE APUSYS_APC_AO_WRAPPER_BASE
+#define APUSYS_APC_CON (APUSYS_APC_AO_BASE + 0x00F00)
+#define APUSYS_SYS0_APC_LOCK_0 (APUSYS_APC_AO_BASE + 0x00700)
+
+/* APUSYS NOC_DPAC_AO Registers */
+#define APUSYS_NOC_DAPC_CON (APUSYS_NOC_DAPC_AO_BASE + 0x00F00)
+
+#define APUSYS_NOC_DAPC_GAP_BOUNDARY 4U
+#define APUSYS_NOC_DAPC_JUMP_GAP 12U
+
+#define APUSYS_APC_SYS0_AO_SLAVE_NUM_IN_1_DOM 16U
+#define APUSYS_APC_SYS0_AO_DOM_NUM 16U
+#define APUSYS_APC_SYS0_AO_SLAVE_NUM 59U
+
+#define APUSYS_APC_SYS0_LOCK_BIT_APU_SCTRL_REVISER 11U
+#define APUSYS_APC_SYS0_LOCK_BIT_APUSYS_AO_5 5U
+
+#define APUSYS_NOC_DAPC_AO_SLAVE_NUM_IN_1_DOM 16U
+#define APUSYS_NOC_DAPC_AO_DOM_NUM 16U
+#define APUSYS_NOC_DAPC_AO_SLAVE_NUM 27U
+
+#endif /* __MTK_APUSYS_APC_DEF_H__ */
diff --git a/plat/mediatek/mt8192/drivers/devapc/devapc.c b/plat/mediatek/mt8192/drivers/devapc/devapc.c
index c7dbbee..b11f272 100644
--- a/plat/mediatek/mt8192/drivers/devapc/devapc.c
+++ b/plat/mediatek/mt8192/drivers/devapc/devapc.c
@@ -9,6 +9,7 @@
#include <lib/mmio.h>
#include <devapc.h>
+#include <mtk_apusys_apc.h>
/* Infra_ao */
static const struct APC_INFRA_PERI_DOM_16 INFRA_AO_SYS0_Devices[] = {
@@ -82,12 +83,12 @@
FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
DAPC_INFRA_AO_SYS0_ATTR("APU_S_S-4",
- NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ SEC_RW_ONLY, FORBIDDEN, FORBIDDEN, FORBIDDEN,
FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
DAPC_INFRA_AO_SYS0_ATTR("APU_S_S-5",
- NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ SEC_RW_ONLY, FORBIDDEN, FORBIDDEN, FORBIDDEN,
FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
@@ -2839,5 +2840,8 @@
dump_peri_ao2_apc();
dump_peri_par_ao_apc();
+ /* Setup APUSYS Permission */
+ set_apusys_apc();
+
INFO("[DEVAPC] %s done\n", __func__);
}
diff --git a/plat/mediatek/mt8192/include/platform_def.h b/plat/mediatek/mt8192/include/platform_def.h
index 320124f..ec377b5 100644
--- a/plat/mediatek/mt8192/include/platform_def.h
+++ b/plat/mediatek/mt8192/include/platform_def.h
@@ -26,6 +26,16 @@
#define MTK_MCDI_SRAM_BASE 0x11B000
#define MTK_MCDI_SRAM_MAP_SIZE 0x1000
+#define APUSYS_BASE 0x19000000
+#define APUSYS_SCTRL_REVISER_BASE 0x19021000
+#define APUSYS_SCTRL_REVISER_SIZE 0x1000
+#define APUSYS_APU_S_S_4_BASE 0x190F2000
+#define APUSYS_APU_S_S_4_SIZE 0x1000
+#define APUSYS_APC_AO_WRAPPER_BASE 0x190F8000
+#define APUSYS_APC_AO_WRAPPER_SIZE 0x1000
+#define APUSYS_NOC_DAPC_AO_BASE 0x190FC000
+#define APUSYS_NOC_DAPC_AO_SIZE 0x1000
+
#define TOPCKGEN_BASE (IO_PHYS + 0x00000000)
#define INFRACFG_AO_BASE (IO_PHYS + 0x00001000)
#define GPIO_BASE (IO_PHYS + 0x00005000)
diff --git a/plat/mediatek/mt8192/plat_sip_calls.c b/plat/mediatek/mt8192/plat_sip_calls.c
index 360ad0f..f567f02 100644
--- a/plat/mediatek/mt8192/plat_sip_calls.c
+++ b/plat/mediatek/mt8192/plat_sip_calls.c
@@ -6,6 +6,7 @@
#include <common/debug.h>
#include <common/runtime_svc.h>
+#include <mtk_apusys.h>
#include <mtk_sip_svc.h>
#include <mt_spm_vcorefs.h>
#include "plat_sip_calls.h"
@@ -20,6 +21,7 @@
u_register_t flags)
{
uint64_t ret;
+ uint32_t rnd_val0 = 0U;
switch (smc_fid) {
case MTK_SIP_VCORE_CONTROL_ARCH32:
@@ -27,6 +29,11 @@
ret = spm_vcorefs_args(x1, x2, x3, (uint64_t *)&x4);
SMC_RET2(handle, ret, x4);
break;
+ case MTK_SIP_APUSYS_CONTROL_AARCH32:
+ case MTK_SIP_APUSYS_CONTROL_AARCH64:
+ ret = apusys_kernel_ctrl(x1, x2, x3, x4, &rnd_val0);
+ SMC_RET2(handle, ret, rnd_val0);
+ break;
default:
ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
break;
diff --git a/plat/mediatek/mt8192/platform.mk b/plat/mediatek/mt8192/platform.mk
index 1a57ea8..7761a55 100644
--- a/plat/mediatek/mt8192/platform.mk
+++ b/plat/mediatek/mt8192/platform.mk
@@ -16,6 +16,7 @@
-I${MTK_PLAT}/common/lpm/ \
-I${MTK_PLAT_SOC}/include/ \
-I${MTK_PLAT_SOC}/drivers/ \
+ -I${MTK_PLAT_SOC}/drivers/apusys/ \
-I${MTK_PLAT_SOC}/drivers/dcm \
-I${MTK_PLAT_SOC}/drivers/devapc \
-I${MTK_PLAT_SOC}/drivers/emi_mpu/ \
@@ -62,6 +63,8 @@
${MTK_PLAT_SOC}/plat_pm.c \
${MTK_PLAT_SOC}/plat_topology.c \
${MTK_PLAT_SOC}/plat_sip_calls.c \
+ ${MTK_PLAT_SOC}/drivers/apusys/mtk_apusys.c \
+ ${MTK_PLAT_SOC}/drivers/apusys/mtk_apusys_apc.c \
${MTK_PLAT_SOC}/drivers/dcm/mtk_dcm.c \
${MTK_PLAT_SOC}/drivers/dcm/mtk_dcm_utils.c \
${MTK_PLAT_SOC}/drivers/devapc/devapc.c \
diff --git a/plat/mediatek/mt8195/aarch64/platform_common.c b/plat/mediatek/mt8195/aarch64/platform_common.c
index 745e547..a9314ea 100644
--- a/plat/mediatek/mt8195/aarch64/platform_common.c
+++ b/plat/mediatek/mt8195/aarch64/platform_common.c
@@ -17,6 +17,10 @@
MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(MTK_DEV_RNG2_BASE, MTK_DEV_RNG2_SIZE,
MT_DEVICE | MT_RW | MT_SECURE),
+ MAP_REGION_FLAT(DP_SEC_BASE, DP_SEC_SIZE,
+ MT_DEVICE | MT_RW | MT_SECURE),
+ MAP_REGION_FLAT(eDP_SEC_BASE, eDP_SEC_SIZE,
+ MT_DEVICE | MT_RW | MT_SECURE),
{ 0 }
};
diff --git a/plat/mediatek/mt8195/drivers/dp/mt_dp.c b/plat/mediatek/mt8195/drivers/dp/mt_dp.c
new file mode 100644
index 0000000..7ab2194
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/dp/mt_dp.c
@@ -0,0 +1,66 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include <common/debug.h>
+#include <lib/mmio.h>
+#include <mt_dp.h>
+#include <mtk_sip_svc.h>
+#include <platform_def.h>
+
+static uint32_t dp_write_sec_reg(uint32_t is_edp, uint32_t offset,
+ uint32_t value, uint32_t mask)
+{
+ uint32_t reg = (is_edp != 0U) ? eDP_SEC_BASE : DP_SEC_BASE;
+
+ mmio_clrsetbits_32(reg + offset, mask, value);
+
+ return mmio_read_32(reg + offset);
+}
+
+int32_t dp_secure_handler(uint64_t cmd, uint64_t para, uint32_t *val)
+{
+ int32_t ret = 0L;
+ uint32_t is_edp = 0UL;
+ uint32_t regval = 0UL;
+ uint32_t regmsk = 0UL;
+ uint32_t fldmask = 0UL;
+
+ if ((cmd > DP_ATF_CMD_COUNT) || (val == NULL)) {
+ INFO("dp_secure_handler error cmd 0x%llx\n", cmd);
+ return MTK_SIP_E_INVALID_PARAM;
+ }
+
+ switch (cmd) {
+ case DP_ATF_DP_VIDEO_UNMUTE:
+ INFO("[%s] DP_ATF_DP_VIDEO_UNMUTE\n", __func__);
+ is_edp = DP_ATF_TYPE_DP;
+ ret = MTK_SIP_E_SUCCESS;
+ break;
+ case DP_ATF_EDP_VIDEO_UNMUTE:
+ INFO("[%s] DP_ATF_EDP_VIDEO_UNMUTE\n", __func__);
+ is_edp = DP_ATF_TYPE_EDP;
+ ret = MTK_SIP_E_SUCCESS;
+ break;
+ default:
+ ret = MTK_SIP_E_INVALID_PARAM;
+ break;
+ }
+
+ if (ret == MTK_SIP_E_SUCCESS) {
+ regmsk = (VIDEO_MUTE_SEL_SECURE_FLDMASK |
+ VIDEO_MUTE_SW_SECURE_FLDMASK);
+ if (para > 0U) {
+ fldmask = VIDEO_MUTE_SW_SECURE_FLDMASK;
+ } else {
+ fldmask = 0;
+ }
+
+ regval = (VIDEO_MUTE_SEL_SECURE_FLDMASK | fldmask);
+ *val = dp_write_sec_reg(is_edp, DP_TX_SECURE_REG11,
+ regval, regmsk);
+ }
+
+ return ret;
+}
diff --git a/plat/mediatek/mt8195/drivers/dp/mt_dp.h b/plat/mediatek/mt8195/drivers/dp/mt_dp.h
new file mode 100644
index 0000000..8157598
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/dp/mt_dp.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_DP_H
+#define MT_DP_H
+
+#define DP_TX_SECURE_REG11 (0x2c)
+
+#define VIDEO_MUTE_SEL_SECURE_FLDMASK (0x10)
+#define VIDEO_MUTE_SW_SECURE_FLDMASK (0x8)
+
+enum DP_ATF_HW_TYPE {
+ DP_ATF_TYPE_DP = 0,
+ DP_ATF_TYPE_EDP = 1
+};
+
+enum DP_ATF_CMD {
+ DP_ATF_DP_VIDEO_UNMUTE = 0x20,
+ DP_ATF_EDP_VIDEO_UNMUTE,
+ DP_ATF_CMD_COUNT
+};
+
+int32_t dp_secure_handler(uint64_t cmd, uint64_t para, uint32_t *val);
+
+#endif
diff --git a/plat/mediatek/mt8195/include/plat_sip_calls.h b/plat/mediatek/mt8195/include/plat_sip_calls.h
index 0e42322..181aec0 100644
--- a/plat/mediatek/mt8195/include/plat_sip_calls.h
+++ b/plat/mediatek/mt8195/include/plat_sip_calls.h
@@ -10,6 +10,10 @@
/*******************************************************************************
* Plat SiP function constants
******************************************************************************/
-#define MTK_PLAT_SIP_NUM_CALLS 0
+#define MTK_PLAT_SIP_NUM_CALLS 2
+
+/* DP/eDP */
+#define MTK_SIP_DP_CONTROL_AARCH32 0x82000523
+#define MTK_SIP_DP_CONTROL_AARCH64 0xC2000523
#endif /* PLAT_SIP_CALLS_H */
diff --git a/plat/mediatek/mt8195/include/platform_def.h b/plat/mediatek/mt8195/include/platform_def.h
index f6eb742..eaf5985 100644
--- a/plat/mediatek/mt8195/include/platform_def.h
+++ b/plat/mediatek/mt8195/include/platform_def.h
@@ -26,6 +26,14 @@
#define SPM_BASE (IO_PHYS + 0x00006000)
/*******************************************************************************
+ * DP/eDP related constants
+ ******************************************************************************/
+#define eDP_SEC_BASE (IO_PHYS + 0x0C504000)
+#define DP_SEC_BASE (IO_PHYS + 0x0C604000)
+#define eDP_SEC_SIZE 0x1000
+#define DP_SEC_SIZE 0x1000
+
+/*******************************************************************************
* GPIO related constants
******************************************************************************/
#define GPIO_BASE (IO_PHYS + 0x00005000)
diff --git a/plat/mediatek/mt8195/plat_sip_calls.c b/plat/mediatek/mt8195/plat_sip_calls.c
index a1e3c36..99e1eb3 100644
--- a/plat/mediatek/mt8195/plat_sip_calls.c
+++ b/plat/mediatek/mt8195/plat_sip_calls.c
@@ -6,6 +6,9 @@
#include <common/debug.h>
#include <common/runtime_svc.h>
+#include <mt_dp.h>
+#include <mtk_sip_svc.h>
+#include "plat_sip_calls.h"
uintptr_t mediatek_plat_sip_handler(uint32_t smc_fid,
u_register_t x1,
@@ -16,7 +19,15 @@
void *handle,
u_register_t flags)
{
+ int32_t ret;
+ uint32_t ret_val;
+
switch (smc_fid) {
+ case MTK_SIP_DP_CONTROL_AARCH32:
+ case MTK_SIP_DP_CONTROL_AARCH64:
+ ret = dp_secure_handler(x1, x2, &ret_val);
+ SMC_RET2(handle, ret, ret_val);
+ break;
default:
ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
break;
diff --git a/plat/mediatek/mt8195/platform.mk b/plat/mediatek/mt8195/platform.mk
index 4d3ad59..026cf41 100644
--- a/plat/mediatek/mt8195/platform.mk
+++ b/plat/mediatek/mt8195/platform.mk
@@ -12,6 +12,7 @@
-I${MTK_PLAT}/common/drivers/gpio/ \
-I${MTK_PLAT}/common/drivers/rtc/ \
-I${MTK_PLAT}/common/drivers/timer/ \
+ -I${MTK_PLAT_SOC}/drivers/dp/ \
-I${MTK_PLAT_SOC}/drivers/gpio/ \
-I${MTK_PLAT_SOC}/drivers/mcdi/ \
-I${MTK_PLAT_SOC}/drivers/pmic/ \
@@ -50,6 +51,7 @@
${MTK_PLAT_SOC}/aarch64/platform_common.c \
${MTK_PLAT_SOC}/aarch64/plat_helpers.S \
${MTK_PLAT_SOC}/bl31_plat_setup.c \
+ ${MTK_PLAT_SOC}/drivers/dp/mt_dp.c \
${MTK_PLAT_SOC}/drivers/gpio/mtgpio.c \
${MTK_PLAT_SOC}/drivers/mcdi/mt_cpu_pm.c \
${MTK_PLAT_SOC}/drivers/mcdi/mt_cpu_pm_cpc.c \
diff --git a/plat/st/common/bl2_io_storage.c b/plat/st/common/bl2_io_storage.c
index 6dedc98..a25643b 100644
--- a/plat/st/common/bl2_io_storage.c
+++ b/plat/st/common/bl2_io_storage.c
@@ -31,9 +31,11 @@
#include <plat/common/platform.h>
/* IO devices */
+#ifndef AARCH32_SP_OPTEE
static const io_dev_connector_t *dummy_dev_con;
static uintptr_t dummy_dev_handle;
static uintptr_t dummy_dev_spec;
+#endif
static uintptr_t image_dev_handle;
static uintptr_t storage_dev_handle;
@@ -102,9 +104,9 @@
.binary_type = OPTEE_HEADER_BINARY_TYPE,
};
-static const struct stm32image_part_info optee_pager_partition_spec = {
- .name = OPTEE_PAGER_IMAGE_NAME,
- .binary_type = OPTEE_PAGER_BINARY_TYPE,
+static const struct stm32image_part_info optee_core_partition_spec = {
+ .name = OPTEE_CORE_IMAGE_NAME,
+ .binary_type = OPTEE_CORE_BINARY_TYPE,
};
static const struct stm32image_part_info optee_paged_partition_spec = {
@@ -118,11 +120,6 @@
};
#endif
-static const io_block_spec_t bl2_block_spec = {
- .offset = BL2_BASE,
- .length = STM32MP_BL2_SIZE,
-};
-
static const struct stm32image_part_info bl33_partition_spec = {
.name = BL33_IMAGE_NAME,
.binary_type = BL33_BINARY_TYPE,
@@ -132,7 +129,7 @@
IMG_IDX_BL33,
#ifdef AARCH32_SP_OPTEE
IMG_IDX_OPTEE_HEADER,
- IMG_IDX_OPTEE_PAGER,
+ IMG_IDX_OPTEE_CORE,
IMG_IDX_OPTEE_PAGED,
#endif
IMG_IDX_NUM
@@ -149,9 +146,9 @@
.name = OPTEE_HEADER_IMAGE_NAME,
.binary_type = OPTEE_HEADER_BINARY_TYPE,
},
- .part_info[IMG_IDX_OPTEE_PAGER] = {
- .name = OPTEE_PAGER_IMAGE_NAME,
- .binary_type = OPTEE_PAGER_BINARY_TYPE,
+ .part_info[IMG_IDX_OPTEE_CORE] = {
+ .name = OPTEE_CORE_IMAGE_NAME,
+ .binary_type = OPTEE_CORE_BINARY_TYPE,
},
.part_info[IMG_IDX_OPTEE_PAGED] = {
.name = OPTEE_PAGED_IMAGE_NAME,
@@ -167,7 +164,9 @@
static const io_dev_connector_t *stm32image_dev_con __unused;
+#ifndef AARCH32_SP_OPTEE
static int open_dummy(const uintptr_t spec);
+#endif
static int open_image(const uintptr_t spec);
static int open_storage(const uintptr_t spec);
@@ -178,11 +177,6 @@
};
static const struct plat_io_policy policies[] = {
- [BL2_IMAGE_ID] = {
- .dev_handle = &dummy_dev_handle,
- .image_spec = (uintptr_t)&bl2_block_spec,
- .check = open_dummy
- },
#ifdef AARCH32_SP_OPTEE
[BL32_IMAGE_ID] = {
.dev_handle = &image_dev_handle,
@@ -191,7 +185,7 @@
},
[BL32_EXTRA1_IMAGE_ID] = {
.dev_handle = &image_dev_handle,
- .image_spec = (uintptr_t)&optee_pager_partition_spec,
+ .image_spec = (uintptr_t)&optee_core_partition_spec,
.check = open_image
},
[BL32_EXTRA2_IMAGE_ID] = {
@@ -225,10 +219,12 @@
}
};
+#ifndef AARCH32_SP_OPTEE
static int open_dummy(const uintptr_t spec)
{
return io_dev_init(dummy_dev_handle, 0);
}
+#endif
static int open_image(const uintptr_t spec)
{
@@ -396,7 +392,7 @@
part->part_offset = STM32MP_NOR_TEED_OFFSET;
part->bkp_offset = 0U;
- idx = IMG_IDX_OPTEE_PAGER;
+ idx = IMG_IDX_OPTEE_CORE;
part = &stm32image_dev_info_spec.part_info[idx];
part->part_offset = STM32MP_NOR_TEEX_OFFSET;
part->bkp_offset = 0U;
@@ -449,7 +445,7 @@
part->part_offset = STM32MP_NAND_TEED_OFFSET;
part->bkp_offset = nand_dev_spec.erase_size;
- idx = IMG_IDX_OPTEE_PAGER;
+ idx = IMG_IDX_OPTEE_CORE;
part = &stm32image_dev_info_spec.part_info[idx];
part->part_offset = STM32MP_NAND_TEEX_OFFSET;
part->bkp_offset = nand_dev_spec.erase_size;
@@ -503,7 +499,7 @@
part->part_offset = STM32MP_NAND_TEED_OFFSET;
part->bkp_offset = spi_nand_dev_spec.erase_size;
- idx = IMG_IDX_OPTEE_PAGER;
+ idx = IMG_IDX_OPTEE_CORE;
part = &stm32image_dev_info_spec.part_info[idx];
part->part_offset = STM32MP_NAND_TEEX_OFFSET;
part->bkp_offset = spi_nand_dev_spec.erase_size;
@@ -533,12 +529,14 @@
boot_context->boot_partition_used_toboot);
}
+#ifndef AARCH32_SP_OPTEE
io_result = register_io_dev_dummy(&dummy_dev_con);
assert(io_result == 0);
io_result = io_dev_open(dummy_dev_con, dummy_dev_spec,
&dummy_dev_handle);
assert(io_result == 0);
+#endif
switch (boot_context->boot_interface_selected) {
#if STM32MP_SDMMC
diff --git a/plat/st/stm32mp1/include/platform_def.h b/plat/st/stm32mp1/include/platform_def.h
index b45f8fb..9a2f54a 100644
--- a/plat/st/stm32mp1/include/platform_def.h
+++ b/plat/st/stm32mp1/include/platform_def.h
@@ -27,10 +27,10 @@
#ifdef AARCH32_SP_OPTEE
#define OPTEE_HEADER_IMAGE_NAME "teeh"
+#define OPTEE_CORE_IMAGE_NAME "teex"
#define OPTEE_PAGED_IMAGE_NAME "teed"
-#define OPTEE_PAGER_IMAGE_NAME "teex"
#define OPTEE_HEADER_BINARY_TYPE U(0x20)
-#define OPTEE_PAGER_BINARY_TYPE U(0x21)
+#define OPTEE_CORE_BINARY_TYPE U(0x21)
#define OPTEE_PAGED_BINARY_TYPE U(0x22)
#endif
diff --git a/plat/xilinx/versal/include/plat_ipi.h b/plat/xilinx/versal/include/plat_ipi.h
index 6b08f32..36a4380 100644
--- a/plat/xilinx/versal/include/plat_ipi.h
+++ b/plat/xilinx/versal/include/plat_ipi.h
@@ -31,7 +31,7 @@
#define IPI_BUFFER_APU_BASE (IPI_BUFFER_BASEADDR + 0x400U)
#define IPI_BUFFER_PMC_BASE (IPI_BUFFER_BASEADDR + 0x200U)
-#define IPI_BUFFER_TARGET_APU_OFFSET 0x0U
+#define IPI_BUFFER_TARGET_APU_OFFSET 0x80U
#define IPI_BUFFER_TARGET_PMC_OFFSET 0x40U
#define IPI_BUFFER_LOCAL_BASE IPI_BUFFER_APU_BASE
diff --git a/plat/xilinx/zynqmp/aarch64/zynqmp_common.c b/plat/xilinx/zynqmp/aarch64/zynqmp_common.c
index b3365d9..ec433ff 100644
--- a/plat/xilinx/zynqmp/aarch64/zynqmp_common.c
+++ b/plat/xilinx/zynqmp/aarch64/zynqmp_common.c
@@ -62,156 +62,156 @@
} zynqmp_devices[] = {
{
.id = 0x10,
- .name = "3EG",
+ .name = "XCZU3EG",
},
{
.id = 0x10,
.ver = 0x2c,
- .name = "3CG",
+ .name = "XCZU3CG",
},
{
.id = 0x11,
- .name = "2EG",
+ .name = "XCZU2EG",
},
{
.id = 0x11,
.ver = 0x2c,
- .name = "2CG",
+ .name = "XCZU2CG",
},
{
.id = 0x20,
- .name = "5EV",
+ .name = "XCZU5EV",
.evexists = true,
},
{
.id = 0x20,
.ver = 0x100,
- .name = "5EG",
+ .name = "XCZU5EG",
.evexists = true,
},
{
.id = 0x20,
.ver = 0x12c,
- .name = "5CG",
+ .name = "XCZU5CG",
},
{
.id = 0x21,
- .name = "4EV",
+ .name = "XCZU4EV",
.evexists = true,
},
{
.id = 0x21,
.ver = 0x100,
- .name = "4EG",
+ .name = "XCZU4EG",
.evexists = true,
},
{
.id = 0x21,
.ver = 0x12c,
- .name = "4CG",
+ .name = "XCZU4CG",
},
{
.id = 0x30,
- .name = "7EV",
+ .name = "XCZU7EV",
.evexists = true,
},
{
.id = 0x30,
.ver = 0x100,
- .name = "7EG",
+ .name = "XCZU7EG",
.evexists = true,
},
{
.id = 0x30,
.ver = 0x12c,
- .name = "7CG",
+ .name = "XCZU7CG",
},
{
.id = 0x38,
- .name = "9EG",
+ .name = "XCZU9EG",
},
{
.id = 0x38,
.ver = 0x2c,
- .name = "9CG",
+ .name = "XCZU9CG",
},
{
.id = 0x39,
- .name = "6EG",
+ .name = "XCZU6EG",
},
{
.id = 0x39,
.ver = 0x2c,
- .name = "6CG",
+ .name = "XCZU6CG",
},
{
.id = 0x40,
- .name = "11EG",
+ .name = "XCZU11EG",
},
{ /* For testing purpose only */
.id = 0x50,
.ver = 0x2c,
- .name = "15CG",
+ .name = "XCZU15CG",
},
{
.id = 0x50,
- .name = "15EG",
+ .name = "XCZU15EG",
},
{
.id = 0x58,
- .name = "19EG",
+ .name = "XCZU19EG",
},
{
.id = 0x59,
- .name = "17EG",
+ .name = "XCZU17EG",
},
{
.id = 0x60,
- .name = "28DR",
+ .name = "XCZU28DR",
},
{
.id = 0x61,
- .name = "21DR",
+ .name = "XCZU21DR",
},
{
.id = 0x62,
- .name = "29DR",
+ .name = "XCZU29DR",
},
{
.id = 0x63,
- .name = "23DR",
+ .name = "XCZU23DR",
},
{
.id = 0x64,
- .name = "27DR",
+ .name = "XCZU27DR",
},
{
.id = 0x65,
- .name = "25DR",
+ .name = "XCZU25DR",
},
{
.id = 0x66,
- .name = "39DR",
+ .name = "XCZU39DR",
},
{
.id = 0x7d,
- .name = "43DR",
+ .name = "XCZU43DR",
},
{
.id = 0x78,
- .name = "46DR",
+ .name = "XCZU46DR",
},
{
.id = 0x7f,
- .name = "47DR",
+ .name = "XCZU47DR",
},
{
.id = 0x7b,
- .name = "48DR",
+ .name = "XCZU48DR",
},
{
.id = 0x7e,
- .name = "49DR",
+ .name = "XCZU49DR",
},
};
@@ -219,6 +219,8 @@
#define ZYNQMP_PL_STATUS_MASK BIT(ZYNQMP_PL_STATUS_BIT)
#define ZYNQMP_CSU_VERSION_MASK ~(ZYNQMP_PL_STATUS_MASK)
+#define SILICON_ID_XCK26 0x4724093
+
static char *zynqmp_get_silicon_idcode_name(void)
{
uint32_t id, ver, chipid[2];
@@ -236,7 +238,7 @@
chipid[1] = mmio_read_32(EFUSE_BASEADDR + EFUSE_IPDISABLE_OFFSET);
#else
if (pm_get_chipid(chipid) != PM_RET_SUCCESS)
- return "UNKN";
+ return "XCZUUNKN";
#endif
id = chipid[0] & (ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
@@ -250,8 +252,13 @@
break;
}
- if (i >= ARRAY_SIZE(zynqmp_devices))
- return "UNKN";
+ if (i >= ARRAY_SIZE(zynqmp_devices)) {
+ if (chipid[0] == SILICON_ID_XCK26) {
+ return "XCK26";
+ } else {
+ return "XCZUUNKN";
+ }
+ }
if (!zynqmp_devices[i].evexists)
return zynqmp_devices[i].name;
@@ -327,7 +334,7 @@
break;
}
- NOTICE("ATF running on XCZU%s/%s v%d/RTL%d.%d at 0x%x\n",
+ NOTICE("TF-A running on %s/%s v%d/RTL%d.%d at 0x%x\n",
zynqmp_print_silicon_idcode(), label, zynqmp_get_ps_ver(),
(rtl & 0xf0) >> 4, rtl & 0xf, BL31_BASE);
}
diff --git a/plat/xilinx/zynqmp/include/platform_def.h b/plat/xilinx/zynqmp/include/platform_def.h
index 2796840..143385d 100644
--- a/plat/xilinx/zynqmp/include/platform_def.h
+++ b/plat/xilinx/zynqmp/include/platform_def.h
@@ -36,7 +36,7 @@
* little space for growth.
*/
#ifndef ZYNQMP_ATF_MEM_BASE
-#if !DEBUG && defined(SPD_none)
+#if !DEBUG && defined(SPD_none) && !SDEI_SUPPORT
# define BL31_BASE 0xfffea000
# define BL31_LIMIT 0xffffffff
#else
@@ -91,6 +91,13 @@
#define CACHE_WRITEBACK_SHIFT 6
#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
+#define ZYNQMP_SDEI_SGI_PRIVATE U(8)
+
+/* Platform macros to support exception handling framework */
+#define PLAT_PRI_BITS U(3)
+#define PLAT_SDEI_CRITICAL_PRI 0x10
+#define PLAT_SDEI_NORMAL_PRI 0x20
+
#define PLAT_ARM_GICD_BASE BASE_GICD_BASE
#define PLAT_ARM_GICC_BASE BASE_GICC_BASE
/*
@@ -102,8 +109,6 @@
#define PLAT_ARM_G1S_IRQ_PROPS(grp) \
INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
GIC_INTR_CFG_LEVEL), \
- INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \
- GIC_INTR_CFG_EDGE), \
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \
GIC_INTR_CFG_EDGE), \
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \
@@ -124,8 +129,6 @@
GIC_INTR_CFG_LEVEL), \
INTR_PROP_DESC(IRQ_TTC3_1, GIC_HIGHEST_SEC_PRIORITY, grp, \
GIC_INTR_CFG_EDGE), \
- INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \
- GIC_INTR_CFG_EDGE), \
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \
GIC_INTR_CFG_EDGE), \
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \
@@ -142,6 +145,8 @@
GIC_INTR_CFG_EDGE)
#endif
-#define PLAT_ARM_G0_IRQ_PROPS(grp)
+#define PLAT_ARM_G0_IRQ_PROPS(grp) \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, grp, \
+ GIC_INTR_CFG_EDGE)
#endif /* PLATFORM_DEF_H */
diff --git a/plat/xilinx/zynqmp/platform.mk b/plat/xilinx/zynqmp/platform.mk
index 99a4beb..5e69151 100644
--- a/plat/xilinx/zynqmp/platform.mk
+++ b/plat/xilinx/zynqmp/platform.mk
@@ -14,6 +14,8 @@
override GICV2_G0_FOR_EL3 := 1
override WARMBOOT_ENABLE_DCACHE_EARLY := 1
+EL3_EXCEPTION_HANDLING := $(SDEI_SUPPORT)
+
# Do not enable SVE
ENABLE_SVE_FOR_NS := 0
@@ -107,6 +109,11 @@
plat/xilinx/zynqmp/pm_service/pm_api_clock.c \
plat/xilinx/zynqmp/pm_service/pm_client.c
+ifeq (${SDEI_SUPPORT},1)
+BL31_SOURCES += plat/xilinx/zynqmp/zynqmp_ehf.c \
+ plat/xilinx/zynqmp/zynqmp_sdei.c
+endif
+
BL31_CPPFLAGS += -fno-jump-tables
ifneq (${RESET_TO_BL31},1)
diff --git a/plat/xilinx/zynqmp/zynqmp_ehf.c b/plat/xilinx/zynqmp/zynqmp_ehf.c
new file mode 100644
index 0000000..fbf1ed0
--- /dev/null
+++ b/plat/xilinx/zynqmp/zynqmp_ehf.c
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) Siemens AG, 2020-2021
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <platform_def.h>
+
+#include <bl31/ehf.h>
+
+/*
+ * Enumeration of priority levels on ARM platforms.
+ */
+ehf_pri_desc_t zynqmp_exceptions[] = {
+ /* Critical priority SDEI */
+ EHF_PRI_DESC(PLAT_PRI_BITS, PLAT_SDEI_CRITICAL_PRI),
+
+ /* Normal priority SDEI */
+ EHF_PRI_DESC(PLAT_PRI_BITS, PLAT_SDEI_NORMAL_PRI),
+};
+
+/* Plug in ARM exceptions to Exception Handling Framework. */
+EHF_REGISTER_PRIORITIES(zynqmp_exceptions, ARRAY_SIZE(zynqmp_exceptions), PLAT_PRI_BITS);
diff --git a/plat/xilinx/zynqmp/zynqmp_sdei.c b/plat/xilinx/zynqmp/zynqmp_sdei.c
new file mode 100644
index 0000000..7e92b58
--- /dev/null
+++ b/plat/xilinx/zynqmp/zynqmp_sdei.c
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) Siemens AG, 2020-2021
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/* SDEI configuration for ARM platforms */
+
+#include <bl31/ehf.h>
+#include <common/debug.h>
+#include <services/sdei.h>
+
+#include <plat/common/platform.h>
+#include <platform_def.h>
+
+int arm_validate_ns_entrypoint(uintptr_t entrypoint)
+{
+ return (entrypoint < BL31_BASE || entrypoint > BL31_LIMIT) ? 0 : -1;
+}
+
+/* Private event mappings */
+static sdei_ev_map_t zynqmp_sdei_private[] = {
+ SDEI_DEFINE_EVENT_0(ZYNQMP_SDEI_SGI_PRIVATE),
+};
+
+/* Shared event mappings */
+static sdei_ev_map_t zynqmp_sdei_shared[] = {
+};
+
+void plat_sdei_setup(void)
+{
+ INFO("SDEI platform setup\n");
+}
+
+/* Export ARM SDEI events */
+REGISTER_SDEI_MAP(zynqmp_sdei_private, zynqmp_sdei_shared);
diff --git a/services/std_svc/pci_svc.c b/services/std_svc/pci_svc.c
new file mode 100644
index 0000000..a02b8a7
--- /dev/null
+++ b/services/std_svc/pci_svc.c
@@ -0,0 +1,113 @@
+/*
+ * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <stdint.h>
+
+#include <common/debug.h>
+#include <common/runtime_svc.h>
+#include <services/pci_svc.h>
+#include <services/std_svc.h>
+#include <smccc_helpers.h>
+
+static uint64_t validate_rw_addr_sz(uint32_t addr, uint64_t off, uint64_t sz)
+{
+ uint32_t nseg;
+ uint32_t ret;
+ uint32_t start_end_bus;
+
+ ret = pci_get_bus_for_seg(PCI_ADDR_SEG(addr), &start_end_bus, &nseg);
+
+ if (ret != SMC_PCI_CALL_SUCCESS) {
+ return SMC_PCI_CALL_INVAL_PARAM;
+ }
+ switch (sz) {
+ case SMC_PCI_SZ_8BIT:
+ case SMC_PCI_SZ_16BIT:
+ case SMC_PCI_SZ_32BIT:
+ break;
+ default:
+ return SMC_PCI_CALL_INVAL_PARAM;
+ }
+ if ((off + sz) > (PCI_OFFSET_MASK + 1U)) {
+ return SMC_PCI_CALL_INVAL_PARAM;
+ }
+ return SMC_PCI_CALL_SUCCESS;
+}
+
+uint64_t pci_smc_handler(uint32_t smc_fid,
+ u_register_t x1,
+ u_register_t x2,
+ u_register_t x3,
+ u_register_t x4,
+ void *cookie,
+ void *handle,
+ u_register_t flags)
+{
+ switch (smc_fid) {
+ case SMC_PCI_VERSION: {
+ pcie_version ver;
+
+ ver.major = 1U;
+ ver.minor = 0U;
+ SMC_RET4(handle, ver.val, 0U, 0U, 0U);
+ }
+ case SMC_PCI_FEATURES:
+ switch (x1) {
+ case SMC_PCI_VERSION:
+ case SMC_PCI_FEATURES:
+ case SMC_PCI_READ:
+ case SMC_PCI_WRITE:
+ case SMC_PCI_SEG_INFO:
+ SMC_RET1(handle, SMC_PCI_CALL_SUCCESS);
+ default:
+ SMC_RET1(handle, SMC_PCI_CALL_NOT_SUPPORTED);
+ }
+ break;
+ case SMC_PCI_READ: {
+ uint32_t ret;
+
+ if (validate_rw_addr_sz(x1, x2, x3) != SMC_PCI_CALL_SUCCESS) {
+ SMC_RET2(handle, SMC_PCI_CALL_INVAL_PARAM, 0U);
+ }
+ if (x4 != 0U) {
+ SMC_RET2(handle, SMC_PCI_CALL_INVAL_PARAM, 0U);
+ }
+ if (pci_read_config(x1, x2, x3, &ret) != 0U) {
+ SMC_RET2(handle, SMC_PCI_CALL_INVAL_PARAM, 0U);
+ } else {
+ SMC_RET2(handle, SMC_PCI_CALL_SUCCESS, ret);
+ }
+ break;
+ }
+ case SMC_PCI_WRITE: {
+ uint32_t ret;
+
+ if (validate_rw_addr_sz(x1, x2, x3) != SMC_PCI_CALL_SUCCESS) {
+ SMC_RET1(handle, SMC_PCI_CALL_INVAL_PARAM);
+ }
+ ret = pci_write_config(x1, x2, x3, x4);
+ SMC_RET1(handle, ret);
+ break;
+ }
+ case SMC_PCI_SEG_INFO: {
+ uint32_t nseg;
+ uint32_t ret;
+ uint32_t start_end_bus;
+
+ if ((x2 != 0U) || (x3 != 0U) || (x4 != 0U)) {
+ SMC_RET3(handle, SMC_PCI_CALL_INVAL_PARAM, 0U, 0U);
+ }
+ ret = pci_get_bus_for_seg(x1, &start_end_bus, &nseg);
+ SMC_RET3(handle, ret, start_end_bus, nseg);
+ break;
+ }
+ default:
+ /* should be unreachable */
+ WARN("Unimplemented PCI Service Call: 0x%x\n", smc_fid);
+ SMC_RET1(handle, SMC_PCI_CALL_NOT_SUPPORTED);
+ }
+}
diff --git a/services/std_svc/spmd/spmd_main.c b/services/std_svc/spmd/spmd_main.c
index 06039f0..e18d94c 100644
--- a/services/std_svc/spmd/spmd_main.c
+++ b/services/std_svc/spmd/spmd_main.c
@@ -108,9 +108,10 @@
cm_set_context(&(spmc_ctx->cpu_ctx), SECURE);
/* Restore the context assigned above */
- cm_el1_sysregs_context_restore(SECURE);
#if SPMD_SPM_AT_SEL2
cm_el2_sysregs_context_restore(SECURE);
+#else
+ cm_el1_sysregs_context_restore(SECURE);
#endif
cm_set_next_eret_context(SECURE);
@@ -118,9 +119,10 @@
rc = spmd_spm_core_enter(&spmc_ctx->c_rt_ctx);
/* Save secure state */
- cm_el1_sysregs_context_save(SECURE);
#if SPMD_SPM_AT_SEL2
cm_el2_sysregs_context_save(SECURE);
+#else
+ cm_el1_sysregs_context_save(SECURE);
#endif
return rc;
@@ -346,15 +348,23 @@
unsigned int secure_state_out = (!secure_origin) ? SECURE : NON_SECURE;
/* Save incoming security state */
- cm_el1_sysregs_context_save(secure_state_in);
#if SPMD_SPM_AT_SEL2
+ if (secure_state_in == NON_SECURE) {
+ cm_el1_sysregs_context_save(secure_state_in);
+ }
cm_el2_sysregs_context_save(secure_state_in);
+#else
+ cm_el1_sysregs_context_save(secure_state_in);
#endif
/* Restore outgoing security state */
- cm_el1_sysregs_context_restore(secure_state_out);
#if SPMD_SPM_AT_SEL2
+ if (secure_state_out == NON_SECURE) {
+ cm_el1_sysregs_context_restore(secure_state_out);
+ }
cm_el2_sysregs_context_restore(secure_state_out);
+#else
+ cm_el1_sysregs_context_restore(secure_state_out);
#endif
cm_set_next_eret_context(secure_state_out);
diff --git a/services/std_svc/std_svc_setup.c b/services/std_svc/std_svc_setup.c
index 23f13ab..1917d0a 100644
--- a/services/std_svc/std_svc_setup.c
+++ b/services/std_svc/std_svc_setup.c
@@ -13,6 +13,7 @@
#include <lib/pmf/pmf.h>
#include <lib/psci/psci.h>
#include <lib/runtime_instr.h>
+#include <services/pci_svc.h>
#include <services/sdei.h>
#include <services/spm_mm_svc.h>
#include <services/spmd_svc.h>
@@ -82,6 +83,15 @@
void *handle,
u_register_t flags)
{
+ if (((smc_fid >> FUNCID_CC_SHIFT) & FUNCID_CC_MASK) == SMC_32) {
+ /* 32-bit SMC function, clear top parameter bits */
+
+ x1 &= UINT32_MAX;
+ x2 &= UINT32_MAX;
+ x3 &= UINT32_MAX;
+ x4 &= UINT32_MAX;
+ }
+
/*
* Dispatch PSCI calls to PSCI SMC handler and return its return
* value
@@ -149,6 +159,13 @@
}
#endif
+#if SMC_PCI_SUPPORT
+ if (is_pci_fid(smc_fid)) {
+ return pci_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle,
+ flags);
+ }
+#endif
+
switch (smc_fid) {
case ARM_STD_SVC_CALL_COUNT:
/*
@@ -166,7 +183,7 @@
SMC_RET2(handle, STD_SVC_VERSION_MAJOR, STD_SVC_VERSION_MINOR);
default:
- WARN("Unimplemented Standard Service Call: 0x%x \n", smc_fid);
+ VERBOSE("Unimplemented Standard Service Call: 0x%x \n", smc_fid);
SMC_RET1(handle, SMC_UNK);
}
}