Tegra: smmu: remove context save sequence
SMMU and MC registers are saved as part of the System Suspend sequence.
The register list includes some NS world SMMU registers that need to be
saved by NS world software instead. All that remains as a result are
the MC registers.
This patch moves code to MC file as a result and renames all the
variables and defines to use the MC prefix instead of SMMU. The
Tegra186 and Tegra194 platform ports are updated to provide the MC
context register list to the parent driver. The memory required for
context save is reduced due to removal of the SMMU registers.
Change-Id: I83a05079039f52f9ce91c938ada6cd6dfd9c843f
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
diff --git a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
index c2ef981..a53f660 100644
--- a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
+++ b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
@@ -21,6 +21,7 @@
#include <smmu.h>
#include <tegra_def.h>
#include <tegra_platform.h>
+#include <tegra_private.h>
/* Video Memory base and size (live values) */
static uint64_t video_mem_base;
@@ -223,6 +224,58 @@
mce_update_gsc_tzram();
}
+/*
+ * Save MC settings before "System Suspend" to TZDRAM
+ */
+void tegra_mc_save_context(uint64_t mc_ctx_addr)
+{
+ const tegra_mc_settings_t *plat_mc_settings = tegra_get_mc_settings();
+ uint32_t i, num_entries = 0;
+ mc_regs_t *mc_ctx_regs;
+ const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
+ uint64_t tzdram_base = params_from_bl2->tzdram_base;
+ uint64_t tzdram_end = tzdram_base + params_from_bl2->tzdram_size;
+
+ assert((mc_ctx_addr >= tzdram_base) && (mc_ctx_addr <= tzdram_end));
+
+ /* get MC context table */
+ mc_ctx_regs = plat_mc_settings->get_mc_system_suspend_ctx();
+ assert(mc_ctx_regs != NULL);
+
+ /*
+ * mc_ctx_regs[0].val contains the size of the context table minus
+ * the last entry. Sanity check the table size before we start with
+ * the context save operation.
+ */
+ while (mc_ctx_regs[num_entries].reg != 0xFFFFFFFFU) {
+ num_entries++;
+ }
+
+ /* panic if the sizes do not match */
+ if (num_entries != mc_ctx_regs[0].val) {
+ ERROR("MC context size mismatch!");
+ panic();
+ }
+
+ /* save MC register values */
+ for (i = 1U; i < num_entries; i++) {
+ mc_ctx_regs[i].val = mmio_read_32(mc_ctx_regs[i].reg);
+ }
+
+ /* increment by 1 to take care of the last entry */
+ num_entries++;
+
+ /* Save MC config settings */
+ (void)memcpy((void *)mc_ctx_addr, mc_ctx_regs,
+ sizeof(mc_regs_t) * num_entries);
+
+ /* save the MC table address */
+ mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_MC_TABLE_ADDR_LO,
+ (uint32_t)mc_ctx_addr);
+ mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_MC_TABLE_ADDR_HI,
+ (uint32_t)(mc_ctx_addr >> 32));
+}
+
static void tegra_lock_videomem_nonoverlap(uint64_t phys_base,
uint64_t size_in_bytes)
{
diff --git a/plat/nvidia/tegra/common/drivers/smmu/smmu.c b/plat/nvidia/tegra/common/drivers/smmu/smmu.c
index 8c1b899..cc07d65 100644
--- a/plat/nvidia/tegra/common/drivers/smmu/smmu.c
+++ b/plat/nvidia/tegra/common/drivers/smmu/smmu.c
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -71,67 +72,8 @@
#endif
}
-/*
- * Save SMMU settings before "System Suspend" to TZDRAM
- */
-void tegra_smmu_save_context(uint64_t smmu_ctx_addr)
-{
- uint32_t i, num_entries = 0;
- smmu_regs_t *smmu_ctx_regs;
- const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
- uint64_t tzdram_base = params_from_bl2->tzdram_base;
- uint64_t tzdram_end = tzdram_base + params_from_bl2->tzdram_size;
- uint32_t reg_id1, pgshift, cb_size;
-
- /* sanity check SMMU settings c*/
- reg_id1 = mmio_read_32((TEGRA_SMMU0_BASE + SMMU_GNSR0_IDR1));
- pgshift = ((reg_id1 & ID1_PAGESIZE) != 0U) ? 16U : 12U;
- cb_size = ((uint32_t)2 << pgshift) * \
- ((uint32_t)1 << (((reg_id1 >> ID1_NUMPAGENDXB_SHIFT) & ID1_NUMPAGENDXB_MASK) + 1U));
-
- assert(!((pgshift != PGSHIFT) || (cb_size != CB_SIZE)));
- assert((smmu_ctx_addr >= tzdram_base) && (smmu_ctx_addr <= tzdram_end));
-
- /* get SMMU context table */
- smmu_ctx_regs = plat_get_smmu_ctx();
- assert(smmu_ctx_regs != NULL);
-
- /*
- * smmu_ctx_regs[0].val contains the size of the context table minus
- * the last entry. Sanity check the table size before we start with
- * the context save operation.
- */
- while ((smmu_ctx_regs[num_entries].reg != 0xFFFFFFFFU)) {
- num_entries++;
- }
-
- /* panic if the sizes do not match */
- if (num_entries != smmu_ctx_regs[0].val) {
- ERROR("SMMU context size mismatch!");
- panic();
- }
-
- /* save SMMU register values */
- for (i = 1U; i < num_entries; i++) {
- smmu_ctx_regs[i].val = mmio_read_32(smmu_ctx_regs[i].reg);
- }
-
- /* increment by 1 to take care of the last entry */
- num_entries++;
-
- /* Save SMMU config settings */
- (void)memcpy16((uint8_t *)smmu_ctx_addr, (uint8_t *)smmu_ctx_regs,
- (sizeof(smmu_regs_t) * num_entries));
-
- /* save the SMMU table address */
- mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_SMMU_TABLE_ADDR_LO,
- (uint32_t)smmu_ctx_addr);
- mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_SMMU_TABLE_ADDR_HI,
- (uint32_t)(smmu_ctx_addr >> 32));
-}
-
-#define SMMU_NUM_CONTEXTS 64
-#define SMMU_CONTEXT_BANK_MAX_IDX 64
+#define SMMU_NUM_CONTEXTS 64U
+#define SMMU_CONTEXT_BANK_MAX_IDX 64U
/*
* Init SMMU during boot or "System Suspend" exit