| commit | 74dde09a822f9bb9853e781e537a56df1da2ee96 | [log] [tgz] |
|---|---|---|
| author | Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com> | Mon Sep 09 10:24:35 2024 +0300 |
| committer | Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com> | Mon Sep 30 14:16:00 2024 +0300 |
| tree | 1f07f0b1a5b4bbff63ef275419977473ef8cf168 | |
| parent | f7dd84a54d73ab84a5aac5772427cc8d18ab50bf [diff] |
feat(nxp-clk): setup the DDR PLL Add the DDR PLL instance and configure it to operate at its maximum allowed frequency. Change-Id: I96efd68687de78f70759f631d10a0f611c234c8d Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
diff --git a/include/drivers/nxp/clk/s32cc/s32cc-clk-ids.h b/include/drivers/nxp/clk/s32cc/s32cc-clk-ids.h index de633ae..32287cf 100644 --- a/include/drivers/nxp/clk/s32cc/s32cc-clk-ids.h +++ b/include/drivers/nxp/clk/s32cc/s32cc-clk-ids.h
@@ -95,4 +95,8 @@ #define S32CC_CLK_LINFLEX_BAUD S32CC_ARCH_CLK(16) #define S32CC_CLK_LINFLEX S32CC_ARCH_CLK(17) +/* DDR PLL */ +#define S32CC_CLK_DDR_PLL_MUX S32CC_ARCH_CLK(18) +#define S32CC_CLK_DDR_PLL_VCO S32CC_ARCH_CLK(19) + #endif /* S32CC_CLK_IDS_H */
diff --git a/include/drivers/nxp/clk/s32cc/s32cc-clk-modules.h b/include/drivers/nxp/clk/s32cc/s32cc-clk-modules.h index acad3cd..26d2782 100644 --- a/include/drivers/nxp/clk/s32cc/s32cc-clk-modules.h +++ b/include/drivers/nxp/clk/s32cc/s32cc-clk-modules.h
@@ -36,6 +36,7 @@ S32CC_PERIPH_PLL, S32CC_CGM0, S32CC_CGM1, + S32CC_DDR_PLL, }; struct s32cc_clk_obj {