diff --git a/drivers/nxp/clk/s32cc/include/s32cc-clk-regs.h b/drivers/nxp/clk/s32cc/include/s32cc-clk-regs.h
index 84e76f7..f49f875 100644
--- a/drivers/nxp/clk/s32cc/include/s32cc-clk-regs.h
+++ b/drivers/nxp/clk/s32cc/include/s32cc-clk-regs.h
@@ -13,6 +13,7 @@
 #define ARM_DFS_BASE_ADDR		(0x40054000UL)
 #define CGM0_BASE_ADDR			(0x40030000UL)
 #define CGM1_BASE_ADDR			(0x40034000UL)
+#define DDRPLL_BASE_ADDR		(0x40044000UL)
 
 /* FXOSC */
 #define FXOSC_CTRL(FXOSC)		((FXOSC) + 0x0UL)
diff --git a/drivers/nxp/clk/s32cc/s32cc_clk_drv.c b/drivers/nxp/clk/s32cc/s32cc_clk_drv.c
index 14b03d9..009bd6b 100644
--- a/drivers/nxp/clk/s32cc/s32cc_clk_drv.c
+++ b/drivers/nxp/clk/s32cc/s32cc_clk_drv.c
@@ -26,6 +26,7 @@
 	uintptr_t armdfs_base;
 	uintptr_t cgm0_base;
 	uintptr_t cgm1_base;
+	uintptr_t ddrpll_base;
 };
 
 static int update_stack_depth(unsigned int *depth)
@@ -47,6 +48,7 @@
 		.armdfs_base = ARM_DFS_BASE_ADDR,
 		.cgm0_base = CGM0_BASE_ADDR,
 		.cgm1_base = CGM1_BASE_ADDR,
+		.ddrpll_base = DDRPLL_BASE_ADDR,
 	};
 
 	return &driver;
@@ -86,6 +88,9 @@
 	case S32CC_PERIPH_PLL:
 		*base = drv->periphpll_base;
 		break;
+	case S32CC_DDR_PLL:
+		*base = drv->ddrpll_base;
+		break;
 	case S32CC_ARM_DFS:
 		*base = drv->armdfs_base;
 		break;
@@ -585,6 +590,7 @@
 	/* PLL mux will be enabled by PLL setup */
 	case S32CC_ARM_PLL:
 	case S32CC_PERIPH_PLL:
+	case S32CC_DDR_PLL:
 		break;
 	case S32CC_CGM1:
 		ret = enable_cgm_mux(mux, drv);
diff --git a/drivers/nxp/clk/s32cc/s32cc_early_clks.c b/drivers/nxp/clk/s32cc/s32cc_early_clks.c
index 3f6d3d7..512ee55 100644
--- a/drivers/nxp/clk/s32cc/s32cc_early_clks.c
+++ b/drivers/nxp/clk/s32cc/s32cc_early_clks.c
@@ -16,6 +16,8 @@
 #define S32CC_XBAR_2X_FREQ		(800U * MHZ)
 #define S32CC_PERIPH_PLL_VCO_FREQ	(2U * GHZ)
 #define S32CC_PERIPH_PLL_PHI3_FREQ	UART_CLOCK_HZ
+#define S32CC_DDR_PLL_VCO_FREQ		(1600U * MHZ)
+#define S32CC_DDR_PLL_PHI0_FREQ		(800U * MHZ)
 
 static int setup_fxosc(void)
 {
@@ -139,6 +141,28 @@
 	return ret;
 }
 
+static int setup_ddr_pll(void)
+{
+	int ret;
+
+	ret = clk_set_parent(S32CC_CLK_DDR_PLL_MUX, S32CC_CLK_FXOSC);
+	if (ret != 0) {
+		return ret;
+	}
+
+	ret = clk_set_rate(S32CC_CLK_DDR_PLL_VCO, S32CC_DDR_PLL_VCO_FREQ, NULL);
+	if (ret != 0) {
+		return ret;
+	}
+
+	ret = clk_set_rate(S32CC_CLK_DDR_PLL_PHI0, S32CC_DDR_PLL_PHI0_FREQ, NULL);
+	if (ret != 0) {
+		return ret;
+	}
+
+	return ret;
+}
+
 int s32cc_init_early_clks(void)
 {
 	int ret;
@@ -175,5 +199,10 @@
 		return ret;
 	}
 
+	ret = setup_ddr_pll();
+	if (ret != 0) {
+		return ret;
+	}
+
 	return ret;
 }