tree 53c39f4bc2de077ae2449011777bffc636964f30
parent 5b88852f5418341963501b8d2ad1cc16c28d3b0d
author Soby Mathew <soby.mathew@arm.com> 1452866737 +0000
committer Soby Mathew <soby.mathew@arm.com> 1455036636 +0000

Fix race in GIC IPRIORITY and ITARGET accessors

GICD_IPRIORITYR and GICD_ITARGETSR specifically support byte addressing
so that individual interrupt priorities can be atomically updated by
issuing a single byte write. The previous implementation of
gicd_set_ipriority() and gicd_set_itargetsr() used 32-bit register
accesses, modifying values for 4 interrupts at a time, using a
read-modify-write approach. This potentially may cause concurrent changes
by other CPUs to the adjacent interrupts to be corrupted. This patch fixes
the issue by modifying these accessors to use byte addressing.

Fixes ARM-software/tf-issues#343

Change-Id: Iec28b5f5074045b00dfb8d5f5339b685f9425915