Merge pull request #1725 from Yann-lms/clang_aarch32
clang: 32 bit compilation should include march32-directive
diff --git a/.gitignore b/.gitignore
index 562f812..341308c 100644
--- a/.gitignore
+++ b/.gitignore
@@ -21,10 +21,12 @@
tools/cert_create/src/**/*.o
tools/cert_create/cert_create
tools/cert_create/cert_create.exe
-tools/doimage/doimage
+tools/marvell/doimage/doimage
tools/stm32image/*.o
tools/stm32image/stm32image
tools/stm32image/stm32image.exe
+tools/sptool/sptool
+tools/sptool/sptool.exe
# GNU GLOBAL files
GPATH
diff --git a/Makefile b/Makefile
index 50fdf89..1b48fe1 100644
--- a/Makefile
+++ b/Makefile
@@ -154,7 +154,7 @@
march32-directive = -march=armv8-a
endif
-ifeq ($(notdir $(CC)),armclang)
+ifneq ($(findstring armclang,$(notdir $(CC))),)
TF_CFLAGS_aarch32 = -target arm-arm-none-eabi $(march32-directive)
TF_CFLAGS_aarch64 = -target aarch64-arm-none-eabi -march=armv8-a
LD = $(LINKER)
@@ -880,7 +880,7 @@
.PHONY: libraries
romlib.bin: libraries
- ${Q}${MAKE} BUILD_PLAT=${BUILD_PLAT} INCLUDES='${INCLUDES}' DEFINES='${DEFINES}' --no-print-directory -C ${ROMLIBPATH} all
+ ${Q}${MAKE} PLAT_DIR=${PLAT_DIR} BUILD_PLAT=${BUILD_PLAT} INCLUDES='${INCLUDES}' DEFINES='${DEFINES}' --no-print-directory -C ${ROMLIBPATH} all
cscope:
@echo " CSCOPE"
diff --git a/include/lib/aarch32/arch_helpers.h b/include/lib/aarch32/arch_helpers.h
index 7d1944c..a6fe14f 100644
--- a/include/lib/aarch32/arch_helpers.h
+++ b/include/lib/aarch32/arch_helpers.h
@@ -248,6 +248,19 @@
DEFINE_COPROCR_RW_FUNCS(cnthp_tval_el2, CNTHP_TVAL)
DEFINE_COPROCR_RW_FUNCS_64(cnthp_cval_el2, CNTHP_CVAL_64)
+#define get_cntp_ctl_enable(x) (((x) >> CNTP_CTL_ENABLE_SHIFT) & \
+ CNTP_CTL_ENABLE_MASK)
+#define get_cntp_ctl_imask(x) (((x) >> CNTP_CTL_IMASK_SHIFT) & \
+ CNTP_CTL_IMASK_MASK)
+#define get_cntp_ctl_istatus(x) (((x) >> CNTP_CTL_ISTATUS_SHIFT) & \
+ CNTP_CTL_ISTATUS_MASK)
+
+#define set_cntp_ctl_enable(x) ((x) |= U(1) << CNTP_CTL_ENABLE_SHIFT)
+#define set_cntp_ctl_imask(x) ((x) |= U(1) << CNTP_CTL_IMASK_SHIFT)
+
+#define clr_cntp_ctl_enable(x) ((x) &= ~(U(1) << CNTP_CTL_ENABLE_SHIFT))
+#define clr_cntp_ctl_imask(x) ((x) &= ~(U(1) << CNTP_CTL_IMASK_SHIFT))
+
DEFINE_COPROCR_RW_FUNCS(icc_sre_el1, ICC_SRE)
DEFINE_COPROCR_RW_FUNCS(icc_sre_el2, ICC_HSRE)
DEFINE_COPROCR_RW_FUNCS(icc_sre_el3, ICC_MSRE)
@@ -378,4 +391,59 @@
#define read_amcntenset0_el0() read_amcntenset0()
#define read_amcntenset1_el0() read_amcntenset1()
+/* Helper functions to manipulate CPSR */
+static inline void enable_irq(void)
+{
+ /*
+ * The compiler memory barrier will prevent the compiler from
+ * scheduling non-volatile memory access after the write to the
+ * register.
+ *
+ * This could happen if some initialization code issues non-volatile
+ * accesses to an area used by an interrupt handler, in the assumption
+ * that it is safe as the interrupts are disabled at the time it does
+ * that (according to program order). However, non-volatile accesses
+ * are not necessarily in program order relatively with volatile inline
+ * assembly statements (and volatile accesses).
+ */
+ COMPILER_BARRIER();
+ __asm__ volatile ("cpsie i");
+ isb();
+}
+
+static inline void enable_serror(void)
+{
+ COMPILER_BARRIER();
+ __asm__ volatile ("cpsie a");
+ isb();
+}
+
+static inline void enable_fiq(void)
+{
+ COMPILER_BARRIER();
+ __asm__ volatile ("cpsie f");
+ isb();
+}
+
+static inline void disable_irq(void)
+{
+ COMPILER_BARRIER();
+ __asm__ volatile ("cpsid i");
+ isb();
+}
+
+static inline void disable_serror(void)
+{
+ COMPILER_BARRIER();
+ __asm__ volatile ("cpsid a");
+ isb();
+}
+
+static inline void disable_fiq(void)
+{
+ COMPILER_BARRIER();
+ __asm__ volatile ("cpsid f");
+ isb();
+}
+
#endif /* ARCH_HELPERS_H */
diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h
index 97595e9..6f81e1b 100644
--- a/include/lib/aarch64/arch.h
+++ b/include/lib/aarch64/arch.h
@@ -534,19 +534,6 @@
#define CNTP_CTL_IMASK_MASK U(1)
#define CNTP_CTL_ISTATUS_MASK U(1)
-#define get_cntp_ctl_enable(x) (((x) >> CNTP_CTL_ENABLE_SHIFT) & \
- CNTP_CTL_ENABLE_MASK)
-#define get_cntp_ctl_imask(x) (((x) >> CNTP_CTL_IMASK_SHIFT) & \
- CNTP_CTL_IMASK_MASK)
-#define get_cntp_ctl_istatus(x) (((x) >> CNTP_CTL_ISTATUS_SHIFT) & \
- CNTP_CTL_ISTATUS_MASK)
-
-#define set_cntp_ctl_enable(x) ((x) |= (U(1) << CNTP_CTL_ENABLE_SHIFT))
-#define set_cntp_ctl_imask(x) ((x) |= (U(1) << CNTP_CTL_IMASK_SHIFT))
-
-#define clr_cntp_ctl_enable(x) ((x) &= ~(U(1) << CNTP_CTL_ENABLE_SHIFT))
-#define clr_cntp_ctl_imask(x) ((x) &= ~(U(1) << CNTP_CTL_IMASK_SHIFT))
-
/* Exception Syndrome register bits and bobs */
#define ESR_EC_SHIFT U(26)
#define ESR_EC_MASK U(0x3f)
diff --git a/include/lib/aarch64/arch_helpers.h b/include/lib/aarch64/arch_helpers.h
index 8b3d53a..7222b9d 100644
--- a/include/lib/aarch64/arch_helpers.h
+++ b/include/lib/aarch64/arch_helpers.h
@@ -215,11 +215,81 @@
DEFINE_SYSOP_TYPE_FUNC(dmb, ish)
DEFINE_SYSOP_FUNC(isb)
+static inline void enable_irq(void)
+{
+ /*
+ * The compiler memory barrier will prevent the compiler from
+ * scheduling non-volatile memory access after the write to the
+ * register.
+ *
+ * This could happen if some initialization code issues non-volatile
+ * accesses to an area used by an interrupt handler, in the assumption
+ * that it is safe as the interrupts are disabled at the time it does
+ * that (according to program order). However, non-volatile accesses
+ * are not necessarily in program order relatively with volatile inline
+ * assembly statements (and volatile accesses).
+ */
+ COMPILER_BARRIER();
+ write_daifclr(DAIF_IRQ_BIT);
+ isb();
+}
+
+static inline void enable_fiq(void)
+{
+ COMPILER_BARRIER();
+ write_daifclr(DAIF_FIQ_BIT);
+ isb();
+}
+
+static inline void enable_serror(void)
+{
+ COMPILER_BARRIER();
+ write_daifclr(DAIF_ABT_BIT);
+ isb();
+}
+
+static inline void enable_debug_exceptions(void)
+{
+ COMPILER_BARRIER();
+ write_daifclr(DAIF_DBG_BIT);
+ isb();
+}
+
+static inline void disable_irq(void)
+{
+ COMPILER_BARRIER();
+ write_daifset(DAIF_IRQ_BIT);
+ isb();
+}
+
+static inline void disable_fiq(void)
+{
+ COMPILER_BARRIER();
+ write_daifset(DAIF_FIQ_BIT);
+ isb();
+}
+
+static inline void disable_serror(void)
+{
+ COMPILER_BARRIER();
+ write_daifset(DAIF_ABT_BIT);
+ isb();
+}
+
+static inline void disable_debug_exceptions(void)
+{
+ COMPILER_BARRIER();
+ write_daifset(DAIF_DBG_BIT);
+ isb();
+}
+
+#if !ERROR_DEPRECATED
uint32_t get_afflvl_shift(uint32_t);
uint32_t mpidr_mask_lower_afflvls(uint64_t, uint32_t);
void __dead2 eret(uint64_t x0, uint64_t x1, uint64_t x2, uint64_t x3,
uint64_t x4, uint64_t x5, uint64_t x6, uint64_t x7);
+#endif
void __dead2 smc(uint64_t x0, uint64_t x1, uint64_t x2, uint64_t x3,
uint64_t x4, uint64_t x5, uint64_t x6, uint64_t x7);
@@ -306,6 +376,19 @@
DEFINE_SYSREG_READ_FUNC(cntpct_el0)
DEFINE_SYSREG_RW_FUNCS(cnthctl_el2)
+#define get_cntp_ctl_enable(x) (((x) >> CNTP_CTL_ENABLE_SHIFT) & \
+ CNTP_CTL_ENABLE_MASK)
+#define get_cntp_ctl_imask(x) (((x) >> CNTP_CTL_IMASK_SHIFT) & \
+ CNTP_CTL_IMASK_MASK)
+#define get_cntp_ctl_istatus(x) (((x) >> CNTP_CTL_ISTATUS_SHIFT) & \
+ CNTP_CTL_ISTATUS_MASK)
+
+#define set_cntp_ctl_enable(x) ((x) |= (U(1) << CNTP_CTL_ENABLE_SHIFT))
+#define set_cntp_ctl_imask(x) ((x) |= (U(1) << CNTP_CTL_IMASK_SHIFT))
+
+#define clr_cntp_ctl_enable(x) ((x) &= ~(U(1) << CNTP_CTL_ENABLE_SHIFT))
+#define clr_cntp_ctl_imask(x) ((x) &= ~(U(1) << CNTP_CTL_IMASK_SHIFT))
+
DEFINE_SYSREG_RW_FUNCS(tpidr_el3)
DEFINE_SYSREG_RW_FUNCS(cntvoff_el2)
diff --git a/lib/aarch64/misc_helpers.S b/lib/aarch64/misc_helpers.S
index 002942e..8920f72 100644
--- a/lib/aarch64/misc_helpers.S
+++ b/lib/aarch64/misc_helpers.S
@@ -9,9 +9,11 @@
#include <assert_macros.S>
#include <xlat_tables_defs.h>
+#if !ERROR_DEPRECATED
.globl get_afflvl_shift
.globl mpidr_mask_lower_afflvls
.globl eret
+#endif /* ERROR_DEPRECATED */
.globl smc
.globl zero_normalmem
@@ -30,6 +32,7 @@
.globl enable_vfp
#endif
+#if !ERROR_DEPRECATED
func get_afflvl_shift
cmp x0, #3
cinc x0, x0, eq
@@ -52,7 +55,7 @@
func eret
eret
endfunc eret
-
+#endif /* ERROR_DEPRECATED */
func smc
smc #0
diff --git a/lib/romlib/Makefile b/lib/romlib/Makefile
index 00dde31..0e5d447 100644
--- a/lib/romlib/Makefile
+++ b/lib/romlib/Makefile
@@ -60,11 +60,16 @@
$(LIB_DIR)/libwrappers.a: jmptbl.i $(WRAPPER_DIR)/jmpvar.o
@echo " AR $@"
- $(Q)./genwrappers.sh -b $(WRAPPER_DIR) -o $@ jmptbl.i
+ $(Q)./genwrappers.sh -b $(WRAPPER_DIR) -o $@ $(BUILD_DIR)/jmptbl.i
$(BUILD_DIR)/jmptbl.s: jmptbl.i
@echo " TBL $@"
- $(Q)./gentbl.sh -o $@ jmptbl.i
+ if [ -e "../../$(PLAT_DIR)/jmptbl.i" ] ; \
+ then \
+ $(Q)./gentbl.sh -o $@ -b $(BUILD_DIR) ../../$(PLAT_DIR)/jmptbl.i; \
+ else \
+ @echo "USE_ROMLIB=1 requires jump table list file: jmptbl.i in platform directory"; \
+ fi
clean:
@rm -f $(BUILD_DIR)/*
diff --git a/lib/romlib/gentbl.sh b/lib/romlib/gentbl.sh
index 0695f6e..e64cfe2 100755
--- a/lib/romlib/gentbl.sh
+++ b/lib/romlib/gentbl.sh
@@ -6,6 +6,7 @@
set -e
output=jmptbl.s
+build=.
for i
do
@@ -14,27 +15,45 @@
output=$2
shift 2
;;
+ -b)
+ build=$2
+ shift 2
+ ;;
--)
shift
break
;;
-*)
- echo usage: gentbl.sh [-o output] file ... >&2
+ echo usage: gentbl.sh [-o output] [-b dir] file ... >&2
exit 1
;;
esac
done
tmp=`mktemp`
-trap "rm -f $tmp" EXIT INT QUIT
-
+trap "rm -f $$.tmp" EXIT INT QUIT
rm -f $output
+# Pre-process include files
+awk '!/^$/ && !/[:blank:]*#.*/{
+if (NF == 2 && $1 == "include") {
+ while ((getline line < $2) > 0)
+ if (line !~ /^$/ && line !~ /[:blank:]*#.*/)
+ print line
+ close($2)
+} else
+ print
+}' "$@" |
+awk -v OFS="\t" '
+BEGIN{print "#index\tlib\tfunction\t[patch]"}
+{print NR-1, $0}' | tee $build/jmptbl.i |
awk -v OFS="\n" '
BEGIN {print "\t.text",
"\t.globl\tjmptbl",
"jmptbl:"}
{sub(/[:blank:]*#.*/,"")}
-!/^$/ {print "\tb\t" $3}' "$@" > $tmp
-
-mv $tmp $output
+!/^$/ {if ($3 == "reserved")
+ print "\t.word\t0x0"
+ else
+ print "\tb\t" $3}' > $$.tmp &&
+mv $$.tmp $output
diff --git a/lib/romlib/genwrappers.sh b/lib/romlib/genwrappers.sh
index 48ee5a4..746e4ba 100755
--- a/lib/romlib/genwrappers.sh
+++ b/lib/romlib/genwrappers.sh
@@ -31,7 +31,7 @@
done
awk '{sub(/[:blank:]*#.*/,"")}
-!/^$/ && !/\\tpatch$/ {print $1*4, $2, $3}' "$@" |
+!/^$/ && !/\\tpatch$/ !/\\treserved$/ {print $1*4, $2, $3}' "$@" |
while read idx lib sym
do
file=$build/${lib}_$sym
diff --git a/lib/romlib/jmptbl.i b/lib/romlib/jmptbl.i
index 5eca5aa..a7280d0 100644
--- a/lib/romlib/jmptbl.i
+++ b/lib/romlib/jmptbl.i
@@ -4,37 +4,40 @@
# SPDX-License-Identifier: BSD-3-Clause
#
# Format:
-# index lib function [patch]
+# lib function [patch]
# Add "patch" at the end of the line to patch a function. For example:
-# 14 mbedtls mbedtls_memory_buffer_alloc_init patch
+# mbedtls mbedtls_memory_buffer_alloc_init patch
+# Holes can be introduced in the table by using a special keyword "reserved".
+# Example:
+# reserved reserved
+# The jump table will contain an invalid instruction instead of branch
-0 rom rom_lib_init
-1 fdt fdt_getprop_namelen
-2 fdt fdt_setprop_inplace
-3 fdt fdt_check_header
-4 fdt fdt_node_offset_by_compatible
-5 mbedtls mbedtls_asn1_get_alg
-6 mbedtls mbedtls_asn1_get_alg_null
-7 mbedtls mbedtls_asn1_get_bitstring_null
-8 mbedtls mbedtls_asn1_get_bool
-9 mbedtls mbedtls_asn1_get_int
-10 mbedtls mbedtls_asn1_get_tag
-11 mbedtls mbedtls_free
-12 mbedtls mbedtls_md
-13 mbedtls mbedtls_md_get_size
-14 mbedtls mbedtls_memory_buffer_alloc_init
-15 mbedtls mbedtls_oid_get_md_alg
-16 mbedtls mbedtls_oid_get_numeric_string
-17 mbedtls mbedtls_oid_get_pk_alg
-18 mbedtls mbedtls_oid_get_sig_alg
-19 mbedtls mbedtls_pk_free
-20 mbedtls mbedtls_pk_init
-21 mbedtls mbedtls_pk_parse_subpubkey
-22 mbedtls mbedtls_pk_verify_ext
-23 mbedtls mbedtls_platform_set_calloc_free
-24 mbedtls mbedtls_platform_set_snprintf
-25 mbedtls mbedtls_x509_get_rsassa_pss_params
-26 mbedtls mbedtls_x509_get_sig_alg
-27 mbedtls mbedtls_md_info_from_type
-28 c exit
-29 c atexit
\ No newline at end of file
+rom rom_lib_init
+fdt fdt_getprop_namelen
+fdt fdt_setprop_inplace
+fdt fdt_check_header
+fdt fdt_node_offset_by_compatible
+mbedtls mbedtls_asn1_get_alg
+mbedtls mbedtls_asn1_get_alg_null
+mbedtls mbedtls_asn1_get_bitstring_null
+mbedtls mbedtls_asn1_get_bool
+mbedtls mbedtls_asn1_get_int
+mbedtls mbedtls_asn1_get_tag
+mbedtls mbedtls_free
+mbedtls mbedtls_md
+mbedtls mbedtls_md_get_size
+mbedtls mbedtls_memory_buffer_alloc_init
+mbedtls mbedtls_oid_get_md_alg
+mbedtls mbedtls_oid_get_numeric_string
+mbedtls mbedtls_oid_get_pk_alg
+mbedtls mbedtls_oid_get_sig_alg
+mbedtls mbedtls_pk_free
+mbedtls mbedtls_pk_init
+mbedtls mbedtls_pk_parse_subpubkey
+mbedtls mbedtls_pk_verify_ext
+mbedtls mbedtls_platform_set_snprintf
+mbedtls mbedtls_x509_get_rsassa_pss_params
+mbedtls mbedtls_x509_get_sig_alg
+mbedtls mbedtls_md_info_from_type
+c exit
+c atexit
diff --git a/plat/arm/board/fvp/jmptbl.i b/plat/arm/board/fvp/jmptbl.i
new file mode 100644
index 0000000..8d232d5
--- /dev/null
+++ b/plat/arm/board/fvp/jmptbl.i
@@ -0,0 +1,17 @@
+#
+# Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+# Platform specific romlib functions can be added or included here.
+# The index in the output file will be generated cumulatively in the same
+# order as it is given in this file.
+# Output file can be found at: $BUILD_DIR/jmptbl.i
+#
+# Format:
+# lib function [patch]
+# Example:
+# rom rom_lib_init
+# fdt fdt_getprop_namelen patch
+
+include ../../lib/romlib/jmptbl.i
diff --git a/plat/arm/board/juno/jmptbl.i b/plat/arm/board/juno/jmptbl.i
new file mode 100644
index 0000000..8d232d5
--- /dev/null
+++ b/plat/arm/board/juno/jmptbl.i
@@ -0,0 +1,17 @@
+#
+# Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+# Platform specific romlib functions can be added or included here.
+# The index in the output file will be generated cumulatively in the same
+# order as it is given in this file.
+# Output file can be found at: $BUILD_DIR/jmptbl.i
+#
+# Format:
+# lib function [patch]
+# Example:
+# rom rom_lib_init
+# fdt fdt_getprop_namelen patch
+
+include ../../lib/romlib/jmptbl.i
diff --git a/plat/nvidia/tegra/common/tegra_common.mk b/plat/nvidia/tegra/common/tegra_common.mk
index abb9bb8..6a0854e 100644
--- a/plat/nvidia/tegra/common/tegra_common.mk
+++ b/plat/nvidia/tegra/common/tegra_common.mk
@@ -13,15 +13,21 @@
COMMON_DIR := plat/nvidia/tegra/common
-BL31_SOURCES += drivers/console/aarch64/console.S \
+TEGRA_GICv2_SOURCES := drivers/arm/gic/common/gic_common.c \
+ drivers/arm/gic/v2/gicv2_main.c \
+ drivers/arm/gic/v2/gicv2_helpers.c \
+ plat/common/plat_gicv2.c \
+ ${COMMON_DIR}/tegra_gicv2.c
+
+BL31_SOURCES += drivers/console/aarch64/console.S \
drivers/delay_timer/delay_timer.c \
drivers/ti/uart/aarch64/16550_console.S \
+ ${TEGRA_GICv2_SOURCES} \
${COMMON_DIR}/aarch64/tegra_helpers.S \
${COMMON_DIR}/drivers/pmc/pmc.c \
${COMMON_DIR}/tegra_bl31_setup.c \
${COMMON_DIR}/tegra_delay_timer.c \
${COMMON_DIR}/tegra_fiq_glue.c \
- ${COMMON_DIR}/tegra_gic.c \
${COMMON_DIR}/tegra_platform.c \
${COMMON_DIR}/tegra_pm.c \
${COMMON_DIR}/tegra_sip_calls.c \
diff --git a/plat/nvidia/tegra/common/tegra_gic.c b/plat/nvidia/tegra/common/tegra_gic.c
deleted file mode 100644
index c3dc5f6..0000000
--- a/plat/nvidia/tegra/common/tegra_gic.c
+++ /dev/null
@@ -1,321 +0,0 @@
-/*
- * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch_helpers.h>
-#include <assert.h>
-#include <bl_common.h>
-#include <debug.h>
-#include <interrupt_mgmt.h>
-#include <platform.h>
-#include <stdint.h>
-#include <tegra_def.h>
-#include <tegra_private.h>
-
-/* Value used to initialize Non-Secure IRQ priorities four at a time */
-#define GICD_IPRIORITYR_DEF_VAL \
- (GIC_HIGHEST_NS_PRIORITY | \
- (GIC_HIGHEST_NS_PRIORITY << 8) | \
- (GIC_HIGHEST_NS_PRIORITY << 16) | \
- (GIC_HIGHEST_NS_PRIORITY << 24))
-
-static const irq_sec_cfg_t *g_irq_sec_ptr;
-static uint32_t g_num_irqs;
-
-/*******************************************************************************
- * Place the cpu interface in a state where it can never make a cpu exit wfi as
- * as result of an asserted interrupt. This is critical for powering down a cpu
- ******************************************************************************/
-void tegra_gic_cpuif_deactivate(void)
-{
- uint32_t val;
-
- /* Disable secure, non-secure interrupts and disable their bypass */
- val = gicc_read_ctlr(TEGRA_GICC_BASE);
- val &= ~(ENABLE_GRP0 | ENABLE_GRP1);
- val |= FIQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP0;
- val |= IRQ_BYP_DIS_GRP0 | IRQ_BYP_DIS_GRP1;
- gicc_write_ctlr(TEGRA_GICC_BASE, val);
-}
-
-/*******************************************************************************
- * Enable secure interrupts and set the priority mask register to allow all
- * interrupts to trickle in.
- ******************************************************************************/
-static void tegra_gic_cpuif_setup(uint32_t gicc_base)
-{
- uint32_t val;
-
- val = ENABLE_GRP0 | ENABLE_GRP1 | FIQ_EN | FIQ_BYP_DIS_GRP0;
- val |= IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP1 | IRQ_BYP_DIS_GRP1;
-
- gicc_write_ctlr(gicc_base, val);
- gicc_write_pmr(gicc_base, GIC_PRI_MASK);
-}
-
-/*******************************************************************************
- * Per cpu gic distributor setup which will be done by all cpus after a cold
- * boot/hotplug. This marks out the secure interrupts & enables them.
- ******************************************************************************/
-static void tegra_gic_pcpu_distif_setup(uint32_t gicd_base)
-{
- uint32_t index, sec_ppi_sgi_mask = 0;
-
- assert(gicd_base != 0U);
-
- /* Setup PPI priorities doing four at a time */
- for (index = 0U; index < 32U; index += 4U) {
- gicd_write_ipriorityr(gicd_base, index,
- GICD_IPRIORITYR_DEF_VAL);
- }
-
- /*
- * Invert the bitmask to create a mask for non-secure PPIs and
- * SGIs. Program the GICD_IGROUPR0 with this bit mask. This write will
- * update the GICR_IGROUPR0 as well in case we are running on a GICv3
- * system. This is critical if GICD_CTLR.ARE_NS=1.
- */
- gicd_write_igroupr(gicd_base, 0, ~sec_ppi_sgi_mask);
-}
-
-/*******************************************************************************
- * Global gic distributor setup which will be done by the primary cpu after a
- * cold boot. It marks out the non secure SPIs, PPIs & SGIs and enables them.
- * It then enables the secure GIC distributor interface.
- ******************************************************************************/
-static void tegra_gic_distif_setup(uint32_t gicd_base)
-{
- uint32_t index, num_ints, irq_num;
- uint8_t target_cpus;
- uint32_t val;
-
- /*
- * Mark out non-secure interrupts. Calculate number of
- * IGROUPR registers to consider. Will be equal to the
- * number of IT_LINES
- */
- num_ints = gicd_read_typer(gicd_base) & IT_LINES_NO_MASK;
- num_ints = (num_ints + 1U) << 5;
- for (index = MIN_SPI_ID; index < num_ints; index += 32U) {
- gicd_write_igroupr(gicd_base, index, 0xFFFFFFFFU);
- }
-
- /* Setup SPI priorities doing four at a time */
- for (index = MIN_SPI_ID; index < num_ints; index += 4U) {
- gicd_write_ipriorityr(gicd_base, index,
- GICD_IPRIORITYR_DEF_VAL);
- }
-
- /* Configure SPI secure interrupts now */
- if (g_irq_sec_ptr != NULL) {
-
- for (index = 0U; index < g_num_irqs; index++) {
- irq_num = g_irq_sec_ptr[index].irq;
- target_cpus = (uint8_t)g_irq_sec_ptr[index].target_cpus;
-
- if (irq_num >= MIN_SPI_ID) {
-
- /* Configure as a secure interrupt */
- gicd_clr_igroupr(gicd_base, irq_num);
-
- /* Configure SPI priority */
- mmio_write_8((uint64_t)gicd_base +
- (uint64_t)GICD_IPRIORITYR +
- (uint64_t)irq_num,
- GIC_HIGHEST_SEC_PRIORITY &
- GIC_PRI_MASK);
-
- /* Configure as level triggered */
- val = gicd_read_icfgr(gicd_base, irq_num);
- val |= (3U << ((irq_num & 0xFU) << 1U));
- gicd_write_icfgr(gicd_base, irq_num, val);
-
- /* Route SPI to the target CPUs */
- gicd_set_itargetsr(gicd_base, irq_num,
- target_cpus);
-
- /* Enable this interrupt */
- gicd_set_isenabler(gicd_base, irq_num);
- }
- }
- }
-
- /*
- * Configure the SGI and PPI. This is done in a separated function
- * because each CPU is responsible for initializing its own private
- * interrupts.
- */
- tegra_gic_pcpu_distif_setup(gicd_base);
-
- /* enable distributor */
- gicd_write_ctlr(gicd_base, ENABLE_GRP0 | ENABLE_GRP1);
-}
-
-void tegra_gic_setup(const irq_sec_cfg_t *irq_sec_ptr, uint32_t num_irqs)
-{
- g_irq_sec_ptr = irq_sec_ptr;
- g_num_irqs = num_irqs;
-
- tegra_gic_cpuif_setup(TEGRA_GICC_BASE);
- tegra_gic_distif_setup(TEGRA_GICD_BASE);
-}
-
-/*******************************************************************************
- * An ARM processor signals interrupt exceptions through the IRQ and FIQ pins.
- * The interrupt controller knows which pin/line it uses to signal a type of
- * interrupt. This function provides a common implementation of
- * plat_interrupt_type_to_line() in an ARM GIC environment for optional re-use
- * across platforms. It lets the interrupt management framework determine
- * for a type of interrupt and security state, which line should be used in the
- * SCR_EL3 to control its routing to EL3. The interrupt line is represented as
- * the bit position of the IRQ or FIQ bit in the SCR_EL3.
- ******************************************************************************/
-static uint32_t tegra_gic_interrupt_type_to_line(uint32_t type,
- uint32_t security_state)
-{
- assert((type == INTR_TYPE_S_EL1) ||
- (type == INTR_TYPE_EL3) ||
- (type == INTR_TYPE_NS));
-
- assert(sec_state_is_valid(security_state));
-
- /*
- * We ignore the security state parameter under the assumption that
- * both normal and secure worlds are using ARM GICv2. This parameter
- * will be used when the secure world starts using GICv3.
- */
- return gicv2_interrupt_type_to_line(TEGRA_GICC_BASE, type);
-}
-
-/*******************************************************************************
- * This function returns the type of the highest priority pending interrupt at
- * the GIC cpu interface. INTR_TYPE_INVAL is returned when there is no
- * interrupt pending.
- ******************************************************************************/
-static uint32_t tegra_gic_get_pending_interrupt_type(void)
-{
- uint32_t id;
- uint32_t index;
- uint32_t ret = INTR_TYPE_NS;
-
- id = gicc_read_hppir(TEGRA_GICC_BASE) & INT_ID_MASK;
-
- /* get the interrupt type */
- if (id < 1022U) {
- for (index = 0U; index < g_num_irqs; index++) {
- if (id == g_irq_sec_ptr[index].irq) {
- ret = g_irq_sec_ptr[index].type;
- break;
- }
- }
- } else {
- if (id == GIC_SPURIOUS_INTERRUPT) {
- ret = INTR_TYPE_INVAL;
- }
- }
-
- return ret;
-}
-
-/*******************************************************************************
- * This function returns the id of the highest priority pending interrupt at
- * the GIC cpu interface. INTR_ID_UNAVAILABLE is returned when there is no
- * interrupt pending.
- ******************************************************************************/
-static uint32_t tegra_gic_get_pending_interrupt_id(void)
-{
- uint32_t id, ret;
-
- id = gicc_read_hppir(TEGRA_GICC_BASE) & INT_ID_MASK;
-
- if (id < 1022U) {
- ret = id;
- } else if (id == 1023U) {
- ret = 0xFFFFFFFFU; /* INTR_ID_UNAVAILABLE */
- } else {
- /*
- * Find out which non-secure interrupt it is under the assumption that
- * the GICC_CTLR.AckCtl bit is 0.
- */
- ret = gicc_read_ahppir(TEGRA_GICC_BASE) & INT_ID_MASK;
- }
-
- return ret;
-}
-
-/*******************************************************************************
- * This functions reads the GIC cpu interface Interrupt Acknowledge register
- * to start handling the pending interrupt. It returns the contents of the IAR.
- ******************************************************************************/
-static uint32_t tegra_gic_acknowledge_interrupt(void)
-{
- return gicc_read_IAR(TEGRA_GICC_BASE);
-}
-
-/*******************************************************************************
- * This functions writes the GIC cpu interface End Of Interrupt register with
- * the passed value to finish handling the active interrupt
- ******************************************************************************/
-static void tegra_gic_end_of_interrupt(uint32_t id)
-{
- gicc_write_EOIR(TEGRA_GICC_BASE, id);
-}
-
-/*******************************************************************************
- * This function returns the type of the interrupt id depending upon the group
- * this interrupt has been configured under by the interrupt controller i.e.
- * group0 or group1.
- ******************************************************************************/
-static uint32_t tegra_gic_get_interrupt_type(uint32_t id)
-{
- uint32_t group;
- uint32_t index;
- uint32_t ret = INTR_TYPE_NS;
-
- group = gicd_get_igroupr(TEGRA_GICD_BASE, id);
-
- /* get the interrupt type */
- if (group == GRP0) {
- for (index = 0U; index < g_num_irqs; index++) {
- if (id == g_irq_sec_ptr[index].irq) {
- ret = g_irq_sec_ptr[index].type;
- break;
- }
- }
- }
-
- return ret;
-}
-
-uint32_t plat_ic_get_pending_interrupt_id(void)
-{
- return tegra_gic_get_pending_interrupt_id();
-}
-
-uint32_t plat_ic_get_pending_interrupt_type(void)
-{
- return tegra_gic_get_pending_interrupt_type();
-}
-
-uint32_t plat_ic_acknowledge_interrupt(void)
-{
- return tegra_gic_acknowledge_interrupt();
-}
-
-uint32_t plat_ic_get_interrupt_type(uint32_t id)
-{
- return tegra_gic_get_interrupt_type(id);
-}
-
-void plat_ic_end_of_interrupt(uint32_t id)
-{
- tegra_gic_end_of_interrupt(id);
-}
-
-uint32_t plat_interrupt_type_to_line(uint32_t type,
- uint32_t security_state)
-{
- return tegra_gic_interrupt_type_to_line(type, security_state);
-}
diff --git a/plat/nvidia/tegra/common/tegra_gicv2.c b/plat/nvidia/tegra/common/tegra_gicv2.c
new file mode 100644
index 0000000..c42c5ec
--- /dev/null
+++ b/plat/nvidia/tegra/common/tegra_gicv2.c
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <bl_common.h>
+#include <gicv2.h>
+#include <platform_def.h>
+#include <tegra_private.h>
+#include <tegra_def.h>
+#include <utils.h>
+
+/******************************************************************************
+ * Tegra common helper to setup the GICv2 driver data.
+ *****************************************************************************/
+void tegra_gic_setup(const interrupt_prop_t *interrupt_props,
+ unsigned int interrupt_props_num)
+{
+ /*
+ * Tegra GIC configuration settings
+ */
+ static gicv2_driver_data_t tegra_gic_data;
+
+ /*
+ * Register Tegra GICv2 driver
+ */
+ tegra_gic_data.gicd_base = TEGRA_GICD_BASE;
+ tegra_gic_data.gicc_base = TEGRA_GICC_BASE;
+ tegra_gic_data.interrupt_props = interrupt_props;
+ tegra_gic_data.interrupt_props_num = interrupt_props_num;
+ gicv2_driver_init(&tegra_gic_data);
+}
+
+/******************************************************************************
+ * Tegra common helper to initialize the GICv2 only driver.
+ *****************************************************************************/
+void tegra_gic_init(void)
+{
+ gicv2_distif_init();
+ gicv2_pcpu_distif_init();
+ gicv2_cpuif_enable();
+}
+
+/******************************************************************************
+ * Tegra common helper to disable the GICv2 CPU interface
+ *****************************************************************************/
+void tegra_gic_cpuif_deactivate(void)
+{
+ gicv2_cpuif_disable();
+}
+
+/******************************************************************************
+ * Tegra common helper to initialize the per cpu distributor interface
+ * in GICv2
+ *****************************************************************************/
+void tegra_gic_pcpu_init(void)
+{
+ gicv2_pcpu_distif_init();
+ gicv2_cpuif_enable();
+}
diff --git a/plat/nvidia/tegra/include/drivers/tegra_gic.h b/plat/nvidia/tegra/include/drivers/tegra_gic.h
new file mode 100644
index 0000000..2fe316d
--- /dev/null
+++ b/plat/nvidia/tegra/include/drivers/tegra_gic.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __TEGRA_GIC_H__
+#define __TEGRA_GIC_H__
+
+#include <interrupt_props.h>
+
+/*******************************************************************************
+ * Per-CPU struct describing FIQ state to be stored
+ ******************************************************************************/
+typedef struct pcpu_fiq_state {
+ uint64_t elr_el3;
+ uint64_t spsr_el3;
+} pcpu_fiq_state_t;
+
+/*******************************************************************************
+ * Fucntion declarations
+ ******************************************************************************/
+void tegra_gic_cpuif_deactivate(void);
+void tegra_gic_init(void);
+void tegra_gic_pcpu_init(void);
+void tegra_gic_setup(const interrupt_prop_t *interrupt_props,
+ unsigned int interrupt_props_num);
+
+#endif /* __TEGRA_GIC_H__ */
diff --git a/plat/nvidia/tegra/include/plat_macros.S b/plat/nvidia/tegra/include/plat_macros.S
index 14e7d8a..01ae821 100644
--- a/plat/nvidia/tegra/include/plat_macros.S
+++ b/plat/nvidia/tegra/include/plat_macros.S
@@ -7,6 +7,7 @@
#ifndef PLAT_MACROS_S
#define PLAT_MACROS_S
+#include <gicv2.h>
#include <tegra_def.h>
.section .rodata.gic_reg_name, "aS"
diff --git a/plat/nvidia/tegra/include/tegra_private.h b/plat/nvidia/tegra/include/tegra_private.h
index c4c277e..7ca32c3 100644
--- a/plat/nvidia/tegra/include/tegra_private.h
+++ b/plat/nvidia/tegra/include/tegra_private.h
@@ -8,8 +8,10 @@
#define TEGRA_PRIVATE_H
#include <arch.h>
+#include <arch_helpers.h>
#include <platform_def.h>
#include <psci.h>
+#include <tegra_gic.h>
#include <xlat_tables_v2.h>
/*******************************************************************************
@@ -31,26 +33,6 @@
} plat_params_from_bl2_t;
/*******************************************************************************
- * Per-CPU struct describing FIQ state to be stored
- ******************************************************************************/
-typedef struct pcpu_fiq_state {
- uint64_t elr_el3;
- uint64_t spsr_el3;
-} pcpu_fiq_state_t;
-
-/*******************************************************************************
- * Struct describing per-FIQ configuration settings
- ******************************************************************************/
-typedef struct irq_sec_cfg {
- /* IRQ number */
- unsigned int irq;
- /* Target CPUs servicing this interrupt */
- unsigned int target_cpus;
- /* type = INTR_TYPE_S_EL1 or INTR_TYPE_EL3 */
- uint32_t type;
-} irq_sec_cfg_t;
-
-/*******************************************************************************
* Struct describing parameters passed to bl31
******************************************************************************/
struct tegra_bl31_params {
@@ -82,10 +64,6 @@
int tegra_fiq_get_intr_context(void);
void tegra_fiq_set_ns_entrypoint(uint64_t entrypoint);
-/* Declarations for tegra_gic.c */
-void tegra_gic_cpuif_deactivate(void);
-void tegra_gic_setup(const irq_sec_cfg_t *irq_sec_ptr, uint32_t num_irqs);
-
/* Declarations for tegra_security.c */
void tegra_security_setup(void);
void tegra_security_setup_videomem(uintptr_t base, uint64_t size);
diff --git a/plat/nvidia/tegra/soc/t132/platform_t132.mk b/plat/nvidia/tegra/soc/t132/platform_t132.mk
index 8b3d238..f15ee74 100644
--- a/plat/nvidia/tegra/soc/t132/platform_t132.mk
+++ b/plat/nvidia/tegra/soc/t132/platform_t132.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
diff --git a/plat/nvidia/tegra/soc/t186/plat_setup.c b/plat/nvidia/tegra/soc/t186/plat_setup.c
index 233644b..da5530f 100644
--- a/plat/nvidia/tegra/soc/t186/plat_setup.c
+++ b/plat/nvidia/tegra/soc/t186/plat_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -14,7 +14,10 @@
#include <cortex_a57.h>
#include <debug.h>
#include <denver.h>
+#include <gic_common.h>
+#include <gicv2.h>
#include <interrupt_mgmt.h>
+#include <interrupt_props.h>
#include <mce.h>
#include <platform.h>
#include <tegra_def.h>
@@ -185,17 +188,11 @@
}
/* Secure IRQs for Tegra186 */
-static const irq_sec_cfg_t tegra186_sec_irqs[] = {
- {
- TEGRA186_TOP_WDT_IRQ,
- TEGRA186_SEC_IRQ_TARGET_MASK,
- INTR_TYPE_EL3,
- },
- {
- TEGRA186_AON_WDT_IRQ,
- TEGRA186_SEC_IRQ_TARGET_MASK,
- INTR_TYPE_EL3,
- },
+static const interrupt_prop_t tegra186_interrupt_props[] = {
+ INTR_PROP_DESC(TEGRA186_TOP_WDT_IRQ, GIC_HIGHEST_SEC_PRIORITY,
+ GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
+ INTR_PROP_DESC(TEGRA186_AON_WDT_IRQ, GIC_HIGHEST_SEC_PRIORITY,
+ GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE)
};
/*******************************************************************************
@@ -203,14 +200,13 @@
******************************************************************************/
void plat_gic_setup(void)
{
- tegra_gic_setup(tegra186_sec_irqs,
- sizeof(tegra186_sec_irqs) / sizeof(tegra186_sec_irqs[0]));
+ tegra_gic_setup(tegra186_interrupt_props, ARRAY_SIZE(tegra186_interrupt_props));
/*
* Initialize the FIQ handler only if the platform supports any
* FIQ interrupt sources.
*/
- if (sizeof(tegra186_sec_irqs) > 0)
+ if (sizeof(tegra186_interrupt_props) > 0)
tegra_fiq_handler_setup();
}
diff --git a/plat/nvidia/tegra/soc/t210/platform_t210.mk b/plat/nvidia/tegra/soc/t210/platform_t210.mk
index 97ca3f1..b0a474c 100644
--- a/plat/nvidia/tegra/soc/t210/platform_t210.mk
+++ b/plat/nvidia/tegra/soc/t210/platform_t210.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -22,12 +22,12 @@
MAX_MMAP_REGIONS := 8
$(eval $(call add_define,MAX_MMAP_REGIONS))
-BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \
- lib/cpus/aarch64/cortex_a57.S \
+BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \
+ lib/cpus/aarch64/cortex_a57.S \
${COMMON_DIR}/drivers/flowctrl/flowctrl.c \
${COMMON_DIR}/drivers/memctrl/memctrl_v1.c \
- ${SOC_DIR}/plat_psci_handlers.c \
- ${SOC_DIR}/plat_setup.c \
+ ${SOC_DIR}/plat_psci_handlers.c \
+ ${SOC_DIR}/plat_setup.c \
${SOC_DIR}/plat_secondary.c
# Enable workarounds for selected Cortex-A57 erratas.
diff --git a/plat/renesas/rcar/bl2_plat_mem_params_desc.c b/plat/renesas/rcar/bl2_plat_mem_params_desc.c
index 728eac6..3dc9eff 100644
--- a/plat/renesas/rcar/bl2_plat_mem_params_desc.c
+++ b/plat/renesas/rcar/bl2_plat_mem_params_desc.c
@@ -72,7 +72,7 @@
#ifdef RCAR_BL33_ARG0
.ep_info.args.arg0 = RCAR_BL33_ARG0,
#endif
- .ep_info.args.arg3 = (uintptr_t)fdt_blob,
+ .ep_info.args.arg1 = (uintptr_t)fdt_blob,
SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2,
image_info_t, 0),
.image_info.image_max_size =
diff --git a/plat/st/stm32mp1/platform.mk b/plat/st/stm32mp1/platform.mk
index 545b140..8890e82 100644
--- a/plat/st/stm32mp1/platform.mk
+++ b/plat/st/stm32mp1/platform.mk
@@ -83,10 +83,6 @@
plat/st/stm32mp1/plat_bl2_mem_params_desc.c \
plat/st/stm32mp1/plat_image_load.c
-# For memory footprint optimization, build with thumb and interwork support
-ASFLAGS += -mthumb -mthumb-interwork
-TF_CFLAGS += -mthumb -mthumb-interwork
-
# Macros and rules to build TF binary
STM32_TF_ELF_LDFLAGS := --hash-style=gnu --as-needed
STM32_DT_BASENAME := $(STM32_DTB_FILE_NAME:.dtb=)