FWU: Add Firmware Update support in BL1 for ARM platforms
This patch adds Firmware Update support for ARM platforms.
New files arm_bl1_fwu.c and juno_bl1_setup.c were added to provide
platform specific Firmware update code.
BL1 now includes mmap entry for `ARM_MAP_NS_DRAM1` to map DRAM for
authenticating NS_BL2U image(For both FVP and JUNO platform).
Change-Id: Ie116cd83f5dc00aa53d904c2f1beb23d58926555
diff --git a/include/plat/arm/board/common/board_arm_def.h b/include/plat/arm/board/common/board_arm_def.h
index 3abf235..dae5418 100644
--- a/include/plat/arm/board/common/board_arm_def.h
+++ b/include/plat/arm/board/common/board_arm_def.h
@@ -65,10 +65,18 @@
*/
#if IMAGE_BL1
# if PLAT_fvp
-# define PLAT_ARM_MMAP_ENTRIES 7
+# if TRUSTED_BOARD_BOOT
+# define PLAT_ARM_MMAP_ENTRIES 8
+# else
+# define PLAT_ARM_MMAP_ENTRIES 7
+# endif /* TRUSTED_BOARD_BOOT */
# else
-# define PLAT_ARM_MMAP_ENTRIES 6
-# endif
+# if TRUSTED_BOARD_BOOT
+# define PLAT_ARM_MMAP_ENTRIES 7
+# else
+# define PLAT_ARM_MMAP_ENTRIES 6
+# endif /* TRUSTED_BOARD_BOOT */
+# endif /* PLAT_ */
#endif
#if IMAGE_BL2
# if PLAT_fvp
@@ -88,11 +96,15 @@
* Platform specific page table and MMU setup constants
*/
#if IMAGE_BL1
-# if PLAT_juno
-# define MAX_XLAT_TABLES 2
+# if TRUSTED_BOARD_BOOT
+# define MAX_XLAT_TABLES 4
# else
-# define MAX_XLAT_TABLES 3
-# endif /* PLAT_ */
+# if PLAT_juno
+# define MAX_XLAT_TABLES 2
+# else
+# define MAX_XLAT_TABLES 3
+# endif /* PLAT_ */
+# endif /* TRUSTED_BOARD_BOOT */
#elif IMAGE_BL2
# if PLAT_juno
# define MAX_XLAT_TABLES 3
diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h
index 5c03feb..4a50c1c 100644
--- a/include/plat/arm/common/arm_def.h
+++ b/include/plat/arm/common/arm_def.h
@@ -310,6 +310,14 @@
# error "Unsupported ARM_TSP_RAM_LOCATION_ID value"
#endif
+/*******************************************************************************
+ * FWU Images: NS_BL1U, BL2U & NS_BL2U defines.
+ ******************************************************************************/
+#define BL2U_BASE BL2_BASE
+#define BL2U_LIMIT BL31_BASE
+#define NS_BL2U_BASE ARM_NS_DRAM1_BASE
+#define NS_BL1U_BASE (V2M_FLASH0_BASE + 0x03EB8000)
+
/*
* ID of the secure physical generic timer interrupt used by the TSP.
*/
diff --git a/include/plat/arm/common/plat_arm.h b/include/plat/arm/common/plat_arm.h
index f0b3ff6..f8541c7 100644
--- a/include/plat/arm/common/plat_arm.h
+++ b/include/plat/arm/common/plat_arm.h
@@ -174,6 +174,8 @@
/* TSP utility functions */
void arm_tsp_early_platform_setup(void);
+/* FIP TOC validity check */
+int arm_io_is_toc_valid(void);
/*
* Mandatory functions required in ARM standard platforms
diff --git a/include/plat/arm/css/common/css_def.h b/include/plat/arm/css/common/css_def.h
index 99491f8..3fa4c15 100644
--- a/include/plat/arm/css/common/css_def.h
+++ b/include/plat/arm/css/common/css_def.h
@@ -50,6 +50,10 @@
#define NSRAM_BASE 0x2e000000
#define NSRAM_SIZE 0x00008000
+/* System Security Control Registers */
+#define SSC_REG_BASE 0x2a420000
+#define SSC_GPRETN (SSC_REG_BASE + 0x030)
+
/* The slave_bootsecure controls access to GPU, DMC and CS. */
#define CSS_NIC400_SLAVE_BOOTSECURE 8
@@ -112,6 +116,8 @@
*/
#define BL30_BASE BL31_BASE
+#define SCP_BL2U_BASE BL31_BASE
+
#define PLAT_ARM_SHARED_RAM_CACHED MHU_PAYLOAD_CACHED
/* Load address of Non-Secure Image for CSS platform ports */