Merge "chore: remove MULTI_CONSOLE_API references" into integration
diff --git a/Makefile b/Makefile
index 8e2fd81..1cce234 100644
--- a/Makefile
+++ b/Makefile
@@ -151,69 +151,6 @@
DOCS_PATH ?= docs
################################################################################
-# Process BRANCH_PROTECTION value and set
-# Pointer Authentication and Branch Target Identification flags
-################################################################################
-ifeq (${BRANCH_PROTECTION},0)
- # Default value turns off all types of branch protection
- BP_OPTION := none
-else ifneq (${ARCH},aarch64)
- $(error BRANCH_PROTECTION requires AArch64)
-else ifeq (${BRANCH_PROTECTION},1)
- # Enables all types of branch protection features
- BP_OPTION := standard
- ENABLE_BTI := 1
- ENABLE_PAUTH := 1
-else ifeq (${BRANCH_PROTECTION},2)
- # Return address signing to its standard level
- BP_OPTION := pac-ret
- ENABLE_PAUTH := 1
-else ifeq (${BRANCH_PROTECTION},3)
- # Extend the signing to include leaf functions
- BP_OPTION := pac-ret+leaf
- ENABLE_PAUTH := 1
-else ifeq (${BRANCH_PROTECTION},4)
- # Turn on branch target identification mechanism
- BP_OPTION := bti
- ENABLE_BTI := 1
-else
- $(error Unknown BRANCH_PROTECTION value ${BRANCH_PROTECTION})
-endif #(BRANCH_PROTECTION)
-
-################################################################################
-# RME dependent flags configuration
-################################################################################
-# FEAT_RME
-ifeq (${ENABLE_RME},1)
- # RME doesn't support PIE
- ifneq (${ENABLE_PIE},0)
- $(error ENABLE_RME does not support PIE)
- endif
-
- # RME doesn't support BRBE
- ifneq (${ENABLE_BRBE_FOR_NS},0)
- $(error ENABLE_RME does not support BRBE.)
- endif
-
- # RME requires AARCH64
- ifneq (${ARCH},aarch64)
- $(error ENABLE_RME requires AArch64)
- endif
-
- # RME requires el2 context to be saved for now.
- CTX_INCLUDE_EL2_REGS := 1
- CTX_INCLUDE_AARCH32_REGS := 0
- ARM_ARCH_MAJOR := 8
- ARM_ARCH_MINOR := 5
- ENABLE_FEAT_ECV = 1
- ENABLE_FEAT_FGT = 1
- CTX_INCLUDE_PAUTH_REGS := 1
-
- # RME enables CSV2_2 extension by default.
- ENABLE_FEAT_CSV2_2 = 1
-endif #(FEAT_RME)
-
-################################################################################
# Compiler Configuration based on ARCH_MAJOR and ARCH_MINOR flags
################################################################################
ifeq (${ARM_ARCH_MAJOR},7)
@@ -228,39 +165,6 @@
################################################################################
arch-features = ${ARM_ARCH_FEATURE}
-####################################################
-# Enable required options for Memory Stack Tagging.
-####################################################
-
-# Memory tagging is supported in architecture Armv8.5-A AArch64 and onwards
-ifeq ($(ARCH), aarch64)
- # Check if revision is greater than or equal to 8.5
- ifeq "8.5" "$(word 1, $(sort 8.5 $(ARM_ARCH_MAJOR).$(ARM_ARCH_MINOR)))"
- mem_tag_arch_support = yes
- endif
-endif #(ARCH=aarch64)
-
-# Currently, these options are enabled only for clang and armclang compiler.
-ifeq (${SUPPORT_STACK_MEMTAG},yes)
- ifdef mem_tag_arch_support
- # Check for armclang and clang compilers
- ifneq ( ,$(filter $(notdir $(CC)),armclang clang))
- # Add "memtag" architecture feature modifier if not specified
- ifeq ( ,$(findstring memtag,$(arch-features)))
- arch-features := $(arch-features)+memtag
- endif # memtag
- ifeq ($(notdir $(CC)),armclang)
- TF_CFLAGS += -mmemtag-stack
- else ifeq ($(notdir $(CC)),clang)
- TF_CFLAGS += -fsanitize=memtag
- endif # armclang
- endif
- else
- $(error "Error: stack memory tagging is not supported for \
- architecture ${ARCH},armv${ARM_ARCH_MAJOR}.${ARM_ARCH_MINOR}-a")
- endif #(mem_tag_arch_support)
-endif #(SUPPORT_STACK_MEMTAG)
-
# Set the compiler's architecture feature modifiers
ifneq ($(arch-features), none)
# Strip "none+" from arch-features
@@ -334,10 +238,6 @@
TF_CFLAGS_aarch32 += -mno-unaligned-access
TF_CFLAGS_aarch64 += -mgeneral-regs-only -mstrict-align
-ifneq (${BP_OPTION},none)
- TF_CFLAGS_aarch64 += -mbranch-protection=${BP_OPTION}
-endif #(BP_OPTION)
-
ASFLAGS += $(march-directive)
##############################################################################
@@ -501,6 +401,14 @@
-x assembler-with-cpp $(DEFINES)
################################################################################
+# Setup ARCH_MAJOR/MINOR before parsing arch_features.
+################################################################################
+ifeq (${ENABLE_RME},1)
+ ARM_ARCH_MAJOR := 8
+ ARM_ARCH_MINOR := 6
+endif
+
+################################################################################
# Common sources and include directories
################################################################################
include ${MAKE_HELPERS_DIRECTORY}arch_features.mk
@@ -519,13 +427,6 @@
plat/common/${ARCH}/platform_helpers.S \
${COMPILER_RT_SRCS}
-# Pointer Authentication sources
-ifeq (${ENABLE_PAUTH}, 1)
-# arm/common/aarch64/arm_pauth.c contains a sample platform hook to complete the
-# Pauth support. As it's not secure, it must be reimplemented for real platforms
- BL_COMMON_SOURCES += lib/extensions/pauth/pauth_helpers.S
-endif
-
ifeq ($(notdir $(CC)),armclang)
BL_COMMON_SOURCES += lib/${ARCH}/armclang_printf.S
endif
@@ -544,6 +445,104 @@
include common/backtrace/backtrace.mk
################################################################################
+# Process BRANCH_PROTECTION value and set
+# Pointer Authentication and Branch Target Identification flags
+################################################################################
+ifeq (${BRANCH_PROTECTION},0)
+ # Default value turns off all types of branch protection
+ BP_OPTION := none
+else ifneq (${ARCH},aarch64)
+ $(error BRANCH_PROTECTION requires AArch64)
+else ifeq (${BRANCH_PROTECTION},1)
+ # Enables all types of branch protection features
+ BP_OPTION := standard
+ ENABLE_BTI := 1
+ ENABLE_PAUTH := 1
+else ifeq (${BRANCH_PROTECTION},2)
+ # Return address signing to its standard level
+ BP_OPTION := pac-ret
+ ENABLE_PAUTH := 1
+else ifeq (${BRANCH_PROTECTION},3)
+ # Extend the signing to include leaf functions
+ BP_OPTION := pac-ret+leaf
+ ENABLE_PAUTH := 1
+else ifeq (${BRANCH_PROTECTION},4)
+ # Turn on branch target identification mechanism
+ BP_OPTION := bti
+ ENABLE_BTI := 1
+else
+ $(error Unknown BRANCH_PROTECTION value ${BRANCH_PROTECTION})
+endif #(BRANCH_PROTECTION)
+
+ifeq ($(ENABLE_PAUTH),1)
+ CTX_INCLUDE_PAUTH_REGS := 1
+endif
+ifneq (${BP_OPTION},none)
+ TF_CFLAGS_aarch64 += -mbranch-protection=${BP_OPTION}
+endif #(BP_OPTION)
+
+# Pointer Authentication sources
+ifeq (${ENABLE_PAUTH}, 1)
+# arm/common/aarch64/arm_pauth.c contains a sample platform hook to complete the
+# Pauth support. As it's not secure, it must be reimplemented for real platforms
+ BL_COMMON_SOURCES += lib/extensions/pauth/pauth_helpers.S
+endif
+
+####################################################
+# Enable required options for Memory Stack Tagging.
+####################################################
+
+# Currently, these options are enabled only for clang and armclang compiler.
+ifeq (${SUPPORT_STACK_MEMTAG},yes)
+ ifdef mem_tag_arch_support
+ # Check for armclang and clang compilers
+ ifneq ( ,$(filter $(notdir $(CC)),armclang clang))
+ # Add "memtag" architecture feature modifier if not specified
+ ifeq ( ,$(findstring memtag,$(arch-features)))
+ arch-features := $(arch-features)+memtag
+ endif # memtag
+ ifeq ($(notdir $(CC)),armclang)
+ TF_CFLAGS += -mmemtag-stack
+ else ifeq ($(notdir $(CC)),clang)
+ TF_CFLAGS += -fsanitize=memtag
+ endif # armclang
+ endif
+ else
+ $(error "Error: stack memory tagging is not supported for \
+ architecture ${ARCH},armv${ARM_ARCH_MAJOR}.${ARM_ARCH_MINOR}-a")
+ endif #(mem_tag_arch_support)
+endif #(SUPPORT_STACK_MEMTAG)
+
+################################################################################
+# RME dependent flags configuration, Enable optional features for RME.
+################################################################################
+# FEAT_RME
+ifeq (${ENABLE_RME},1)
+ # RME doesn't support PIE
+ ifneq (${ENABLE_PIE},0)
+ $(error ENABLE_RME does not support PIE)
+ endif
+
+ # RME doesn't support BRBE
+ ifneq (${ENABLE_BRBE_FOR_NS},0)
+ $(error ENABLE_RME does not support BRBE.)
+ endif
+
+ # RME requires AARCH64
+ ifneq (${ARCH},aarch64)
+ $(error ENABLE_RME requires AArch64)
+ endif
+
+ # RME requires el2 context to be saved for now.
+ CTX_INCLUDE_EL2_REGS := 1
+ CTX_INCLUDE_AARCH32_REGS := 0
+ CTX_INCLUDE_PAUTH_REGS := 1
+
+ # RME enables CSV2_2 extension by default.
+ ENABLE_FEAT_CSV2_2 = 1
+endif #(FEAT_RME)
+
+################################################################################
# Generic definitions
################################################################################
include ${MAKE_HELPERS_DIRECTORY}plat_helpers.mk
diff --git a/bl1/bl1.mk b/bl1/bl1.mk
index 95fe50e..53946ab 100644
--- a/bl1/bl1.mk
+++ b/bl1/bl1.mk
@@ -25,6 +25,10 @@
BL1_SOURCES += bl1/bl1_fwu.c
endif
+ifeq (${ENABLE_PMF},1)
+BL1_SOURCES += lib/pmf/pmf_main.c
+endif
+
ifneq ($(findstring gcc,$(notdir $(LD))),)
BL1_LDFLAGS += -Wl,--sort-section=alignment
else ifneq ($(findstring ld,$(notdir $(LD))),)
diff --git a/bl1/bl1_main.c b/bl1/bl1_main.c
index 3f64e27..6fe5511 100644
--- a/bl1/bl1_main.c
+++ b/bl1/bl1_main.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -17,7 +17,9 @@
#include <drivers/auth/auth_mod.h>
#include <drivers/auth/crypto_mod.h>
#include <drivers/console.h>
+#include <lib/bootmarker_capture.h>
#include <lib/cpus/errata.h>
+#include <lib/pmf/pmf.h>
#include <lib/utils.h>
#include <plat/common/platform.h>
#include <smccc_helpers.h>
@@ -31,6 +33,11 @@
uint64_t bl1_apiakey[2];
#endif
+#if ENABLE_RUNTIME_INSTRUMENTATION
+ PMF_REGISTER_SERVICE(bl_svc, PMF_RT_INSTR_SVC_ID,
+ BL_TOTAL_IDS, PMF_DUMP_ENABLE)
+#endif
+
/*******************************************************************************
* Helper utility to calculate the BL2 memory layout taking into consideration
* the BL1 RW data assuming that it is at the top of the memory layout.
@@ -81,6 +88,10 @@
{
unsigned int image_id;
+#if ENABLE_RUNTIME_INSTRUMENTATION
+ PMF_CAPTURE_TIMESTAMP(bl_svc, BL1_ENTRY, PMF_CACHE_MAINT);
+#endif
+
/* Announce our arrival */
NOTICE(FIRMWARE_WELCOME_STR);
NOTICE("BL1: %s\n", version_string);
@@ -156,6 +167,10 @@
bl1_prepare_next_image(image_id);
+#if ENABLE_RUNTIME_INSTRUMENTATION
+ PMF_CAPTURE_TIMESTAMP(bl_svc, BL1_EXIT, PMF_CACHE_MAINT);
+#endif
+
console_flush();
}
diff --git a/bl2/bl2.mk b/bl2/bl2.mk
index 1663c52..b70a3fb 100644
--- a/bl2/bl2.mk
+++ b/bl2/bl2.mk
@@ -49,3 +49,7 @@
BL2_DEFAULT_LINKER_SCRIPT_SOURCE := bl2/bl2_el3.ld.S
endif
+
+ifeq (${ENABLE_PMF},1)
+BL2_SOURCES += lib/pmf/pmf_main.c
+endif
\ No newline at end of file
diff --git a/bl2/bl2_main.c b/bl2/bl2_main.c
index ce83692..923a554 100644
--- a/bl2/bl2_main.c
+++ b/bl2/bl2_main.c
@@ -16,7 +16,9 @@
#include <drivers/auth/crypto_mod.h>
#include <drivers/console.h>
#include <drivers/fwu/fwu.h>
+#include <lib/bootmarker_capture.h>
#include <lib/extensions/pauth.h>
+#include <lib/pmf/pmf.h>
#include <plat/common/platform.h>
#include "bl2_private.h"
@@ -27,6 +29,11 @@
#define NEXT_IMAGE "BL32"
#endif
+#if ENABLE_RUNTIME_INSTRUMENTATION
+ PMF_REGISTER_SERVICE(bl_svc, PMF_RT_INSTR_SVC_ID,
+ BL_TOTAL_IDS, PMF_DUMP_ENABLE);
+#endif
+
#if RESET_TO_BL2
/*******************************************************************************
* Setup function for BL2 when RESET_TO_BL2=1
@@ -81,6 +88,10 @@
{
entry_point_info_t *next_bl_ep_info;
+#if ENABLE_RUNTIME_INSTRUMENTATION
+ PMF_CAPTURE_TIMESTAMP(bl_svc, BL2_ENTRY, PMF_CACHE_MAINT);
+#endif
+
NOTICE("BL2: %s\n", version_string);
NOTICE("BL2: %s\n", build_message);
@@ -118,8 +129,6 @@
disable_mmu_icache_secure();
#endif /* !__aarch64__ */
- console_flush();
-
#if ENABLE_PAUTH
/*
* Disable pointer authentication before running next boot image
@@ -127,6 +136,12 @@
pauth_disable_el1();
#endif /* ENABLE_PAUTH */
+#if ENABLE_RUNTIME_INSTRUMENTATION
+ PMF_CAPTURE_TIMESTAMP(bl_svc, BL2_EXIT, PMF_CACHE_MAINT);
+#endif
+
+ console_flush();
+
/*
* Run next BL image via an SMC to BL1. Information on how to pass
* control to the BL32 (if present) and BL33 software images will
@@ -137,6 +152,9 @@
NOTICE("BL2: Booting " NEXT_IMAGE "\n");
print_entry_point_info(next_bl_ep_info);
+#if ENABLE_RUNTIME_INSTRUMENTATION
+ PMF_CAPTURE_TIMESTAMP(bl_svc, BL2_EXIT, PMF_CACHE_MAINT);
+#endif
console_flush();
#if ENABLE_PAUTH
diff --git a/bl31/bl31_main.c b/bl31/bl31_main.c
index 8f1f043..cae55f3 100644
--- a/bl31/bl31_main.c
+++ b/bl31/bl31_main.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -17,6 +17,7 @@
#include <common/feat_detect.h>
#include <common/runtime_svc.h>
#include <drivers/console.h>
+#include <lib/bootmarker_capture.h>
#include <lib/el3_runtime/context_mgmt.h>
#include <lib/pmf/pmf.h>
#include <lib/runtime_instr.h>
@@ -24,10 +25,15 @@
#include <services/std_svc.h>
#if ENABLE_RUNTIME_INSTRUMENTATION
-PMF_REGISTER_SERVICE_SMC(rt_instr_svc, PMF_RT_INSTR_SVC_ID,
- RT_INSTR_TOTAL_IDS, PMF_STORE_ENABLE)
+ PMF_REGISTER_SERVICE_SMC(rt_instr_svc, PMF_RT_INSTR_SVC_ID,
+ RT_INSTR_TOTAL_IDS, PMF_STORE_ENABLE)
#endif
+#if ENABLE_RUNTIME_INSTRUMENTATION
+ PMF_REGISTER_SERVICE(bl_svc, PMF_RT_INSTR_SVC_ID,
+ BL_TOTAL_IDS, PMF_DUMP_ENABLE)
+#endif
+
/*******************************************************************************
* This function pointer is used to initialise the BL32 image. It's initialized
* by SPD calling bl31_register_bl32_init after setting up all things necessary
@@ -123,6 +129,10 @@
detect_arch_features();
#endif /* FEATURE_DETECTION */
+#if ENABLE_RUNTIME_INSTRUMENTATION
+ PMF_CAPTURE_TIMESTAMP(bl_svc, BL31_ENTRY, PMF_CACHE_MAINT);
+#endif
+
#ifdef SUPPORT_UNKNOWN_MPID
if (unsupported_mpid_flag == 0) {
NOTICE("Unsupported MPID detected!\n");
@@ -163,6 +173,7 @@
if (bl32_init != NULL) {
INFO("BL31: Initializing BL32\n");
+ console_flush();
int32_t rc = (*bl32_init)();
if (rc == 0) {
@@ -178,6 +189,7 @@
if (rmm_init != NULL) {
INFO("BL31: Initializing RMM\n");
+ console_flush();
int32_t rc = (*rmm_init)();
if (rc == 0) {
@@ -199,6 +211,11 @@
* from BL31
*/
bl31_plat_runtime_setup();
+
+#if ENABLE_RUNTIME_INSTRUMENTATION
+ PMF_CAPTURE_TIMESTAMP(bl_svc, BL31_EXIT, PMF_CACHE_MAINT);
+ console_flush();
+#endif
}
/*******************************************************************************
diff --git a/changelog.yaml b/changelog.yaml
index 3534cb0..cdbedbb 100644
--- a/changelog.yaml
+++ b/changelog.yaml
@@ -589,6 +589,9 @@
- title: STM32MP15
scope: stm32mp15
+ - title: STM32MP2
+ scope: stm32mp2
+
- title: Texas Instruments
scope: ti
@@ -1225,6 +1228,9 @@
- title: STM32MP15
scope: stm32mp15-fdts
+ - title: STM32MP2
+ scope: stm32mp2-fdts
+
- title: PIE
scope: pie
@@ -1350,5 +1356,8 @@
- title: Node Package Manager (NPM)
scope: npm
+ - title: Poetry
+ scope: poetry
+
- title: zlib
scope: zlib
diff --git a/docs/about/maintainers.rst b/docs/about/maintainers.rst
index 20c56fd..6042053 100644
--- a/docs/about/maintainers.rst
+++ b/docs/about/maintainers.rst
@@ -501,8 +501,8 @@
^^^^^^^^^^^^^^^^^^^^^^^^^^^
:|M|: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
:|G|: `abdellatif-elkhlifi`_
-:|M|: Vishnu Banavath <vishnu.banavath@arm.com>
-:|G|: `vishnu-banavath`_
+:|M|: Xueliang Zhong <xueliang.zhong@arm.com>
+:|G|: `xueliang-zhong-arm`_
:|F|: plat/arm/board/corstone700
:|F|: plat/arm/board/a5ds
:|F|: plat/arm/board/corstone1000
@@ -635,6 +635,13 @@
:|F|: docs/plat/imx8m.rst
:|F|: plat/imx/imx8m/
+NXP i.MX9 platform port
+^^^^^^^^^^^^^^^^^^^^^^^^
+:|M|: Jacky Bai <ping.bai@nxp.com>
+:|G|: `JackyBai`_
+:|F|: docs/plat/imx9.rst
+:|F|: plat/imx/imx93/
+
NXP QorIQ Layerscape common code for platform ports
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
:|M|: Pankaj Gupta <pankaj.gupta@nxp.com>
@@ -782,6 +789,7 @@
^^^^^^^^^^^^^^^^^^^^^^
:|M|: Yann Gautier <yann.gautier@st.com>
:|G|: `Yann-lms`_
+:|F|: docs/plat/st/*
:|F|: docs/plat/stm32mp1.rst
:|F|: drivers/st/
:|F|: fdts/stm32\*
@@ -1019,3 +1027,4 @@
.. _hilamirandakuzi1: https://github.com/hilamirandakuzi1
.. _rutigl: https://github.com/rutigl
.. _avifishman: https://github.com/avifishman
+.. _xueliang-zhong-arm: https://github.com/xueliang-zhong-arm
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index 69d3722..d1bf0d3 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -604,6 +604,9 @@
- ``ERRATA_N2_2002655``: This applies errata 2002655 workaround to Neoverse-N2
CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
+- ``ERRATA_N2_2009478``: This applies errata 2009478 workaround to Neoverse-N2
+ CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
+
- ``ERRATA_N2_2067956``: This applies errata 2067956 workaround to Neoverse-N2
CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
@@ -715,6 +718,10 @@
CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1 of the
CPU, it is still open.
+- ``ERRATA_X3_2742421``: This applies errata 2742421 workaround to
+ Cortex-X3 CPU. This needs to be enabled only for revisions r0p0, r1p0 and
+ r1p1. It is fixed in r1p2.
+
For Cortex-A510, the following errata build flags are defined :
- ``ERRATA_A510_1922240``: This applies errata 1922240 workaround to
diff --git a/docs/getting_started/prerequisites.rst b/docs/getting_started/prerequisites.rst
index f4c3c28..332ed58 100644
--- a/docs/getting_started/prerequisites.rst
+++ b/docs/getting_started/prerequisites.rst
@@ -77,7 +77,7 @@
The following libraries are required for Trusted Board Boot and Measured Boot
support:
-- mbed TLS == 3.4.0 (tag: ``mbedtls-3.4.0``)
+- mbed TLS == 3.4.1 (tag: ``mbedtls-3.4.1``)
These tools are optional:
diff --git a/docs/perf/psci-performance-instr.rst b/docs/perf/psci-performance-instr.rst
index 16f386f..41094b2 100644
--- a/docs/perf/psci-performance-instr.rst
+++ b/docs/perf/psci-performance-instr.rst
@@ -13,16 +13,17 @@
Performance Measurement Framework
---------------------------------
-The Performance Measurement Framework `PMF`_ is a framework that provides
-mechanisms for collecting and retrieving timestamps at runtime from the
-Performance Measurement Unit (`PMU`_). The PMU is a generalized abstraction for
-accessing CPU hardware registers used to measure hardware events. This means,
-for instance, that the PMU might be used to place instrumentation points at
-logical locations in code for tracing purposes.
+The Performance Measurement Framework :ref:`PMF <firmware_design_pmf>`
+is a framework that provides mechanisms for collecting and retrieving timestamps
+at runtime from the Performance Measurement Unit
+(:ref:`PMU <Performance Monitoring Unit>`).
+The PMU is a generalized abstraction for accessing CPU hardware registers used to
+measure hardware events. This means, for instance, that the PMU might be used to
+place instrumentation points at logical locations in code for tracing purposes.
TF-A utilises the PMF as a backend for the two instrumentation services it
provides--PSCI Statistics and Runtime Instrumentation. The PMF is used by
-these services to facilitate collection and retrieval of timestamps. For
+these services to facilitate collection and retrieval of timestamps. For
instance, the PSCI Statistics service registers the PMF service
``psci_svc`` to track its residency statistics.
@@ -112,6 +113,4 @@
*Copyright (c) 2023, Arm Limited. All rights reserved.*
-.. _PMF: ../design/firmware-design.html#performance-measurement-framework
-.. _PMU: performance-monitoring-unit.html
.. _PSCI: https://developer.arm.com/documentation/den0022/latest/
diff --git a/docs/perf/psci-performance-juno.rst b/docs/perf/psci-performance-juno.rst
index 7a484b8..d458d86 100644
--- a/docs/perf/psci-performance-juno.rst
+++ b/docs/perf/psci-performance-juno.rst
@@ -34,8 +34,9 @@
- TF-A [`v2.9-rc0`_]
- TFTF [`v2.9-rc0`_]
-Please see the Runtime Instrumentation `Testing Methodology`_ page for more
-details.
+Please see the Runtime Instrumentation :ref:`Testing Methodology
+<Runtime Instrumentation Methodology>`
+page for more details.
Procedure
---------
@@ -418,4 +419,3 @@
.. _Juno R1 platform: https://developer.arm.com/documentation/100122/latest/
.. _TF master as of 31/01/2017: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/?id=c38b36d
.. _v2.9-rc0: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/?h=v2.9-rc0
-.. _Testing Methodology: ../perf/psci-performance-methodology.html
diff --git a/docs/perf/psci-performance-n1sdp.rst b/docs/perf/psci-performance-n1sdp.rst
index 70a1436..ae1b89b 100644
--- a/docs/perf/psci-performance-n1sdp.rst
+++ b/docs/perf/psci-performance-n1sdp.rst
@@ -10,8 +10,8 @@
- TFTF [`v2.9-rc0`_]
- SCP/MCP `Prebuilt Images`_
-Please see the Runtime Instrumentation `Testing Methodology`_ page for more
-details.
+Please see the Runtime Instrumentation :ref:`Testing Methodology
+<Runtime Instrumentation Methodology>` page for more details.
Procedure
---------
@@ -200,4 +200,3 @@
.. _user guide: https://gitlab.arm.com/arm-reference-solutions/arm-reference-solutions-docs/-/blob/master/docs/n1sdp/user-guide.rst
.. _Prebuilt Images: https://downloads.trustedfirmware.org/tf-a/css_scp_2.11.0/n1sdp/release/
.. _N1SDP: https://developer.arm.com/documentation/101489/latest
-.. _Testing Methodology: ../perf/psci-performance-methodology.html
\ No newline at end of file
diff --git a/docs/plat/index.rst b/docs/plat/index.rst
index 2eec68c..7a05fb6 100644
--- a/docs/plat/index.rst
+++ b/docs/plat/index.rst
@@ -42,7 +42,7 @@
rockchip
socionext-uniphier
synquacer
- stm32mp1
+ st/index
ti-k3
xilinx-versal-net
xilinx-versal
diff --git a/docs/plat/st/index.rst b/docs/plat/st/index.rst
new file mode 100644
index 0000000..95ec3d2
--- /dev/null
+++ b/docs/plat/st/index.rst
@@ -0,0 +1,14 @@
+STMicroelectronics STM32 MPUs
+=============================
+
+.. toctree::
+ :maxdepth: 1
+ :caption: Contents
+
+ stm32mpus
+ stm32mp1
+ stm32mp2
+
+--------------
+
+*Copyright (c) 2023, STMicroelectronics - All Rights Reserved*
diff --git a/docs/plat/st/stm32mp1.rst b/docs/plat/st/stm32mp1.rst
new file mode 100644
index 0000000..35e8f8c
--- /dev/null
+++ b/docs/plat/st/stm32mp1.rst
@@ -0,0 +1,219 @@
+STM32MP1
+========
+
+STM32MP1 is a microprocessor designed by STMicroelectronics
+based on Arm Cortex-A7.
+It is an Armv7-A platform, using dedicated code from TF-A.
+More information can be found on `STM32MP1 Series`_ page.
+
+For TF-A common configuration of STM32 MPUs, please check
+:ref:`STM32 MPUs` page.
+
+STM32MP1 Versions
+-----------------
+
+There are 2 variants for STM32MP1: STM32MP13 and STM32MP15
+
+STM32MP13 Versions
+~~~~~~~~~~~~~~~~~~
+The STM32MP13 series is available in 3 different lines which are pin-to-pin compatible:
+
+- STM32MP131: Single Cortex-A7 core
+- STM32MP133: STM32MP131 + 2*CAN, ETH2(GMAC), ADC1
+- STM32MP135: STM32MP133 + DCMIPP, LTDC
+
+Each line comes with a security option (cryptography & secure boot) and a Cortex-A frequency option:
+
+- A Cortex-A7 @ 650 MHz
+- C Secure Boot + HW Crypto + Cortex-A7 @ 650 MHz
+- D Cortex-A7 @ 900 MHz
+- F Secure Boot + HW Crypto + Cortex-A7 @ 900 MHz
+
+STM32MP15 Versions
+~~~~~~~~~~~~~~~~~~
+The STM32MP15 series is available in 3 different lines which are pin-to-pin compatible:
+
+- STM32MP157: Dual Cortex-A7 cores, Cortex-M4 core @ 209 MHz, 3D GPU, DSI display interface and CAN FD
+- STM32MP153: Dual Cortex-A7 cores, Cortex-M4 core @ 209 MHz and CAN FD
+- STM32MP151: Single Cortex-A7 core, Cortex-M4 core @ 209 MHz
+
+Each line comes with a security option (cryptography & secure boot) and a Cortex-A frequency option:
+
+- A Basic + Cortex-A7 @ 650 MHz
+- C Secure Boot + HW Crypto + Cortex-A7 @ 650 MHz
+- D Basic + Cortex-A7 @ 800 MHz
+- F Secure Boot + HW Crypto + Cortex-A7 @ 800 MHz
+
+The `STM32MP1 part number codification`_ page gives more information about part numbers.
+
+Memory mapping
+--------------
+
+::
+
+ 0x00000000 +-----------------+
+ | | ROM
+ 0x00020000 +-----------------+
+ | |
+ | ... |
+ | |
+ 0x2FFC0000 +-----------------+ \
+ | BL32 DTB | |
+ 0x2FFC5000 +-----------------+ |
+ | BL32 | |
+ 0x2FFDF000 +-----------------+ |
+ | ... | |
+ 0x2FFE3000 +-----------------+ |
+ | BL2 DTB | | Embedded SRAM
+ 0x2FFEA000 +-----------------+ |
+ | BL2 | |
+ 0x2FFFF000 +-----------------+ |
+ | SCMI mailbox | |
+ 0x30000000 +-----------------+ /
+ | |
+ | ... |
+ | |
+ 0x40000000 +-----------------+
+ | |
+ | | Devices
+ | |
+ 0xC0000000 +-----------------+ \
+ | | |
+ 0xC0100000 +-----------------+ |
+ | BL33 | | Non-secure RAM (DDR)
+ | ... | |
+ | | |
+ 0xFFFFFFFF +-----------------+ /
+
+
+Build Instructions
+------------------
+
+STM32MP1x specific flags
+~~~~~~~~~~~~~~~~~~~~~~~~
+
+Dedicated STM32MP1 flags:
+
+- | ``STM32_TF_VERSION``: to manage BL2 monotonic counter.
+ | Default: 0
+- | ``STM32MP13``: to select STM32MP13 variant configuration.
+ | Default: 0
+- | ``STM32MP15``: to select STM32MP15 variant configuration.
+ | Default: 1
+
+
+Boot with FIP
+~~~~~~~~~~~~~
+You need to build BL2, BL32 (SP_min or OP-TEE) and BL33 (U-Boot) before building FIP binary.
+
+U-Boot
+______
+
+.. code:: bash
+
+ cd <u-boot_directory>
+ make stm32mp15_trusted_defconfig
+ make DEVICE_TREE=stm32mp157c-ev1 all
+
+OP-TEE (optional)
+_________________
+
+.. code:: bash
+
+ cd <optee_directory>
+ make CROSS_COMPILE=arm-linux-gnueabihf- ARCH=arm PLATFORM=stm32mp1 \
+ CFG_EMBED_DTB_SOURCE_FILE=stm32mp157c-ev1.dts
+
+
+TF-A BL32 (SP_min)
+__________________
+If you choose not to use OP-TEE, you can use TF-A SP_min.
+To build TF-A BL32, and its device tree file:
+
+.. code:: bash
+
+ make CROSS_COMPILE=arm-none-eabi- PLAT=stm32mp1 ARCH=aarch32 ARM_ARCH_MAJOR=7 \
+ AARCH32_SP=sp_min DTB_FILE_NAME=stm32mp157c-ev1.dtb bl32 dtbs
+
+TF-A BL2
+________
+To build TF-A BL2 with its STM32 header for SD-card boot:
+
+.. code:: bash
+
+ make CROSS_COMPILE=arm-none-eabi- PLAT=stm32mp1 ARCH=aarch32 ARM_ARCH_MAJOR=7 \
+ DTB_FILE_NAME=stm32mp157c-ev1.dtb STM32MP_SDMMC=1
+
+For other boot devices, you have to replace STM32MP_SDMMC in the previous command
+with the desired device flag.
+
+This BL2 is independent of the BL32 used (SP_min or OP-TEE)
+
+
+FIP
+___
+With BL32 SP_min:
+
+.. code:: bash
+
+ make CROSS_COMPILE=arm-none-eabi- PLAT=stm32mp1 ARCH=aarch32 ARM_ARCH_MAJOR=7 \
+ AARCH32_SP=sp_min \
+ DTB_FILE_NAME=stm32mp157c-ev1.dtb \
+ BL33=<u-boot_directory>/u-boot-nodtb.bin \
+ BL33_CFG=<u-boot_directory>/u-boot.dtb \
+ fip
+
+With OP-TEE:
+
+.. code:: bash
+
+ make CROSS_COMPILE=arm-none-eabi- PLAT=stm32mp1 ARCH=aarch32 ARM_ARCH_MAJOR=7 \
+ AARCH32_SP=optee \
+ DTB_FILE_NAME=stm32mp157c-ev1.dtb \
+ BL33=<u-boot_directory>/u-boot-nodtb.bin \
+ BL33_CFG=<u-boot_directory>/u-boot.dtb \
+ BL32=<optee_directory>/tee-header_v2.bin \
+ BL32_EXTRA1=<optee_directory>/tee-pager_v2.bin
+ BL32_EXTRA2=<optee_directory>/tee-pageable_v2.bin
+ fip
+
+Trusted Boot Board
+__________________
+
+.. code:: shell
+
+ tools/cert_create/cert_create -n --rot-key build/stm32mp1/release/rot_key.pem \
+ --tfw-nvctr 0 \
+ --ntfw-nvctr 0 \
+ --key-alg ecdsa --hash-alg sha256 \
+ --trusted-key-cert build/stm32mp1/release/trusted_key.crt \
+ --tos-fw <optee_directory>/tee-header_v2.bin \
+ --tos-fw-extra1 <optee_directory>/tee-pager_v2.bin \
+ --tos-fw-extra2 <optee_directory>/tee-pageable_v2.bin \
+ --tos-fw-cert build/stm32mp1/release/tos_fw_content.crt \
+ --tos-fw-key-cert build/stm32mp1/release/tos_fw_key.crt \
+ --nt-fw <u-boot_directory>/u-boot-nodtb.bin \
+ --nt-fw-cert build/stm32mp1/release/nt_fw_content.crt \
+ --nt-fw-key-cert build/stm32mp1/release/nt_fw_key.crt \
+ --hw-config <u-boot_directory>/u-boot.dtb \
+ --fw-config build/stm32mp1/release/fdts/fw-config.dtb \
+ --stm32mp-cfg-cert build/stm32mp1/release/stm32mp_cfg_cert.crt
+
+ tools/fiptool/fiptool create --tos-fw <optee_directory>/tee-header_v2.bin \
+ --tos-fw-extra1 <optee_directory>/tee-pager_v2.bin \
+ --tos-fw-extra2 <optee_directory>/tee-pageable_v2.bin \
+ --nt-fw <u-boot_directory>/u-boot-nodtb.bin \
+ --hw-config <u-boot_directory>/u-boot.dtb \
+ --fw-config build/stm32mp1/release/fdts/fw-config.dtb \
+ --tos-fw-cert build/stm32mp1/release/tos_fw_content.crt \
+ --tos-fw-key-cert build/stm32mp1/release/tos_fw_key.crt \
+ --nt-fw-cert build/stm32mp1/release/nt_fw_content.crt \
+ --nt-fw-key-cert build/stm32mp1/release/nt_fw_key.crt \
+ --stm32mp-cfg-cert build/stm32mp1/release/stm32mp_cfg_cert.crt \
+ build/stm32mp1/release/stm32mp1.fip
+
+
+.. _STM32MP1 Series: https://www.st.com/en/microcontrollers-microprocessors/stm32mp1-series.html
+.. _STM32MP1 part number codification: https://wiki.st.com/stm32mpu/wiki/STM32MP15_microprocessor#Part_number_codification
+
+*Copyright (c) 2023, STMicroelectronics - All Rights Reserved*
diff --git a/docs/plat/st/stm32mp2.rst b/docs/plat/st/stm32mp2.rst
new file mode 100644
index 0000000..43e131d
--- /dev/null
+++ b/docs/plat/st/stm32mp2.rst
@@ -0,0 +1,133 @@
+STM32MP2
+========
+
+STM32MP2 is a microprocessor designed by STMicroelectronics
+based on Arm Cortex-A35.
+
+For TF-A common configuration of STM32 MPUs, please check
+:ref:`STM32 MPUs` page.
+
+STM32MP2 Versions
+-----------------
+
+The STM32MP25 series is available in 4 different lines which are pin-to-pin compatible:
+
+- STM32MP257: Dual Cortex-A35 cores, Cortex-M33 core - 3x Ethernet (2+1 switch) - 3x CAN FD – H264 - 3D GPU – AI / NN - LVDS
+- STM32MP255: Dual Cortex-A35 cores, Cortex-M33 core - 2x Ethernet – 3x CAN FD - H264 - 3D GPU – AI / NN - LVDS
+- STM32MP253: Dual Cortex-A35 cores, Cortex-M33 core - 2x Ethernet – 3x CAN FD - LVDS
+- STM32MP251: Single Cortex-A35 core, Cortex-M33 core - 1x Ethernet
+
+Each line comes with a security option (cryptography & secure boot) and a Cortex-A frequency option:
+
+- A Basic + Cortex-A35 @ 1GHz
+- C Secure Boot + HW Crypto + Cortex-A35 @ 1GHz
+- D Basic + Cortex-A35 @ 1.5GHz
+- F Secure Boot + HW Crypto + Cortex-A35 @ 1.5GHz
+
+Memory mapping
+--------------
+
+::
+
+ 0x00000000 +-----------------+
+ | |
+ | ... |
+ | |
+ 0x0E000000 +-----------------+ \
+ | BL31 | |
+ +-----------------+ |
+ | ... | |
+ 0x0E012000 +-----------------+ |
+ | BL2 DTB | | Embedded SRAM
+ 0x0E016000 +-----------------+ |
+ | BL2 | |
+ 0x0E040000 +-----------------+ /
+ | |
+ | ... |
+ | |
+ 0x40000000 +-----------------+
+ | |
+ | | Devices
+ | |
+ 0x80000000 +-----------------+ \
+ | | |
+ | | | Non-secure RAM (DDR)
+ | | |
+ 0xFFFFFFFF +-----------------+ /
+
+
+Build Instructions
+------------------
+
+STM32MP2x specific flags
+~~~~~~~~~~~~~~~~~~~~~~~~
+
+Dedicated STM32MP2 build flags:
+
+- | ``STM32MP_DDR_FIP_IO_STORAGE``: to store DDR firmware in FIP.
+ | Default: 1
+- | ``STM32MP25``: to select STM32MP25 variant configuration.
+ | Default: 1
+
+To compile the correct DDR driver, one flag must be set among:
+
+- | ``STM32MP_DDR3_TYPE``: to compile DDR3 driver and DT.
+ | Default: 0
+- | ``STM32MP_DDR4_TYPE``: to compile DDR4 driver and DT.
+ | Default: 0
+- | ``STM32MP_LPDDR4_TYPE``: to compile LpDDR4 driver and DT.
+ | Default: 0
+
+
+Boot with FIP
+~~~~~~~~~~~~~
+You need to build BL2, BL31, BL32 (OP-TEE) and BL33 (U-Boot) before building FIP binary.
+
+U-Boot
+______
+
+.. code:: bash
+
+ cd <u-boot_directory>
+ make stm32mp25_defconfig
+ make DEVICE_TREE=stm32mp257f-ev1 all
+
+OP-TEE
+______
+
+.. code:: bash
+
+ cd <optee_directory>
+ make CROSS_COMPILE64=aarch64-none-elf- CROSS_COMPILE32=arm-none-eabi-
+ ARCH=arm PLATFORM=stm32mp2 \
+ CFG_EMBED_DTB_SOURCE_FILE=stm32mp257f-ev1.dts
+
+TF-A BL2 & BL31
+_______________
+To build TF-A BL2 with its STM32 header and BL31 for SD-card boot:
+
+.. code:: bash
+
+ make CROSS_COMPILE=aarch64-none-elf- PLAT=stm32mp2 \
+ STM32MP_DDR4_TYPE=1 SPD=opteed \
+ DTB_FILE_NAME=stm32mp257f-ev1.dtb STM32MP_SDMMC=1
+
+For other boot devices, you have to replace STM32MP_SDMMC in the previous command
+with the desired device flag.
+
+
+FIP
+___
+
+.. code:: bash
+
+ make CROSS_COMPILE=aarch64-none-elf- PLAT=stm32mp2 \
+ STM32MP_DDR4_TYPE=1 SPD=opteed \
+ DTB_FILE_NAME=stm32mp257f-ev1.dtb \
+ BL33=<u-boot_directory>/u-boot-nodtb.bin \
+ BL33_CFG=<u-boot_directory>/u-boot.dtb \
+ BL32=<optee_directory>/tee-header_v2.bin \
+ BL32_EXTRA1=<optee_directory>/tee-pager_v2.bin
+ fip
+
+*Copyright (c) 2023, STMicroelectronics - All Rights Reserved*
diff --git a/docs/plat/st/stm32mpus.rst b/docs/plat/st/stm32mpus.rst
new file mode 100644
index 0000000..931dd57
--- /dev/null
+++ b/docs/plat/st/stm32mpus.rst
@@ -0,0 +1,78 @@
+STM32 MPUs
+==========
+
+STM32 MPUs are microprocessors designed by STMicroelectronics
+based on Arm Cortex-A. This page presents the common configuration of STM32
+MPUs, more details and dedicated configuration can be found in each STM32 MPU
+page (:ref:`STM32MP1` or :ref:`STM32MP2`)
+
+Design
+------
+The STM32 MPU resets in the ROM code of the Cortex-A.
+The primary boot core (core 0) executes the boot sequence while
+secondary boot core (core 1) is kept in a holding pen loop.
+The ROM code boot sequence loads the TF-A binary image from boot device
+to embedded SRAM.
+
+The TF-A image must be properly formatted with a STM32 header structure
+for ROM code is able to load this image.
+Tool stm32image can be used to prepend this header to the generated TF-A binary.
+
+Boot
+~~~~
+Only BL2 (with STM32 header) is loaded by ROM code. The other binaries are
+inside the FIP binary: BL31 (for Aarch64 platforms), BL32 (OP-TEE), U-Boot
+and their respective device tree blobs.
+
+Boot sequence
+~~~~~~~~~~~~~
+
+ROM code -> BL2 (compiled with RESET_TO_BL2) -> OP-TEE -> BL33 (U-Boot)
+
+Build Instructions
+------------------
+Boot media(s) supported by BL2 must be specified in the build command.
+Available storage medias are:
+
+- ``STM32MP_SDMMC``
+- ``STM32MP_EMMC``
+- ``STM32MP_RAW_NAND``
+- ``STM32MP_SPI_NAND``
+- ``STM32MP_SPI_NOR``
+
+Serial boot devices:
+
+- ``STM32MP_UART_PROGRAMMER``
+- ``STM32MP_USB_PROGRAMMER``
+
+
+Other configuration flags:
+
+- | ``DTB_FILE_NAME``: to precise board device-tree blob to be used.
+ | Default: stm32mp157c-ev1.dtb
+- | ``DWL_BUFFER_BASE``: the 'serial boot' load address of FIP,
+ | default location (end of the first 128MB) is used when absent
+- | ``STM32MP_EARLY_CONSOLE``: to enable early traces before clock driver is setup.
+ | Default: 0 (disabled)
+- | ``STM32MP_RECONFIGURE_CONSOLE``: to re-configure crash console (especially after BL2).
+ | Default: 0 (disabled)
+- | ``STM32MP_UART_BAUDRATE``: to select UART baud rate.
+ | Default: 115200
+
+
+Populate SD-card
+----------------
+
+Boot with FIP
+~~~~~~~~~~~~~
+The SD-card has to be formatted with GPT.
+It should contain at least those partitions:
+
+- fsbl: to copy the tf-a-stm32mp157c-ev1.stm32 binary (BL2)
+- fip (GUID 19d5df83-11b0-457b-be2c-7559c13142a5): which contains the FIP binary
+
+Usually, two copies of fsbl are used (fsbl1 and fsbl2) instead of one partition fsbl.
+
+--------------
+
+*Copyright (c) 2023, STMicroelectronics - All Rights Reserved*
diff --git a/docs/plat/stm32mp1.rst b/docs/plat/stm32mp1.rst
index a983606..f2c8fd2 100644
--- a/docs/plat/stm32mp1.rst
+++ b/docs/plat/stm32mp1.rst
@@ -1,280 +1,10 @@
-STMicroelectronics STM32MP1
-===========================
+:orphan:
-STM32MP1 is a microprocessor designed by STMicroelectronics
-based on Arm Cortex-A7.
-It is an Armv7-A platform, using dedicated code from TF-A.
-More information can be found on `STM32MP1 Series`_ page.
+STMicroelectronics STM32MP1 (old page)
+======================================
-
-STM32MP1 Versions
------------------
-
-There are 2 variants for STM32MP1: STM32MP13 and STM32MP15
-
-STM32MP13 Versions
-~~~~~~~~~~~~~~~~~~
-The STM32MP13 series is available in 3 different lines which are pin-to-pin compatible:
-
-- STM32MP131: Single Cortex-A7 core
-- STM32MP133: STM32MP131 + 2*CAN, ETH2(GMAC), ADC1
-- STM32MP135: STM32MP133 + DCMIPP, LTDC
-
-Each line comes with a security option (cryptography & secure boot) and a Cortex-A frequency option:
-
-- A Cortex-A7 @ 650 MHz
-- C Secure Boot + HW Crypto + Cortex-A7 @ 650 MHz
-- D Cortex-A7 @ 900 MHz
-- F Secure Boot + HW Crypto + Cortex-A7 @ 900 MHz
-
-STM32MP15 Versions
-~~~~~~~~~~~~~~~~~~
-The STM32MP15 series is available in 3 different lines which are pin-to-pin compatible:
-
-- STM32MP157: Dual Cortex-A7 cores, Cortex-M4 core @ 209 MHz, 3D GPU, DSI display interface and CAN FD
-- STM32MP153: Dual Cortex-A7 cores, Cortex-M4 core @ 209 MHz and CAN FD
-- STM32MP151: Single Cortex-A7 core, Cortex-M4 core @ 209 MHz
-
-Each line comes with a security option (cryptography & secure boot) and a Cortex-A frequency option:
-
-- A Basic + Cortex-A7 @ 650 MHz
-- C Secure Boot + HW Crypto + Cortex-A7 @ 650 MHz
-- D Basic + Cortex-A7 @ 800 MHz
-- F Secure Boot + HW Crypto + Cortex-A7 @ 800 MHz
-
-The `STM32MP1 part number codification`_ page gives more information about part numbers.
-
-Design
-------
-The STM32MP1 resets in the ROM code of the Cortex-A7.
-The primary boot core (core 0) executes the boot sequence while
-secondary boot core (core 1) is kept in a holding pen loop.
-The ROM code boot sequence loads the TF-A binary image from boot device
-to embedded SRAM.
-
-The TF-A image must be properly formatted with a STM32 header structure
-for ROM code is able to load this image.
-Tool stm32image can be used to prepend this header to the generated TF-A binary.
-
-Boot with FIP
-~~~~~~~~~~~~~
-The use of FIP is now the recommended way to boot STM32MP1 platform.
-Only BL2 (with STM32 header) is loaded by ROM code. The other binaries are
-inside the FIP binary: BL32 (SP_min or OP-TEE), U-Boot and their respective
-device tree blobs.
-
-
-Memory mapping
-~~~~~~~~~~~~~~
-
-::
-
- 0x00000000 +-----------------+
- | | ROM
- 0x00020000 +-----------------+
- | |
- | ... |
- | |
- 0x2FFC0000 +-----------------+ \
- | BL32 DTB | |
- 0x2FFC5000 +-----------------+ |
- | BL32 | |
- 0x2FFDF000 +-----------------+ |
- | ... | |
- 0x2FFE3000 +-----------------+ |
- | BL2 DTB | | Embedded SRAM
- 0x2FFEA000 +-----------------+ |
- | BL2 | |
- 0x2FFFF000 +-----------------+ |
- | SCMI mailbox | |
- 0x30000000 +-----------------+ /
- | |
- | ... |
- | |
- 0x40000000 +-----------------+
- | |
- | | Devices
- | |
- 0xC0000000 +-----------------+ \
- | | |
- 0xC0100000 +-----------------+ |
- | BL33 | | Non-secure RAM (DDR)
- | ... | |
- | | |
- 0xFFFFFFFF +-----------------+ /
-
-
-Boot sequence
-~~~~~~~~~~~~~
-
-ROM code -> BL2(compiled with RESET_TO_BL2) -> BL32(SP_min)-> BL33(U-Boot)
-
-or if Op-TEE is used:
-
-ROM code -> BL2 (compiled with RESET_TO_BL2) -> OP-TEE -> BL33 (U-Boot)
-
-
-Build Instructions
-------------------
-Boot media(s) supported by BL2 must be specified in the build command.
-Available storage medias are:
-
-- ``STM32MP_SDMMC``
-- ``STM32MP_EMMC``
-- ``STM32MP_RAW_NAND``
-- ``STM32MP_SPI_NAND``
-- ``STM32MP_SPI_NOR``
-
-Serial boot devices:
-
-- ``STM32MP_UART_PROGRAMMER``
-- ``STM32MP_USB_PROGRAMMER``
-
-
-Other configuration flags:
-
-- | ``DTB_FILE_NAME``: to precise board device-tree blob to be used.
- | Default: stm32mp157c-ev1.dtb
-- | ``DWL_BUFFER_BASE``: the 'serial boot' load address of FIP,
- | default location (end of the first 128MB) is used when absent
-- | ``STM32MP_EARLY_CONSOLE``: to enable early traces before clock driver is setup.
- | Default: 0 (disabled)
-- | ``STM32MP_RECONFIGURE_CONSOLE``: to re-configure crash console (especially after BL2).
- | Default: 0 (disabled)
-- | ``STM32MP_UART_BAUDRATE``: to select UART baud rate.
- | Default: 115200
-- | ``STM32_TF_VERSION``: to manage BL2 monotonic counter.
- | Default: 0
-- | ``STM32MP13``: to select STM32MP13 variant configuration.
- | Default: 0
-- | ``STM32MP15``: to select STM32MP15 variant configuration.
- | Default: 1
-
-
-Boot with FIP
-~~~~~~~~~~~~~
-You need to build BL2, BL32 (SP_min or OP-TEE) and BL33 (U-Boot) before building FIP binary.
-
-U-Boot
-______
-
-.. code:: bash
-
- cd <u-boot_directory>
- make stm32mp15_trusted_defconfig
- make DEVICE_TREE=stm32mp157c-ev1 all
-
-OP-TEE (optional)
-_________________
-
-.. code:: bash
-
- cd <optee_directory>
- make CROSS_COMPILE=arm-linux-gnueabihf- ARCH=arm PLATFORM=stm32mp1 \
- CFG_EMBED_DTB_SOURCE_FILE=stm32mp157c-ev1.dts
-
-
-TF-A BL32 (SP_min)
-__________________
-If you choose not to use OP-TEE, you can use TF-A SP_min.
-To build TF-A BL32, and its device tree file:
-
-.. code:: bash
-
- make CROSS_COMPILE=arm-none-eabi- PLAT=stm32mp1 ARCH=aarch32 ARM_ARCH_MAJOR=7 \
- AARCH32_SP=sp_min DTB_FILE_NAME=stm32mp157c-ev1.dtb bl32 dtbs
-
-TF-A BL2
-________
-To build TF-A BL2 with its STM32 header for SD-card boot:
-
-.. code:: bash
-
- make CROSS_COMPILE=arm-none-eabi- PLAT=stm32mp1 ARCH=aarch32 ARM_ARCH_MAJOR=7 \
- DTB_FILE_NAME=stm32mp157c-ev1.dtb STM32MP_SDMMC=1
-
-For other boot devices, you have to replace STM32MP_SDMMC in the previous command
-with the desired device flag.
-
-This BL2 is independent of the BL32 used (SP_min or OP-TEE)
-
-
-FIP
-___
-With BL32 SP_min:
-
-.. code:: bash
-
- make CROSS_COMPILE=arm-none-eabi- PLAT=stm32mp1 ARCH=aarch32 ARM_ARCH_MAJOR=7 \
- AARCH32_SP=sp_min \
- DTB_FILE_NAME=stm32mp157c-ev1.dtb \
- BL33=<u-boot_directory>/u-boot-nodtb.bin \
- BL33_CFG=<u-boot_directory>/u-boot.dtb \
- fip
-
-With OP-TEE:
-
-.. code:: bash
-
- make CROSS_COMPILE=arm-none-eabi- PLAT=stm32mp1 ARCH=aarch32 ARM_ARCH_MAJOR=7 \
- AARCH32_SP=optee \
- DTB_FILE_NAME=stm32mp157c-ev1.dtb \
- BL33=<u-boot_directory>/u-boot-nodtb.bin \
- BL33_CFG=<u-boot_directory>/u-boot.dtb \
- BL32=<optee_directory>/tee-header_v2.bin \
- BL32_EXTRA1=<optee_directory>/tee-pager_v2.bin
- BL32_EXTRA2=<optee_directory>/tee-pageable_v2.bin
- fip
-
-Trusted Boot Board
-__________________
-
-.. code:: shell
-
- tools/cert_create/cert_create -n --rot-key "build/stm32mp1/debug/rot_key.pem" \
- --tfw-nvctr 0 \
- --ntfw-nvctr 0 \
- --key-alg ecdsa --hash-alg sha256 \
- --trusted-key-cert build/stm32mp1/cert_images/trusted-key-cert.key-crt \
- --tos-fw <optee_directory>/tee-header_v2.bin \
- --tos-fw-extra1 <optee_directory>/tee-pager_v2.bin \
- --tos-fw-extra2 <optee_directory>/tee-pageable_v2.bin \
- --tos-fw-cert build/stm32mp1/cert_images/tee-header_v2.bin.crt \
- --tos-fw-key-cert build/stm32mp1/cert_images/tee-header_v2.bin.key-crt \
- --nt-fw <u-boot_directory>/u-boot-nodtb.bin \
- --nt-fw-cert build/stm32mp1/cert_images/u-boot.bin.crt \
- --nt-fw-key-cert build/stm32mp1/cert_images/u-boot.bin.key-crt \
- --hw-config <u-boot_directory>/u-boot.dtb \
- --fw-config build/stm32mp1/debug/fdts/fw-config.dtb \
- --stm32mp-cfg-cert build/stm32mp1/cert_images/stm32mp_cfg_cert.crt
-
- tools/fiptool/fiptool create --tos-fw <optee_directory>/tee-header_v2.bin \
- --tos-fw-extra1 <optee_directory>/tee-pager_v2.bin \
- --tos-fw-extra2 <optee_directory>/tee-pageable_v2.bin \
- --nt-fw <u-boot_directory>/u-boot-nodtb.bin \
- --hw-config <u-boot_directory>/u-boot.dtb \
- --fw-config build/stm32mp1/debug/fdts/fw-config.dtb \
- --tos-fw-cert build/stm32mp1/cert_images/tee-header_v2.bin.crt \
- --tos-fw-key-cert build/stm32mp1/cert_images/tee-header_v2.bin.key-crt \
- --nt-fw-cert build/stm32mp1/cert_images/u-boot.bin.crt \
- --nt-fw-key-cert build/stm32mp1/cert_images/u-boot.bin.key-crt \
- --stm32mp-cfg-cert build/stm32mp1/cert_images/stm32mp_cfg_cert.crt stm32mp1.fip
-
-
-
-Populate SD-card
-----------------
-
-Boot with FIP
-~~~~~~~~~~~~~
-The SD-card has to be formatted with GPT.
-It should contain at least those partitions:
-
-- fsbl: to copy the tf-a-stm32mp157c-ev1.stm32 binary (BL2)
-- fip: which contains the FIP binary
-
-Usually, two copies of fsbl are used (fsbl1 and fsbl2) instead of one partition fsbl.
-
+Please check :ref:`STM32 MPUs` page for generic information about
+STMicroelectronics STM32 microprocessors in TF-A, and :ref:`STM32MP1` page
+for specificities on STM32MP1x platforms.
-.. _STM32MP1 Series: https://www.st.com/en/microcontrollers-microprocessors/stm32mp1-series.html
-.. _STM32MP1 part number codification: https://wiki.st.com/stm32mpu/wiki/STM32MP15_microprocessor#Part_number_codification
+*Copyright (c) 2018-2023, STMicroelectronics - All Rights Reserved*
diff --git a/docs/porting-guide.rst b/docs/porting-guide.rst
index 5a017ce..f612e1c 100644
--- a/docs/porting-guide.rst
+++ b/docs/porting-guide.rst
@@ -3463,6 +3463,15 @@
to ``no``. If any of the options ``EL3_PAYLOAD_BASE`` or ``PRELOADED_BL33_BASE``
are used, this flag will be set to ``no`` automatically.
+- **ARM_ARCH_MAJOR and ARM_ARCH_MINOR**
+ By default, ARM_ARCH_MAJOR.ARM_ARCH_MINOR is set to 8.0 in ``defaults.mk``,
+ if the platform makefile/build defines or uses the correct ARM_ARCH_MAJOR and
+ ARM_ARCH_MINOR then mandatory Architectural features available for that Arch
+ version will be enabled by default and any optional Arch feature supported by
+ the Architecture and available in TF-A can be enabled from platform specific
+ makefile. Look up to ``arch_features.mk`` for details pertaining to mandatory
+ and optional Arch specific features.
+
Platform include paths
----------------------
diff --git a/docs/threat_model/threat_model.rst b/docs/threat_model/threat_model.rst
index c50ed8e..57a5e1b 100644
--- a/docs/threat_model/threat_model.rst
+++ b/docs/threat_model/threat_model.rst
@@ -85,6 +85,8 @@
+-----------------+--------------------------------------------------------+
+.. _threat_analysis:
+
***************
Threat Analysis
***************
diff --git a/docs/threat_model/threat_model_el3_spm.rst b/docs/threat_model/threat_model_el3_spm.rst
index c3af7a2..8adf3df 100644
--- a/docs/threat_model/threat_model_el3_spm.rst
+++ b/docs/threat_model/threat_model_el3_spm.rst
@@ -4,7 +4,7 @@
************
Introduction
************
-This document provides a threat model for the TF-A `EL3 Secure Partition Manager`_
+This document provides a threat model for the TF-A :ref:`EL3 Secure Partition Manager`
(EL3 SPM) implementation. The EL3 SPM implementation is based on the
`Arm Firmware Framework for Arm A-profile`_ specification.
@@ -13,7 +13,8 @@
********************
In this threat model, the target of evaluation is the ``Secure Partition Manager Core``
component (SPMC) within the EL3 firmware.
-The monitor and SPMD at EL3 are covered by the `Generic TF-A threat model`_.
+The monitor and SPMD at EL3 are covered by the :ref:`Generic TF-A threat model
+<threat_analysis>`.
The scope for this threat model is:
@@ -70,8 +71,8 @@
Threat Analysis
***************
-This threat model follows a similar methodology to the `Generic TF-A threat model`_.
-The following sections define:
+This threat model follows a similar methodology to the :ref:`Generic TF-A threat model
+<threat_analysis>`. The following sections define:
- Trust boundaries
- Assets
@@ -115,7 +116,8 @@
Threat types
============
-The following threat categories as exposed in the `Generic TF-A threat model`_
+The following threat categories as exposed in the :ref:`Generic TF-A threat model
+<threat_analysis>`
are re-used:
- Spoofing
@@ -642,9 +644,7 @@
---------------
-*Copyright (c) 2022, Arm Limited. All rights reserved.*
+*Copyright (c) 2022-2023, Arm Limited. All rights reserved.*
.. _Arm Firmware Framework for Arm A-profile: https://developer.arm.com/docs/den0077/latest
-.. _EL3 Secure Partition Manager: ../components/el3-spmc.html
-.. _Generic TF-A threat model: ./threat_model.html#threat-analysis
.. _FF-A ACS: https://github.com/ARM-software/ff-a-acs/releases
diff --git a/docs/threat_model/threat_model_spm.rst b/docs/threat_model/threat_model_spm.rst
index 9458a9f..24a115b 100644
--- a/docs/threat_model/threat_model_spm.rst
+++ b/docs/threat_model/threat_model_spm.rst
@@ -4,7 +4,7 @@
************************
Introduction
************************
-This document provides a threat model for the TF-A `Secure Partition Manager`_
+This document provides a threat model for the TF-A :ref:`Secure Partition Manager`
(SPM) implementation or more generally the S-EL2 reference firmware running on
systems implementing the FEAT_SEL2 (formerly Armv8.4 Secure EL2) architecture
extension. The SPM implementation is based on the `Arm Firmware Framework for
@@ -28,7 +28,8 @@
************************
In this threat model, the target of evaluation is the S-EL2 firmware or the
``Secure Partition Manager Core`` component (SPMC).
-The monitor and SPMD at EL3 are covered by the `Generic TF-A threat model`_.
+The monitor and SPMD at EL3 are covered by the :ref:`Generic TF-A threat model
+<threat_analysis>`.
The scope for this threat model is:
@@ -92,7 +93,8 @@
Threat Analysis
*********************
-This threat model follows a similar methodology to the `Generic TF-A threat model`_.
+This threat model follows a similar methodology to the :ref:`Generic TF-A threat model
+<threat_analysis>`.
The following sections define:
- Trust boundaries
@@ -141,7 +143,8 @@
Threat types
============================
-The following threat categories as exposed in the `Generic TF-A threat model`_
+The following threat categories as exposed in the :ref:`Generic TF-A threat model
+<threat_analysis>`
are re-used:
- Spoofing
@@ -1333,7 +1336,5 @@
*Copyright (c) 2021-2023, Arm Limited. All rights reserved.*
.. _Arm Firmware Framework for Arm A-profile: https://developer.arm.com/docs/den0077/latest
-.. _Secure Partition Manager: ../components/secure-partition-manager.html
-.. _Generic TF-A threat model: ./threat_model.html#threat-analysis
.. _FF-A ACS: https://github.com/ARM-software/ff-a-acs/releases
diff --git a/drivers/auth/auth_mod.c b/drivers/auth/auth_mod.c
index 105dc05..14c3172 100644
--- a/drivers/auth/auth_mod.c
+++ b/drivers/auth/auth_mod.c
@@ -150,8 +150,8 @@
const auth_img_desc_t *img_desc,
void *img, unsigned int img_len)
{
- void *data_ptr, *pk_ptr, *pk_plat_ptr, *sig_ptr, *sig_alg_ptr, *pk_oid;
- unsigned int data_len, pk_len, pk_plat_len, sig_len, sig_alg_len;
+ void *data_ptr, *pk_ptr, *cnv_pk_ptr, *pk_plat_ptr, *sig_ptr, *sig_alg_ptr, *pk_oid;
+ unsigned int data_len, pk_len, cnv_pk_len, pk_plat_len, sig_len, sig_alg_len;
unsigned int flags = 0;
int rc = 0;
@@ -210,14 +210,14 @@
* platform may store the hash of a prefixed,
* suffixed or modified pk
*/
- rc = crypto_mod_convert_pk(pk_ptr, pk_len, &pk_ptr, &pk_len);
+ rc = crypto_mod_convert_pk(pk_ptr, pk_len, &cnv_pk_ptr, &cnv_pk_len);
return_if_error(rc);
/*
* The hash of the certificate's public key must match
* the hash of the ROTPK.
*/
- rc = crypto_mod_verify_hash(pk_ptr, pk_len,
+ rc = crypto_mod_verify_hash(cnv_pk_ptr, cnv_pk_len,
pk_plat_ptr, pk_plat_len);
return_if_error(rc);
} else {
diff --git a/drivers/cadence/uart/aarch64/cdns_console.S b/drivers/cadence/uart/aarch64/cdns_console.S
index 4c1a80e..1bdaa48 100644
--- a/drivers/cadence/uart/aarch64/cdns_console.S
+++ b/drivers/cadence/uart/aarch64/cdns_console.S
@@ -197,7 +197,14 @@
cmp x0, #0
ASM_ASSERT(ne)
#endif /* ENABLE_ASSERTIONS */
- /* Placeholder */
+ /* Loop until the transmit FIFO is empty */
+check_txfifo_empty:
+ ldr w2, [x0, #R_UART_SR]
+ tbz w2, #UART_SR_INTR_TEMPTY_BIT, check_txfifo_empty
+ /* Wait until the Transmit is Inactive */
+check_tx_inactive_state:
+ ldr w2, [x0, #R_UART_SR]
+ tbnz w2, #UART_SR_INTR_TACTIVE_BIT, check_tx_inactive_state
ret
endfunc console_cdns_core_flush
diff --git a/drivers/st/clk/stm32mp_clkfunc.c b/drivers/st/clk/stm32mp_clkfunc.c
index 01d1420..379547f 100644
--- a/drivers/st/clk/stm32mp_clkfunc.c
+++ b/drivers/st/clk/stm32mp_clkfunc.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2022, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2017-2023, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -248,6 +248,7 @@
return cuint;
}
+#if defined(IMAGE_BL32)
/*
* Get the secure state for rcc node in device tree.
* @return: true if rcc is configured for secure world access, false if not.
@@ -266,6 +267,7 @@
return true;
}
+#endif
/*
* Get the clock ID of the given node in device tree.
@@ -320,6 +322,19 @@
}
/*******************************************************************************
+ * This function sets the STGEN counter value.
+ ******************************************************************************/
+static void stgen_set_counter(unsigned long long counter)
+{
+#ifdef __aarch64__
+ mmio_write_64(STGEN_BASE + CNTCV_OFF, counter);
+#else
+ mmio_write_32(STGEN_BASE + CNTCVL_OFF, (uint32_t)counter);
+ mmio_write_32(STGEN_BASE + CNTCVU_OFF, (uint32_t)(counter >> 32));
+#endif
+}
+
+/*******************************************************************************
* This function configures and restores the STGEN counter depending on the
* connected clock.
******************************************************************************/
@@ -337,8 +352,7 @@
mmio_clrbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN);
counter = stm32mp_stgen_get_counter() * rate / cntfid0;
- mmio_write_32(STGEN_BASE + CNTCVL_OFF, (uint32_t)counter);
- mmio_write_32(STGEN_BASE + CNTCVU_OFF, (uint32_t)(counter >> 32));
+ stgen_set_counter(counter);
mmio_write_32(STGEN_BASE + CNTFID_OFF, rate);
mmio_setbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN);
@@ -353,8 +367,12 @@
******************************************************************************/
unsigned long long stm32mp_stgen_get_counter(void)
{
+#ifdef __aarch64__
+ return mmio_read_64(STGEN_BASE + CNTCV_OFF);
+#else
return (((unsigned long long)mmio_read_32(STGEN_BASE + CNTCVU_OFF) << 32) |
mmio_read_32(STGEN_BASE + CNTCVL_OFF));
+#endif
}
/*******************************************************************************
@@ -371,7 +389,6 @@
mmio_read_32(STGEN_BASE + CNTFID_OFF)) / 1000U);
mmio_clrbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN);
- mmio_write_32(STGEN_BASE + CNTCVL_OFF, (uint32_t)cnt);
- mmio_write_32(STGEN_BASE + CNTCVU_OFF, (uint32_t)(cnt >> 32));
+ stgen_set_counter(cnt);
mmio_setbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN);
}
diff --git a/drivers/st/mmc/stm32_sdmmc2.c b/drivers/st/mmc/stm32_sdmmc2.c
index 1ee3580..be722f3 100644
--- a/drivers/st/mmc/stm32_sdmmc2.c
+++ b/drivers/st/mmc/stm32_sdmmc2.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2022, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2018-2023, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -131,6 +131,12 @@
#define SDMMC_FIFO_SIZE 64U
+#define STM32MP_MMC_INIT_FREQ U(400000) /*400 KHz*/
+#define STM32MP_SD_NORMAL_SPEED_MAX_FREQ U(25000000) /*25 MHz*/
+#define STM32MP_SD_HIGH_SPEED_MAX_FREQ U(50000000) /*50 MHz*/
+#define STM32MP_EMMC_NORMAL_SPEED_MAX_FREQ U(26000000) /*26 MHz*/
+#define STM32MP_EMMC_HIGH_SPEED_MAX_FREQ U(52000000) /*52 MHz*/
+
static void stm32_sdmmc2_init(void);
static int stm32_sdmmc2_send_cmd_req(struct mmc_cmd *cmd);
static int stm32_sdmmc2_send_cmd(struct mmc_cmd *cmd);
diff --git a/drivers/st/regulator/regulator_fixed.c b/drivers/st/regulator/regulator_fixed.c
index f1c224e..6c9d3b1 100644
--- a/drivers/st/regulator/regulator_fixed.c
+++ b/drivers/st/regulator/regulator_fixed.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2021-2023, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -13,8 +13,8 @@
#include <drivers/st/regulator_fixed.h>
#include <libfdt.h>
-#ifndef PLAT_NB_FIXED_REGS
-#error "Missing PLAT_NB_FIXED_REGS"
+#ifndef PLAT_NB_FIXED_REGUS
+#error "Missing PLAT_NB_FIXED_REGUS"
#endif
#define FIXED_NAME_LEN 32
@@ -25,7 +25,7 @@
struct regul_description desc;
};
-static struct fixed_data data[PLAT_NB_FIXED_REGS];
+static struct fixed_data data[PLAT_NB_FIXED_REGUS];
static int fixed_set_state(const struct regul_description *desc, bool state)
{
@@ -79,7 +79,7 @@
}
count++;
- assert(count <= PLAT_NB_FIXED_REGS);
+ assert(count <= PLAT_NB_FIXED_REGUS);
}
diff --git a/drivers/st/uart/aarch64/stm32_console.S b/drivers/st/uart/aarch64/stm32_console.S
new file mode 100644
index 0000000..312b35d
--- /dev/null
+++ b/drivers/st/uart/aarch64/stm32_console.S
@@ -0,0 +1,255 @@
+/*
+ * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <asm_macros.S>
+#include <assert_macros.S>
+#include <console_macros.S>
+#include <drivers/st/stm32_console.h>
+#include <drivers/st/stm32_uart_regs.h>
+
+#define USART_TIMEOUT 0x1000
+
+ /*
+ * "core" functions are low-level implementations that don't require
+ * writeable memory and are thus safe to call in BL1 crash context.
+ */
+ .globl console_stm32_core_init
+ .globl console_stm32_core_putc
+ .globl console_stm32_core_getc
+ .globl console_stm32_core_flush
+
+ .globl console_stm32_putc
+ .globl console_stm32_flush
+
+
+
+ /* -----------------------------------------------------------------
+ * int console_core_init(uintptr_t base_addr,
+ * unsigned int uart_clk,
+ * unsigned int baud_rate)
+ *
+ * Function to initialize the console without a C Runtime to print
+ * debug information. This function will be accessed by console_init
+ * and crash reporting.
+ *
+ * In: x0 - console base address
+ * w1 - Uart clock in Hz
+ * w2 - Baud rate
+ * Out: return 1 on success else 0 on error
+ * Clobber list : x1, x2, x3, x4
+ * -----------------------------------------------
+ */
+func console_stm32_core_init
+ /* Check the input base address */
+ cbz x0, core_init_fail
+#if !defined(IMAGE_BL2)
+#if STM32MP_RECONFIGURE_CONSOLE
+ /* UART clock rate is set to 0 in BL32, skip init in that case */
+ cbz x1, 1f
+#else /* STM32MP_RECONFIGURE_CONSOLE */
+ /* Skip UART initialization if it is already enabled */
+ ldr w3, [x0, #USART_CR1]
+ tst w3, #USART_CR1_UE
+ b.ne 1f
+#endif /* STM32MP_RECONFIGURE_CONSOLE */
+#endif /* IMAGE_BL2 */
+ /* Check baud rate and uart clock for sanity */
+ cbz w1, core_init_fail
+ cbz w2, core_init_fail
+ /* Disable UART */
+ ldr w3, [x0, #USART_CR1]
+ mov w4, #USART_CR1_UE
+ bic w3, w3, w4
+ str w3, [x0, #USART_CR1]
+ /* Configure UART */
+ mov w4, #(USART_CR1_TE)
+ orr w4, w4, #(USART_CR1_FIFOEN)
+ orr w3, w3, w4
+ str w3, [x0, #USART_CR1]
+ ldr w3, [x0, #USART_CR2]
+ mov w4, #USART_CR2_STOP
+ bic w3, w3, w4
+ str w3, [x0, #USART_CR2]
+ /* Divisor = (Uart clock + (baudrate / 2)) / baudrate */
+ lsr w3, w2, #1
+ add w3, w1, w3
+ udiv w3, w3, w2
+ cmp w3, #16
+ b.hi 2f
+ /* Oversampling 8 */
+ /* Divisor = (2 * Uart clock + (baudrate / 2)) / baudrate */
+ lsr w3, w2, #1
+ add w3, w3, w1, lsl #1
+ udiv w3, w3, w2
+ and w1, w3, #USART_BRR_DIV_FRACTION
+ lsr w1, w1, #1
+ bic w3, w3, #USART_BRR_DIV_FRACTION
+ orr w3, w3, w1
+ ldr w1, [x0, #USART_CR1]
+ orr w1, w1, #USART_CR1_OVER8
+ str w1, [x0, #USART_CR1]
+2:
+ str w3, [x0, #USART_BRR]
+ /* Enable UART */
+ ldr w3, [x0, #USART_CR1]
+ mov w4, #USART_CR1_UE
+ orr w3, w3, w4
+ str w3, [x0, #USART_CR1]
+ /* Check TEACK bit */
+ mov w2, #USART_TIMEOUT
+teack_loop:
+ subs w2, w2, #1
+ beq core_init_fail
+ ldr w3, [x0, #USART_ISR]
+ tst w3, #USART_ISR_TEACK
+ beq teack_loop
+1:
+ mov w0, #1
+ ret
+core_init_fail:
+ mov w0, wzr
+ ret
+endfunc console_stm32_core_init
+
+ .globl console_stm32_register
+
+ /* -------------------------------------------------------
+ * int console_stm32_register(uintptr_t baseaddr,
+ * uint32_t clock, uint32_t baud,
+ * console_t *console);
+ * Function to initialize and register a new STM32
+ * console. Storage passed in for the console struct
+ * *must* be persistent (i.e. not from the stack).
+ * In: x0 - UART register base address
+ * w1 - UART clock in Hz
+ * w2 - Baud rate
+ * x3 - pointer to empty console_t struct
+ * Out: return 1 on success, 0 on error
+ * Clobber list : x0, x1, x2, x6, x7, x14
+ * -------------------------------------------------------
+ */
+func console_stm32_register
+ mov x7, x30
+ mov x6, x3
+ cbz x6, register_fail
+ str x0, [x6, #CONSOLE_T_BASE]
+
+ bl console_stm32_core_init
+ cbz x0, register_fail
+
+ mov x0, x6
+ mov x30, x7
+ finish_console_register stm32 putc=1, getc=0, flush=1
+
+register_fail:
+ ret x7
+endfunc console_stm32_register
+
+ /* --------------------------------------------------------
+ * int console_stm32_core_putc(int c, uintptr_t base_addr)
+ * Function to output a character over the console. It
+ * returns the character printed on success or -1 on error.
+ * In : w0 - character to be printed
+ * x1 - console base address
+ * Out : return -1 on error else return character.
+ * Clobber list : x2
+ * --------------------------------------------------------
+ */
+func console_stm32_core_putc
+#if ENABLE_ASSERTIONS
+ cmp x1, #0
+ ASM_ASSERT(ne)
+#endif /* ENABLE_ASSERTIONS */
+
+ /* Check Transmit Data Register Empty */
+txe_loop:
+ ldr w2, [x1, #USART_ISR]
+ tst w2, #USART_ISR_TXE
+ beq txe_loop
+ str w0, [x1, #USART_TDR]
+ /* Check transmit complete flag */
+tc_loop:
+ ldr w2, [x1, #USART_ISR]
+ tst w2, #USART_ISR_TC
+ beq tc_loop
+ ret
+endfunc console_stm32_core_putc
+
+ /* --------------------------------------------------------
+ * int console_stm32_putc(int c, console_t *console)
+ * Function to output a character over the console. It
+ * returns the character printed on success or -1 on error.
+ * In : w0 - character to be printed
+ * x1 - pointer to console_t structure
+ * Out : return -1 on error else return character.
+ * Clobber list : x2
+ * --------------------------------------------------------
+ */
+func console_stm32_putc
+#if ENABLE_ASSERTIONS
+ cmp x1, #0
+ ASM_ASSERT(ne)
+#endif /* ENABLE_ASSERTIONS */
+ ldr x1, [x1, #CONSOLE_T_BASE]
+ b console_stm32_core_putc
+endfunc console_stm32_putc
+
+ /* ---------------------------------------------
+ * int console_stm32_core_getc(uintptr_t base_addr)
+ * Function to get a character from the console.
+ * It returns the character grabbed on success
+ * or -1 if no character is available.
+ * In : x0 - console base address
+ * Out: w0 - character if available, else -1
+ * Clobber list : x0, x1
+ * ---------------------------------------------
+ */
+func console_stm32_core_getc
+ /* Not supported */
+ mov w0, #-1
+ ret
+endfunc console_stm32_core_getc
+
+ /* ---------------------------------------------
+ * int console_stm32_core_flush(uintptr_t base_addr)
+ * Function to force a write of all buffered
+ * data that hasn't been output.
+ * In : x0 - console base address
+ * Out : return -1 on error else return 0.
+ * Clobber list : x0, x1
+ * ---------------------------------------------
+ */
+func console_stm32_core_flush
+#if ENABLE_ASSERTIONS
+ cmp x0, #0
+ ASM_ASSERT(ne)
+#endif /* ENABLE_ASSERTIONS */
+ /* Check Transmit Data Register Empty */
+txe_loop_3:
+ ldr w1, [x0, #USART_ISR]
+ tst w1, #USART_ISR_TXE
+ beq txe_loop_3
+ mov w0, #0
+ ret
+endfunc console_stm32_core_flush
+
+ /* ---------------------------------------------
+ * int console_stm32_flush(console_t *console)
+ * Function to force a write of all buffered
+ * data that hasn't been output.
+ * In : x0 - pointer to console_t structure
+ * Out : return -1 on error else return 0.
+ * Clobber list : x0, x1
+ * ---------------------------------------------
+ */
+func console_stm32_flush
+#if ENABLE_ASSERTIONS
+ cmp x0, #0
+ ASM_ASSERT(ne)
+#endif /* ENABLE_ASSERTIONS */
+ ldr x0, [x0, #CONSOLE_T_BASE]
+ b console_stm32_core_flush
+endfunc console_stm32_flush
diff --git a/fdts/morello-fvp.dts b/fdts/morello-fvp.dts
index dc3df41..fda0f55 100644
--- a/fdts/morello-fvp.dts
+++ b/fdts/morello-fvp.dts
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020-2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2020-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -25,6 +25,32 @@
};
};
+ /*
+ * The timings below are just to demonstrate working cpuidle.
+ * These values may be inaccurate.
+ */
+ idle-states {
+ entry-method = "psci";
+
+ cluster_sleep: cluster-sleep {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x40000022>;
+ local-timer-stop;
+ entry-latency-us = <500>;
+ exit-latency-us = <1000>;
+ min-residency-us = <2500>;
+ };
+
+ cpu_sleep: cpu-sleep {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x40000002>;
+ local-timer-stop;
+ entry-latency-us = <150>;
+ exit-latency-us = <300>;
+ min-residency-us = <200>;
+ };
+ };
+
cpus {
#address-cells = <2>;
#size-cells = <0>;
@@ -53,6 +79,7 @@
device_type = "cpu";
enable-method = "psci";
clocks = <&scmi_dvfs 0>;
+ cpu-idle-states = <&cpu_sleep &cluster_sleep>;
};
CPU1: cpu1@100 {
compatible = "arm,armv8";
@@ -60,6 +87,7 @@
device_type = "cpu";
enable-method = "psci";
clocks = <&scmi_dvfs 0>;
+ cpu-idle-states = <&cpu_sleep &cluster_sleep>;
};
CPU2: cpu2@10000 {
compatible = "arm,armv8";
@@ -67,6 +95,7 @@
device_type = "cpu";
enable-method = "psci";
clocks = <&scmi_dvfs 1>;
+ cpu-idle-states = <&cpu_sleep &cluster_sleep>;
};
CPU3: cpu3@10100 {
compatible = "arm,armv8";
@@ -74,6 +103,7 @@
device_type = "cpu";
enable-method = "psci";
clocks = <&scmi_dvfs 1>;
+ cpu-idle-states = <&cpu_sleep &cluster_sleep>;
};
};
diff --git a/fdts/morello-soc.dts b/fdts/morello-soc.dts
index f207c06..fba904b 100644
--- a/fdts/morello-soc.dts
+++ b/fdts/morello-soc.dts
@@ -26,6 +26,32 @@
};
};
+ /*
+ * The timings below are just to demonstrate working cpuidle.
+ * These values may be inaccurate.
+ */
+ idle-states {
+ entry-method = "psci";
+
+ cluster_sleep: cluster-sleep {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x40000022>;
+ local-timer-stop;
+ entry-latency-us = <500>;
+ exit-latency-us = <1000>;
+ min-residency-us = <2500>;
+ };
+
+ cpu_sleep: cpu-sleep {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x40000002>;
+ local-timer-stop;
+ entry-latency-us = <150>;
+ exit-latency-us = <300>;
+ min-residency-us = <200>;
+ };
+ };
+
cpus {
#address-cells = <2>;
#size-cells = <0>;
@@ -44,6 +70,7 @@
1800000 750000
>;
#cooling-cells = <2>;
+ cpu-idle-states = <&cpu_sleep &cluster_sleep>;
};
cpu1: cpu1@100 {
compatible = "arm,armv8";
@@ -60,6 +87,7 @@
1800000 750000
>;
#cooling-cells = <2>;
+ cpu-idle-states = <&cpu_sleep &cluster_sleep>;
};
cpu2: cpu2@10000 {
compatible = "arm,armv8";
@@ -76,6 +104,7 @@
1800000 750000
>;
#cooling-cells = <2>;
+ cpu-idle-states = <&cpu_sleep &cluster_sleep>;
};
cpu3: cpu3@10100 {
compatible = "arm,armv8";
@@ -92,6 +121,7 @@
1800000 750000
>;
#cooling-cells = <2>;
+ cpu-idle-states = <&cpu_sleep &cluster_sleep>;
};
};
diff --git a/fdts/stm32mp25-bl2.dtsi b/fdts/stm32mp25-bl2.dtsi
new file mode 100644
index 0000000..7a6bbbe
--- /dev/null
+++ b/fdts/stm32mp25-bl2.dtsi
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
+ */
+
+/omit-if-no-ref/ &usart2_pins_a;
diff --git a/fdts/stm32mp25-pinctrl.dtsi b/fdts/stm32mp25-pinctrl.dtsi
new file mode 100644
index 0000000..8d0eaaf
--- /dev/null
+++ b/fdts/stm32mp25-pinctrl.dtsi
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+#include <dt-bindings/pinctrl/stm32-pinfunc.h>
+
+&pinctrl {
+ usart2_pins_a: usart2-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('A', 4, AF6)>; /* USART2_TX */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('A', 8, AF8)>; /* USART2_RX */
+ bias-disable;
+ };
+ };
+};
diff --git a/fdts/stm32mp251.dtsi b/fdts/stm32mp251.dtsi
new file mode 100644
index 0000000..821eb49
--- /dev/null
+++ b/fdts/stm32mp251.dtsi
@@ -0,0 +1,289 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+
+#include <dt-bindings/clock/stm32mp25-clks.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/reset/stm32mp25-resets.h>
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a35";
+ device_type = "cpu";
+ reg = <0>;
+ enable-method = "psci";
+ };
+ };
+
+ clocks {
+ clk_hse: clk-hse {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <48000000>;
+ };
+
+ clk_hsi: clk-hsi {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <64000000>;
+ };
+
+ clk_lse: clk-lse {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ };
+
+ clk_lsi: clk-lsi {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32000>;
+ };
+
+ clk_msi: clk-msi {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <16000000>;
+ };
+ };
+
+ intc: interrupt-controller@4ac00000 {
+ compatible = "arm,cortex-a7-gic";
+ #interrupt-cells = <3>;
+ #address-cells = <1>;
+ interrupt-controller;
+ reg = <0x0 0x4ac10000 0x0 0x1000>,
+ <0x0 0x4ac20000 0x0 0x2000>,
+ <0x0 0x4ac40000 0x0 0x2000>,
+ <0x0 0x4ac60000 0x0 0x2000>;
+ };
+
+ timer: timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&intc>;
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ always-on;
+ };
+
+ soc@0 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&intc>;
+ ranges = <0x0 0x0 0x0 0x80000000>;
+
+ rifsc: rifsc@42080000 {
+ compatible = "st,stm32mp25-rifsc";
+ reg = <0x42080000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ usart2: serial@400e0000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x400e0000 0x400>;
+ clocks = <&rcc CK_KER_USART2>;
+ resets = <&rcc USART2_R>;
+ status = "disabled";
+ };
+ };
+
+ rcc: rcc@44200000 {
+ compatible = "st,stm32mp25-rcc";
+ reg = <0x44200000 0x10000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ pwr: pwr@44210000 {
+ compatible = "st,stm32mp25-pwr";
+ reg = <0x44210000 0x400>;
+
+ vddio1: vddio1 {
+ regulator-name = "vddio1";
+ };
+
+ vddio2: vddio2 {
+ regulator-name = "vddio2";
+ };
+
+ vddio3: vddio3 {
+ regulator-name = "vddio3";
+ };
+
+ vddio4: vddio4 {
+ regulator-name = "vddio4";
+ };
+
+ vddio: vddio {
+ regulator-name = "vddio";
+ };
+ };
+
+ syscfg: syscon@44230000 {
+ compatible = "st,stm32mp25-syscfg", "syscon";
+ reg = <0x44230000 0x10000>;
+ };
+
+ pinctrl: pinctrl@44240000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,stm32mp257-pinctrl";
+ ranges = <0 0x44240000 0xa0400>;
+ pins-are-numbered;
+
+ gpioa: gpio@44240000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x0 0x400>;
+ clocks = <&rcc CK_BUS_GPIOA>;
+ st,bank-name = "GPIOA";
+ status = "disabled";
+ };
+
+ gpiob: gpio@44250000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x10000 0x400>;
+ clocks = <&rcc CK_BUS_GPIOB>;
+ st,bank-name = "GPIOB";
+ status = "disabled";
+ };
+
+ gpioc: gpio@44260000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x20000 0x400>;
+ clocks = <&rcc CK_BUS_GPIOC>;
+ st,bank-name = "GPIOC";
+ status = "disabled";
+ };
+
+ gpiod: gpio@44270000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x30000 0x400>;
+ clocks = <&rcc CK_BUS_GPIOD>;
+ st,bank-name = "GPIOD";
+ status = "disabled";
+ };
+
+ gpioe: gpio@44280000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x40000 0x400>;
+ clocks = <&rcc CK_BUS_GPIOE>;
+ st,bank-name = "GPIOE";
+ status = "disabled";
+ };
+
+ gpiof: gpio@44290000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x50000 0x400>;
+ clocks = <&rcc CK_BUS_GPIOF>;
+ st,bank-name = "GPIOF";
+ status = "disabled";
+ };
+
+ gpiog: gpio@442a0000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x60000 0x400>;
+ clocks = <&rcc CK_BUS_GPIOG>;
+ st,bank-name = "GPIOG";
+ status = "disabled";
+ };
+
+ gpioh: gpio@442b0000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x70000 0x400>;
+ clocks = <&rcc CK_BUS_GPIOH>;
+ st,bank-name = "GPIOH";
+ status = "disabled";
+ };
+
+ gpioi: gpio@442c0000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x80000 0x400>;
+ clocks = <&rcc CK_BUS_GPIOI>;
+ st,bank-name = "GPIOI";
+ status = "disabled";
+ };
+
+ gpioj: gpio@442d0000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x90000 0x400>;
+ clocks = <&rcc CK_BUS_GPIOJ>;
+ st,bank-name = "GPIOJ";
+ status = "disabled";
+ };
+
+ gpiok: gpio@442e0000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0xa0000 0x400>;
+ clocks = <&rcc CK_BUS_GPIOK>;
+ st,bank-name = "GPIOK";
+ status = "disabled";
+ };
+ };
+
+ pinctrl_z: pinctrl@46200000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,stm32mp257-z-pinctrl";
+ ranges = <0 0x46200000 0x400>;
+ pins-are-numbered;
+
+ gpioz: gpio@46200000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0 0x400>;
+ clocks = <&rcc CK_BUS_GPIOZ>;
+ st,bank-name = "GPIOZ";
+ st,bank-ioport = <11>;
+ status = "disabled";
+ };
+
+ };
+ };
+};
diff --git a/fdts/stm32mp253.dtsi b/fdts/stm32mp253.dtsi
new file mode 100644
index 0000000..cc7dad5
--- /dev/null
+++ b/fdts/stm32mp253.dtsi
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+#include "stm32mp251.dtsi"
diff --git a/fdts/stm32mp255.dtsi b/fdts/stm32mp255.dtsi
new file mode 100644
index 0000000..14164ce
--- /dev/null
+++ b/fdts/stm32mp255.dtsi
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+#include "stm32mp253.dtsi"
+
+/ {
+};
diff --git a/fdts/stm32mp257.dtsi b/fdts/stm32mp257.dtsi
new file mode 100644
index 0000000..a8c9f51
--- /dev/null
+++ b/fdts/stm32mp257.dtsi
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+#include "stm32mp255.dtsi"
+
+/ {
+};
diff --git a/fdts/stm32mp257f-ev1.dts b/fdts/stm32mp257f-ev1.dts
new file mode 100644
index 0000000..916d1e2
--- /dev/null
+++ b/fdts/stm32mp257f-ev1.dts
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+
+/dts-v1/;
+
+#include "stm32mp257.dtsi"
+#include "stm32mp25xf.dtsi"
+#include "stm32mp25-pinctrl.dtsi"
+#include "stm32mp25xxai-pinctrl.dtsi"
+
+/ {
+ model = "STMicroelectronics STM32MP257F-EV1 Evaluation Board";
+ compatible = "st,stm32mp257f-ev1", "st,stm32mp257";
+
+ aliases {
+ serial0 = &usart2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x1 0x00000000>;
+ };
+};
+
+&usart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&usart2_pins_a>;
+ status = "okay";
+};
diff --git a/fdts/stm32mp25xc.dtsi b/fdts/stm32mp25xc.dtsi
new file mode 100644
index 0000000..8afb685
--- /dev/null
+++ b/fdts/stm32mp25xc.dtsi
@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+
+/ {
+};
diff --git a/fdts/stm32mp25xf.dtsi b/fdts/stm32mp25xf.dtsi
new file mode 100644
index 0000000..8afb685
--- /dev/null
+++ b/fdts/stm32mp25xf.dtsi
@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+
+/ {
+};
diff --git a/fdts/stm32mp25xxai-pinctrl.dtsi b/fdts/stm32mp25xxai-pinctrl.dtsi
new file mode 100644
index 0000000..d6e47f5
--- /dev/null
+++ b/fdts/stm32mp25xxai-pinctrl.dtsi
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+
+&pinctrl {
+ gpioa: gpio@44240000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 0 16>;
+ };
+
+ gpiob: gpio@44250000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 16 16>;
+ };
+
+ gpioc: gpio@44260000 {
+ status = "okay";
+ ngpios = <14>;
+ gpio-ranges = <&pinctrl 0 32 14>;
+ };
+
+ gpiod: gpio@44270000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 48 16>;
+ };
+
+ gpioe: gpio@44280000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 64 16>;
+ };
+
+ gpiof: gpio@44290000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 80 16>;
+ };
+
+ gpiog: gpio@442a0000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 96 16>;
+ };
+
+ gpioh: gpio@442b0000 {
+ status = "okay";
+ ngpios = <12>;
+ gpio-ranges = <&pinctrl 2 114 12>;
+ };
+
+ gpioi: gpio@442c0000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 128 16>;
+ };
+
+ gpioj: gpio@442d0000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 144 16>;
+ };
+
+ gpiok: gpio@442e0000 {
+ status = "okay";
+ ngpios = <8>;
+ gpio-ranges = <&pinctrl 0 160 8>;
+ };
+};
+
+&pinctrl_z {
+ gpioz: gpio@46200000 {
+ status = "okay";
+ ngpios = <10>;
+ gpio-ranges = <&pinctrl_z 0 400 10>;
+ };
+};
diff --git a/fdts/stm32mp25xxak-pinctrl.dtsi b/fdts/stm32mp25xxak-pinctrl.dtsi
new file mode 100644
index 0000000..0ae46e9
--- /dev/null
+++ b/fdts/stm32mp25xxak-pinctrl.dtsi
@@ -0,0 +1,69 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+
+&pinctrl {
+ gpioa: gpio@44240000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 0 16>;
+ };
+
+ gpiob: gpio@44250000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 16 16>;
+ };
+
+ gpioc: gpio@44260000 {
+ status = "okay";
+ ngpios = <14>;
+ gpio-ranges = <&pinctrl 0 32 14>;
+ };
+
+ gpiod: gpio@44270000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 48 16>;
+ };
+
+ gpioe: gpio@44280000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 64 16>;
+ };
+
+ gpiof: gpio@44290000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 80 16>;
+ };
+
+ gpiog: gpio@442a0000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 96 16>;
+ };
+
+ gpioh: gpio@442b0000 {
+ status = "okay";
+ ngpios = <12>;
+ gpio-ranges = <&pinctrl 2 114 12>;
+ };
+
+ gpioi: gpio@442c0000 {
+ status = "okay";
+ ngpios = <12>;
+ gpio-ranges = <&pinctrl 0 128 12>;
+ };
+};
+
+&pinctrl_z {
+ gpioz: gpio@46200000 {
+ status = "okay";
+ ngpios = <10>;
+ gpio-ranges = <&pinctrl_z 0 400 10>;
+ };
+};
diff --git a/fdts/stm32mp25xxal-pinctrl.dtsi b/fdts/stm32mp25xxal-pinctrl.dtsi
new file mode 100644
index 0000000..0ae46e9
--- /dev/null
+++ b/fdts/stm32mp25xxal-pinctrl.dtsi
@@ -0,0 +1,69 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+
+&pinctrl {
+ gpioa: gpio@44240000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 0 16>;
+ };
+
+ gpiob: gpio@44250000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 16 16>;
+ };
+
+ gpioc: gpio@44260000 {
+ status = "okay";
+ ngpios = <14>;
+ gpio-ranges = <&pinctrl 0 32 14>;
+ };
+
+ gpiod: gpio@44270000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 48 16>;
+ };
+
+ gpioe: gpio@44280000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 64 16>;
+ };
+
+ gpiof: gpio@44290000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 80 16>;
+ };
+
+ gpiog: gpio@442a0000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 96 16>;
+ };
+
+ gpioh: gpio@442b0000 {
+ status = "okay";
+ ngpios = <12>;
+ gpio-ranges = <&pinctrl 2 114 12>;
+ };
+
+ gpioi: gpio@442c0000 {
+ status = "okay";
+ ngpios = <12>;
+ gpio-ranges = <&pinctrl 0 128 12>;
+ };
+};
+
+&pinctrl_z {
+ gpioz: gpio@46200000 {
+ status = "okay";
+ ngpios = <10>;
+ gpio-ranges = <&pinctrl_z 0 400 10>;
+ };
+};
diff --git a/include/drivers/cadence/cdns_uart.h b/include/drivers/cadence/cdns_uart.h
index 30ca910..327c1d9 100644
--- a/include/drivers/cadence/cdns_uart.h
+++ b/include/drivers/cadence/cdns_uart.h
@@ -22,6 +22,7 @@
#define UART_SR_INTR_REMPTY_BIT 1
#define UART_SR_INTR_TFUL_BIT 4
#define UART_SR_INTR_TEMPTY_BIT 3
+#define UART_SR_INTR_TACTIVE_BIT 11
#define R_UART_TX 0x30
#define R_UART_RX 0x30
diff --git a/include/drivers/st/stm32mp25_rcc.h b/include/drivers/st/stm32mp25_rcc.h
new file mode 100644
index 0000000..9dd25f3
--- /dev/null
+++ b/include/drivers/st/stm32mp25_rcc.h
@@ -0,0 +1,4986 @@
+/*
+ * Copyright (c) 2023, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef STM32MP2_RCC_H
+#define STM32MP2_RCC_H
+
+#include <lib/utils_def.h>
+
+#define RCC_SECCFGR0 U(0x0)
+#define RCC_SECCFGR1 U(0x4)
+#define RCC_SECCFGR2 U(0x8)
+#define RCC_SECCFGR3 U(0xC)
+#define RCC_PRIVCFGR0 U(0x10)
+#define RCC_PRIVCFGR1 U(0x14)
+#define RCC_PRIVCFGR2 U(0x18)
+#define RCC_PRIVCFGR3 U(0x1C)
+#define RCC_RCFGLOCKR0 U(0x20)
+#define RCC_RCFGLOCKR1 U(0x24)
+#define RCC_RCFGLOCKR2 U(0x28)
+#define RCC_RCFGLOCKR3 U(0x2C)
+#define RCC_R0CIDCFGR U(0x30)
+#define RCC_R0SEMCR U(0x34)
+#define RCC_R1CIDCFGR U(0x38)
+#define RCC_R1SEMCR U(0x3C)
+#define RCC_R2CIDCFGR U(0x40)
+#define RCC_R2SEMCR U(0x44)
+#define RCC_R3CIDCFGR U(0x48)
+#define RCC_R3SEMCR U(0x4C)
+#define RCC_R4CIDCFGR U(0x50)
+#define RCC_R4SEMCR U(0x54)
+#define RCC_R5CIDCFGR U(0x58)
+#define RCC_R5SEMCR U(0x5C)
+#define RCC_R6CIDCFGR U(0x60)
+#define RCC_R6SEMCR U(0x64)
+#define RCC_R7CIDCFGR U(0x68)
+#define RCC_R7SEMCR U(0x6C)
+#define RCC_R8CIDCFGR U(0x70)
+#define RCC_R8SEMCR U(0x74)
+#define RCC_R9CIDCFGR U(0x78)
+#define RCC_R9SEMCR U(0x7C)
+#define RCC_R10CIDCFGR U(0x80)
+#define RCC_R10SEMCR U(0x84)
+#define RCC_R11CIDCFGR U(0x88)
+#define RCC_R11SEMCR U(0x8C)
+#define RCC_R12CIDCFGR U(0x90)
+#define RCC_R12SEMCR U(0x94)
+#define RCC_R13CIDCFGR U(0x98)
+#define RCC_R13SEMCR U(0x9C)
+#define RCC_R14CIDCFGR U(0xA0)
+#define RCC_R14SEMCR U(0xA4)
+#define RCC_R15CIDCFGR U(0xA8)
+#define RCC_R15SEMCR U(0xAC)
+#define RCC_R16CIDCFGR U(0xB0)
+#define RCC_R16SEMCR U(0xB4)
+#define RCC_R17CIDCFGR U(0xB8)
+#define RCC_R17SEMCR U(0xBC)
+#define RCC_R18CIDCFGR U(0xC0)
+#define RCC_R18SEMCR U(0xC4)
+#define RCC_R19CIDCFGR U(0xC8)
+#define RCC_R19SEMCR U(0xCC)
+#define RCC_R20CIDCFGR U(0xD0)
+#define RCC_R20SEMCR U(0xD4)
+#define RCC_R21CIDCFGR U(0xD8)
+#define RCC_R21SEMCR U(0xDC)
+#define RCC_R22CIDCFGR U(0xE0)
+#define RCC_R22SEMCR U(0xE4)
+#define RCC_R23CIDCFGR U(0xE8)
+#define RCC_R23SEMCR U(0xEC)
+#define RCC_R24CIDCFGR U(0xF0)
+#define RCC_R24SEMCR U(0xF4)
+#define RCC_R25CIDCFGR U(0xF8)
+#define RCC_R25SEMCR U(0xFC)
+#define RCC_R26CIDCFGR U(0x100)
+#define RCC_R26SEMCR U(0x104)
+#define RCC_R27CIDCFGR U(0x108)
+#define RCC_R27SEMCR U(0x10C)
+#define RCC_R28CIDCFGR U(0x110)
+#define RCC_R28SEMCR U(0x114)
+#define RCC_R29CIDCFGR U(0x118)
+#define RCC_R29SEMCR U(0x11C)
+#define RCC_R30CIDCFGR U(0x120)
+#define RCC_R30SEMCR U(0x124)
+#define RCC_R31CIDCFGR U(0x128)
+#define RCC_R31SEMCR U(0x12C)
+#define RCC_R32CIDCFGR U(0x130)
+#define RCC_R32SEMCR U(0x134)
+#define RCC_R33CIDCFGR U(0x138)
+#define RCC_R33SEMCR U(0x13C)
+#define RCC_R34CIDCFGR U(0x140)
+#define RCC_R34SEMCR U(0x144)
+#define RCC_R35CIDCFGR U(0x148)
+#define RCC_R35SEMCR U(0x14C)
+#define RCC_R36CIDCFGR U(0x150)
+#define RCC_R36SEMCR U(0x154)
+#define RCC_R37CIDCFGR U(0x158)
+#define RCC_R37SEMCR U(0x15C)
+#define RCC_R38CIDCFGR U(0x160)
+#define RCC_R38SEMCR U(0x164)
+#define RCC_R39CIDCFGR U(0x168)
+#define RCC_R39SEMCR U(0x16C)
+#define RCC_R40CIDCFGR U(0x170)
+#define RCC_R40SEMCR U(0x174)
+#define RCC_R41CIDCFGR U(0x178)
+#define RCC_R41SEMCR U(0x17C)
+#define RCC_R42CIDCFGR U(0x180)
+#define RCC_R42SEMCR U(0x184)
+#define RCC_R43CIDCFGR U(0x188)
+#define RCC_R43SEMCR U(0x18C)
+#define RCC_R44CIDCFGR U(0x190)
+#define RCC_R44SEMCR U(0x194)
+#define RCC_R45CIDCFGR U(0x198)
+#define RCC_R45SEMCR U(0x19C)
+#define RCC_R46CIDCFGR U(0x1A0)
+#define RCC_R46SEMCR U(0x1A4)
+#define RCC_R47CIDCFGR U(0x1A8)
+#define RCC_R47SEMCR U(0x1AC)
+#define RCC_R48CIDCFGR U(0x1B0)
+#define RCC_R48SEMCR U(0x1B4)
+#define RCC_R49CIDCFGR U(0x1B8)
+#define RCC_R49SEMCR U(0x1BC)
+#define RCC_R50CIDCFGR U(0x1C0)
+#define RCC_R50SEMCR U(0x1C4)
+#define RCC_R51CIDCFGR U(0x1C8)
+#define RCC_R51SEMCR U(0x1CC)
+#define RCC_R52CIDCFGR U(0x1D0)
+#define RCC_R52SEMCR U(0x1D4)
+#define RCC_R53CIDCFGR U(0x1D8)
+#define RCC_R53SEMCR U(0x1DC)
+#define RCC_R54CIDCFGR U(0x1E0)
+#define RCC_R54SEMCR U(0x1E4)
+#define RCC_R55CIDCFGR U(0x1E8)
+#define RCC_R55SEMCR U(0x1EC)
+#define RCC_R56CIDCFGR U(0x1F0)
+#define RCC_R56SEMCR U(0x1F4)
+#define RCC_R57CIDCFGR U(0x1F8)
+#define RCC_R57SEMCR U(0x1FC)
+#define RCC_R58CIDCFGR U(0x200)
+#define RCC_R58SEMCR U(0x204)
+#define RCC_R59CIDCFGR U(0x208)
+#define RCC_R59SEMCR U(0x20C)
+#define RCC_R60CIDCFGR U(0x210)
+#define RCC_R60SEMCR U(0x214)
+#define RCC_R61CIDCFGR U(0x218)
+#define RCC_R61SEMCR U(0x21C)
+#define RCC_R62CIDCFGR U(0x220)
+#define RCC_R62SEMCR U(0x224)
+#define RCC_R63CIDCFGR U(0x228)
+#define RCC_R63SEMCR U(0x22C)
+#define RCC_R64CIDCFGR U(0x230)
+#define RCC_R64SEMCR U(0x234)
+#define RCC_R65CIDCFGR U(0x238)
+#define RCC_R65SEMCR U(0x23C)
+#define RCC_R66CIDCFGR U(0x240)
+#define RCC_R66SEMCR U(0x244)
+#define RCC_R67CIDCFGR U(0x248)
+#define RCC_R67SEMCR U(0x24C)
+#define RCC_R68CIDCFGR U(0x250)
+#define RCC_R68SEMCR U(0x254)
+#define RCC_R69CIDCFGR U(0x258)
+#define RCC_R69SEMCR U(0x25C)
+#define RCC_R70CIDCFGR U(0x260)
+#define RCC_R70SEMCR U(0x264)
+#define RCC_R71CIDCFGR U(0x268)
+#define RCC_R71SEMCR U(0x26C)
+#define RCC_R72CIDCFGR U(0x270)
+#define RCC_R72SEMCR U(0x274)
+#define RCC_R73CIDCFGR U(0x278)
+#define RCC_R73SEMCR U(0x27C)
+#define RCC_R74CIDCFGR U(0x280)
+#define RCC_R74SEMCR U(0x284)
+#define RCC_R75CIDCFGR U(0x288)
+#define RCC_R75SEMCR U(0x28C)
+#define RCC_R76CIDCFGR U(0x290)
+#define RCC_R76SEMCR U(0x294)
+#define RCC_R77CIDCFGR U(0x298)
+#define RCC_R77SEMCR U(0x29C)
+#define RCC_R78CIDCFGR U(0x2A0)
+#define RCC_R78SEMCR U(0x2A4)
+#define RCC_R79CIDCFGR U(0x2A8)
+#define RCC_R79SEMCR U(0x2AC)
+#define RCC_R80CIDCFGR U(0x2B0)
+#define RCC_R80SEMCR U(0x2B4)
+#define RCC_R81CIDCFGR U(0x2B8)
+#define RCC_R81SEMCR U(0x2BC)
+#define RCC_R82CIDCFGR U(0x2C0)
+#define RCC_R82SEMCR U(0x2C4)
+#define RCC_R83CIDCFGR U(0x2C8)
+#define RCC_R83SEMCR U(0x2CC)
+#define RCC_R84CIDCFGR U(0x2D0)
+#define RCC_R84SEMCR U(0x2D4)
+#define RCC_R85CIDCFGR U(0x2D8)
+#define RCC_R85SEMCR U(0x2DC)
+#define RCC_R86CIDCFGR U(0x2E0)
+#define RCC_R86SEMCR U(0x2E4)
+#define RCC_R87CIDCFGR U(0x2E8)
+#define RCC_R87SEMCR U(0x2EC)
+#define RCC_R88CIDCFGR U(0x2F0)
+#define RCC_R88SEMCR U(0x2F4)
+#define RCC_R89CIDCFGR U(0x2F8)
+#define RCC_R89SEMCR U(0x2FC)
+#define RCC_R90CIDCFGR U(0x300)
+#define RCC_R90SEMCR U(0x304)
+#define RCC_R91CIDCFGR U(0x308)
+#define RCC_R91SEMCR U(0x30C)
+#define RCC_R92CIDCFGR U(0x310)
+#define RCC_R92SEMCR U(0x314)
+#define RCC_R93CIDCFGR U(0x318)
+#define RCC_R93SEMCR U(0x31C)
+#define RCC_R94CIDCFGR U(0x320)
+#define RCC_R94SEMCR U(0x324)
+#define RCC_R95CIDCFGR U(0x328)
+#define RCC_R95SEMCR U(0x32C)
+#define RCC_R96CIDCFGR U(0x330)
+#define RCC_R96SEMCR U(0x334)
+#define RCC_R97CIDCFGR U(0x338)
+#define RCC_R97SEMCR U(0x33C)
+#define RCC_R98CIDCFGR U(0x340)
+#define RCC_R98SEMCR U(0x344)
+#define RCC_R99CIDCFGR U(0x348)
+#define RCC_R99SEMCR U(0x34C)
+#define RCC_R100CIDCFGR U(0x350)
+#define RCC_R100SEMCR U(0x354)
+#define RCC_R101CIDCFGR U(0x358)
+#define RCC_R101SEMCR U(0x35C)
+#define RCC_R102CIDCFGR U(0x360)
+#define RCC_R102SEMCR U(0x364)
+#define RCC_R103CIDCFGR U(0x368)
+#define RCC_R103SEMCR U(0x36C)
+#define RCC_R104CIDCFGR U(0x370)
+#define RCC_R104SEMCR U(0x374)
+#define RCC_R105CIDCFGR U(0x378)
+#define RCC_R105SEMCR U(0x37C)
+#define RCC_R106CIDCFGR U(0x380)
+#define RCC_R106SEMCR U(0x384)
+#define RCC_R107CIDCFGR U(0x388)
+#define RCC_R107SEMCR U(0x38C)
+#define RCC_R108CIDCFGR U(0x390)
+#define RCC_R108SEMCR U(0x394)
+#define RCC_R109CIDCFGR U(0x398)
+#define RCC_R109SEMCR U(0x39C)
+#define RCC_R110CIDCFGR U(0x3A0)
+#define RCC_R110SEMCR U(0x3A4)
+#define RCC_R111CIDCFGR U(0x3A8)
+#define RCC_R111SEMCR U(0x3AC)
+#define RCC_R112CIDCFGR U(0x3B0)
+#define RCC_R112SEMCR U(0x3B4)
+#define RCC_R113CIDCFGR U(0x3B8)
+#define RCC_R113SEMCR U(0x3BC)
+#define RCC_GRSTCSETR U(0x400)
+#define RCC_C1RSTCSETR U(0x404)
+#define RCC_C1P1RSTCSETR U(0x408)
+#define RCC_C2RSTCSETR U(0x40C)
+#define RCC_HWRSTSCLRR U(0x410)
+#define RCC_C1HWRSTSCLRR U(0x414)
+#define RCC_C2HWRSTSCLRR U(0x418)
+#define RCC_C1BOOTRSTSSETR U(0x41C)
+#define RCC_C1BOOTRSTSCLRR U(0x420)
+#define RCC_C2BOOTRSTSSETR U(0x424)
+#define RCC_C2BOOTRSTSCLRR U(0x428)
+#define RCC_C1SREQSETR U(0x42C)
+#define RCC_C1SREQCLRR U(0x430)
+#define RCC_CPUBOOTCR U(0x434)
+#define RCC_STBYBOOTCR U(0x438)
+#define RCC_LEGBOOTCR U(0x43C)
+#define RCC_BDCR U(0x440)
+#define RCC_D3DCR U(0x444)
+#define RCC_D3DSR U(0x448)
+#define RCC_RDCR U(0x44C)
+#define RCC_C1MSRDCR U(0x450)
+#define RCC_PWRLPDLYCR U(0x454)
+#define RCC_C1CIESETR U(0x458)
+#define RCC_C1CIFCLRR U(0x45C)
+#define RCC_C2CIESETR U(0x460)
+#define RCC_C2CIFCLRR U(0x464)
+#define RCC_IWDGC1FZSETR U(0x468)
+#define RCC_IWDGC1FZCLRR U(0x46C)
+#define RCC_IWDGC1CFGSETR U(0x470)
+#define RCC_IWDGC1CFGCLRR U(0x474)
+#define RCC_IWDGC2FZSETR U(0x478)
+#define RCC_IWDGC2FZCLRR U(0x47C)
+#define RCC_IWDGC2CFGSETR U(0x480)
+#define RCC_IWDGC2CFGCLRR U(0x484)
+#define RCC_IWDGC3CFGSETR U(0x488)
+#define RCC_IWDGC3CFGCLRR U(0x48C)
+#define RCC_C3CFGR U(0x490)
+#define RCC_MCO1CFGR U(0x494)
+#define RCC_MCO2CFGR U(0x498)
+#define RCC_OCENSETR U(0x49C)
+#define RCC_OCENCLRR U(0x4A0)
+#define RCC_OCRDYR U(0x4A4)
+#define RCC_HSICFGR U(0x4A8)
+#define RCC_CSICFGR U(0x4AC)
+#define RCC_RTCDIVR U(0x4B0)
+#define RCC_APB1DIVR U(0x4B4)
+#define RCC_APB2DIVR U(0x4B8)
+#define RCC_APB3DIVR U(0x4BC)
+#define RCC_APB4DIVR U(0x4C0)
+#define RCC_APBDBGDIVR U(0x4C4)
+#define RCC_TIMG1PRER U(0x4C8)
+#define RCC_TIMG2PRER U(0x4CC)
+#define RCC_LSMCUDIVR U(0x4D0)
+#define RCC_DDRCPCFGR U(0x4D4)
+#define RCC_DDRCAPBCFGR U(0x4D8)
+#define RCC_DDRPHYCAPBCFGR U(0x4DC)
+#define RCC_DDRPHYCCFGR U(0x4E0)
+#define RCC_DDRCFGR U(0x4E4)
+#define RCC_DDRITFCFGR U(0x4E8)
+#define RCC_SYSRAMCFGR U(0x4F0)
+#define RCC_VDERAMCFGR U(0x4F4)
+#define RCC_SRAM1CFGR U(0x4F8)
+#define RCC_SRAM2CFGR U(0x4FC)
+#define RCC_RETRAMCFGR U(0x500)
+#define RCC_BKPSRAMCFGR U(0x504)
+#define RCC_LPSRAM1CFGR U(0x508)
+#define RCC_LPSRAM2CFGR U(0x50C)
+#define RCC_LPSRAM3CFGR U(0x510)
+#define RCC_OSPI1CFGR U(0x514)
+#define RCC_OSPI2CFGR U(0x518)
+#define RCC_FMCCFGR U(0x51C)
+#define RCC_DBGCFGR U(0x520)
+#define RCC_STM500CFGR U(0x524)
+#define RCC_ETRCFGR U(0x528)
+#define RCC_GPIOACFGR U(0x52C)
+#define RCC_GPIOBCFGR U(0x530)
+#define RCC_GPIOCCFGR U(0x534)
+#define RCC_GPIODCFGR U(0x538)
+#define RCC_GPIOECFGR U(0x53C)
+#define RCC_GPIOFCFGR U(0x540)
+#define RCC_GPIOGCFGR U(0x544)
+#define RCC_GPIOHCFGR U(0x548)
+#define RCC_GPIOICFGR U(0x54C)
+#define RCC_GPIOJCFGR U(0x550)
+#define RCC_GPIOKCFGR U(0x554)
+#define RCC_GPIOZCFGR U(0x558)
+#define RCC_HPDMA1CFGR U(0x55C)
+#define RCC_HPDMA2CFGR U(0x560)
+#define RCC_HPDMA3CFGR U(0x564)
+#define RCC_LPDMACFGR U(0x568)
+#define RCC_HSEMCFGR U(0x56C)
+#define RCC_IPCC1CFGR U(0x570)
+#define RCC_IPCC2CFGR U(0x574)
+#define RCC_RTCCFGR U(0x578)
+#define RCC_SYSCPU1CFGR U(0x580)
+#define RCC_BSECCFGR U(0x584)
+#define RCC_IS2MCFGR U(0x58C)
+#define RCC_PLL2CFGR1 U(0x590)
+#define RCC_PLL2CFGR2 U(0x594)
+#define RCC_PLL2CFGR3 U(0x598)
+#define RCC_PLL2CFGR4 U(0x59C)
+#define RCC_PLL2CFGR5 U(0x5A0)
+#define RCC_PLL2CFGR6 U(0x5A8)
+#define RCC_PLL2CFGR7 U(0x5AC)
+#define RCC_PLL3CFGR1 U(0x5B8)
+#define RCC_PLL3CFGR2 U(0x5BC)
+#define RCC_PLL3CFGR3 U(0x5C0)
+#define RCC_PLL3CFGR4 U(0x5C4)
+#define RCC_PLL3CFGR5 U(0x5C8)
+#define RCC_PLL3CFGR6 U(0x5D0)
+#define RCC_PLL3CFGR7 U(0x5D4)
+#define RCC_HSIFMONCR U(0x5E0)
+#define RCC_HSIFVALR U(0x5E4)
+#define RCC_TIM1CFGR U(0x700)
+#define RCC_TIM2CFGR U(0x704)
+#define RCC_TIM3CFGR U(0x708)
+#define RCC_TIM4CFGR U(0x70C)
+#define RCC_TIM5CFGR U(0x710)
+#define RCC_TIM6CFGR U(0x714)
+#define RCC_TIM7CFGR U(0x718)
+#define RCC_TIM8CFGR U(0x71C)
+#define RCC_TIM10CFGR U(0x720)
+#define RCC_TIM11CFGR U(0x724)
+#define RCC_TIM12CFGR U(0x728)
+#define RCC_TIM13CFGR U(0x72C)
+#define RCC_TIM14CFGR U(0x730)
+#define RCC_TIM15CFGR U(0x734)
+#define RCC_TIM16CFGR U(0x738)
+#define RCC_TIM17CFGR U(0x73C)
+#define RCC_TIM20CFGR U(0x740)
+#define RCC_LPTIM1CFGR U(0x744)
+#define RCC_LPTIM2CFGR U(0x748)
+#define RCC_LPTIM3CFGR U(0x74C)
+#define RCC_LPTIM4CFGR U(0x750)
+#define RCC_LPTIM5CFGR U(0x754)
+#define RCC_SPI1CFGR U(0x758)
+#define RCC_SPI2CFGR U(0x75C)
+#define RCC_SPI3CFGR U(0x760)
+#define RCC_SPI4CFGR U(0x764)
+#define RCC_SPI5CFGR U(0x768)
+#define RCC_SPI6CFGR U(0x76C)
+#define RCC_SPI7CFGR U(0x770)
+#define RCC_SPI8CFGR U(0x774)
+#define RCC_SPDIFRXCFGR U(0x778)
+#define RCC_USART1CFGR U(0x77C)
+#define RCC_USART2CFGR U(0x780)
+#define RCC_USART3CFGR U(0x784)
+#define RCC_UART4CFGR U(0x788)
+#define RCC_UART5CFGR U(0x78C)
+#define RCC_USART6CFGR U(0x790)
+#define RCC_UART7CFGR U(0x794)
+#define RCC_UART8CFGR U(0x798)
+#define RCC_UART9CFGR U(0x79C)
+#define RCC_LPUART1CFGR U(0x7A0)
+#define RCC_I2C1CFGR U(0x7A4)
+#define RCC_I2C2CFGR U(0x7A8)
+#define RCC_I2C3CFGR U(0x7AC)
+#define RCC_I2C4CFGR U(0x7B0)
+#define RCC_I2C5CFGR U(0x7B4)
+#define RCC_I2C6CFGR U(0x7B8)
+#define RCC_I2C7CFGR U(0x7BC)
+#define RCC_I2C8CFGR U(0x7C0)
+#define RCC_SAI1CFGR U(0x7C4)
+#define RCC_SAI2CFGR U(0x7C8)
+#define RCC_SAI3CFGR U(0x7CC)
+#define RCC_SAI4CFGR U(0x7D0)
+#define RCC_MDF1CFGR U(0x7D8)
+#define RCC_ADF1CFGR U(0x7DC)
+#define RCC_FDCANCFGR U(0x7E0)
+#define RCC_HDPCFGR U(0x7E4)
+#define RCC_ADC12CFGR U(0x7E8)
+#define RCC_ADC3CFGR U(0x7EC)
+#define RCC_ETH1CFGR U(0x7F0)
+#define RCC_ETH2CFGR U(0x7F4)
+#define RCC_USB2CFGR U(0x7FC)
+#define RCC_USB2PHY1CFGR U(0x800)
+#define RCC_USB2PHY2CFGR U(0x804)
+#define RCC_USB3DRDCFGR U(0x808)
+#define RCC_USB3PCIEPHYCFGR U(0x80C)
+#define RCC_PCIECFGR U(0x810)
+#define RCC_USBTCCFGR U(0x814)
+#define RCC_ETHSWCFGR U(0x818)
+#define RCC_ETHSWACMCFGR U(0x81C)
+#define RCC_ETHSWACMMSGCFGR U(0x820)
+#define RCC_STGENCFGR U(0x824)
+#define RCC_SDMMC1CFGR U(0x830)
+#define RCC_SDMMC2CFGR U(0x834)
+#define RCC_SDMMC3CFGR U(0x838)
+#define RCC_GPUCFGR U(0x83C)
+#define RCC_LTDCCFGR U(0x840)
+#define RCC_DSICFGR U(0x844)
+#define RCC_LVDSCFGR U(0x850)
+#define RCC_CSI2CFGR U(0x858)
+#define RCC_DCMIPPCFGR U(0x85C)
+#define RCC_CCICFGR U(0x860)
+#define RCC_VDECCFGR U(0x864)
+#define RCC_VENCCFGR U(0x868)
+#define RCC_RNGCFGR U(0x870)
+#define RCC_PKACFGR U(0x874)
+#define RCC_SAESCFGR U(0x878)
+#define RCC_HASHCFGR U(0x87C)
+#define RCC_CRYP1CFGR U(0x880)
+#define RCC_CRYP2CFGR U(0x884)
+#define RCC_IWDG1CFGR U(0x888)
+#define RCC_IWDG2CFGR U(0x88C)
+#define RCC_IWDG3CFGR U(0x890)
+#define RCC_IWDG4CFGR U(0x894)
+#define RCC_IWDG5CFGR U(0x898)
+#define RCC_WWDG1CFGR U(0x89C)
+#define RCC_WWDG2CFGR U(0x8A0)
+#define RCC_BUSPERFMCFGR U(0x8A4)
+#define RCC_VREFCFGR U(0x8A8)
+#define RCC_TMPSENSCFGR U(0x8AC)
+#define RCC_CRCCFGR U(0x8B4)
+#define RCC_SERCCFGR U(0x8B8)
+#define RCC_OSPIIOMCFGR U(0x8BC)
+#define RCC_GICV2MCFGR U(0x8C0)
+#define RCC_I3C1CFGR U(0x8C8)
+#define RCC_I3C2CFGR U(0x8CC)
+#define RCC_I3C3CFGR U(0x8D0)
+#define RCC_I3C4CFGR U(0x8D4)
+#define RCC_MUXSELCFGR U(0x1000)
+#define RCC_XBAR0CFGR U(0x1018)
+#define RCC_XBAR1CFGR U(0x101C)
+#define RCC_XBAR2CFGR U(0x1020)
+#define RCC_XBAR3CFGR U(0x1024)
+#define RCC_XBAR4CFGR U(0x1028)
+#define RCC_XBAR5CFGR U(0x102C)
+#define RCC_XBAR6CFGR U(0x1030)
+#define RCC_XBAR7CFGR U(0x1034)
+#define RCC_XBAR8CFGR U(0x1038)
+#define RCC_XBAR9CFGR U(0x103C)
+#define RCC_XBAR10CFGR U(0x1040)
+#define RCC_XBAR11CFGR U(0x1044)
+#define RCC_XBAR12CFGR U(0x1048)
+#define RCC_XBAR13CFGR U(0x104C)
+#define RCC_XBAR14CFGR U(0x1050)
+#define RCC_XBAR15CFGR U(0x1054)
+#define RCC_XBAR16CFGR U(0x1058)
+#define RCC_XBAR17CFGR U(0x105C)
+#define RCC_XBAR18CFGR U(0x1060)
+#define RCC_XBAR19CFGR U(0x1064)
+#define RCC_XBAR20CFGR U(0x1068)
+#define RCC_XBAR21CFGR U(0x106C)
+#define RCC_XBAR22CFGR U(0x1070)
+#define RCC_XBAR23CFGR U(0x1074)
+#define RCC_XBAR24CFGR U(0x1078)
+#define RCC_XBAR25CFGR U(0x107C)
+#define RCC_XBAR26CFGR U(0x1080)
+#define RCC_XBAR27CFGR U(0x1084)
+#define RCC_XBAR28CFGR U(0x1088)
+#define RCC_XBAR29CFGR U(0x108C)
+#define RCC_XBAR30CFGR U(0x1090)
+#define RCC_XBAR31CFGR U(0x1094)
+#define RCC_XBAR32CFGR U(0x1098)
+#define RCC_XBAR33CFGR U(0x109C)
+#define RCC_XBAR34CFGR U(0x10A0)
+#define RCC_XBAR35CFGR U(0x10A4)
+#define RCC_XBAR36CFGR U(0x10A8)
+#define RCC_XBAR37CFGR U(0x10AC)
+#define RCC_XBAR38CFGR U(0x10B0)
+#define RCC_XBAR39CFGR U(0x10B4)
+#define RCC_XBAR40CFGR U(0x10B8)
+#define RCC_XBAR41CFGR U(0x10BC)
+#define RCC_XBAR42CFGR U(0x10C0)
+#define RCC_XBAR43CFGR U(0x10C4)
+#define RCC_XBAR44CFGR U(0x10C8)
+#define RCC_XBAR45CFGR U(0x10CC)
+#define RCC_XBAR46CFGR U(0x10D0)
+#define RCC_XBAR47CFGR U(0x10D4)
+#define RCC_XBAR48CFGR U(0x10D8)
+#define RCC_XBAR49CFGR U(0x10DC)
+#define RCC_XBAR50CFGR U(0x10E0)
+#define RCC_XBAR51CFGR U(0x10E4)
+#define RCC_XBAR52CFGR U(0x10E8)
+#define RCC_XBAR53CFGR U(0x10EC)
+#define RCC_XBAR54CFGR U(0x10F0)
+#define RCC_XBAR55CFGR U(0x10F4)
+#define RCC_XBAR56CFGR U(0x10F8)
+#define RCC_XBAR57CFGR U(0x10FC)
+#define RCC_XBAR58CFGR U(0x1100)
+#define RCC_XBAR59CFGR U(0x1104)
+#define RCC_XBAR60CFGR U(0x1108)
+#define RCC_XBAR61CFGR U(0x110C)
+#define RCC_XBAR62CFGR U(0x1110)
+#define RCC_XBAR63CFGR U(0x1114)
+#define RCC_PREDIV0CFGR U(0x1118)
+#define RCC_PREDIV1CFGR U(0x111C)
+#define RCC_PREDIV2CFGR U(0x1120)
+#define RCC_PREDIV3CFGR U(0x1124)
+#define RCC_PREDIV4CFGR U(0x1128)
+#define RCC_PREDIV5CFGR U(0x112C)
+#define RCC_PREDIV6CFGR U(0x1130)
+#define RCC_PREDIV7CFGR U(0x1134)
+#define RCC_PREDIV8CFGR U(0x1138)
+#define RCC_PREDIV9CFGR U(0x113C)
+#define RCC_PREDIV10CFGR U(0x1140)
+#define RCC_PREDIV11CFGR U(0x1144)
+#define RCC_PREDIV12CFGR U(0x1148)
+#define RCC_PREDIV13CFGR U(0x114C)
+#define RCC_PREDIV14CFGR U(0x1150)
+#define RCC_PREDIV15CFGR U(0x1154)
+#define RCC_PREDIV16CFGR U(0x1158)
+#define RCC_PREDIV17CFGR U(0x115C)
+#define RCC_PREDIV18CFGR U(0x1160)
+#define RCC_PREDIV19CFGR U(0x1164)
+#define RCC_PREDIV20CFGR U(0x1168)
+#define RCC_PREDIV21CFGR U(0x116C)
+#define RCC_PREDIV22CFGR U(0x1170)
+#define RCC_PREDIV23CFGR U(0x1174)
+#define RCC_PREDIV24CFGR U(0x1178)
+#define RCC_PREDIV25CFGR U(0x117C)
+#define RCC_PREDIV26CFGR U(0x1180)
+#define RCC_PREDIV27CFGR U(0x1184)
+#define RCC_PREDIV28CFGR U(0x1188)
+#define RCC_PREDIV29CFGR U(0x118C)
+#define RCC_PREDIV30CFGR U(0x1190)
+#define RCC_PREDIV31CFGR U(0x1194)
+#define RCC_PREDIV32CFGR U(0x1198)
+#define RCC_PREDIV33CFGR U(0x119C)
+#define RCC_PREDIV34CFGR U(0x11A0)
+#define RCC_PREDIV35CFGR U(0x11A4)
+#define RCC_PREDIV36CFGR U(0x11A8)
+#define RCC_PREDIV37CFGR U(0x11AC)
+#define RCC_PREDIV38CFGR U(0x11B0)
+#define RCC_PREDIV39CFGR U(0x11B4)
+#define RCC_PREDIV40CFGR U(0x11B8)
+#define RCC_PREDIV41CFGR U(0x11BC)
+#define RCC_PREDIV42CFGR U(0x11C0)
+#define RCC_PREDIV43CFGR U(0x11C4)
+#define RCC_PREDIV44CFGR U(0x11C8)
+#define RCC_PREDIV45CFGR U(0x11CC)
+#define RCC_PREDIV46CFGR U(0x11D0)
+#define RCC_PREDIV47CFGR U(0x11D4)
+#define RCC_PREDIV48CFGR U(0x11D8)
+#define RCC_PREDIV49CFGR U(0x11DC)
+#define RCC_PREDIV50CFGR U(0x11E0)
+#define RCC_PREDIV51CFGR U(0x11E4)
+#define RCC_PREDIV52CFGR U(0x11E8)
+#define RCC_PREDIV53CFGR U(0x11EC)
+#define RCC_PREDIV54CFGR U(0x11F0)
+#define RCC_PREDIV55CFGR U(0x11F4)
+#define RCC_PREDIV56CFGR U(0x11F8)
+#define RCC_PREDIV57CFGR U(0x11FC)
+#define RCC_PREDIV58CFGR U(0x1200)
+#define RCC_PREDIV59CFGR U(0x1204)
+#define RCC_PREDIV60CFGR U(0x1208)
+#define RCC_PREDIV61CFGR U(0x120C)
+#define RCC_PREDIV62CFGR U(0x1210)
+#define RCC_PREDIV63CFGR U(0x1214)
+#define RCC_PREDIVSR1 U(0x1218)
+#define RCC_PREDIVSR2 U(0x121C)
+#define RCC_FINDIV0CFGR U(0x1224)
+#define RCC_FINDIV1CFGR U(0x1228)
+#define RCC_FINDIV2CFGR U(0x122C)
+#define RCC_FINDIV3CFGR U(0x1230)
+#define RCC_FINDIV4CFGR U(0x1234)
+#define RCC_FINDIV5CFGR U(0x1238)
+#define RCC_FINDIV6CFGR U(0x123C)
+#define RCC_FINDIV7CFGR U(0x1240)
+#define RCC_FINDIV8CFGR U(0x1244)
+#define RCC_FINDIV9CFGR U(0x1248)
+#define RCC_FINDIV10CFGR U(0x124C)
+#define RCC_FINDIV11CFGR U(0x1250)
+#define RCC_FINDIV12CFGR U(0x1254)
+#define RCC_FINDIV13CFGR U(0x1258)
+#define RCC_FINDIV14CFGR U(0x125C)
+#define RCC_FINDIV15CFGR U(0x1260)
+#define RCC_FINDIV16CFGR U(0x1264)
+#define RCC_FINDIV17CFGR U(0x1268)
+#define RCC_FINDIV18CFGR U(0x126C)
+#define RCC_FINDIV19CFGR U(0x1270)
+#define RCC_FINDIV20CFGR U(0x1274)
+#define RCC_FINDIV21CFGR U(0x1278)
+#define RCC_FINDIV22CFGR U(0x127C)
+#define RCC_FINDIV23CFGR U(0x1280)
+#define RCC_FINDIV24CFGR U(0x1284)
+#define RCC_FINDIV25CFGR U(0x1288)
+#define RCC_FINDIV26CFGR U(0x128C)
+#define RCC_FINDIV27CFGR U(0x1290)
+#define RCC_FINDIV28CFGR U(0x1294)
+#define RCC_FINDIV29CFGR U(0x1298)
+#define RCC_FINDIV30CFGR U(0x129C)
+#define RCC_FINDIV31CFGR U(0x12A0)
+#define RCC_FINDIV32CFGR U(0x12A4)
+#define RCC_FINDIV33CFGR U(0x12A8)
+#define RCC_FINDIV34CFGR U(0x12AC)
+#define RCC_FINDIV35CFGR U(0x12B0)
+#define RCC_FINDIV36CFGR U(0x12B4)
+#define RCC_FINDIV37CFGR U(0x12B8)
+#define RCC_FINDIV38CFGR U(0x12BC)
+#define RCC_FINDIV39CFGR U(0x12C0)
+#define RCC_FINDIV40CFGR U(0x12C4)
+#define RCC_FINDIV41CFGR U(0x12C8)
+#define RCC_FINDIV42CFGR U(0x12CC)
+#define RCC_FINDIV43CFGR U(0x12D0)
+#define RCC_FINDIV44CFGR U(0x12D4)
+#define RCC_FINDIV45CFGR U(0x12D8)
+#define RCC_FINDIV46CFGR U(0x12DC)
+#define RCC_FINDIV47CFGR U(0x12E0)
+#define RCC_FINDIV48CFGR U(0x12E4)
+#define RCC_FINDIV49CFGR U(0x12E8)
+#define RCC_FINDIV50CFGR U(0x12EC)
+#define RCC_FINDIV51CFGR U(0x12F0)
+#define RCC_FINDIV52CFGR U(0x12F4)
+#define RCC_FINDIV53CFGR U(0x12F8)
+#define RCC_FINDIV54CFGR U(0x12FC)
+#define RCC_FINDIV55CFGR U(0x1300)
+#define RCC_FINDIV56CFGR U(0x1304)
+#define RCC_FINDIV57CFGR U(0x1308)
+#define RCC_FINDIV58CFGR U(0x130C)
+#define RCC_FINDIV59CFGR U(0x1310)
+#define RCC_FINDIV60CFGR U(0x1314)
+#define RCC_FINDIV61CFGR U(0x1318)
+#define RCC_FINDIV62CFGR U(0x131C)
+#define RCC_FINDIV63CFGR U(0x1320)
+#define RCC_FINDIVSR1 U(0x1324)
+#define RCC_FINDIVSR2 U(0x1328)
+#define RCC_FCALCOBS0CFGR U(0x1340)
+#define RCC_FCALCOBS1CFGR U(0x1344)
+#define RCC_FCALCREFCFGR U(0x1348)
+#define RCC_FCALCCR1 U(0x134C)
+#define RCC_FCALCCR2 U(0x1354)
+#define RCC_FCALCSR U(0x1358)
+#define RCC_PLL4CFGR1 U(0x1360)
+#define RCC_PLL4CFGR2 U(0x1364)
+#define RCC_PLL4CFGR3 U(0x1368)
+#define RCC_PLL4CFGR4 U(0x136C)
+#define RCC_PLL4CFGR5 U(0x1370)
+#define RCC_PLL4CFGR6 U(0x1378)
+#define RCC_PLL4CFGR7 U(0x137C)
+#define RCC_PLL5CFGR1 U(0x1388)
+#define RCC_PLL5CFGR2 U(0x138C)
+#define RCC_PLL5CFGR3 U(0x1390)
+#define RCC_PLL5CFGR4 U(0x1394)
+#define RCC_PLL5CFGR5 U(0x1398)
+#define RCC_PLL5CFGR6 U(0x13A0)
+#define RCC_PLL5CFGR7 U(0x13A4)
+#define RCC_PLL6CFGR1 U(0x13B0)
+#define RCC_PLL6CFGR2 U(0x13B4)
+#define RCC_PLL6CFGR3 U(0x13B8)
+#define RCC_PLL6CFGR4 U(0x13BC)
+#define RCC_PLL6CFGR5 U(0x13C0)
+#define RCC_PLL6CFGR6 U(0x13C8)
+#define RCC_PLL6CFGR7 U(0x13CC)
+#define RCC_PLL7CFGR1 U(0x13D8)
+#define RCC_PLL7CFGR2 U(0x13DC)
+#define RCC_PLL7CFGR3 U(0x13E0)
+#define RCC_PLL7CFGR4 U(0x13E4)
+#define RCC_PLL7CFGR5 U(0x13E8)
+#define RCC_PLL7CFGR6 U(0x13F0)
+#define RCC_PLL7CFGR7 U(0x13F4)
+#define RCC_PLL8CFGR1 U(0x1400)
+#define RCC_PLL8CFGR2 U(0x1404)
+#define RCC_PLL8CFGR3 U(0x1408)
+#define RCC_PLL8CFGR4 U(0x140C)
+#define RCC_PLL8CFGR5 U(0x1410)
+#define RCC_PLL8CFGR6 U(0x1418)
+#define RCC_PLL8CFGR7 U(0x141C)
+#define RCC_VERR U(0xFFF4)
+#define RCC_IDR U(0xFFF8)
+#define RCC_SIDR U(0xFFFC)
+
+/* Offset between RCC_MP_xxxENSETR and RCC_MP_xxxENCLRR registers */
+#define RCC_MP_ENCLRR_OFFSET U(4)
+
+/* RCC_SECCFGR3 register fields */
+#define RCC_SECCFGR3_SEC_MASK GENMASK_32(17, 0)
+#define RCC_SECCFGR3_SEC_SHIFT 0
+
+/* RCC_PRIVCFGR3 register fields */
+#define RCC_PRIVCFGR3_PRIV_MASK GENMASK_32(17, 0)
+#define RCC_PRIVCFGR3_PRIV_SHIFT 0
+
+/* RCC_RCFGLOCKR3 register fields */
+#define RCC_RCFGLOCKR3_RLOCK_MASK GENMASK_32(17, 0)
+#define RCC_RCFGLOCKR3_RLOCK_SHIFT 0
+
+/* RCC_R0CIDCFGR register fields */
+#define RCC_R0CIDCFGR_CFEN BIT(0)
+#define RCC_R0CIDCFGR_SEM_EN BIT(1)
+#define RCC_R0CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R0CIDCFGR_SCID_SHIFT 4
+#define RCC_R0CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R0CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R0SEMCR register fields */
+#define RCC_R0SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R0SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R0SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R1CIDCFGR register fields */
+#define RCC_R1CIDCFGR_CFEN BIT(0)
+#define RCC_R1CIDCFGR_SEM_EN BIT(1)
+#define RCC_R1CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R1CIDCFGR_SCID_SHIFT 4
+#define RCC_R1CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R1CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R1SEMCR register fields */
+#define RCC_R1SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R1SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R1SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R2CIDCFGR register fields */
+#define RCC_R2CIDCFGR_CFEN BIT(0)
+#define RCC_R2CIDCFGR_SEM_EN BIT(1)
+#define RCC_R2CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R2CIDCFGR_SCID_SHIFT 4
+#define RCC_R2CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R2CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R2SEMCR register fields */
+#define RCC_R2SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R2SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R2SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R3CIDCFGR register fields */
+#define RCC_R3CIDCFGR_CFEN BIT(0)
+#define RCC_R3CIDCFGR_SEM_EN BIT(1)
+#define RCC_R3CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R3CIDCFGR_SCID_SHIFT 4
+#define RCC_R3CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R3CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R3SEMCR register fields */
+#define RCC_R3SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R3SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R3SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R4CIDCFGR register fields */
+#define RCC_R4CIDCFGR_CFEN BIT(0)
+#define RCC_R4CIDCFGR_SEM_EN BIT(1)
+#define RCC_R4CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R4CIDCFGR_SCID_SHIFT 4
+#define RCC_R4CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R4CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R4SEMCR register fields */
+#define RCC_R4SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R4SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R4SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R5CIDCFGR register fields */
+#define RCC_R5CIDCFGR_CFEN BIT(0)
+#define RCC_R5CIDCFGR_SEM_EN BIT(1)
+#define RCC_R5CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R5CIDCFGR_SCID_SHIFT 4
+#define RCC_R5CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R5CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R5SEMCR register fields */
+#define RCC_R5SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R5SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R5SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R6CIDCFGR register fields */
+#define RCC_R6CIDCFGR_CFEN BIT(0)
+#define RCC_R6CIDCFGR_SEM_EN BIT(1)
+#define RCC_R6CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R6CIDCFGR_SCID_SHIFT 4
+#define RCC_R6CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R6CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R6SEMCR register fields */
+#define RCC_R6SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R6SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R6SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R7CIDCFGR register fields */
+#define RCC_R7CIDCFGR_CFEN BIT(0)
+#define RCC_R7CIDCFGR_SEM_EN BIT(1)
+#define RCC_R7CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R7CIDCFGR_SCID_SHIFT 4
+#define RCC_R7CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R7CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R7SEMCR register fields */
+#define RCC_R7SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R7SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R7SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R8CIDCFGR register fields */
+#define RCC_R8CIDCFGR_CFEN BIT(0)
+#define RCC_R8CIDCFGR_SEM_EN BIT(1)
+#define RCC_R8CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R8CIDCFGR_SCID_SHIFT 4
+#define RCC_R8CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R8CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R8SEMCR register fields */
+#define RCC_R8SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R8SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R8SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R9CIDCFGR register fields */
+#define RCC_R9CIDCFGR_CFEN BIT(0)
+#define RCC_R9CIDCFGR_SEM_EN BIT(1)
+#define RCC_R9CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R9CIDCFGR_SCID_SHIFT 4
+#define RCC_R9CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R9CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R9SEMCR register fields */
+#define RCC_R9SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R9SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R9SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R10CIDCFGR register fields */
+#define RCC_R10CIDCFGR_CFEN BIT(0)
+#define RCC_R10CIDCFGR_SEM_EN BIT(1)
+#define RCC_R10CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R10CIDCFGR_SCID_SHIFT 4
+#define RCC_R10CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R10CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R10SEMCR register fields */
+#define RCC_R10SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R10SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R10SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R11CIDCFGR register fields */
+#define RCC_R11CIDCFGR_CFEN BIT(0)
+#define RCC_R11CIDCFGR_SEM_EN BIT(1)
+#define RCC_R11CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R11CIDCFGR_SCID_SHIFT 4
+#define RCC_R11CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R11CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R11SEMCR register fields */
+#define RCC_R11SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R11SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R11SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R12CIDCFGR register fields */
+#define RCC_R12CIDCFGR_CFEN BIT(0)
+#define RCC_R12CIDCFGR_SEM_EN BIT(1)
+#define RCC_R12CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R12CIDCFGR_SCID_SHIFT 4
+#define RCC_R12CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R12CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R12SEMCR register fields */
+#define RCC_R12SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R12SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R12SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R13CIDCFGR register fields */
+#define RCC_R13CIDCFGR_CFEN BIT(0)
+#define RCC_R13CIDCFGR_SEM_EN BIT(1)
+#define RCC_R13CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R13CIDCFGR_SCID_SHIFT 4
+#define RCC_R13CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R13CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R13SEMCR register fields */
+#define RCC_R13SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R13SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R13SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R14CIDCFGR register fields */
+#define RCC_R14CIDCFGR_CFEN BIT(0)
+#define RCC_R14CIDCFGR_SEM_EN BIT(1)
+#define RCC_R14CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R14CIDCFGR_SCID_SHIFT 4
+#define RCC_R14CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R14CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R14SEMCR register fields */
+#define RCC_R14SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R14SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R14SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R15CIDCFGR register fields */
+#define RCC_R15CIDCFGR_CFEN BIT(0)
+#define RCC_R15CIDCFGR_SEM_EN BIT(1)
+#define RCC_R15CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R15CIDCFGR_SCID_SHIFT 4
+#define RCC_R15CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R15CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R15SEMCR register fields */
+#define RCC_R15SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R15SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R15SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R16CIDCFGR register fields */
+#define RCC_R16CIDCFGR_CFEN BIT(0)
+#define RCC_R16CIDCFGR_SEM_EN BIT(1)
+#define RCC_R16CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R16CIDCFGR_SCID_SHIFT 4
+#define RCC_R16CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R16CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R16SEMCR register fields */
+#define RCC_R16SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R16SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R16SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R17CIDCFGR register fields */
+#define RCC_R17CIDCFGR_CFEN BIT(0)
+#define RCC_R17CIDCFGR_SEM_EN BIT(1)
+#define RCC_R17CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R17CIDCFGR_SCID_SHIFT 4
+#define RCC_R17CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R17CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R17SEMCR register fields */
+#define RCC_R17SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R17SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R17SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R18CIDCFGR register fields */
+#define RCC_R18CIDCFGR_CFEN BIT(0)
+#define RCC_R18CIDCFGR_SEM_EN BIT(1)
+#define RCC_R18CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R18CIDCFGR_SCID_SHIFT 4
+#define RCC_R18CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R18CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R18SEMCR register fields */
+#define RCC_R18SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R18SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R18SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R19CIDCFGR register fields */
+#define RCC_R19CIDCFGR_CFEN BIT(0)
+#define RCC_R19CIDCFGR_SEM_EN BIT(1)
+#define RCC_R19CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R19CIDCFGR_SCID_SHIFT 4
+#define RCC_R19CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R19CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R19SEMCR register fields */
+#define RCC_R19SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R19SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R19SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R20CIDCFGR register fields */
+#define RCC_R20CIDCFGR_CFEN BIT(0)
+#define RCC_R20CIDCFGR_SEM_EN BIT(1)
+#define RCC_R20CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R20CIDCFGR_SCID_SHIFT 4
+#define RCC_R20CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R20CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R20SEMCR register fields */
+#define RCC_R20SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R20SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R20SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R21CIDCFGR register fields */
+#define RCC_R21CIDCFGR_CFEN BIT(0)
+#define RCC_R21CIDCFGR_SEM_EN BIT(1)
+#define RCC_R21CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R21CIDCFGR_SCID_SHIFT 4
+#define RCC_R21CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R21CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R21SEMCR register fields */
+#define RCC_R21SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R21SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R21SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R22CIDCFGR register fields */
+#define RCC_R22CIDCFGR_CFEN BIT(0)
+#define RCC_R22CIDCFGR_SEM_EN BIT(1)
+#define RCC_R22CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R22CIDCFGR_SCID_SHIFT 4
+#define RCC_R22CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R22CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R22SEMCR register fields */
+#define RCC_R22SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R22SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R22SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R23CIDCFGR register fields */
+#define RCC_R23CIDCFGR_CFEN BIT(0)
+#define RCC_R23CIDCFGR_SEM_EN BIT(1)
+#define RCC_R23CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R23CIDCFGR_SCID_SHIFT 4
+#define RCC_R23CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R23CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R23SEMCR register fields */
+#define RCC_R23SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R23SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R23SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R24CIDCFGR register fields */
+#define RCC_R24CIDCFGR_CFEN BIT(0)
+#define RCC_R24CIDCFGR_SEM_EN BIT(1)
+#define RCC_R24CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R24CIDCFGR_SCID_SHIFT 4
+#define RCC_R24CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R24CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R24SEMCR register fields */
+#define RCC_R24SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R24SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R24SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R25CIDCFGR register fields */
+#define RCC_R25CIDCFGR_CFEN BIT(0)
+#define RCC_R25CIDCFGR_SEM_EN BIT(1)
+#define RCC_R25CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R25CIDCFGR_SCID_SHIFT 4
+#define RCC_R25CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R25CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R25SEMCR register fields */
+#define RCC_R25SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R25SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R25SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R26CIDCFGR register fields */
+#define RCC_R26CIDCFGR_CFEN BIT(0)
+#define RCC_R26CIDCFGR_SEM_EN BIT(1)
+#define RCC_R26CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R26CIDCFGR_SCID_SHIFT 4
+#define RCC_R26CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R26CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R26SEMCR register fields */
+#define RCC_R26SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R26SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R26SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R27CIDCFGR register fields */
+#define RCC_R27CIDCFGR_CFEN BIT(0)
+#define RCC_R27CIDCFGR_SEM_EN BIT(1)
+#define RCC_R27CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R27CIDCFGR_SCID_SHIFT 4
+#define RCC_R27CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R27CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R27SEMCR register fields */
+#define RCC_R27SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R27SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R27SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R28CIDCFGR register fields */
+#define RCC_R28CIDCFGR_CFEN BIT(0)
+#define RCC_R28CIDCFGR_SEM_EN BIT(1)
+#define RCC_R28CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R28CIDCFGR_SCID_SHIFT 4
+#define RCC_R28CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R28CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R28SEMCR register fields */
+#define RCC_R28SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R28SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R28SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R29CIDCFGR register fields */
+#define RCC_R29CIDCFGR_CFEN BIT(0)
+#define RCC_R29CIDCFGR_SEM_EN BIT(1)
+#define RCC_R29CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R29CIDCFGR_SCID_SHIFT 4
+#define RCC_R29CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R29CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R29SEMCR register fields */
+#define RCC_R29SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R29SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R29SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R30CIDCFGR register fields */
+#define RCC_R30CIDCFGR_CFEN BIT(0)
+#define RCC_R30CIDCFGR_SEM_EN BIT(1)
+#define RCC_R30CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R30CIDCFGR_SCID_SHIFT 4
+#define RCC_R30CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R30CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R30SEMCR register fields */
+#define RCC_R30SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R30SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R30SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R31CIDCFGR register fields */
+#define RCC_R31CIDCFGR_CFEN BIT(0)
+#define RCC_R31CIDCFGR_SEM_EN BIT(1)
+#define RCC_R31CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R31CIDCFGR_SCID_SHIFT 4
+#define RCC_R31CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R31CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R31SEMCR register fields */
+#define RCC_R31SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R31SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R31SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R32CIDCFGR register fields */
+#define RCC_R32CIDCFGR_CFEN BIT(0)
+#define RCC_R32CIDCFGR_SEM_EN BIT(1)
+#define RCC_R32CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R32CIDCFGR_SCID_SHIFT 4
+#define RCC_R32CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R32CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R32SEMCR register fields */
+#define RCC_R32SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R32SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R32SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R33CIDCFGR register fields */
+#define RCC_R33CIDCFGR_CFEN BIT(0)
+#define RCC_R33CIDCFGR_SEM_EN BIT(1)
+#define RCC_R33CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R33CIDCFGR_SCID_SHIFT 4
+#define RCC_R33CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R33CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R33SEMCR register fields */
+#define RCC_R33SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R33SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R33SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R34CIDCFGR register fields */
+#define RCC_R34CIDCFGR_CFEN BIT(0)
+#define RCC_R34CIDCFGR_SEM_EN BIT(1)
+#define RCC_R34CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R34CIDCFGR_SCID_SHIFT 4
+#define RCC_R34CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R34CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R34SEMCR register fields */
+#define RCC_R34SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R34SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R34SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R35CIDCFGR register fields */
+#define RCC_R35CIDCFGR_CFEN BIT(0)
+#define RCC_R35CIDCFGR_SEM_EN BIT(1)
+#define RCC_R35CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R35CIDCFGR_SCID_SHIFT 4
+#define RCC_R35CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R35CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R35SEMCR register fields */
+#define RCC_R35SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R35SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R35SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R36CIDCFGR register fields */
+#define RCC_R36CIDCFGR_CFEN BIT(0)
+#define RCC_R36CIDCFGR_SEM_EN BIT(1)
+#define RCC_R36CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R36CIDCFGR_SCID_SHIFT 4
+#define RCC_R36CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R36CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R36SEMCR register fields */
+#define RCC_R36SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R36SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R36SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R37CIDCFGR register fields */
+#define RCC_R37CIDCFGR_CFEN BIT(0)
+#define RCC_R37CIDCFGR_SEM_EN BIT(1)
+#define RCC_R37CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R37CIDCFGR_SCID_SHIFT 4
+#define RCC_R37CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R37CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R37SEMCR register fields */
+#define RCC_R37SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R37SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R37SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R38CIDCFGR register fields */
+#define RCC_R38CIDCFGR_CFEN BIT(0)
+#define RCC_R38CIDCFGR_SEM_EN BIT(1)
+#define RCC_R38CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R38CIDCFGR_SCID_SHIFT 4
+#define RCC_R38CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R38CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R38SEMCR register fields */
+#define RCC_R38SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R38SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R38SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R39CIDCFGR register fields */
+#define RCC_R39CIDCFGR_CFEN BIT(0)
+#define RCC_R39CIDCFGR_SEM_EN BIT(1)
+#define RCC_R39CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R39CIDCFGR_SCID_SHIFT 4
+#define RCC_R39CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R39CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R39SEMCR register fields */
+#define RCC_R39SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R39SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R39SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R40CIDCFGR register fields */
+#define RCC_R40CIDCFGR_CFEN BIT(0)
+#define RCC_R40CIDCFGR_SEM_EN BIT(1)
+#define RCC_R40CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R40CIDCFGR_SCID_SHIFT 4
+#define RCC_R40CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R40CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R40SEMCR register fields */
+#define RCC_R40SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R40SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R40SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R41CIDCFGR register fields */
+#define RCC_R41CIDCFGR_CFEN BIT(0)
+#define RCC_R41CIDCFGR_SEM_EN BIT(1)
+#define RCC_R41CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R41CIDCFGR_SCID_SHIFT 4
+#define RCC_R41CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R41CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R41SEMCR register fields */
+#define RCC_R41SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R41SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R41SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R42CIDCFGR register fields */
+#define RCC_R42CIDCFGR_CFEN BIT(0)
+#define RCC_R42CIDCFGR_SEM_EN BIT(1)
+#define RCC_R42CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R42CIDCFGR_SCID_SHIFT 4
+#define RCC_R42CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R42CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R42SEMCR register fields */
+#define RCC_R42SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R42SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R42SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R43CIDCFGR register fields */
+#define RCC_R43CIDCFGR_CFEN BIT(0)
+#define RCC_R43CIDCFGR_SEM_EN BIT(1)
+#define RCC_R43CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R43CIDCFGR_SCID_SHIFT 4
+#define RCC_R43CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R43CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R43SEMCR register fields */
+#define RCC_R43SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R43SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R43SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R44CIDCFGR register fields */
+#define RCC_R44CIDCFGR_CFEN BIT(0)
+#define RCC_R44CIDCFGR_SEM_EN BIT(1)
+#define RCC_R44CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R44CIDCFGR_SCID_SHIFT 4
+#define RCC_R44CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R44CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R44SEMCR register fields */
+#define RCC_R44SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R44SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R44SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R45CIDCFGR register fields */
+#define RCC_R45CIDCFGR_CFEN BIT(0)
+#define RCC_R45CIDCFGR_SEM_EN BIT(1)
+#define RCC_R45CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R45CIDCFGR_SCID_SHIFT 4
+#define RCC_R45CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R45CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R45SEMCR register fields */
+#define RCC_R45SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R45SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R45SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R46CIDCFGR register fields */
+#define RCC_R46CIDCFGR_CFEN BIT(0)
+#define RCC_R46CIDCFGR_SEM_EN BIT(1)
+#define RCC_R46CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R46CIDCFGR_SCID_SHIFT 4
+#define RCC_R46CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R46CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R46SEMCR register fields */
+#define RCC_R46SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R46SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R46SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R47CIDCFGR register fields */
+#define RCC_R47CIDCFGR_CFEN BIT(0)
+#define RCC_R47CIDCFGR_SEM_EN BIT(1)
+#define RCC_R47CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R47CIDCFGR_SCID_SHIFT 4
+#define RCC_R47CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R47CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R47SEMCR register fields */
+#define RCC_R47SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R47SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R47SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R48CIDCFGR register fields */
+#define RCC_R48CIDCFGR_CFEN BIT(0)
+#define RCC_R48CIDCFGR_SEM_EN BIT(1)
+#define RCC_R48CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R48CIDCFGR_SCID_SHIFT 4
+#define RCC_R48CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R48CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R48SEMCR register fields */
+#define RCC_R48SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R48SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R48SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R49CIDCFGR register fields */
+#define RCC_R49CIDCFGR_CFEN BIT(0)
+#define RCC_R49CIDCFGR_SEM_EN BIT(1)
+#define RCC_R49CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R49CIDCFGR_SCID_SHIFT 4
+#define RCC_R49CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R49CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R49SEMCR register fields */
+#define RCC_R49SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R49SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R49SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R50CIDCFGR register fields */
+#define RCC_R50CIDCFGR_CFEN BIT(0)
+#define RCC_R50CIDCFGR_SEM_EN BIT(1)
+#define RCC_R50CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R50CIDCFGR_SCID_SHIFT 4
+#define RCC_R50CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R50CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R50SEMCR register fields */
+#define RCC_R50SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R50SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R50SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R51CIDCFGR register fields */
+#define RCC_R51CIDCFGR_CFEN BIT(0)
+#define RCC_R51CIDCFGR_SEM_EN BIT(1)
+#define RCC_R51CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R51CIDCFGR_SCID_SHIFT 4
+#define RCC_R51CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R51CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R51SEMCR register fields */
+#define RCC_R51SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R51SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R51SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R52CIDCFGR register fields */
+#define RCC_R52CIDCFGR_CFEN BIT(0)
+#define RCC_R52CIDCFGR_SEM_EN BIT(1)
+#define RCC_R52CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R52CIDCFGR_SCID_SHIFT 4
+#define RCC_R52CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R52CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R52SEMCR register fields */
+#define RCC_R52SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R52SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R52SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R53CIDCFGR register fields */
+#define RCC_R53CIDCFGR_CFEN BIT(0)
+#define RCC_R53CIDCFGR_SEM_EN BIT(1)
+#define RCC_R53CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R53CIDCFGR_SCID_SHIFT 4
+#define RCC_R53CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R53CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R53SEMCR register fields */
+#define RCC_R53SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R53SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R53SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R54CIDCFGR register fields */
+#define RCC_R54CIDCFGR_CFEN BIT(0)
+#define RCC_R54CIDCFGR_SEM_EN BIT(1)
+#define RCC_R54CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R54CIDCFGR_SCID_SHIFT 4
+#define RCC_R54CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R54CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R54SEMCR register fields */
+#define RCC_R54SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R54SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R54SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R55CIDCFGR register fields */
+#define RCC_R55CIDCFGR_CFEN BIT(0)
+#define RCC_R55CIDCFGR_SEM_EN BIT(1)
+#define RCC_R55CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R55CIDCFGR_SCID_SHIFT 4
+#define RCC_R55CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R55CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R55SEMCR register fields */
+#define RCC_R55SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R55SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R55SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R56CIDCFGR register fields */
+#define RCC_R56CIDCFGR_CFEN BIT(0)
+#define RCC_R56CIDCFGR_SEM_EN BIT(1)
+#define RCC_R56CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R56CIDCFGR_SCID_SHIFT 4
+#define RCC_R56CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R56CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R56SEMCR register fields */
+#define RCC_R56SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R56SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R56SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R57CIDCFGR register fields */
+#define RCC_R57CIDCFGR_CFEN BIT(0)
+#define RCC_R57CIDCFGR_SEM_EN BIT(1)
+#define RCC_R57CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R57CIDCFGR_SCID_SHIFT 4
+#define RCC_R57CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R57CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R57SEMCR register fields */
+#define RCC_R57SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R57SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R57SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R58CIDCFGR register fields */
+#define RCC_R58CIDCFGR_CFEN BIT(0)
+#define RCC_R58CIDCFGR_SEM_EN BIT(1)
+#define RCC_R58CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R58CIDCFGR_SCID_SHIFT 4
+#define RCC_R58CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R58CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R58SEMCR register fields */
+#define RCC_R58SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R58SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R58SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R59CIDCFGR register fields */
+#define RCC_R59CIDCFGR_CFEN BIT(0)
+#define RCC_R59CIDCFGR_SEM_EN BIT(1)
+#define RCC_R59CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R59CIDCFGR_SCID_SHIFT 4
+#define RCC_R59CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R59CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R59SEMCR register fields */
+#define RCC_R59SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R59SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R59SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R60CIDCFGR register fields */
+#define RCC_R60CIDCFGR_CFEN BIT(0)
+#define RCC_R60CIDCFGR_SEM_EN BIT(1)
+#define RCC_R60CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R60CIDCFGR_SCID_SHIFT 4
+#define RCC_R60CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R60CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R60SEMCR register fields */
+#define RCC_R60SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R60SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R60SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R61CIDCFGR register fields */
+#define RCC_R61CIDCFGR_CFEN BIT(0)
+#define RCC_R61CIDCFGR_SEM_EN BIT(1)
+#define RCC_R61CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R61CIDCFGR_SCID_SHIFT 4
+#define RCC_R61CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R61CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R61SEMCR register fields */
+#define RCC_R61SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R61SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R61SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R62CIDCFGR register fields */
+#define RCC_R62CIDCFGR_CFEN BIT(0)
+#define RCC_R62CIDCFGR_SEM_EN BIT(1)
+#define RCC_R62CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R62CIDCFGR_SCID_SHIFT 4
+#define RCC_R62CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R62CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R62SEMCR register fields */
+#define RCC_R62SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R62SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R62SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R63CIDCFGR register fields */
+#define RCC_R63CIDCFGR_CFEN BIT(0)
+#define RCC_R63CIDCFGR_SEM_EN BIT(1)
+#define RCC_R63CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R63CIDCFGR_SCID_SHIFT 4
+#define RCC_R63CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R63CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R63SEMCR register fields */
+#define RCC_R63SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R63SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R63SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R64CIDCFGR register fields */
+#define RCC_R64CIDCFGR_CFEN BIT(0)
+#define RCC_R64CIDCFGR_SEM_EN BIT(1)
+#define RCC_R64CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R64CIDCFGR_SCID_SHIFT 4
+#define RCC_R64CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R64CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R64SEMCR register fields */
+#define RCC_R64SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R64SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R64SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R65CIDCFGR register fields */
+#define RCC_R65CIDCFGR_CFEN BIT(0)
+#define RCC_R65CIDCFGR_SEM_EN BIT(1)
+#define RCC_R65CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R65CIDCFGR_SCID_SHIFT 4
+#define RCC_R65CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R65CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R65SEMCR register fields */
+#define RCC_R65SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R65SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R65SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R66CIDCFGR register fields */
+#define RCC_R66CIDCFGR_CFEN BIT(0)
+#define RCC_R66CIDCFGR_SEM_EN BIT(1)
+#define RCC_R66CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R66CIDCFGR_SCID_SHIFT 4
+#define RCC_R66CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R66CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R66SEMCR register fields */
+#define RCC_R66SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R66SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R66SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R67CIDCFGR register fields */
+#define RCC_R67CIDCFGR_CFEN BIT(0)
+#define RCC_R67CIDCFGR_SEM_EN BIT(1)
+#define RCC_R67CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R67CIDCFGR_SCID_SHIFT 4
+#define RCC_R67CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R67CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R67SEMCR register fields */
+#define RCC_R67SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R67SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R67SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R68CIDCFGR register fields */
+#define RCC_R68CIDCFGR_CFEN BIT(0)
+#define RCC_R68CIDCFGR_SEM_EN BIT(1)
+#define RCC_R68CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R68CIDCFGR_SCID_SHIFT 4
+#define RCC_R68CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R68CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R68SEMCR register fields */
+#define RCC_R68SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R68SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R68SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R69CIDCFGR register fields */
+#define RCC_R69CIDCFGR_CFEN BIT(0)
+#define RCC_R69CIDCFGR_SEM_EN BIT(1)
+#define RCC_R69CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R69CIDCFGR_SCID_SHIFT 4
+#define RCC_R69CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R69CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R69SEMCR register fields */
+#define RCC_R69SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R69SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R69SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R70CIDCFGR register fields */
+#define RCC_R70CIDCFGR_CFEN BIT(0)
+#define RCC_R70CIDCFGR_SEM_EN BIT(1)
+#define RCC_R70CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R70CIDCFGR_SCID_SHIFT 4
+#define RCC_R70CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R70CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R70SEMCR register fields */
+#define RCC_R70SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R70SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R70SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R71CIDCFGR register fields */
+#define RCC_R71CIDCFGR_CFEN BIT(0)
+#define RCC_R71CIDCFGR_SEM_EN BIT(1)
+#define RCC_R71CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R71CIDCFGR_SCID_SHIFT 4
+#define RCC_R71CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R71CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R71SEMCR register fields */
+#define RCC_R71SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R71SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R71SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R72CIDCFGR register fields */
+#define RCC_R72CIDCFGR_CFEN BIT(0)
+#define RCC_R72CIDCFGR_SEM_EN BIT(1)
+#define RCC_R72CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R72CIDCFGR_SCID_SHIFT 4
+#define RCC_R72CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R72CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R72SEMCR register fields */
+#define RCC_R72SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R72SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R72SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R73CIDCFGR register fields */
+#define RCC_R73CIDCFGR_CFEN BIT(0)
+#define RCC_R73CIDCFGR_SEM_EN BIT(1)
+#define RCC_R73CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R73CIDCFGR_SCID_SHIFT 4
+#define RCC_R73CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R73CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R73SEMCR register fields */
+#define RCC_R73SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R73SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R73SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R74CIDCFGR register fields */
+#define RCC_R74CIDCFGR_CFEN BIT(0)
+#define RCC_R74CIDCFGR_SEM_EN BIT(1)
+#define RCC_R74CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R74CIDCFGR_SCID_SHIFT 4
+#define RCC_R74CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R74CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R74SEMCR register fields */
+#define RCC_R74SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R74SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R74SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R75CIDCFGR register fields */
+#define RCC_R75CIDCFGR_CFEN BIT(0)
+#define RCC_R75CIDCFGR_SEM_EN BIT(1)
+#define RCC_R75CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R75CIDCFGR_SCID_SHIFT 4
+#define RCC_R75CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R75CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R75SEMCR register fields */
+#define RCC_R75SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R75SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R75SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R76CIDCFGR register fields */
+#define RCC_R76CIDCFGR_CFEN BIT(0)
+#define RCC_R76CIDCFGR_SEM_EN BIT(1)
+#define RCC_R76CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R76CIDCFGR_SCID_SHIFT 4
+#define RCC_R76CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R76CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R76SEMCR register fields */
+#define RCC_R76SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R76SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R76SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R77CIDCFGR register fields */
+#define RCC_R77CIDCFGR_CFEN BIT(0)
+#define RCC_R77CIDCFGR_SEM_EN BIT(1)
+#define RCC_R77CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R77CIDCFGR_SCID_SHIFT 4
+#define RCC_R77CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R77CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R77SEMCR register fields */
+#define RCC_R77SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R77SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R77SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R78CIDCFGR register fields */
+#define RCC_R78CIDCFGR_CFEN BIT(0)
+#define RCC_R78CIDCFGR_SEM_EN BIT(1)
+#define RCC_R78CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R78CIDCFGR_SCID_SHIFT 4
+#define RCC_R78CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R78CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R78SEMCR register fields */
+#define RCC_R78SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R78SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R78SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R79CIDCFGR register fields */
+#define RCC_R79CIDCFGR_CFEN BIT(0)
+#define RCC_R79CIDCFGR_SEM_EN BIT(1)
+#define RCC_R79CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R79CIDCFGR_SCID_SHIFT 4
+#define RCC_R79CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R79CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R79SEMCR register fields */
+#define RCC_R79SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R79SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R79SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R80CIDCFGR register fields */
+#define RCC_R80CIDCFGR_CFEN BIT(0)
+#define RCC_R80CIDCFGR_SEM_EN BIT(1)
+#define RCC_R80CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R80CIDCFGR_SCID_SHIFT 4
+#define RCC_R80CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R80CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R80SEMCR register fields */
+#define RCC_R80SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R80SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R80SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R81CIDCFGR register fields */
+#define RCC_R81CIDCFGR_CFEN BIT(0)
+#define RCC_R81CIDCFGR_SEM_EN BIT(1)
+#define RCC_R81CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R81CIDCFGR_SCID_SHIFT 4
+#define RCC_R81CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R81CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R81SEMCR register fields */
+#define RCC_R81SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R81SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R81SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R82CIDCFGR register fields */
+#define RCC_R82CIDCFGR_CFEN BIT(0)
+#define RCC_R82CIDCFGR_SEM_EN BIT(1)
+#define RCC_R82CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R82CIDCFGR_SCID_SHIFT 4
+#define RCC_R82CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R82CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R82SEMCR register fields */
+#define RCC_R82SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R82SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R82SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R83CIDCFGR register fields */
+#define RCC_R83CIDCFGR_CFEN BIT(0)
+#define RCC_R83CIDCFGR_SEM_EN BIT(1)
+#define RCC_R83CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R83CIDCFGR_SCID_SHIFT 4
+#define RCC_R83CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R83CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R83SEMCR register fields */
+#define RCC_R83SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R83SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R83SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R84CIDCFGR register fields */
+#define RCC_R84CIDCFGR_CFEN BIT(0)
+#define RCC_R84CIDCFGR_SEM_EN BIT(1)
+#define RCC_R84CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R84CIDCFGR_SCID_SHIFT 4
+#define RCC_R84CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R84CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R84SEMCR register fields */
+#define RCC_R84SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R84SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R84SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R85CIDCFGR register fields */
+#define RCC_R85CIDCFGR_CFEN BIT(0)
+#define RCC_R85CIDCFGR_SEM_EN BIT(1)
+#define RCC_R85CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R85CIDCFGR_SCID_SHIFT 4
+#define RCC_R85CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R85CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R85SEMCR register fields */
+#define RCC_R85SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R85SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R85SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R86CIDCFGR register fields */
+#define RCC_R86CIDCFGR_CFEN BIT(0)
+#define RCC_R86CIDCFGR_SEM_EN BIT(1)
+#define RCC_R86CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R86CIDCFGR_SCID_SHIFT 4
+#define RCC_R86CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R86CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R86SEMCR register fields */
+#define RCC_R86SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R86SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R86SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R87CIDCFGR register fields */
+#define RCC_R87CIDCFGR_CFEN BIT(0)
+#define RCC_R87CIDCFGR_SEM_EN BIT(1)
+#define RCC_R87CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R87CIDCFGR_SCID_SHIFT 4
+#define RCC_R87CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R87CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R87SEMCR register fields */
+#define RCC_R87SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R87SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R87SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R88CIDCFGR register fields */
+#define RCC_R88CIDCFGR_CFEN BIT(0)
+#define RCC_R88CIDCFGR_SEM_EN BIT(1)
+#define RCC_R88CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R88CIDCFGR_SCID_SHIFT 4
+#define RCC_R88CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R88CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R88SEMCR register fields */
+#define RCC_R88SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R88SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R88SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R89CIDCFGR register fields */
+#define RCC_R89CIDCFGR_CFEN BIT(0)
+#define RCC_R89CIDCFGR_SEM_EN BIT(1)
+#define RCC_R89CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R89CIDCFGR_SCID_SHIFT 4
+#define RCC_R89CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R89CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R89SEMCR register fields */
+#define RCC_R89SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R89SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R89SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R90CIDCFGR register fields */
+#define RCC_R90CIDCFGR_CFEN BIT(0)
+#define RCC_R90CIDCFGR_SEM_EN BIT(1)
+#define RCC_R90CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R90CIDCFGR_SCID_SHIFT 4
+#define RCC_R90CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R90CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R90SEMCR register fields */
+#define RCC_R90SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R90SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R90SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R91CIDCFGR register fields */
+#define RCC_R91CIDCFGR_CFEN BIT(0)
+#define RCC_R91CIDCFGR_SEM_EN BIT(1)
+#define RCC_R91CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R91CIDCFGR_SCID_SHIFT 4
+#define RCC_R91CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R91CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R91SEMCR register fields */
+#define RCC_R91SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R91SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R91SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R92CIDCFGR register fields */
+#define RCC_R92CIDCFGR_CFEN BIT(0)
+#define RCC_R92CIDCFGR_SEM_EN BIT(1)
+#define RCC_R92CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R92CIDCFGR_SCID_SHIFT 4
+#define RCC_R92CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R92CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R92SEMCR register fields */
+#define RCC_R92SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R92SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R92SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R93CIDCFGR register fields */
+#define RCC_R93CIDCFGR_CFEN BIT(0)
+#define RCC_R93CIDCFGR_SEM_EN BIT(1)
+#define RCC_R93CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R93CIDCFGR_SCID_SHIFT 4
+#define RCC_R93CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R93CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R93SEMCR register fields */
+#define RCC_R93SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R93SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R93SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R94CIDCFGR register fields */
+#define RCC_R94CIDCFGR_CFEN BIT(0)
+#define RCC_R94CIDCFGR_SEM_EN BIT(1)
+#define RCC_R94CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R94CIDCFGR_SCID_SHIFT 4
+#define RCC_R94CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R94CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R94SEMCR register fields */
+#define RCC_R94SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R94SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R94SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R95CIDCFGR register fields */
+#define RCC_R95CIDCFGR_CFEN BIT(0)
+#define RCC_R95CIDCFGR_SEM_EN BIT(1)
+#define RCC_R95CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R95CIDCFGR_SCID_SHIFT 4
+#define RCC_R95CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R95CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R95SEMCR register fields */
+#define RCC_R95SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R95SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R95SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R96CIDCFGR register fields */
+#define RCC_R96CIDCFGR_CFEN BIT(0)
+#define RCC_R96CIDCFGR_SEM_EN BIT(1)
+#define RCC_R96CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R96CIDCFGR_SCID_SHIFT 4
+#define RCC_R96CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R96CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R96SEMCR register fields */
+#define RCC_R96SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R96SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R96SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R97CIDCFGR register fields */
+#define RCC_R97CIDCFGR_CFEN BIT(0)
+#define RCC_R97CIDCFGR_SEM_EN BIT(1)
+#define RCC_R97CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R97CIDCFGR_SCID_SHIFT 4
+#define RCC_R97CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R97CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R97SEMCR register fields */
+#define RCC_R97SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R97SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R97SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R98CIDCFGR register fields */
+#define RCC_R98CIDCFGR_CFEN BIT(0)
+#define RCC_R98CIDCFGR_SEM_EN BIT(1)
+#define RCC_R98CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R98CIDCFGR_SCID_SHIFT 4
+#define RCC_R98CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R98CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R98SEMCR register fields */
+#define RCC_R98SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R98SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R98SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R99CIDCFGR register fields */
+#define RCC_R99CIDCFGR_CFEN BIT(0)
+#define RCC_R99CIDCFGR_SEM_EN BIT(1)
+#define RCC_R99CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R99CIDCFGR_SCID_SHIFT 4
+#define RCC_R99CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R99CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R99SEMCR register fields */
+#define RCC_R99SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R99SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R99SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R100CIDCFGR register fields */
+#define RCC_R100CIDCFGR_CFEN BIT(0)
+#define RCC_R100CIDCFGR_SEM_EN BIT(1)
+#define RCC_R100CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R100CIDCFGR_SCID_SHIFT 4
+#define RCC_R100CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R100CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R100SEMCR register fields */
+#define RCC_R100SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R100SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R100SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R101CIDCFGR register fields */
+#define RCC_R101CIDCFGR_CFEN BIT(0)
+#define RCC_R101CIDCFGR_SEM_EN BIT(1)
+#define RCC_R101CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R101CIDCFGR_SCID_SHIFT 4
+#define RCC_R101CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R101CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R101SEMCR register fields */
+#define RCC_R101SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R101SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R101SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R102CIDCFGR register fields */
+#define RCC_R102CIDCFGR_CFEN BIT(0)
+#define RCC_R102CIDCFGR_SEM_EN BIT(1)
+#define RCC_R102CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R102CIDCFGR_SCID_SHIFT 4
+#define RCC_R102CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R102CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R102SEMCR register fields */
+#define RCC_R102SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R102SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R102SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R103CIDCFGR register fields */
+#define RCC_R103CIDCFGR_CFEN BIT(0)
+#define RCC_R103CIDCFGR_SEM_EN BIT(1)
+#define RCC_R103CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R103CIDCFGR_SCID_SHIFT 4
+#define RCC_R103CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R103CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R103SEMCR register fields */
+#define RCC_R103SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R103SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R103SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R104CIDCFGR register fields */
+#define RCC_R104CIDCFGR_CFEN BIT(0)
+#define RCC_R104CIDCFGR_SEM_EN BIT(1)
+#define RCC_R104CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R104CIDCFGR_SCID_SHIFT 4
+#define RCC_R104CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R104CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R104SEMCR register fields */
+#define RCC_R104SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R104SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R104SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R105CIDCFGR register fields */
+#define RCC_R105CIDCFGR_CFEN BIT(0)
+#define RCC_R105CIDCFGR_SEM_EN BIT(1)
+#define RCC_R105CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R105CIDCFGR_SCID_SHIFT 4
+#define RCC_R105CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R105CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R105SEMCR register fields */
+#define RCC_R105SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R105SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R105SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R106CIDCFGR register fields */
+#define RCC_R106CIDCFGR_CFEN BIT(0)
+#define RCC_R106CIDCFGR_SEM_EN BIT(1)
+#define RCC_R106CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R106CIDCFGR_SCID_SHIFT 4
+#define RCC_R106CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R106CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R106SEMCR register fields */
+#define RCC_R106SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R106SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R106SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R107CIDCFGR register fields */
+#define RCC_R107CIDCFGR_CFEN BIT(0)
+#define RCC_R107CIDCFGR_SEM_EN BIT(1)
+#define RCC_R107CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R107CIDCFGR_SCID_SHIFT 4
+#define RCC_R107CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R107CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R107SEMCR register fields */
+#define RCC_R107SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R107SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R107SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R108CIDCFGR register fields */
+#define RCC_R108CIDCFGR_CFEN BIT(0)
+#define RCC_R108CIDCFGR_SEM_EN BIT(1)
+#define RCC_R108CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R108CIDCFGR_SCID_SHIFT 4
+#define RCC_R108CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R108CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R108SEMCR register fields */
+#define RCC_R108SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R108SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R108SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R109CIDCFGR register fields */
+#define RCC_R109CIDCFGR_CFEN BIT(0)
+#define RCC_R109CIDCFGR_SEM_EN BIT(1)
+#define RCC_R109CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R109CIDCFGR_SCID_SHIFT 4
+#define RCC_R109CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R109CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R109SEMCR register fields */
+#define RCC_R109SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R109SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R109SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R110CIDCFGR register fields */
+#define RCC_R110CIDCFGR_CFEN BIT(0)
+#define RCC_R110CIDCFGR_SEM_EN BIT(1)
+#define RCC_R110CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R110CIDCFGR_SCID_SHIFT 4
+#define RCC_R110CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R110CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R110SEMCR register fields */
+#define RCC_R110SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R110SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R110SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R111CIDCFGR register fields */
+#define RCC_R111CIDCFGR_CFEN BIT(0)
+#define RCC_R111CIDCFGR_SEM_EN BIT(1)
+#define RCC_R111CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R111CIDCFGR_SCID_SHIFT 4
+#define RCC_R111CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R111CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R111SEMCR register fields */
+#define RCC_R111SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R111SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R111SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R112CIDCFGR register fields */
+#define RCC_R112CIDCFGR_CFEN BIT(0)
+#define RCC_R112CIDCFGR_SEM_EN BIT(1)
+#define RCC_R112CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R112CIDCFGR_SCID_SHIFT 4
+#define RCC_R112CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R112CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R112SEMCR register fields */
+#define RCC_R112SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R112SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R112SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R113CIDCFGR register fields */
+#define RCC_R113CIDCFGR_CFEN BIT(0)
+#define RCC_R113CIDCFGR_SEM_EN BIT(1)
+#define RCC_R113CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R113CIDCFGR_SCID_SHIFT 4
+#define RCC_R113CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R113CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R113SEMCR register fields */
+#define RCC_R113SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R113SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R113SEMCR_SEMCID_SHIFT 4
+
+/* RCC_RxCIDCFGR register fields */
+#define RCC_RxCIDCFGR_CFEN BIT(0)
+#define RCC_RxCIDCFGR_SEM_EN BIT(1)
+#define RCC_RxCIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_RxCIDCFGR_SCID_SHIFT 4
+#define RCC_RxCIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_RxCIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_RxSEMCR register fields */
+#define RCC_RxSEMCR_SEM_MUTEX BIT(0)
+#define RCC_RxSEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_RxSEMCR_SEMCID_SHIFT 4
+
+/* RCC_GRSTCSETR register fields */
+#define RCC_GRSTCSETR_SYSRST BIT(0)
+
+/* RCC_C1RSTCSETR register fields */
+#define RCC_C1RSTCSETR_C1RST BIT(0)
+
+/* RCC_C1P1RSTCSETR register fields */
+#define RCC_C1P1RSTCSETR_C1P1PORRST BIT(0)
+#define RCC_C1P1RSTCSETR_C1P1RST BIT(1)
+
+/* RCC_C2RSTCSETR register fields */
+#define RCC_C2RSTCSETR_C2RST BIT(0)
+
+/* RCC_CxRSTCSETR register fields */
+#define RCC_CxRSTCSETR_CxRST BIT(0)
+
+/* RCC_HWRSTSCLRR register fields */
+#define RCC_HWRSTSCLRR_PORRSTF BIT(0)
+#define RCC_HWRSTSCLRR_BORRSTF BIT(1)
+#define RCC_HWRSTSCLRR_PADRSTF BIT(2)
+#define RCC_HWRSTSCLRR_HCSSRSTF BIT(3)
+#define RCC_HWRSTSCLRR_VCORERSTF BIT(4)
+#define RCC_HWRSTSCLRR_SYSC1RSTF BIT(5)
+#define RCC_HWRSTSCLRR_SYSC2RSTF BIT(6)
+#define RCC_HWRSTSCLRR_IWDG1SYSRSTF BIT(7)
+#define RCC_HWRSTSCLRR_IWDG2SYSRSTF BIT(8)
+#define RCC_HWRSTSCLRR_IWDG3SYSRSTF BIT(9)
+#define RCC_HWRSTSCLRR_IWDG4SYSRSTF BIT(10)
+#define RCC_HWRSTSCLRR_IWDG5SYSRSTF BIT(11)
+#define RCC_HWRSTSCLRR_RETCRCERRRSTF BIT(12)
+#define RCC_HWRSTSCLRR_RETECCFAILCRCRSTF BIT(13)
+#define RCC_HWRSTSCLRR_RETECCFAILRESTRSTF BIT(14)
+
+/* RCC_C1HWRSTSCLRR register fields */
+#define RCC_C1HWRSTSCLRR_VCPURSTF BIT(0)
+#define RCC_C1HWRSTSCLRR_C1RSTF BIT(1)
+#define RCC_C1HWRSTSCLRR_C1P1RSTF BIT(2)
+
+/* RCC_C2HWRSTSCLRR register fields */
+#define RCC_C2HWRSTSCLRR_C2RSTF BIT(0)
+
+/* RCC_C1BOOTRSTSSETR register fields */
+#define RCC_C1BOOTRSTSSETR_PORRSTF BIT(0)
+#define RCC_C1BOOTRSTSSETR_BORRSTF BIT(1)
+#define RCC_C1BOOTRSTSSETR_PADRSTF BIT(2)
+#define RCC_C1BOOTRSTSSETR_HCSSRSTF BIT(3)
+#define RCC_C1BOOTRSTSSETR_VCORERSTF BIT(4)
+#define RCC_C1BOOTRSTSSETR_VCPURSTF BIT(5)
+#define RCC_C1BOOTRSTSSETR_SYSC1RSTF BIT(6)
+#define RCC_C1BOOTRSTSSETR_SYSC2RSTF BIT(7)
+#define RCC_C1BOOTRSTSSETR_IWDG1SYSRSTF BIT(8)
+#define RCC_C1BOOTRSTSSETR_IWDG2SYSRSTF BIT(9)
+#define RCC_C1BOOTRSTSSETR_IWDG3SYSRSTF BIT(10)
+#define RCC_C1BOOTRSTSSETR_IWDG4SYSRSTF BIT(11)
+#define RCC_C1BOOTRSTSSETR_IWDG5SYSRSTF BIT(12)
+#define RCC_C1BOOTRSTSSETR_C1RSTF BIT(13)
+#define RCC_C1BOOTRSTSSETR_C1P1RSTF BIT(16)
+#define RCC_C1BOOTRSTSSETR_RETCRCERRRSTF BIT(17)
+#define RCC_C1BOOTRSTSSETR_RETECCFAILCRCRSTF BIT(18)
+#define RCC_C1BOOTRSTSSETR_RETECCFAILRESTRSTF BIT(19)
+#define RCC_C1BOOTRSTSSETR_STBYC1RSTF BIT(20)
+#define RCC_C1BOOTRSTSSETR_D1STBYRSTF BIT(22)
+#define RCC_C1BOOTRSTSSETR_D2STBYRSTF BIT(23)
+
+/* RCC_C1BOOTRSTSCLRR register fields */
+#define RCC_C1BOOTRSTSCLRR_PORRSTF BIT(0)
+#define RCC_C1BOOTRSTSCLRR_BORRSTF BIT(1)
+#define RCC_C1BOOTRSTSCLRR_PADRSTF BIT(2)
+#define RCC_C1BOOTRSTSCLRR_HCSSRSTF BIT(3)
+#define RCC_C1BOOTRSTSCLRR_VCORERSTF BIT(4)
+#define RCC_C1BOOTRSTSCLRR_VCPURSTF BIT(5)
+#define RCC_C1BOOTRSTSCLRR_SYSC1RSTF BIT(6)
+#define RCC_C1BOOTRSTSCLRR_SYSC2RSTF BIT(7)
+#define RCC_C1BOOTRSTSCLRR_IWDG1SYSRSTF BIT(8)
+#define RCC_C1BOOTRSTSCLRR_IWDG2SYSRSTF BIT(9)
+#define RCC_C1BOOTRSTSCLRR_IWDG3SYSRSTF BIT(10)
+#define RCC_C1BOOTRSTSCLRR_IWDG4SYSRSTF BIT(11)
+#define RCC_C1BOOTRSTSCLRR_IWDG5SYSRSTF BIT(12)
+#define RCC_C1BOOTRSTSCLRR_C1RSTF BIT(13)
+#define RCC_C1BOOTRSTSCLRR_C1P1RSTF BIT(16)
+#define RCC_C1BOOTRSTSCLRR_RETCRCERRRSTF BIT(17)
+#define RCC_C1BOOTRSTSCLRR_RETECCFAILCRCRSTF BIT(18)
+#define RCC_C1BOOTRSTSCLRR_RETECCFAILRESTRSTF BIT(19)
+#define RCC_C1BOOTRSTSCLRR_STBYC1RSTF BIT(20)
+#define RCC_C1BOOTRSTSCLRR_D1STBYRSTF BIT(22)
+#define RCC_C1BOOTRSTSCLRR_D2STBYRSTF BIT(23)
+
+/* RCC_C2BOOTRSTSSETR register fields */
+#define RCC_C2BOOTRSTSSETR_PORRSTF BIT(0)
+#define RCC_C2BOOTRSTSSETR_BORRSTF BIT(1)
+#define RCC_C2BOOTRSTSSETR_PADRSTF BIT(2)
+#define RCC_C2BOOTRSTSSETR_HCSSRSTF BIT(3)
+#define RCC_C2BOOTRSTSSETR_VCORERSTF BIT(4)
+#define RCC_C2BOOTRSTSSETR_SYSC1RSTF BIT(6)
+#define RCC_C2BOOTRSTSSETR_SYSC2RSTF BIT(7)
+#define RCC_C2BOOTRSTSSETR_IWDG1SYSRSTF BIT(8)
+#define RCC_C2BOOTRSTSSETR_IWDG2SYSRSTF BIT(9)
+#define RCC_C2BOOTRSTSSETR_IWDG3SYSRSTF BIT(10)
+#define RCC_C2BOOTRSTSSETR_IWDG4SYSRSTF BIT(11)
+#define RCC_C2BOOTRSTSSETR_IWDG5SYSRSTF BIT(12)
+#define RCC_C2BOOTRSTSSETR_C2RSTF BIT(14)
+#define RCC_C2BOOTRSTSSETR_RETCRCERRRSTF BIT(17)
+#define RCC_C2BOOTRSTSSETR_RETECCFAILCRCRSTF BIT(18)
+#define RCC_C2BOOTRSTSSETR_RETECCFAILRESTRSTF BIT(19)
+#define RCC_C2BOOTRSTSSETR_STBYC2RSTF BIT(21)
+#define RCC_C2BOOTRSTSSETR_D2STBYRSTF BIT(23)
+
+/* RCC_C2BOOTRSTSCLRR register fields */
+#define RCC_C2BOOTRSTSCLRR_PORRSTF BIT(0)
+#define RCC_C2BOOTRSTSCLRR_BORRSTF BIT(1)
+#define RCC_C2BOOTRSTSCLRR_PADRSTF BIT(2)
+#define RCC_C2BOOTRSTSCLRR_HCSSRSTF BIT(3)
+#define RCC_C2BOOTRSTSCLRR_VCORERSTF BIT(4)
+#define RCC_C2BOOTRSTSCLRR_SYSC1RSTF BIT(6)
+#define RCC_C2BOOTRSTSCLRR_SYSC2RSTF BIT(7)
+#define RCC_C2BOOTRSTSCLRR_IWDG1SYSRSTF BIT(8)
+#define RCC_C2BOOTRSTSCLRR_IWDG2SYSRSTF BIT(9)
+#define RCC_C2BOOTRSTSCLRR_IWDG3SYSRSTF BIT(10)
+#define RCC_C2BOOTRSTSCLRR_IWDG4SYSRSTF BIT(11)
+#define RCC_C2BOOTRSTSCLRR_IWDG5SYSRSTF BIT(12)
+#define RCC_C2BOOTRSTSCLRR_C2RSTF BIT(14)
+#define RCC_C2BOOTRSTSCLRR_RETCRCERRRSTF BIT(17)
+#define RCC_C2BOOTRSTSCLRR_RETECCFAILCRCRSTF BIT(18)
+#define RCC_C2BOOTRSTSCLRR_RETECCFAILRESTRSTF BIT(19)
+#define RCC_C2BOOTRSTSCLRR_STBYC2RSTF BIT(21)
+#define RCC_C2BOOTRSTSCLRR_D2STBYRSTF BIT(23)
+
+/* RCC_C1SREQSETR register fields */
+#define RCC_C1SREQSETR_STPREQ_P0 BIT(0)
+#define RCC_C1SREQSETR_STPREQ_P1 BIT(1)
+#define RCC_C1SREQSETR_ESLPREQ BIT(16)
+
+/* RCC_C1SREQCLRR register fields */
+#define RCC_C1SREQCLRR_STPREQ_P0 BIT(0)
+#define RCC_C1SREQCLRR_STPREQ_P1 BIT(1)
+#define RCC_C1SREQCLRR_ESLPREQ BIT(16)
+
+/* RCC_CPUBOOTCR register fields */
+#define RCC_CPUBOOTCR_BOOT_CPU2 BIT(0)
+#define RCC_CPUBOOTCR_BOOT_CPU1 BIT(1)
+
+/* RCC_STBYBOOTCR register fields */
+#define RCC_STBYBOOTCR_CPU_BEN_SEL BIT(1)
+#define RCC_STBYBOOTCR_COLD_CPU2 BIT(2)
+#define RCC_STBYBOOTCR_CPU2_HW_BEN BIT(4)
+#define RCC_STBYBOOTCR_CPU1_HW_BEN BIT(5)
+#define RCC_STBYBOOTCR_RET_CRCERR_RSTEN BIT(8)
+
+/* RCC_LEGBOOTCR register fields */
+#define RCC_LEGBOOTCR_LEGACY_BEN BIT(0)
+
+/* RCC_BDCR register fields */
+#define RCC_BDCR_LSEON BIT(0)
+#define RCC_BDCR_LSEBYP BIT(1)
+#define RCC_BDCR_LSERDY BIT(2)
+#define RCC_BDCR_LSEDIGBYP BIT(3)
+#define RCC_BDCR_LSEDRV_MASK GENMASK_32(5, 4)
+#define RCC_BDCR_LSEDRV_SHIFT 4
+#define RCC_BDCR_LSECSSON BIT(6)
+#define RCC_BDCR_LSEGFON BIT(7)
+#define RCC_BDCR_LSECSSD BIT(8)
+#define RCC_BDCR_LSION BIT(9)
+#define RCC_BDCR_LSIRDY BIT(10)
+#define RCC_BDCR_RTCSRC_MASK GENMASK_32(17, 16)
+#define RCC_BDCR_RTCSRC_SHIFT 16
+#define RCC_BDCR_RTCCKEN BIT(20)
+#define RCC_BDCR_MSIFREQSEL BIT(24)
+#define RCC_BDCR_C3SYSTICKSEL BIT(25)
+#define RCC_BDCR_VSWRST BIT(31)
+#define RCC_BDCR_LSEBYP_BIT 1
+#define RCC_BDCR_LSEDIGBYP_BIT 3
+#define RCC_BDCR_LSECSSON_BIT 6
+#define RCC_BDCR_LSERDY_BIT 2
+#define RCC_BDCR_LSIRDY_BIT 10
+
+#define RCC_BDCR_LSEDRV_SHIFT 4
+#define RCC_BDCR_LSEDRV_WIDTH 2
+
+/* RCC_D3DCR register fields */
+#define RCC_D3DCR_CSION BIT(0)
+#define RCC_D3DCR_CSIKERON BIT(1)
+#define RCC_D3DCR_CSIRDY BIT(2)
+#define RCC_D3DCR_D3PERCKSEL_MASK GENMASK_32(17, 16)
+#define RCC_D3DCR_D3PERCKSEL_SHIFT 16
+#define RCC_D3DCR_CSIRDY_BIT 2
+
+/* RCC_D3DSR register fields */
+#define RCC_D3DSR_D3STATE_MASK GENMASK_32(1, 0)
+#define RCC_D3DSR_D3STATE_SHIFT 0
+
+/* RCC_RDCR register fields */
+#define RCC_RDCR_MRD_MASK GENMASK_32(20, 16)
+#define RCC_RDCR_MRD_SHIFT 16
+#define RCC_RDCR_EADLY_MASK GENMASK_32(27, 24)
+#define RCC_RDCR_EADLY_SHIFT 24
+
+/* RCC_C1MSRDCR register fields */
+#define RCC_C1MSRDCR_C1MSRD_MASK GENMASK_32(4, 0)
+#define RCC_C1MSRDCR_C1MSRD_SHIFT 0
+#define RCC_C1MSRDCR_C1MSRST BIT(8)
+
+/* RCC_PWRLPDLYCR register fields */
+#define RCC_PWRLPDLYCR_PWRLP_DLY_MASK GENMASK_32(21, 0)
+#define RCC_PWRLPDLYCR_PWRLP_DLY_SHIFT 0
+#define RCC_PWRLPDLYCR_CPU2TMPSKP BIT(24)
+
+/* RCC_C1CIESETR register fields */
+#define RCC_C1CIESETR_LSIRDYIE BIT(0)
+#define RCC_C1CIESETR_LSERDYIE BIT(1)
+#define RCC_C1CIESETR_HSIRDYIE BIT(2)
+#define RCC_C1CIESETR_HSERDYIE BIT(3)
+#define RCC_C1CIESETR_CSIRDYIE BIT(4)
+#define RCC_C1CIESETR_PLL1RDYIE BIT(5)
+#define RCC_C1CIESETR_PLL2RDYIE BIT(6)
+#define RCC_C1CIESETR_PLL3RDYIE BIT(7)
+#define RCC_C1CIESETR_PLL4RDYIE BIT(8)
+#define RCC_C1CIESETR_PLL5RDYIE BIT(9)
+#define RCC_C1CIESETR_PLL6RDYIE BIT(10)
+#define RCC_C1CIESETR_PLL7RDYIE BIT(11)
+#define RCC_C1CIESETR_PLL8RDYIE BIT(12)
+#define RCC_C1CIESETR_LSECSSIE BIT(16)
+#define RCC_C1CIESETR_WKUPIE BIT(20)
+
+/* RCC_C1CIFCLRR register fields */
+#define RCC_C1CIFCLRR_LSIRDYF BIT(0)
+#define RCC_C1CIFCLRR_LSERDYF BIT(1)
+#define RCC_C1CIFCLRR_HSIRDYF BIT(2)
+#define RCC_C1CIFCLRR_HSERDYF BIT(3)
+#define RCC_C1CIFCLRR_CSIRDYF BIT(4)
+#define RCC_C1CIFCLRR_PLL1RDYF BIT(5)
+#define RCC_C1CIFCLRR_PLL2RDYF BIT(6)
+#define RCC_C1CIFCLRR_PLL3RDYF BIT(7)
+#define RCC_C1CIFCLRR_PLL4RDYF BIT(8)
+#define RCC_C1CIFCLRR_PLL5RDYF BIT(9)
+#define RCC_C1CIFCLRR_PLL6RDYF BIT(10)
+#define RCC_C1CIFCLRR_PLL7RDYF BIT(11)
+#define RCC_C1CIFCLRR_PLL8RDYF BIT(12)
+#define RCC_C1CIFCLRR_LSECSSF BIT(16)
+#define RCC_C1CIFCLRR_WKUPF BIT(20)
+
+/* RCC_C2CIESETR register fields */
+#define RCC_C2CIESETR_LSIRDYIE BIT(0)
+#define RCC_C2CIESETR_LSERDYIE BIT(1)
+#define RCC_C2CIESETR_HSIRDYIE BIT(2)
+#define RCC_C2CIESETR_HSERDYIE BIT(3)
+#define RCC_C2CIESETR_CSIRDYIE BIT(4)
+#define RCC_C2CIESETR_PLL1RDYIE BIT(5)
+#define RCC_C2CIESETR_PLL2RDYIE BIT(6)
+#define RCC_C2CIESETR_PLL3RDYIE BIT(7)
+#define RCC_C2CIESETR_PLL4RDYIE BIT(8)
+#define RCC_C2CIESETR_PLL5RDYIE BIT(9)
+#define RCC_C2CIESETR_PLL6RDYIE BIT(10)
+#define RCC_C2CIESETR_PLL7RDYIE BIT(11)
+#define RCC_C2CIESETR_PLL8RDYIE BIT(12)
+#define RCC_C2CIESETR_LSECSSIE BIT(16)
+#define RCC_C2CIESETR_WKUPIE BIT(20)
+
+/* RCC_C2CIFCLRR register fields */
+#define RCC_C2CIFCLRR_LSIRDYF BIT(0)
+#define RCC_C2CIFCLRR_LSERDYF BIT(1)
+#define RCC_C2CIFCLRR_HSIRDYF BIT(2)
+#define RCC_C2CIFCLRR_HSERDYF BIT(3)
+#define RCC_C2CIFCLRR_CSIRDYF BIT(4)
+#define RCC_C2CIFCLRR_PLL1RDYF BIT(5)
+#define RCC_C2CIFCLRR_PLL2RDYF BIT(6)
+#define RCC_C2CIFCLRR_PLL3RDYF BIT(7)
+#define RCC_C2CIFCLRR_PLL4RDYF BIT(8)
+#define RCC_C2CIFCLRR_PLL5RDYF BIT(9)
+#define RCC_C2CIFCLRR_PLL6RDYF BIT(10)
+#define RCC_C2CIFCLRR_PLL7RDYF BIT(11)
+#define RCC_C2CIFCLRR_PLL8RDYF BIT(12)
+#define RCC_C2CIFCLRR_LSECSSF BIT(16)
+#define RCC_C2CIFCLRR_WKUPF BIT(20)
+
+/* RCC_CxCIESETR register fields */
+#define RCC_CxCIESETR_LSIRDYIE BIT(0)
+#define RCC_CxCIESETR_LSERDYIE BIT(1)
+#define RCC_CxCIESETR_HSIRDYIE BIT(2)
+#define RCC_CxCIESETR_HSERDYIE BIT(3)
+#define RCC_CxCIESETR_CSIRDYIE BIT(4)
+#define RCC_CxCIESETR_SHSIRDYIE BIT(5)
+#define RCC_CxCIESETR_PLL1RDYIE BIT(6)
+#define RCC_CxCIESETR_PLL2RDYIE BIT(7)
+#define RCC_CxCIESETR_PLL3RDYIE BIT(8)
+#define RCC_CxCIESETR_PLL4RDYIE BIT(9)
+#define RCC_CxCIESETR_PLL5RDYIE BIT(10)
+#define RCC_CxCIESETR_PLL6RDYIE BIT(11)
+#define RCC_CxCIESETR_PLL7RDYIE BIT(12)
+#define RCC_CxCIESETR_PLL8RDYIE BIT(13)
+#define RCC_CxCIESETR_LSECSSIE BIT(16)
+#define RCC_CxCIESETR_WKUPIE BIT(20)
+
+/* RCC_CxCIFCLRR register fields */
+#define RCC_CxCIFCLRR_LSIRDYF BIT(0)
+#define RCC_CxCIFCLRR_LSERDYF BIT(1)
+#define RCC_CxCIFCLRR_HSIRDYF BIT(2)
+#define RCC_CxCIFCLRR_HSERDYF BIT(3)
+#define RCC_CxCIFCLRR_CSIRDYF BIT(4)
+#define RCC_CxCIFCLRR_SHSIRDYF BIT(5)
+#define RCC_CxCIFCLRR_PLL1RDYF BIT(6)
+#define RCC_CxCIFCLRR_PLL2RDYF BIT(7)
+#define RCC_CxCIFCLRR_PLL3RDYF BIT(8)
+#define RCC_CxCIFCLRR_PLL4RDYF BIT(9)
+#define RCC_CxCIFCLRR_PLL5RDYF BIT(10)
+#define RCC_CxCIFCLRR_PLL6RDYF BIT(11)
+#define RCC_CxCIFCLRR_PLL7RDYF BIT(12)
+#define RCC_CxCIFCLRR_PLL8RDYF BIT(13)
+#define RCC_CxCIFCLRR_LSECSSF BIT(16)
+#define RCC_CxCIFCLRR_WKUPF BIT(20)
+
+/* RCC_IWDGC1FZSETR register fields */
+#define RCC_IWDGC1FZSETR_FZ_IWDG1 BIT(0)
+#define RCC_IWDGC1FZSETR_FZ_IWDG2 BIT(1)
+
+/* RCC_IWDGC1FZCLRR register fields */
+#define RCC_IWDGC1FZCLRR_FZ_IWDG1 BIT(0)
+#define RCC_IWDGC1FZCLRR_FZ_IWDG2 BIT(1)
+
+/* RCC_IWDGC1CFGSETR register fields */
+#define RCC_IWDGC1CFGSETR_IWDG1_SYSRSTEN BIT(0)
+#define RCC_IWDGC1CFGSETR_IWDG2_SYSRSTEN BIT(2)
+#define RCC_IWDGC1CFGSETR_IWDG2_KERRST BIT(18)
+
+/* RCC_IWDGC1CFGCLRR register fields */
+#define RCC_IWDGC1CFGCLRR_IWDG1_SYSRSTEN BIT(0)
+#define RCC_IWDGC1CFGCLRR_IWDG2_SYSRSTEN BIT(2)
+#define RCC_IWDGC1CFGCLRR_IWDG2_KERRST BIT(18)
+
+/* RCC_IWDGC2FZSETR register fields */
+#define RCC_IWDGC2FZSETR_FZ_IWDG3 BIT(0)
+#define RCC_IWDGC2FZSETR_FZ_IWDG4 BIT(1)
+
+/* RCC_IWDGC2FZCLRR register fields */
+#define RCC_IWDGC2FZCLRR_FZ_IWDG3 BIT(0)
+#define RCC_IWDGC2FZCLRR_FZ_IWDG4 BIT(1)
+
+/* RCC_IWDGC2CFGSETR register fields */
+#define RCC_IWDGC2CFGSETR_IWDG3_SYSRSTEN BIT(0)
+#define RCC_IWDGC2CFGSETR_IWDG4_SYSRSTEN BIT(2)
+#define RCC_IWDGC2CFGSETR_IWDG4_KERRST BIT(18)
+
+/* RCC_IWDGC2CFGCLRR register fields */
+#define RCC_IWDGC2CFGCLRR_IWDG3_SYSRSTEN BIT(0)
+#define RCC_IWDGC2CFGCLRR_IWDG4_SYSRSTEN BIT(2)
+#define RCC_IWDGC2CFGCLRR_IWDG4_KERRST BIT(18)
+
+/* RCC_IWDGC3CFGSETR register fields */
+#define RCC_IWDGC3CFGSETR_IWDG5_SYSRSTEN BIT(0)
+
+/* RCC_IWDGC3CFGCLRR register fields */
+#define RCC_IWDGC3CFGCLRR_IWDG5_SYSRSTEN BIT(0)
+
+/* RCC_C3CFGR register fields */
+#define RCC_C3CFGR_C3RST BIT(0)
+#define RCC_C3CFGR_C3EN BIT(1)
+#define RCC_C3CFGR_C3LPEN BIT(2)
+#define RCC_C3CFGR_C3AMEN BIT(3)
+#define RCC_C3CFGR_LPTIM3C3EN BIT(16)
+#define RCC_C3CFGR_LPTIM4C3EN BIT(17)
+#define RCC_C3CFGR_LPTIM5C3EN BIT(18)
+#define RCC_C3CFGR_SPI8C3EN BIT(19)
+#define RCC_C3CFGR_LPUART1C3EN BIT(20)
+#define RCC_C3CFGR_I2C8C3EN BIT(21)
+#define RCC_C3CFGR_ADF1C3EN BIT(23)
+#define RCC_C3CFGR_GPIOZC3EN BIT(24)
+#define RCC_C3CFGR_LPDMAC3EN BIT(25)
+#define RCC_C3CFGR_RTCC3EN BIT(26)
+#define RCC_C3CFGR_I3C4C3EN BIT(27)
+
+/* RCC_MCO1CFGR register fields */
+#define RCC_MCO1CFGR_MCO1SEL BIT(0)
+#define RCC_MCO1CFGR_MCO1ON BIT(8)
+
+/* RCC_MCO2CFGR register fields */
+#define RCC_MCO2CFGR_MCO2SEL BIT(0)
+#define RCC_MCO2CFGR_MCO2ON BIT(8)
+
+/* RCC_MCOxCFGR register fields */
+#define RCC_MCOxCFGR_MCOxSEL BIT(0)
+#define RCC_MCOxCFGR_MCOxON BIT(8)
+
+/* RCC_OCENSETR register fields */
+#define RCC_OCENSETR_HSION BIT(0)
+#define RCC_OCENSETR_HSIKERON BIT(1)
+#define RCC_OCENSETR_HSEDIV2ON BIT(5)
+#define RCC_OCENSETR_HSEDIV2BYP BIT(6)
+#define RCC_OCENSETR_HSEDIGBYP BIT(7)
+#define RCC_OCENSETR_HSEON BIT(8)
+#define RCC_OCENSETR_HSEKERON BIT(9)
+#define RCC_OCENSETR_HSEBYP BIT(10)
+#define RCC_OCENSETR_HSECSSON BIT(11)
+
+/* RCC_OCENCLRR register fields */
+#define RCC_OCENCLRR_HSION BIT(0)
+#define RCC_OCENCLRR_HSIKERON BIT(1)
+#define RCC_OCENCLRR_HSEDIV2ON BIT(5)
+#define RCC_OCENCLRR_HSEDIV2BYP BIT(6)
+#define RCC_OCENCLRR_HSEDIGBYP BIT(7)
+#define RCC_OCENCLRR_HSEON BIT(8)
+#define RCC_OCENCLRR_HSEKERON BIT(9)
+#define RCC_OCENCLRR_HSEBYP BIT(10)
+
+/* RCC_OCRDYR register fields */
+#define RCC_OCRDYR_HSIRDY BIT(0)
+#define RCC_OCRDYR_HSERDY BIT(8)
+#define RCC_OCRDYR_CKREST BIT(25)
+
+#define RCC_OCRDYR_HSIRDY_BIT 0
+#define RCC_OCRDYR_HSERDY_BIT 8
+
+/* RCC_HSICFGR register fields */
+#define RCC_HSICFGR_HSITRIM_MASK GENMASK_32(14, 8)
+#define RCC_HSICFGR_HSITRIM_SHIFT 8
+#define RCC_HSICFGR_HSICAL_MASK GENMASK_32(24, 16)
+#define RCC_HSICFGR_HSICAL_SHIFT 16
+
+/* RCC_CSICFGR register fields */
+#define RCC_CSICFGR_CSITRIM_MASK GENMASK_32(12, 8)
+#define RCC_CSICFGR_CSITRIM_SHIFT 8
+#define RCC_CSICFGR_CSICAL_MASK GENMASK_32(23, 16)
+#define RCC_CSICFGR_CSICAL_SHIFT 16
+
+/* RCC_RTCDIVR register fields */
+#define RCC_RTCDIVR_RTCDIV_MASK GENMASK_32(5, 0)
+#define RCC_RTCDIVR_RTCDIV_SHIFT 0
+
+/* RCC_APB1DIVR register fields */
+#define RCC_APB1DIVR_APB1DIV_MASK GENMASK_32(2, 0)
+#define RCC_APB1DIVR_APB1DIV_SHIFT 0
+#define RCC_APB1DIVR_APB1DIVRDY BIT(31)
+
+/* RCC_APB2DIVR register fields */
+#define RCC_APB2DIVR_APB2DIV_MASK GENMASK_32(2, 0)
+#define RCC_APB2DIVR_APB2DIV_SHIFT 0
+#define RCC_APB2DIVR_APB2DIVRDY BIT(31)
+
+/* RCC_APB3DIVR register fields */
+#define RCC_APB3DIVR_APB3DIV_MASK GENMASK_32(2, 0)
+#define RCC_APB3DIVR_APB3DIV_SHIFT 0
+#define RCC_APB3DIVR_APB3DIVRDY BIT(31)
+
+/* RCC_APB4DIVR register fields */
+#define RCC_APB4DIVR_APB4DIV_MASK GENMASK_32(2, 0)
+#define RCC_APB4DIVR_APB4DIV_SHIFT 0
+#define RCC_APB4DIVR_APB4DIVRDY BIT(31)
+
+/* RCC_APBDBGDIVR register fields */
+#define RCC_APBDBGDIVR_APBDBGDIV_MASK GENMASK_32(2, 0)
+#define RCC_APBDBGDIVR_APBDBGDIV_SHIFT 0
+#define RCC_APBDBGDIVR_APBDBGDIVRDY BIT(31)
+
+/* RCC_APBxDIVR register fields */
+#define RCC_APBxDIVR_APBxDIV_MASK GENMASK_32(2, 0)
+#define RCC_APBxDIVR_APBxDIV_SHIFT 0
+#define RCC_APBxDIVR_APBxDIVRDY BIT(31)
+
+/* RCC_TIMG1PRER register fields */
+#define RCC_TIMG1PRER_TIMG1PRE BIT(0)
+#define RCC_TIMG1PRER_TIMG1PRERDY BIT(31)
+
+/* RCC_TIMG2PRER register fields */
+#define RCC_TIMG2PRER_TIMG2PRE BIT(0)
+#define RCC_TIMG2PRER_TIMG2PRERDY BIT(31)
+
+/* RCC_TIMGxPRER register fields */
+#define RCC_TIMGxPRER_TIMGxPRE BIT(0)
+#define RCC_TIMGxPRER_TIMGxPRERDY BIT(31)
+
+/* RCC_LSMCUDIVR register fields */
+#define RCC_LSMCUDIVR_LSMCUDIV BIT(0)
+#define RCC_LSMCUDIVR_LSMCUDIVRDY BIT(31)
+
+/* RCC_DDRCPCFGR register fields */
+#define RCC_DDRCPCFGR_DDRCPRST BIT(0)
+#define RCC_DDRCPCFGR_DDRCPEN BIT(1)
+#define RCC_DDRCPCFGR_DDRCPLPEN BIT(2)
+
+/* RCC_DDRCAPBCFGR register fields */
+#define RCC_DDRCAPBCFGR_DDRCAPBRST BIT(0)
+#define RCC_DDRCAPBCFGR_DDRCAPBEN BIT(1)
+#define RCC_DDRCAPBCFGR_DDRCAPBLPEN BIT(2)
+
+/* RCC_DDRPHYCAPBCFGR register fields */
+#define RCC_DDRPHYCAPBCFGR_DDRPHYCAPBRST BIT(0)
+#define RCC_DDRPHYCAPBCFGR_DDRPHYCAPBEN BIT(1)
+#define RCC_DDRPHYCAPBCFGR_DDRPHYCAPBLPEN BIT(2)
+
+/* RCC_DDRPHYCCFGR register fields */
+#define RCC_DDRPHYCCFGR_DDRPHYCEN BIT(1)
+
+/* RCC_DDRCFGR register fields */
+#define RCC_DDRCFGR_DDRCFGRST BIT(0)
+#define RCC_DDRCFGR_DDRCFGEN BIT(1)
+#define RCC_DDRCFGR_DDRCFGLPEN BIT(2)
+
+/* RCC_DDRITFCFGR register fields */
+#define RCC_DDRITFCFGR_DDRRST BIT(0)
+#define RCC_DDRITFCFGR_DDRCKMOD_MASK GENMASK_32(5, 4)
+#define RCC_DDRITFCFGR_DDRCKMOD_SHIFT 4
+#define RCC_DDRITFCFGR_DDRCKMOD_HSR BIT(5)
+#define RCC_DDRITFCFGR_DDRSHR BIT(8)
+#define RCC_DDRITFCFGR_DDRPHYDLP BIT(16)
+
+/* RCC_SYSRAMCFGR register fields */
+#define RCC_SYSRAMCFGR_SYSRAMEN BIT(1)
+#define RCC_SYSRAMCFGR_SYSRAMLPEN BIT(2)
+
+/* RCC_VDERAMCFGR register fields */
+#define RCC_VDERAMCFGR_VDERAMEN BIT(1)
+#define RCC_VDERAMCFGR_VDERAMLPEN BIT(2)
+
+/* RCC_SRAM1CFGR register fields */
+#define RCC_SRAM1CFGR_SRAM1EN BIT(1)
+#define RCC_SRAM1CFGR_SRAM1LPEN BIT(2)
+
+/* RCC_SRAM2CFGR register fields */
+#define RCC_SRAM2CFGR_SRAM2EN BIT(1)
+#define RCC_SRAM2CFGR_SRAM2LPEN BIT(2)
+
+/* RCC_RETRAMCFGR register fields */
+#define RCC_RETRAMCFGR_RETRAMEN BIT(1)
+#define RCC_RETRAMCFGR_RETRAMLPEN BIT(2)
+
+/* RCC_BKPSRAMCFGR register fields */
+#define RCC_BKPSRAMCFGR_BKPSRAMEN BIT(1)
+#define RCC_BKPSRAMCFGR_BKPSRAMLPEN BIT(2)
+
+/* RCC_LPSRAM1CFGR register fields */
+#define RCC_LPSRAM1CFGR_LPSRAM1EN BIT(1)
+#define RCC_LPSRAM1CFGR_LPSRAM1LPEN BIT(2)
+#define RCC_LPSRAM1CFGR_LPSRAM1AMEN BIT(3)
+
+/* RCC_LPSRAM2CFGR register fields */
+#define RCC_LPSRAM2CFGR_LPSRAM2EN BIT(1)
+#define RCC_LPSRAM2CFGR_LPSRAM2LPEN BIT(2)
+#define RCC_LPSRAM2CFGR_LPSRAM2AMEN BIT(3)
+
+/* RCC_LPSRAM3CFGR register fields */
+#define RCC_LPSRAM3CFGR_LPSRAM3EN BIT(1)
+#define RCC_LPSRAM3CFGR_LPSRAM3LPEN BIT(2)
+#define RCC_LPSRAM3CFGR_LPSRAM3AMEN BIT(3)
+
+/* RCC_OSPI1CFGR register fields */
+#define RCC_OSPI1CFGR_OSPI1RST BIT(0)
+#define RCC_OSPI1CFGR_OSPI1EN BIT(1)
+#define RCC_OSPI1CFGR_OSPI1LPEN BIT(2)
+#define RCC_OSPI1CFGR_OTFDEC1RST BIT(8)
+#define RCC_OSPI1CFGR_OSPI1DLLRST BIT(16)
+
+/* RCC_OSPI2CFGR register fields */
+#define RCC_OSPI2CFGR_OSPI2RST BIT(0)
+#define RCC_OSPI2CFGR_OSPI2EN BIT(1)
+#define RCC_OSPI2CFGR_OSPI2LPEN BIT(2)
+#define RCC_OSPI2CFGR_OTFDEC2RST BIT(8)
+#define RCC_OSPI2CFGR_OSPI2DLLRST BIT(16)
+
+/* RCC_OSPIxCFGR register fields */
+#define RCC_OSPIxCFGR_OSPIxRST BIT(0)
+#define RCC_OSPIxCFGR_OSPIxEN BIT(1)
+#define RCC_OSPIxCFGR_OSPIxLPEN BIT(2)
+#define RCC_OSPIxCFGR_OTFDECxRST BIT(8)
+#define RCC_OSPIxCFGR_OSPIxDLLRST BIT(16)
+
+/* RCC_FMCCFGR register fields */
+#define RCC_FMCCFGR_FMCRST BIT(0)
+#define RCC_FMCCFGR_FMCEN BIT(1)
+#define RCC_FMCCFGR_FMCLPEN BIT(2)
+
+/* RCC_DBGCFGR register fields */
+#define RCC_DBGCFGR_DBGEN BIT(8)
+#define RCC_DBGCFGR_TRACEEN BIT(9)
+#define RCC_DBGCFGR_DBGRST BIT(12)
+
+/* RCC_STM500CFGR register fields */
+#define RCC_STM500CFGR_STM500EN BIT(1)
+#define RCC_STM500CFGR_STM500LPEN BIT(2)
+
+/* RCC_ETRCFGR register fields */
+#define RCC_ETRCFGR_ETREN BIT(1)
+#define RCC_ETRCFGR_ETRLPEN BIT(2)
+
+/* RCC_GPIOACFGR register fields */
+#define RCC_GPIOACFGR_GPIOARST BIT(0)
+#define RCC_GPIOACFGR_GPIOAEN BIT(1)
+#define RCC_GPIOACFGR_GPIOALPEN BIT(2)
+
+/* RCC_GPIOBCFGR register fields */
+#define RCC_GPIOBCFGR_GPIOBRST BIT(0)
+#define RCC_GPIOBCFGR_GPIOBEN BIT(1)
+#define RCC_GPIOBCFGR_GPIOBLPEN BIT(2)
+
+/* RCC_GPIOCCFGR register fields */
+#define RCC_GPIOCCFGR_GPIOCRST BIT(0)
+#define RCC_GPIOCCFGR_GPIOCEN BIT(1)
+#define RCC_GPIOCCFGR_GPIOCLPEN BIT(2)
+
+/* RCC_GPIODCFGR register fields */
+#define RCC_GPIODCFGR_GPIODRST BIT(0)
+#define RCC_GPIODCFGR_GPIODEN BIT(1)
+#define RCC_GPIODCFGR_GPIODLPEN BIT(2)
+
+/* RCC_GPIOECFGR register fields */
+#define RCC_GPIOECFGR_GPIOERST BIT(0)
+#define RCC_GPIOECFGR_GPIOEEN BIT(1)
+#define RCC_GPIOECFGR_GPIOELPEN BIT(2)
+
+/* RCC_GPIOFCFGR register fields */
+#define RCC_GPIOFCFGR_GPIOFRST BIT(0)
+#define RCC_GPIOFCFGR_GPIOFEN BIT(1)
+#define RCC_GPIOFCFGR_GPIOFLPEN BIT(2)
+
+/* RCC_GPIOGCFGR register fields */
+#define RCC_GPIOGCFGR_GPIOGRST BIT(0)
+#define RCC_GPIOGCFGR_GPIOGEN BIT(1)
+#define RCC_GPIOGCFGR_GPIOGLPEN BIT(2)
+
+/* RCC_GPIOHCFGR register fields */
+#define RCC_GPIOHCFGR_GPIOHRST BIT(0)
+#define RCC_GPIOHCFGR_GPIOHEN BIT(1)
+#define RCC_GPIOHCFGR_GPIOHLPEN BIT(2)
+
+/* RCC_GPIOICFGR register fields */
+#define RCC_GPIOICFGR_GPIOIRST BIT(0)
+#define RCC_GPIOICFGR_GPIOIEN BIT(1)
+#define RCC_GPIOICFGR_GPIOILPEN BIT(2)
+
+/* RCC_GPIOJCFGR register fields */
+#define RCC_GPIOJCFGR_GPIOJRST BIT(0)
+#define RCC_GPIOJCFGR_GPIOJEN BIT(1)
+#define RCC_GPIOJCFGR_GPIOJLPEN BIT(2)
+
+/* RCC_GPIOKCFGR register fields */
+#define RCC_GPIOKCFGR_GPIOKRST BIT(0)
+#define RCC_GPIOKCFGR_GPIOKEN BIT(1)
+#define RCC_GPIOKCFGR_GPIOKLPEN BIT(2)
+
+/* RCC_GPIOZCFGR register fields */
+#define RCC_GPIOZCFGR_GPIOZRST BIT(0)
+#define RCC_GPIOZCFGR_GPIOZEN BIT(1)
+#define RCC_GPIOZCFGR_GPIOZLPEN BIT(2)
+#define RCC_GPIOZCFGR_GPIOZAMEN BIT(3)
+
+/* RCC_GPIOxCFGR register fields */
+#define RCC_GPIOxCFGR_GPIOxRST BIT(0)
+#define RCC_GPIOxCFGR_GPIOxEN BIT(1)
+#define RCC_GPIOxCFGR_GPIOxLPEN BIT(2)
+#define RCC_GPIOxCFGR_GPIOxAMEN BIT(3)
+
+/* RCC_HPDMA1CFGR register fields */
+#define RCC_HPDMA1CFGR_HPDMA1RST BIT(0)
+#define RCC_HPDMA1CFGR_HPDMA1EN BIT(1)
+#define RCC_HPDMA1CFGR_HPDMA1LPEN BIT(2)
+
+/* RCC_HPDMA2CFGR register fields */
+#define RCC_HPDMA2CFGR_HPDMA2RST BIT(0)
+#define RCC_HPDMA2CFGR_HPDMA2EN BIT(1)
+#define RCC_HPDMA2CFGR_HPDMA2LPEN BIT(2)
+
+/* RCC_HPDMA3CFGR register fields */
+#define RCC_HPDMA3CFGR_HPDMA3RST BIT(0)
+#define RCC_HPDMA3CFGR_HPDMA3EN BIT(1)
+#define RCC_HPDMA3CFGR_HPDMA3LPEN BIT(2)
+
+/* RCC_HPDMAxCFGR register fields */
+#define RCC_HPDMAxCFGR_HPDMAxRST BIT(0)
+#define RCC_HPDMAxCFGR_HPDMAxEN BIT(1)
+#define RCC_HPDMAxCFGR_HPDMAxLPEN BIT(2)
+
+/* RCC_LPDMACFGR register fields */
+#define RCC_LPDMACFGR_LPDMARST BIT(0)
+#define RCC_LPDMACFGR_LPDMAEN BIT(1)
+#define RCC_LPDMACFGR_LPDMALPEN BIT(2)
+#define RCC_LPDMACFGR_LPDMAAMEN BIT(3)
+
+/* RCC_HSEMCFGR register fields */
+#define RCC_HSEMCFGR_HSEMRST BIT(0)
+#define RCC_HSEMCFGR_HSEMEN BIT(1)
+#define RCC_HSEMCFGR_HSEMLPEN BIT(2)
+#define RCC_HSEMCFGR_HSEMAMEN BIT(3)
+
+/* RCC_IPCC1CFGR register fields */
+#define RCC_IPCC1CFGR_IPCC1RST BIT(0)
+#define RCC_IPCC1CFGR_IPCC1EN BIT(1)
+#define RCC_IPCC1CFGR_IPCC1LPEN BIT(2)
+
+/* RCC_IPCC2CFGR register fields */
+#define RCC_IPCC2CFGR_IPCC2RST BIT(0)
+#define RCC_IPCC2CFGR_IPCC2EN BIT(1)
+#define RCC_IPCC2CFGR_IPCC2LPEN BIT(2)
+#define RCC_IPCC2CFGR_IPCC2AMEN BIT(3)
+
+/* RCC_RTCCFGR register fields */
+#define RCC_RTCCFGR_RTCEN BIT(1)
+#define RCC_RTCCFGR_RTCLPEN BIT(2)
+#define RCC_RTCCFGR_RTCAMEN BIT(3)
+
+/* RCC_SYSCPU1CFGR register fields */
+#define RCC_SYSCPU1CFGR_SYSCPU1EN BIT(1)
+#define RCC_SYSCPU1CFGR_SYSCPU1LPEN BIT(2)
+
+/* RCC_BSECCFGR register fields */
+#define RCC_BSECCFGR_BSECEN BIT(1)
+#define RCC_BSECCFGR_BSECLPEN BIT(2)
+
+/* RCC_IS2MCFGR register fields */
+#define RCC_IS2MCFGR_IS2MRST BIT(0)
+#define RCC_IS2MCFGR_IS2MEN BIT(1)
+#define RCC_IS2MCFGR_IS2MLPEN BIT(2)
+
+/* RCC_PLL2CFGR1 register fields */
+#define RCC_PLL2CFGR1_SSMODRST BIT(0)
+#define RCC_PLL2CFGR1_PLLEN BIT(8)
+#define RCC_PLL2CFGR1_PLLRDY BIT(24)
+#define RCC_PLL2CFGR1_CKREFST BIT(28)
+
+/* RCC_PLL2CFGR2 register fields */
+#define RCC_PLL2CFGR2_FREFDIV_MASK GENMASK_32(5, 0)
+#define RCC_PLL2CFGR2_FREFDIV_SHIFT 0
+#define RCC_PLL2CFGR2_FBDIV_MASK GENMASK_32(27, 16)
+#define RCC_PLL2CFGR2_FBDIV_SHIFT 16
+
+/* RCC_PLL2CFGR3 register fields */
+#define RCC_PLL2CFGR3_FRACIN_MASK GENMASK_32(23, 0)
+#define RCC_PLL2CFGR3_FRACIN_SHIFT 0
+#define RCC_PLL2CFGR3_DOWNSPREAD BIT(24)
+#define RCC_PLL2CFGR3_DACEN BIT(25)
+#define RCC_PLL2CFGR3_SSCGDIS BIT(26)
+
+/* RCC_PLL2CFGR4 register fields */
+#define RCC_PLL2CFGR4_DSMEN BIT(8)
+#define RCC_PLL2CFGR4_FOUTPOSTDIVEN BIT(9)
+#define RCC_PLL2CFGR4_BYPASS BIT(10)
+
+/* RCC_PLL2CFGR5 register fields */
+#define RCC_PLL2CFGR5_DIVVAL_MASK GENMASK_32(3, 0)
+#define RCC_PLL2CFGR5_DIVVAL_SHIFT 0
+#define RCC_PLL2CFGR5_SPREAD_MASK GENMASK_32(20, 16)
+#define RCC_PLL2CFGR5_SPREAD_SHIFT 16
+
+/* RCC_PLL2CFGR6 register fields */
+#define RCC_PLL2CFGR6_POSTDIV1_MASK GENMASK_32(2, 0)
+#define RCC_PLL2CFGR6_POSTDIV1_SHIFT 0
+
+/* RCC_PLL2CFGR7 register fields */
+#define RCC_PLL2CFGR7_POSTDIV2_MASK GENMASK_32(2, 0)
+#define RCC_PLL2CFGR7_POSTDIV2_SHIFT 0
+
+/* RCC_PLL3CFGR1 register fields */
+#define RCC_PLL3CFGR1_SSMODRST BIT(0)
+#define RCC_PLL3CFGR1_PLLEN BIT(8)
+#define RCC_PLL3CFGR1_PLLRDY BIT(24)
+#define RCC_PLL3CFGR1_CKREFST BIT(28)
+
+/* RCC_PLL3CFGR2 register fields */
+#define RCC_PLL3CFGR2_FREFDIV_MASK GENMASK_32(5, 0)
+#define RCC_PLL3CFGR2_FREFDIV_SHIFT 0
+#define RCC_PLL3CFGR2_FBDIV_MASK GENMASK_32(27, 16)
+#define RCC_PLL3CFGR2_FBDIV_SHIFT 16
+
+/* RCC_PLL3CFGR3 register fields */
+#define RCC_PLL3CFGR3_FRACIN_MASK GENMASK_32(23, 0)
+#define RCC_PLL3CFGR3_FRACIN_SHIFT 0
+#define RCC_PLL3CFGR3_DOWNSPREAD BIT(24)
+#define RCC_PLL3CFGR3_DACEN BIT(25)
+#define RCC_PLL3CFGR3_SSCGDIS BIT(26)
+
+/* RCC_PLL3CFGR4 register fields */
+#define RCC_PLL3CFGR4_DSMEN BIT(8)
+#define RCC_PLL3CFGR4_FOUTPOSTDIVEN BIT(9)
+#define RCC_PLL3CFGR4_BYPASS BIT(10)
+
+/* RCC_PLL3CFGR5 register fields */
+#define RCC_PLL3CFGR5_DIVVAL_MASK GENMASK_32(3, 0)
+#define RCC_PLL3CFGR5_DIVVAL_SHIFT 0
+#define RCC_PLL3CFGR5_SPREAD_MASK GENMASK_32(20, 16)
+#define RCC_PLL3CFGR5_SPREAD_SHIFT 16
+
+/* RCC_PLL3CFGR6 register fields */
+#define RCC_PLL3CFGR6_POSTDIV1_MASK GENMASK_32(2, 0)
+#define RCC_PLL3CFGR6_POSTDIV1_SHIFT 0
+
+/* RCC_PLL3CFGR7 register fields */
+#define RCC_PLL3CFGR7_POSTDIV2_MASK GENMASK_32(2, 0)
+#define RCC_PLL3CFGR7_POSTDIV2_SHIFT 0
+
+/* RCC_PLLxCFGR1 register fields */
+#define RCC_PLLxCFGR1_SSMODRST BIT(0)
+#define RCC_PLLxCFGR1_PLLEN BIT(8)
+#define RCC_PLLxCFGR1_PLLRDY BIT(24)
+#define RCC_PLLxCFGR1_CKREFST BIT(28)
+
+/* RCC_PLLxCFGR2 register fields */
+#define RCC_PLLxCFGR2_FREFDIV_MASK GENMASK_32(5, 0)
+#define RCC_PLLxCFGR2_FREFDIV_SHIFT 0
+#define RCC_PLLxCFGR2_FBDIV_MASK GENMASK_32(27, 16)
+#define RCC_PLLxCFGR2_FBDIV_SHIFT 16
+
+/* RCC_PLLxCFGR3 register fields */
+#define RCC_PLLxCFGR3_FRACIN_MASK GENMASK_32(23, 0)
+#define RCC_PLLxCFGR3_FRACIN_SHIFT 0
+#define RCC_PLLxCFGR3_DOWNSPREAD BIT(24)
+#define RCC_PLLxCFGR3_DACEN BIT(25)
+#define RCC_PLLxCFGR3_SSCGDIS BIT(26)
+
+/* RCC_PLLxCFGR4 register fields */
+#define RCC_PLLxCFGR4_DSMEN BIT(8)
+#define RCC_PLLxCFGR4_FOUTPOSTDIVEN BIT(9)
+#define RCC_PLLxCFGR4_BYPASS BIT(10)
+
+/* RCC_PLLxCFGR5 register fields */
+#define RCC_PLLxCFGR5_DIVVAL_MASK GENMASK_32(3, 0)
+#define RCC_PLLxCFGR5_DIVVAL_SHIFT 0
+#define RCC_PLLxCFGR5_SPREAD_MASK GENMASK_32(20, 16)
+#define RCC_PLLxCFGR5_SPREAD_SHIFT 16
+
+/* RCC_PLLxCFGR6 register fields */
+#define RCC_PLLxCFGR6_POSTDIV1_MASK GENMASK_32(2, 0)
+#define RCC_PLLxCFGR6_POSTDIV1_SHIFT 0
+
+/* RCC_PLLxCFGR7 register fields */
+#define RCC_PLLxCFGR7_POSTDIV2_MASK GENMASK_32(2, 0)
+#define RCC_PLLxCFGR7_POSTDIV2_SHIFT 0
+
+/* RCC_HSIFMONCR register fields */
+#define RCC_HSIFMONCR_HSIREF_MASK GENMASK_32(10, 0)
+#define RCC_HSIFMONCR_HSIREF_SHIFT 0
+#define RCC_HSIFMONCR_HSIMONEN BIT(15)
+#define RCC_HSIFMONCR_HSIDEV_MASK GENMASK_32(21, 16)
+#define RCC_HSIFMONCR_HSIDEV_SHIFT 16
+#define RCC_HSIFMONCR_HSIMONIE BIT(30)
+#define RCC_HSIFMONCR_HSIMONF BIT(31)
+
+/* RCC_HSIFVALR register fields */
+#define RCC_HSIFVALR_HSIVAL_MASK GENMASK_32(10, 0)
+#define RCC_HSIFVALR_HSIVAL_SHIFT 0
+
+/* RCC_TIM1CFGR register fields */
+#define RCC_TIM1CFGR_TIM1RST BIT(0)
+#define RCC_TIM1CFGR_TIM1EN BIT(1)
+#define RCC_TIM1CFGR_TIM1LPEN BIT(2)
+
+/* RCC_TIM2CFGR register fields */
+#define RCC_TIM2CFGR_TIM2RST BIT(0)
+#define RCC_TIM2CFGR_TIM2EN BIT(1)
+#define RCC_TIM2CFGR_TIM2LPEN BIT(2)
+
+/* RCC_TIM3CFGR register fields */
+#define RCC_TIM3CFGR_TIM3RST BIT(0)
+#define RCC_TIM3CFGR_TIM3EN BIT(1)
+#define RCC_TIM3CFGR_TIM3LPEN BIT(2)
+
+/* RCC_TIM4CFGR register fields */
+#define RCC_TIM4CFGR_TIM4RST BIT(0)
+#define RCC_TIM4CFGR_TIM4EN BIT(1)
+#define RCC_TIM4CFGR_TIM4LPEN BIT(2)
+
+/* RCC_TIM5CFGR register fields */
+#define RCC_TIM5CFGR_TIM5RST BIT(0)
+#define RCC_TIM5CFGR_TIM5EN BIT(1)
+#define RCC_TIM5CFGR_TIM5LPEN BIT(2)
+
+/* RCC_TIM6CFGR register fields */
+#define RCC_TIM6CFGR_TIM6RST BIT(0)
+#define RCC_TIM6CFGR_TIM6EN BIT(1)
+#define RCC_TIM6CFGR_TIM6LPEN BIT(2)
+
+/* RCC_TIM7CFGR register fields */
+#define RCC_TIM7CFGR_TIM7RST BIT(0)
+#define RCC_TIM7CFGR_TIM7EN BIT(1)
+#define RCC_TIM7CFGR_TIM7LPEN BIT(2)
+
+/* RCC_TIM8CFGR register fields */
+#define RCC_TIM8CFGR_TIM8RST BIT(0)
+#define RCC_TIM8CFGR_TIM8EN BIT(1)
+#define RCC_TIM8CFGR_TIM8LPEN BIT(2)
+
+/* RCC_TIM10CFGR register fields */
+#define RCC_TIM10CFGR_TIM10RST BIT(0)
+#define RCC_TIM10CFGR_TIM10EN BIT(1)
+#define RCC_TIM10CFGR_TIM10LPEN BIT(2)
+
+/* RCC_TIM11CFGR register fields */
+#define RCC_TIM11CFGR_TIM11RST BIT(0)
+#define RCC_TIM11CFGR_TIM11EN BIT(1)
+#define RCC_TIM11CFGR_TIM11LPEN BIT(2)
+
+/* RCC_TIM12CFGR register fields */
+#define RCC_TIM12CFGR_TIM12RST BIT(0)
+#define RCC_TIM12CFGR_TIM12EN BIT(1)
+#define RCC_TIM12CFGR_TIM12LPEN BIT(2)
+
+/* RCC_TIM13CFGR register fields */
+#define RCC_TIM13CFGR_TIM13RST BIT(0)
+#define RCC_TIM13CFGR_TIM13EN BIT(1)
+#define RCC_TIM13CFGR_TIM13LPEN BIT(2)
+
+/* RCC_TIM14CFGR register fields */
+#define RCC_TIM14CFGR_TIM14RST BIT(0)
+#define RCC_TIM14CFGR_TIM14EN BIT(1)
+#define RCC_TIM14CFGR_TIM14LPEN BIT(2)
+
+/* RCC_TIM15CFGR register fields */
+#define RCC_TIM15CFGR_TIM15RST BIT(0)
+#define RCC_TIM15CFGR_TIM15EN BIT(1)
+#define RCC_TIM15CFGR_TIM15LPEN BIT(2)
+
+/* RCC_TIM16CFGR register fields */
+#define RCC_TIM16CFGR_TIM16RST BIT(0)
+#define RCC_TIM16CFGR_TIM16EN BIT(1)
+#define RCC_TIM16CFGR_TIM16LPEN BIT(2)
+
+/* RCC_TIM17CFGR register fields */
+#define RCC_TIM17CFGR_TIM17RST BIT(0)
+#define RCC_TIM17CFGR_TIM17EN BIT(1)
+#define RCC_TIM17CFGR_TIM17LPEN BIT(2)
+
+/* RCC_TIM20CFGR register fields */
+#define RCC_TIM20CFGR_TIM20RST BIT(0)
+#define RCC_TIM20CFGR_TIM20EN BIT(1)
+#define RCC_TIM20CFGR_TIM20LPEN BIT(2)
+
+/* RCC_LPTIM1CFGR register fields */
+#define RCC_LPTIM1CFGR_LPTIM1RST BIT(0)
+#define RCC_LPTIM1CFGR_LPTIM1EN BIT(1)
+#define RCC_LPTIM1CFGR_LPTIM1LPEN BIT(2)
+
+/* RCC_LPTIM2CFGR register fields */
+#define RCC_LPTIM2CFGR_LPTIM2RST BIT(0)
+#define RCC_LPTIM2CFGR_LPTIM2EN BIT(1)
+#define RCC_LPTIM2CFGR_LPTIM2LPEN BIT(2)
+
+/* RCC_LPTIM3CFGR register fields */
+#define RCC_LPTIM3CFGR_LPTIM3RST BIT(0)
+#define RCC_LPTIM3CFGR_LPTIM3EN BIT(1)
+#define RCC_LPTIM3CFGR_LPTIM3LPEN BIT(2)
+#define RCC_LPTIM3CFGR_LPTIM3AMEN BIT(3)
+
+/* RCC_LPTIM4CFGR register fields */
+#define RCC_LPTIM4CFGR_LPTIM4RST BIT(0)
+#define RCC_LPTIM4CFGR_LPTIM4EN BIT(1)
+#define RCC_LPTIM4CFGR_LPTIM4LPEN BIT(2)
+#define RCC_LPTIM4CFGR_LPTIM4AMEN BIT(3)
+
+/* RCC_LPTIM5CFGR register fields */
+#define RCC_LPTIM5CFGR_LPTIM5RST BIT(0)
+#define RCC_LPTIM5CFGR_LPTIM5EN BIT(1)
+#define RCC_LPTIM5CFGR_LPTIM5LPEN BIT(2)
+#define RCC_LPTIM5CFGR_LPTIM5AMEN BIT(3)
+
+/* RCC_LPTIMxCFGR register fields */
+#define RCC_LPTIMxCFGR_LPTIMxRST BIT(0)
+#define RCC_LPTIMxCFGR_LPTIMxEN BIT(1)
+#define RCC_LPTIMxCFGR_LPTIMxLPEN BIT(2)
+#define RCC_LPTIMxCFGR_LPTIMxAMEN BIT(3)
+
+/* RCC_SPI1CFGR register fields */
+#define RCC_SPI1CFGR_SPI1RST BIT(0)
+#define RCC_SPI1CFGR_SPI1EN BIT(1)
+#define RCC_SPI1CFGR_SPI1LPEN BIT(2)
+
+/* RCC_SPI2CFGR register fields */
+#define RCC_SPI2CFGR_SPI2RST BIT(0)
+#define RCC_SPI2CFGR_SPI2EN BIT(1)
+#define RCC_SPI2CFGR_SPI2LPEN BIT(2)
+
+/* RCC_SPI3CFGR register fields */
+#define RCC_SPI3CFGR_SPI3RST BIT(0)
+#define RCC_SPI3CFGR_SPI3EN BIT(1)
+#define RCC_SPI3CFGR_SPI3LPEN BIT(2)
+
+/* RCC_SPI4CFGR register fields */
+#define RCC_SPI4CFGR_SPI4RST BIT(0)
+#define RCC_SPI4CFGR_SPI4EN BIT(1)
+#define RCC_SPI4CFGR_SPI4LPEN BIT(2)
+
+/* RCC_SPI5CFGR register fields */
+#define RCC_SPI5CFGR_SPI5RST BIT(0)
+#define RCC_SPI5CFGR_SPI5EN BIT(1)
+#define RCC_SPI5CFGR_SPI5LPEN BIT(2)
+
+/* RCC_SPI6CFGR register fields */
+#define RCC_SPI6CFGR_SPI6RST BIT(0)
+#define RCC_SPI6CFGR_SPI6EN BIT(1)
+#define RCC_SPI6CFGR_SPI6LPEN BIT(2)
+
+/* RCC_SPI7CFGR register fields */
+#define RCC_SPI7CFGR_SPI7RST BIT(0)
+#define RCC_SPI7CFGR_SPI7EN BIT(1)
+#define RCC_SPI7CFGR_SPI7LPEN BIT(2)
+
+/* RCC_SPI8CFGR register fields */
+#define RCC_SPI8CFGR_SPI8RST BIT(0)
+#define RCC_SPI8CFGR_SPI8EN BIT(1)
+#define RCC_SPI8CFGR_SPI8LPEN BIT(2)
+#define RCC_SPI8CFGR_SPI8AMEN BIT(3)
+
+/* RCC_SPIxCFGR register fields */
+#define RCC_SPIxCFGR_SPIxRST BIT(0)
+#define RCC_SPIxCFGR_SPIxEN BIT(1)
+#define RCC_SPIxCFGR_SPIxLPEN BIT(2)
+#define RCC_SPIxCFGR_SPIxAMEN BIT(3)
+
+/* RCC_SPDIFRXCFGR register fields */
+#define RCC_SPDIFRXCFGR_SPDIFRXRST BIT(0)
+#define RCC_SPDIFRXCFGR_SPDIFRXEN BIT(1)
+#define RCC_SPDIFRXCFGR_SPDIFRXLPEN BIT(2)
+
+/* RCC_USART1CFGR register fields */
+#define RCC_USART1CFGR_USART1RST BIT(0)
+#define RCC_USART1CFGR_USART1EN BIT(1)
+#define RCC_USART1CFGR_USART1LPEN BIT(2)
+
+/* RCC_USART2CFGR register fields */
+#define RCC_USART2CFGR_USART2RST BIT(0)
+#define RCC_USART2CFGR_USART2EN BIT(1)
+#define RCC_USART2CFGR_USART2LPEN BIT(2)
+
+/* RCC_USART3CFGR register fields */
+#define RCC_USART3CFGR_USART3RST BIT(0)
+#define RCC_USART3CFGR_USART3EN BIT(1)
+#define RCC_USART3CFGR_USART3LPEN BIT(2)
+
+/* RCC_UART4CFGR register fields */
+#define RCC_UART4CFGR_UART4RST BIT(0)
+#define RCC_UART4CFGR_UART4EN BIT(1)
+#define RCC_UART4CFGR_UART4LPEN BIT(2)
+
+/* RCC_UART5CFGR register fields */
+#define RCC_UART5CFGR_UART5RST BIT(0)
+#define RCC_UART5CFGR_UART5EN BIT(1)
+#define RCC_UART5CFGR_UART5LPEN BIT(2)
+
+/* RCC_USART6CFGR register fields */
+#define RCC_USART6CFGR_USART6RST BIT(0)
+#define RCC_USART6CFGR_USART6EN BIT(1)
+#define RCC_USART6CFGR_USART6LPEN BIT(2)
+
+/* RCC_UART7CFGR register fields */
+#define RCC_UART7CFGR_UART7RST BIT(0)
+#define RCC_UART7CFGR_UART7EN BIT(1)
+#define RCC_UART7CFGR_UART7LPEN BIT(2)
+
+/* RCC_UART8CFGR register fields */
+#define RCC_UART8CFGR_UART8RST BIT(0)
+#define RCC_UART8CFGR_UART8EN BIT(1)
+#define RCC_UART8CFGR_UART8LPEN BIT(2)
+
+/* RCC_UART9CFGR register fields */
+#define RCC_UART9CFGR_UART9RST BIT(0)
+#define RCC_UART9CFGR_UART9EN BIT(1)
+#define RCC_UART9CFGR_UART9LPEN BIT(2)
+
+/* RCC_USARTxCFGR register fields */
+#define RCC_USARTxCFGR_USARTxRST BIT(0)
+#define RCC_USARTxCFGR_USARTxEN BIT(1)
+#define RCC_USARTxCFGR_USARTxLPEN BIT(2)
+
+/* RCC_UARTxCFGR register fields */
+#define RCC_UARTxCFGR_UARTxRST BIT(0)
+#define RCC_UARTxCFGR_UARTxEN BIT(1)
+#define RCC_UARTxCFGR_UARTxLPEN BIT(2)
+
+/* RCC_LPUART1CFGR register fields */
+#define RCC_LPUART1CFGR_LPUART1RST BIT(0)
+#define RCC_LPUART1CFGR_LPUART1EN BIT(1)
+#define RCC_LPUART1CFGR_LPUART1LPEN BIT(2)
+#define RCC_LPUART1CFGR_LPUART1AMEN BIT(3)
+
+/* RCC_I2C1CFGR register fields */
+#define RCC_I2C1CFGR_I2C1RST BIT(0)
+#define RCC_I2C1CFGR_I2C1EN BIT(1)
+#define RCC_I2C1CFGR_I2C1LPEN BIT(2)
+
+/* RCC_I2C2CFGR register fields */
+#define RCC_I2C2CFGR_I2C2RST BIT(0)
+#define RCC_I2C2CFGR_I2C2EN BIT(1)
+#define RCC_I2C2CFGR_I2C2LPEN BIT(2)
+
+/* RCC_I2C3CFGR register fields */
+#define RCC_I2C3CFGR_I2C3RST BIT(0)
+#define RCC_I2C3CFGR_I2C3EN BIT(1)
+#define RCC_I2C3CFGR_I2C3LPEN BIT(2)
+
+/* RCC_I2C4CFGR register fields */
+#define RCC_I2C4CFGR_I2C4RST BIT(0)
+#define RCC_I2C4CFGR_I2C4EN BIT(1)
+#define RCC_I2C4CFGR_I2C4LPEN BIT(2)
+
+/* RCC_I2C5CFGR register fields */
+#define RCC_I2C5CFGR_I2C5RST BIT(0)
+#define RCC_I2C5CFGR_I2C5EN BIT(1)
+#define RCC_I2C5CFGR_I2C5LPEN BIT(2)
+
+/* RCC_I2C6CFGR register fields */
+#define RCC_I2C6CFGR_I2C6RST BIT(0)
+#define RCC_I2C6CFGR_I2C6EN BIT(1)
+#define RCC_I2C6CFGR_I2C6LPEN BIT(2)
+
+/* RCC_I2C7CFGR register fields */
+#define RCC_I2C7CFGR_I2C7RST BIT(0)
+#define RCC_I2C7CFGR_I2C7EN BIT(1)
+#define RCC_I2C7CFGR_I2C7LPEN BIT(2)
+
+/* RCC_I2C8CFGR register fields */
+#define RCC_I2C8CFGR_I2C8RST BIT(0)
+#define RCC_I2C8CFGR_I2C8EN BIT(1)
+#define RCC_I2C8CFGR_I2C8LPEN BIT(2)
+#define RCC_I2C8CFGR_I2C8AMEN BIT(3)
+
+/* RCC_I2CxCFGR register fields */
+#define RCC_I2CxCFGR_I2CxRST BIT(0)
+#define RCC_I2CxCFGR_I2CxEN BIT(1)
+#define RCC_I2CxCFGR_I2CxLPEN BIT(2)
+#define RCC_I2CxCFGR_I2CxAMEN BIT(3)
+
+/* RCC_SAI1CFGR register fields */
+#define RCC_SAI1CFGR_SAI1RST BIT(0)
+#define RCC_SAI1CFGR_SAI1EN BIT(1)
+#define RCC_SAI1CFGR_SAI1LPEN BIT(2)
+
+/* RCC_SAI2CFGR register fields */
+#define RCC_SAI2CFGR_SAI2RST BIT(0)
+#define RCC_SAI2CFGR_SAI2EN BIT(1)
+#define RCC_SAI2CFGR_SAI2LPEN BIT(2)
+
+/* RCC_SAI3CFGR register fields */
+#define RCC_SAI3CFGR_SAI3RST BIT(0)
+#define RCC_SAI3CFGR_SAI3EN BIT(1)
+#define RCC_SAI3CFGR_SAI3LPEN BIT(2)
+
+/* RCC_SAI4CFGR register fields */
+#define RCC_SAI4CFGR_SAI4RST BIT(0)
+#define RCC_SAI4CFGR_SAI4EN BIT(1)
+#define RCC_SAI4CFGR_SAI4LPEN BIT(2)
+
+/* RCC_SAIxCFGR register fields */
+#define RCC_SAIxCFGR_SAIxRST BIT(0)
+#define RCC_SAIxCFGR_SAIxEN BIT(1)
+#define RCC_SAIxCFGR_SAIxLPEN BIT(2)
+
+/* RCC_MDF1CFGR register fields */
+#define RCC_MDF1CFGR_MDF1RST BIT(0)
+#define RCC_MDF1CFGR_MDF1EN BIT(1)
+#define RCC_MDF1CFGR_MDF1LPEN BIT(2)
+
+/* RCC_ADF1CFGR register fields */
+#define RCC_ADF1CFGR_ADF1RST BIT(0)
+#define RCC_ADF1CFGR_ADF1EN BIT(1)
+#define RCC_ADF1CFGR_ADF1LPEN BIT(2)
+#define RCC_ADF1CFGR_ADF1AMEN BIT(3)
+
+/* RCC_FDCANCFGR register fields */
+#define RCC_FDCANCFGR_FDCANRST BIT(0)
+#define RCC_FDCANCFGR_FDCANEN BIT(1)
+#define RCC_FDCANCFGR_FDCANLPEN BIT(2)
+
+/* RCC_HDPCFGR register fields */
+#define RCC_HDPCFGR_HDPRST BIT(0)
+#define RCC_HDPCFGR_HDPEN BIT(1)
+
+/* RCC_ADC12CFGR register fields */
+#define RCC_ADC12CFGR_ADC12RST BIT(0)
+#define RCC_ADC12CFGR_ADC12EN BIT(1)
+#define RCC_ADC12CFGR_ADC12LPEN BIT(2)
+#define RCC_ADC12CFGR_ADC12KERSEL BIT(12)
+
+/* RCC_ADC3CFGR register fields */
+#define RCC_ADC3CFGR_ADC3RST BIT(0)
+#define RCC_ADC3CFGR_ADC3EN BIT(1)
+#define RCC_ADC3CFGR_ADC3LPEN BIT(2)
+#define RCC_ADC3CFGR_ADC3KERSEL_MASK GENMASK_32(13, 12)
+#define RCC_ADC3CFGR_ADC3KERSEL_SHIFT 12
+
+/* RCC_ETH1CFGR register fields */
+#define RCC_ETH1CFGR_ETH1RST BIT(0)
+#define RCC_ETH1CFGR_ETH1MACEN BIT(1)
+#define RCC_ETH1CFGR_ETH1MACLPEN BIT(2)
+#define RCC_ETH1CFGR_ETH1STPEN BIT(4)
+#define RCC_ETH1CFGR_ETH1EN BIT(5)
+#define RCC_ETH1CFGR_ETH1LPEN BIT(6)
+#define RCC_ETH1CFGR_ETH1TXEN BIT(8)
+#define RCC_ETH1CFGR_ETH1TXLPEN BIT(9)
+#define RCC_ETH1CFGR_ETH1RXEN BIT(10)
+#define RCC_ETH1CFGR_ETH1RXLPEN BIT(11)
+
+/* RCC_ETH2CFGR register fields */
+#define RCC_ETH2CFGR_ETH2RST BIT(0)
+#define RCC_ETH2CFGR_ETH2MACEN BIT(1)
+#define RCC_ETH2CFGR_ETH2MACLPEN BIT(2)
+#define RCC_ETH2CFGR_ETH2STPEN BIT(4)
+#define RCC_ETH2CFGR_ETH2EN BIT(5)
+#define RCC_ETH2CFGR_ETH2LPEN BIT(6)
+#define RCC_ETH2CFGR_ETH2TXEN BIT(8)
+#define RCC_ETH2CFGR_ETH2TXLPEN BIT(9)
+#define RCC_ETH2CFGR_ETH2RXEN BIT(10)
+#define RCC_ETH2CFGR_ETH2RXLPEN BIT(11)
+
+/* RCC_ETHxCFGR register fields */
+#define RCC_ETHxCFGR_ETHxRST BIT(0)
+#define RCC_ETHxCFGR_ETHxMACEN BIT(1)
+#define RCC_ETHxCFGR_ETHxMACLPEN BIT(2)
+#define RCC_ETHxCFGR_ETHxSTPEN BIT(4)
+#define RCC_ETHxCFGR_ETHxEN BIT(5)
+#define RCC_ETHxCFGR_ETHxLPEN BIT(6)
+#define RCC_ETHxCFGR_ETHxTXEN BIT(8)
+#define RCC_ETHxCFGR_ETHxTXLPEN BIT(9)
+#define RCC_ETHxCFGR_ETHxRXEN BIT(10)
+#define RCC_ETHxCFGR_ETHxRXLPEN BIT(11)
+
+/* RCC_USB2CFGR register fields */
+#define RCC_USB2CFGR_USB2RST BIT(0)
+#define RCC_USB2CFGR_USB2EN BIT(1)
+#define RCC_USB2CFGR_USB2LPEN BIT(2)
+#define RCC_USB2CFGR_USB2STPEN BIT(4)
+
+/* RCC_USB2PHY1CFGR register fields */
+#define RCC_USB2PHY1CFGR_USB2PHY1RST BIT(0)
+#define RCC_USB2PHY1CFGR_USB2PHY1EN BIT(1)
+#define RCC_USB2PHY1CFGR_USB2PHY1LPEN BIT(2)
+#define RCC_USB2PHY1CFGR_USB2PHY1STPEN BIT(4)
+#define RCC_USB2PHY1CFGR_USB2PHY1CKREFSEL BIT(15)
+
+/* RCC_USB2PHY2CFGR register fields */
+#define RCC_USB2PHY2CFGR_USB2PHY2RST BIT(0)
+#define RCC_USB2PHY2CFGR_USB2PHY2EN BIT(1)
+#define RCC_USB2PHY2CFGR_USB2PHY2LPEN BIT(2)
+#define RCC_USB2PHY2CFGR_USB2PHY2STPEN BIT(4)
+#define RCC_USB2PHY2CFGR_USB2PHY2CKREFSEL BIT(15)
+
+/* RCC_USB2PHYxCFGR register fields */
+#define RCC_USB2PHYxCFGR_USB2PHY1RST BIT(0)
+#define RCC_USB2PHYxCFGR_USB2PHY1EN BIT(1)
+#define RCC_USB2PHYxCFGR_USB2PHY1LPEN BIT(2)
+#define RCC_USB2PHYxCFGR_USB2PHY1STPEN BIT(4)
+#define RCC_USB2PHYxCFGR_USB2PHY1CKREFSEL BIT(15)
+
+/* RCC_USB3DRDCFGR register fields */
+#define RCC_USB3DRDCFGR_USB3DRDRST BIT(0)
+#define RCC_USB3DRDCFGR_USB3DRDEN BIT(1)
+#define RCC_USB3DRDCFGR_USB3DRDLPEN BIT(2)
+#define RCC_USB3DRDCFGR_USB3DRDSTPEN BIT(4)
+
+/* RCC_USB3PCIEPHYCFGR register fields */
+#define RCC_USB3PCIEPHYCFGR_USB3PCIEPHYRST BIT(0)
+#define RCC_USB3PCIEPHYCFGR_USB3PCIEPHYEN BIT(1)
+#define RCC_USB3PCIEPHYCFGR_USB3PCIEPHYLPEN BIT(2)
+#define RCC_USB3PCIEPHYCFGR_USB3PCIEPHYSTPEN BIT(4)
+#define RCC_USB3PCIEPHYCFGR_USB3PCIEPHYCKREFSEL BIT(15)
+
+/* RCC_PCIECFGR register fields */
+#define RCC_PCIECFGR_PCIERST BIT(0)
+#define RCC_PCIECFGR_PCIEEN BIT(1)
+#define RCC_PCIECFGR_PCIELPEN BIT(2)
+#define RCC_PCIECFGR_PCIESTPEN BIT(4)
+
+/* RCC_USBTCCFGR register fields */
+#define RCC_USBTCCFGR_USBTCRST BIT(0)
+#define RCC_USBTCCFGR_USBTCEN BIT(1)
+#define RCC_USBTCCFGR_USBTCLPEN BIT(2)
+
+/* RCC_ETHSWCFGR register fields */
+#define RCC_ETHSWCFGR_ETHSWRST BIT(0)
+#define RCC_ETHSWCFGR_ETHSWMACEN BIT(1)
+#define RCC_ETHSWCFGR_ETHSWMACLPEN BIT(2)
+#define RCC_ETHSWCFGR_ETHSWEN BIT(5)
+#define RCC_ETHSWCFGR_ETHSWLPEN BIT(6)
+#define RCC_ETHSWCFGR_ETHSWREFEN BIT(21)
+#define RCC_ETHSWCFGR_ETHSWREFLPEN BIT(22)
+
+/* RCC_ETHSWACMCFGR register fields */
+#define RCC_ETHSWACMCFGR_ETHSWACMEN BIT(1)
+#define RCC_ETHSWACMCFGR_ETHSWACMLPEN BIT(2)
+
+/* RCC_ETHSWACMMSGCFGR register fields */
+#define RCC_ETHSWACMMSGCFGR_ETHSWACMMSGEN BIT(1)
+#define RCC_ETHSWACMMSGCFGR_ETHSWACMMSGLPEN BIT(2)
+
+/* RCC_STGENCFGR register fields */
+#define RCC_STGENCFGR_STGENEN BIT(1)
+#define RCC_STGENCFGR_STGENLPEN BIT(2)
+#define RCC_STGENCFGR_STGENSTPEN BIT(4)
+
+/* RCC_SDMMC1CFGR register fields */
+#define RCC_SDMMC1CFGR_SDMMC1RST BIT(0)
+#define RCC_SDMMC1CFGR_SDMMC1EN BIT(1)
+#define RCC_SDMMC1CFGR_SDMMC1LPEN BIT(2)
+#define RCC_SDMMC1CFGR_SDMMC1DLLRST BIT(16)
+
+/* RCC_SDMMC2CFGR register fields */
+#define RCC_SDMMC2CFGR_SDMMC2RST BIT(0)
+#define RCC_SDMMC2CFGR_SDMMC2EN BIT(1)
+#define RCC_SDMMC2CFGR_SDMMC2LPEN BIT(2)
+#define RCC_SDMMC2CFGR_SDMMC2DLLRST BIT(16)
+
+/* RCC_SDMMC3CFGR register fields */
+#define RCC_SDMMC3CFGR_SDMMC3RST BIT(0)
+#define RCC_SDMMC3CFGR_SDMMC3EN BIT(1)
+#define RCC_SDMMC3CFGR_SDMMC3LPEN BIT(2)
+#define RCC_SDMMC3CFGR_SDMMC3DLLRST BIT(16)
+
+/* RCC_SDMMCxCFGR register fields */
+#define RCC_SDMMCxCFGR_SDMMC1RST BIT(0)
+#define RCC_SDMMCxCFGR_SDMMC1EN BIT(1)
+#define RCC_SDMMCxCFGR_SDMMC1LPEN BIT(2)
+#define RCC_SDMMCxCFGR_SDMMC1DLLRST BIT(16)
+
+/* RCC_GPUCFGR register fields */
+#define RCC_GPUCFGR_GPURST BIT(0)
+#define RCC_GPUCFGR_GPUEN BIT(1)
+#define RCC_GPUCFGR_GPULPEN BIT(2)
+
+/* RCC_LTDCCFGR register fields */
+#define RCC_LTDCCFGR_LTDCRST BIT(0)
+#define RCC_LTDCCFGR_LTDCEN BIT(1)
+#define RCC_LTDCCFGR_LTDCLPEN BIT(2)
+
+/* RCC_DSICFGR register fields */
+#define RCC_DSICFGR_DSIRST BIT(0)
+#define RCC_DSICFGR_DSIEN BIT(1)
+#define RCC_DSICFGR_DSILPEN BIT(2)
+#define RCC_DSICFGR_DSIBLSEL BIT(12)
+#define RCC_DSICFGR_DSIPHYCKREFSEL BIT(15)
+
+/* RCC_LVDSCFGR register fields */
+#define RCC_LVDSCFGR_LVDSRST BIT(0)
+#define RCC_LVDSCFGR_LVDSEN BIT(1)
+#define RCC_LVDSCFGR_LVDSLPEN BIT(2)
+#define RCC_LVDSCFGR_LVDSPHYCKREFSEL BIT(15)
+
+/* RCC_CSI2CFGR register fields */
+#define RCC_CSI2CFGR_CSI2RST BIT(0)
+#define RCC_CSI2CFGR_CSI2EN BIT(1)
+#define RCC_CSI2CFGR_CSI2LPEN BIT(2)
+
+/* RCC_DCMIPPCFGR register fields */
+#define RCC_DCMIPPCFGR_DCMIPPRST BIT(0)
+#define RCC_DCMIPPCFGR_DCMIPPEN BIT(1)
+#define RCC_DCMIPPCFGR_DCMIPPLPEN BIT(2)
+
+/* RCC_CCICFGR register fields */
+#define RCC_CCICFGR_CCIRST BIT(0)
+#define RCC_CCICFGR_CCIEN BIT(1)
+#define RCC_CCICFGR_CCILPEN BIT(2)
+
+/* RCC_VDECCFGR register fields */
+#define RCC_VDECCFGR_VDECRST BIT(0)
+#define RCC_VDECCFGR_VDECEN BIT(1)
+#define RCC_VDECCFGR_VDECLPEN BIT(2)
+
+/* RCC_VENCCFGR register fields */
+#define RCC_VENCCFGR_VENCRST BIT(0)
+#define RCC_VENCCFGR_VENCEN BIT(1)
+#define RCC_VENCCFGR_VENCLPEN BIT(2)
+
+/* RCC_RNGCFGR register fields */
+#define RCC_RNGCFGR_RNGRST BIT(0)
+#define RCC_RNGCFGR_RNGEN BIT(1)
+#define RCC_RNGCFGR_RNGLPEN BIT(2)
+
+/* RCC_PKACFGR register fields */
+#define RCC_PKACFGR_PKARST BIT(0)
+#define RCC_PKACFGR_PKAEN BIT(1)
+#define RCC_PKACFGR_PKALPEN BIT(2)
+
+/* RCC_SAESCFGR register fields */
+#define RCC_SAESCFGR_SAESRST BIT(0)
+#define RCC_SAESCFGR_SAESEN BIT(1)
+#define RCC_SAESCFGR_SAESLPEN BIT(2)
+
+/* RCC_HASHCFGR register fields */
+#define RCC_HASHCFGR_HASHRST BIT(0)
+#define RCC_HASHCFGR_HASHEN BIT(1)
+#define RCC_HASHCFGR_HASHLPEN BIT(2)
+
+/* RCC_CRYP1CFGR register fields */
+#define RCC_CRYP1CFGR_CRYP1RST BIT(0)
+#define RCC_CRYP1CFGR_CRYP1EN BIT(1)
+#define RCC_CRYP1CFGR_CRYP1LPEN BIT(2)
+
+/* RCC_CRYP2CFGR register fields */
+#define RCC_CRYP2CFGR_CRYP2RST BIT(0)
+#define RCC_CRYP2CFGR_CRYP2EN BIT(1)
+#define RCC_CRYP2CFGR_CRYP2LPEN BIT(2)
+
+/* RCC_CRYPxCFGR register fields */
+#define RCC_CRYPxCFGR_CRYPxRST BIT(0)
+#define RCC_CRYPxCFGR_CRYPxEN BIT(1)
+#define RCC_CRYPxCFGR_CRYPxLPEN BIT(2)
+
+/* RCC_IWDG1CFGR register fields */
+#define RCC_IWDG1CFGR_IWDG1EN BIT(1)
+#define RCC_IWDG1CFGR_IWDG1LPEN BIT(2)
+
+/* RCC_IWDG2CFGR register fields */
+#define RCC_IWDG2CFGR_IWDG2EN BIT(1)
+#define RCC_IWDG2CFGR_IWDG2LPEN BIT(2)
+
+/* RCC_IWDG3CFGR register fields */
+#define RCC_IWDG3CFGR_IWDG3EN BIT(1)
+#define RCC_IWDG3CFGR_IWDG3LPEN BIT(2)
+
+/* RCC_IWDG4CFGR register fields */
+#define RCC_IWDG4CFGR_IWDG4EN BIT(1)
+#define RCC_IWDG4CFGR_IWDG4LPEN BIT(2)
+
+/* RCC_IWDGxCFGR register fields */
+#define RCC_IWDGxCFGR_IWDGxEN BIT(1)
+#define RCC_IWDGxCFGR_IWDGxLPEN BIT(2)
+
+/* RCC_IWDG5CFGR register fields */
+#define RCC_IWDG5CFGR_IWDG5EN BIT(1)
+#define RCC_IWDG5CFGR_IWDG5LPEN BIT(2)
+#define RCC_IWDG5CFGR_IWDG5AMEN BIT(3)
+
+/* RCC_WWDG1CFGR register fields */
+#define RCC_WWDG1CFGR_WWDG1RST BIT(0)
+#define RCC_WWDG1CFGR_WWDG1EN BIT(1)
+#define RCC_WWDG1CFGR_WWDG1LPEN BIT(2)
+
+/* RCC_WWDG2CFGR register fields */
+#define RCC_WWDG2CFGR_WWDG2RST BIT(0)
+#define RCC_WWDG2CFGR_WWDG2EN BIT(1)
+#define RCC_WWDG2CFGR_WWDG2LPEN BIT(2)
+#define RCC_WWDG2CFGR_WWDG2AMEN BIT(3)
+
+/* RCC_BUSPERFMCFGR register fields */
+#define RCC_BUSPERFMCFGR_BUSPERFMRST BIT(0)
+#define RCC_BUSPERFMCFGR_BUSPERFMEN BIT(1)
+#define RCC_BUSPERFMCFGR_BUSPERFMLPEN BIT(2)
+
+/* RCC_VREFCFGR register fields */
+#define RCC_VREFCFGR_VREFRST BIT(0)
+#define RCC_VREFCFGR_VREFEN BIT(1)
+#define RCC_VREFCFGR_VREFLPEN BIT(2)
+
+/* RCC_TMPSENSCFGR register fields */
+#define RCC_TMPSENSCFGR_TMPSENSRST BIT(0)
+#define RCC_TMPSENSCFGR_TMPSENSEN BIT(1)
+#define RCC_TMPSENSCFGR_TMPSENSLPEN BIT(2)
+#define RCC_TMPSENSCFGR_TMPSENSKERSEL_MASK GENMASK_32(13, 12)
+#define RCC_TMPSENSCFGR_TMPSENSKERSEL_SHIFT 12
+
+/* RCC_CRCCFGR register fields */
+#define RCC_CRCCFGR_CRCRST BIT(0)
+#define RCC_CRCCFGR_CRCEN BIT(1)
+#define RCC_CRCCFGR_CRCLPEN BIT(2)
+
+/* RCC_SERCCFGR register fields */
+#define RCC_SERCCFGR_SERCRST BIT(0)
+#define RCC_SERCCFGR_SERCEN BIT(1)
+#define RCC_SERCCFGR_SERCLPEN BIT(2)
+
+/* RCC_OSPIIOMCFGR register fields */
+#define RCC_OSPIIOMCFGR_OSPIIOMRST BIT(0)
+#define RCC_OSPIIOMCFGR_OSPIIOMEN BIT(1)
+#define RCC_OSPIIOMCFGR_OSPIIOMLPEN BIT(2)
+
+/* RCC_GICV2MCFGR register fields */
+#define RCC_GICV2MCFGR_GICV2MEN BIT(1)
+#define RCC_GICV2MCFGR_GICV2MLPEN BIT(2)
+
+/* RCC_I3C1CFGR register fields */
+#define RCC_I3C1CFGR_I3C1RST BIT(0)
+#define RCC_I3C1CFGR_I3C1EN BIT(1)
+#define RCC_I3C1CFGR_I3C1LPEN BIT(2)
+
+/* RCC_I3C2CFGR register fields */
+#define RCC_I3C2CFGR_I3C2RST BIT(0)
+#define RCC_I3C2CFGR_I3C2EN BIT(1)
+#define RCC_I3C2CFGR_I3C2LPEN BIT(2)
+
+/* RCC_I3C3CFGR register fields */
+#define RCC_I3C3CFGR_I3C3RST BIT(0)
+#define RCC_I3C3CFGR_I3C3EN BIT(1)
+#define RCC_I3C3CFGR_I3C3LPEN BIT(2)
+
+/* RCC_I3C4CFGR register fields */
+#define RCC_I3C4CFGR_I3C4RST BIT(0)
+#define RCC_I3C4CFGR_I3C4EN BIT(1)
+#define RCC_I3C4CFGR_I3C4LPEN BIT(2)
+#define RCC_I3C4CFGR_I3C4AMEN BIT(3)
+
+/* RCC_I3CxCFGR register fields */
+#define RCC_I3CxCFGR_I3CxRST BIT(0)
+#define RCC_I3CxCFGR_I3CxEN BIT(1)
+#define RCC_I3CxCFGR_I3CxLPEN BIT(2)
+#define RCC_I3CxCFGR_I3CxAMEN BIT(3)
+
+/* RCC_MUXSELCFGR register fields */
+#define RCC_MUXSELCFGR_MUXSEL0_MASK GENMASK_32(1, 0)
+#define RCC_MUXSELCFGR_MUXSEL0_SHIFT 0
+#define RCC_MUXSELCFGR_MUXSEL1_MASK GENMASK_32(5, 4)
+#define RCC_MUXSELCFGR_MUXSEL1_SHIFT 4
+#define RCC_MUXSELCFGR_MUXSEL2_MASK GENMASK_32(9, 8)
+#define RCC_MUXSELCFGR_MUXSEL2_SHIFT 8
+#define RCC_MUXSELCFGR_MUXSEL3_MASK GENMASK_32(13, 12)
+#define RCC_MUXSELCFGR_MUXSEL3_SHIFT 12
+#define RCC_MUXSELCFGR_MUXSEL4_MASK GENMASK_32(17, 16)
+#define RCC_MUXSELCFGR_MUXSEL4_SHIFT 16
+#define RCC_MUXSELCFGR_MUXSEL5_MASK GENMASK_32(21, 20)
+#define RCC_MUXSELCFGR_MUXSEL5_SHIFT 20
+#define RCC_MUXSELCFGR_MUXSEL6_MASK GENMASK_32(25, 24)
+#define RCC_MUXSELCFGR_MUXSEL6_SHIFT 24
+#define RCC_MUXSELCFGR_MUXSEL7_MASK GENMASK_32(29, 28)
+#define RCC_MUXSELCFGR_MUXSEL7_SHIFT 28
+
+/* RCC_XBAR0CFGR register fields */
+#define RCC_XBAR0CFGR_XBAR0SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR0CFGR_XBAR0SEL_SHIFT 0
+#define RCC_XBAR0CFGR_XBAR0EN BIT(6)
+#define RCC_XBAR0CFGR_XBAR0STS BIT(7)
+
+/* RCC_XBAR1CFGR register fields */
+#define RCC_XBAR1CFGR_XBAR1SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR1CFGR_XBAR1SEL_SHIFT 0
+#define RCC_XBAR1CFGR_XBAR1EN BIT(6)
+#define RCC_XBAR1CFGR_XBAR1STS BIT(7)
+
+/* RCC_XBAR2CFGR register fields */
+#define RCC_XBAR2CFGR_XBAR2SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR2CFGR_XBAR2SEL_SHIFT 0
+#define RCC_XBAR2CFGR_XBAR2EN BIT(6)
+#define RCC_XBAR2CFGR_XBAR2STS BIT(7)
+
+/* RCC_XBAR3CFGR register fields */
+#define RCC_XBAR3CFGR_XBAR3SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR3CFGR_XBAR3SEL_SHIFT 0
+#define RCC_XBAR3CFGR_XBAR3EN BIT(6)
+#define RCC_XBAR3CFGR_XBAR3STS BIT(7)
+
+/* RCC_XBAR4CFGR register fields */
+#define RCC_XBAR4CFGR_XBAR4SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR4CFGR_XBAR4SEL_SHIFT 0
+#define RCC_XBAR4CFGR_XBAR4EN BIT(6)
+#define RCC_XBAR4CFGR_XBAR4STS BIT(7)
+
+/* RCC_XBAR5CFGR register fields */
+#define RCC_XBAR5CFGR_XBAR5SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR5CFGR_XBAR5SEL_SHIFT 0
+#define RCC_XBAR5CFGR_XBAR5EN BIT(6)
+#define RCC_XBAR5CFGR_XBAR5STS BIT(7)
+
+/* RCC_XBAR6CFGR register fields */
+#define RCC_XBAR6CFGR_XBAR6SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR6CFGR_XBAR6SEL_SHIFT 0
+#define RCC_XBAR6CFGR_XBAR6EN BIT(6)
+#define RCC_XBAR6CFGR_XBAR6STS BIT(7)
+
+/* RCC_XBAR7CFGR register fields */
+#define RCC_XBAR7CFGR_XBAR7SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR7CFGR_XBAR7SEL_SHIFT 0
+#define RCC_XBAR7CFGR_XBAR7EN BIT(6)
+#define RCC_XBAR7CFGR_XBAR7STS BIT(7)
+
+/* RCC_XBAR8CFGR register fields */
+#define RCC_XBAR8CFGR_XBAR8SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR8CFGR_XBAR8SEL_SHIFT 0
+#define RCC_XBAR8CFGR_XBAR8EN BIT(6)
+#define RCC_XBAR8CFGR_XBAR8STS BIT(7)
+
+/* RCC_XBAR9CFGR register fields */
+#define RCC_XBAR9CFGR_XBAR9SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR9CFGR_XBAR9SEL_SHIFT 0
+#define RCC_XBAR9CFGR_XBAR9EN BIT(6)
+#define RCC_XBAR9CFGR_XBAR9STS BIT(7)
+
+/* RCC_XBAR10CFGR register fields */
+#define RCC_XBAR10CFGR_XBAR10SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR10CFGR_XBAR10SEL_SHIFT 0
+#define RCC_XBAR10CFGR_XBAR10EN BIT(6)
+#define RCC_XBAR10CFGR_XBAR10STS BIT(7)
+
+/* RCC_XBAR11CFGR register fields */
+#define RCC_XBAR11CFGR_XBAR11SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR11CFGR_XBAR11SEL_SHIFT 0
+#define RCC_XBAR11CFGR_XBAR11EN BIT(6)
+#define RCC_XBAR11CFGR_XBAR11STS BIT(7)
+
+/* RCC_XBAR12CFGR register fields */
+#define RCC_XBAR12CFGR_XBAR12SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR12CFGR_XBAR12SEL_SHIFT 0
+#define RCC_XBAR12CFGR_XBAR12EN BIT(6)
+#define RCC_XBAR12CFGR_XBAR12STS BIT(7)
+
+/* RCC_XBAR13CFGR register fields */
+#define RCC_XBAR13CFGR_XBAR13SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR13CFGR_XBAR13SEL_SHIFT 0
+#define RCC_XBAR13CFGR_XBAR13EN BIT(6)
+#define RCC_XBAR13CFGR_XBAR13STS BIT(7)
+
+/* RCC_XBAR14CFGR register fields */
+#define RCC_XBAR14CFGR_XBAR14SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR14CFGR_XBAR14SEL_SHIFT 0
+#define RCC_XBAR14CFGR_XBAR14EN BIT(6)
+#define RCC_XBAR14CFGR_XBAR14STS BIT(7)
+
+/* RCC_XBAR15CFGR register fields */
+#define RCC_XBAR15CFGR_XBAR15SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR15CFGR_XBAR15SEL_SHIFT 0
+#define RCC_XBAR15CFGR_XBAR15EN BIT(6)
+#define RCC_XBAR15CFGR_XBAR15STS BIT(7)
+
+/* RCC_XBAR16CFGR register fields */
+#define RCC_XBAR16CFGR_XBAR16SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR16CFGR_XBAR16SEL_SHIFT 0
+#define RCC_XBAR16CFGR_XBAR16EN BIT(6)
+#define RCC_XBAR16CFGR_XBAR16STS BIT(7)
+
+/* RCC_XBAR17CFGR register fields */
+#define RCC_XBAR17CFGR_XBAR17SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR17CFGR_XBAR17SEL_SHIFT 0
+#define RCC_XBAR17CFGR_XBAR17EN BIT(6)
+#define RCC_XBAR17CFGR_XBAR17STS BIT(7)
+
+/* RCC_XBAR18CFGR register fields */
+#define RCC_XBAR18CFGR_XBAR18SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR18CFGR_XBAR18SEL_SHIFT 0
+#define RCC_XBAR18CFGR_XBAR18EN BIT(6)
+#define RCC_XBAR18CFGR_XBAR18STS BIT(7)
+
+/* RCC_XBAR19CFGR register fields */
+#define RCC_XBAR19CFGR_XBAR19SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR19CFGR_XBAR19SEL_SHIFT 0
+#define RCC_XBAR19CFGR_XBAR19EN BIT(6)
+#define RCC_XBAR19CFGR_XBAR19STS BIT(7)
+
+/* RCC_XBAR20CFGR register fields */
+#define RCC_XBAR20CFGR_XBAR20SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR20CFGR_XBAR20SEL_SHIFT 0
+#define RCC_XBAR20CFGR_XBAR20EN BIT(6)
+#define RCC_XBAR20CFGR_XBAR20STS BIT(7)
+
+/* RCC_XBAR21CFGR register fields */
+#define RCC_XBAR21CFGR_XBAR21SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR21CFGR_XBAR21SEL_SHIFT 0
+#define RCC_XBAR21CFGR_XBAR21EN BIT(6)
+#define RCC_XBAR21CFGR_XBAR21STS BIT(7)
+
+/* RCC_XBAR22CFGR register fields */
+#define RCC_XBAR22CFGR_XBAR22SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR22CFGR_XBAR22SEL_SHIFT 0
+#define RCC_XBAR22CFGR_XBAR22EN BIT(6)
+#define RCC_XBAR22CFGR_XBAR22STS BIT(7)
+
+/* RCC_XBAR23CFGR register fields */
+#define RCC_XBAR23CFGR_XBAR23SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR23CFGR_XBAR23SEL_SHIFT 0
+#define RCC_XBAR23CFGR_XBAR23EN BIT(6)
+#define RCC_XBAR23CFGR_XBAR23STS BIT(7)
+
+/* RCC_XBAR24CFGR register fields */
+#define RCC_XBAR24CFGR_XBAR24SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR24CFGR_XBAR24SEL_SHIFT 0
+#define RCC_XBAR24CFGR_XBAR24EN BIT(6)
+#define RCC_XBAR24CFGR_XBAR24STS BIT(7)
+
+/* RCC_XBAR25CFGR register fields */
+#define RCC_XBAR25CFGR_XBAR25SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR25CFGR_XBAR25SEL_SHIFT 0
+#define RCC_XBAR25CFGR_XBAR25EN BIT(6)
+#define RCC_XBAR25CFGR_XBAR25STS BIT(7)
+
+/* RCC_XBAR26CFGR register fields */
+#define RCC_XBAR26CFGR_XBAR26SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR26CFGR_XBAR26SEL_SHIFT 0
+#define RCC_XBAR26CFGR_XBAR26EN BIT(6)
+#define RCC_XBAR26CFGR_XBAR26STS BIT(7)
+
+/* RCC_XBAR27CFGR register fields */
+#define RCC_XBAR27CFGR_XBAR27SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR27CFGR_XBAR27SEL_SHIFT 0
+#define RCC_XBAR27CFGR_XBAR27EN BIT(6)
+#define RCC_XBAR27CFGR_XBAR27STS BIT(7)
+
+/* RCC_XBAR28CFGR register fields */
+#define RCC_XBAR28CFGR_XBAR28SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR28CFGR_XBAR28SEL_SHIFT 0
+#define RCC_XBAR28CFGR_XBAR28EN BIT(6)
+#define RCC_XBAR28CFGR_XBAR28STS BIT(7)
+
+/* RCC_XBAR29CFGR register fields */
+#define RCC_XBAR29CFGR_XBAR29SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR29CFGR_XBAR29SEL_SHIFT 0
+#define RCC_XBAR29CFGR_XBAR29EN BIT(6)
+#define RCC_XBAR29CFGR_XBAR29STS BIT(7)
+
+/* RCC_XBAR30CFGR register fields */
+#define RCC_XBAR30CFGR_XBAR30SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR30CFGR_XBAR30SEL_SHIFT 0
+#define RCC_XBAR30CFGR_XBAR30EN BIT(6)
+#define RCC_XBAR30CFGR_XBAR30STS BIT(7)
+
+/* RCC_XBAR31CFGR register fields */
+#define RCC_XBAR31CFGR_XBAR31SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR31CFGR_XBAR31SEL_SHIFT 0
+#define RCC_XBAR31CFGR_XBAR31EN BIT(6)
+#define RCC_XBAR31CFGR_XBAR31STS BIT(7)
+
+/* RCC_XBAR32CFGR register fields */
+#define RCC_XBAR32CFGR_XBAR32SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR32CFGR_XBAR32SEL_SHIFT 0
+#define RCC_XBAR32CFGR_XBAR32EN BIT(6)
+#define RCC_XBAR32CFGR_XBAR32STS BIT(7)
+
+/* RCC_XBAR33CFGR register fields */
+#define RCC_XBAR33CFGR_XBAR33SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR33CFGR_XBAR33SEL_SHIFT 0
+#define RCC_XBAR33CFGR_XBAR33EN BIT(6)
+#define RCC_XBAR33CFGR_XBAR33STS BIT(7)
+
+/* RCC_XBAR34CFGR register fields */
+#define RCC_XBAR34CFGR_XBAR34SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR34CFGR_XBAR34SEL_SHIFT 0
+#define RCC_XBAR34CFGR_XBAR34EN BIT(6)
+#define RCC_XBAR34CFGR_XBAR34STS BIT(7)
+
+/* RCC_XBAR35CFGR register fields */
+#define RCC_XBAR35CFGR_XBAR35SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR35CFGR_XBAR35SEL_SHIFT 0
+#define RCC_XBAR35CFGR_XBAR35EN BIT(6)
+#define RCC_XBAR35CFGR_XBAR35STS BIT(7)
+
+/* RCC_XBAR36CFGR register fields */
+#define RCC_XBAR36CFGR_XBAR36SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR36CFGR_XBAR36SEL_SHIFT 0
+#define RCC_XBAR36CFGR_XBAR36EN BIT(6)
+#define RCC_XBAR36CFGR_XBAR36STS BIT(7)
+
+/* RCC_XBAR37CFGR register fields */
+#define RCC_XBAR37CFGR_XBAR37SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR37CFGR_XBAR37SEL_SHIFT 0
+#define RCC_XBAR37CFGR_XBAR37EN BIT(6)
+#define RCC_XBAR37CFGR_XBAR37STS BIT(7)
+
+/* RCC_XBAR38CFGR register fields */
+#define RCC_XBAR38CFGR_XBAR38SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR38CFGR_XBAR38SEL_SHIFT 0
+#define RCC_XBAR38CFGR_XBAR38EN BIT(6)
+#define RCC_XBAR38CFGR_XBAR38STS BIT(7)
+
+/* RCC_XBAR39CFGR register fields */
+#define RCC_XBAR39CFGR_XBAR39SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR39CFGR_XBAR39SEL_SHIFT 0
+#define RCC_XBAR39CFGR_XBAR39EN BIT(6)
+#define RCC_XBAR39CFGR_XBAR39STS BIT(7)
+
+/* RCC_XBAR40CFGR register fields */
+#define RCC_XBAR40CFGR_XBAR40SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR40CFGR_XBAR40SEL_SHIFT 0
+#define RCC_XBAR40CFGR_XBAR40EN BIT(6)
+#define RCC_XBAR40CFGR_XBAR40STS BIT(7)
+
+/* RCC_XBAR41CFGR register fields */
+#define RCC_XBAR41CFGR_XBAR41SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR41CFGR_XBAR41SEL_SHIFT 0
+#define RCC_XBAR41CFGR_XBAR41EN BIT(6)
+#define RCC_XBAR41CFGR_XBAR41STS BIT(7)
+
+/* RCC_XBAR42CFGR register fields */
+#define RCC_XBAR42CFGR_XBAR42SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR42CFGR_XBAR42SEL_SHIFT 0
+#define RCC_XBAR42CFGR_XBAR42EN BIT(6)
+#define RCC_XBAR42CFGR_XBAR42STS BIT(7)
+
+/* RCC_XBAR43CFGR register fields */
+#define RCC_XBAR43CFGR_XBAR43SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR43CFGR_XBAR43SEL_SHIFT 0
+#define RCC_XBAR43CFGR_XBAR43EN BIT(6)
+#define RCC_XBAR43CFGR_XBAR43STS BIT(7)
+
+/* RCC_XBAR44CFGR register fields */
+#define RCC_XBAR44CFGR_XBAR44SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR44CFGR_XBAR44SEL_SHIFT 0
+#define RCC_XBAR44CFGR_XBAR44EN BIT(6)
+#define RCC_XBAR44CFGR_XBAR44STS BIT(7)
+
+/* RCC_XBAR45CFGR register fields */
+#define RCC_XBAR45CFGR_XBAR45SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR45CFGR_XBAR45SEL_SHIFT 0
+#define RCC_XBAR45CFGR_XBAR45EN BIT(6)
+#define RCC_XBAR45CFGR_XBAR45STS BIT(7)
+
+/* RCC_XBAR46CFGR register fields */
+#define RCC_XBAR46CFGR_XBAR46SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR46CFGR_XBAR46SEL_SHIFT 0
+#define RCC_XBAR46CFGR_XBAR46EN BIT(6)
+#define RCC_XBAR46CFGR_XBAR46STS BIT(7)
+
+/* RCC_XBAR47CFGR register fields */
+#define RCC_XBAR47CFGR_XBAR47SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR47CFGR_XBAR47SEL_SHIFT 0
+#define RCC_XBAR47CFGR_XBAR47EN BIT(6)
+#define RCC_XBAR47CFGR_XBAR47STS BIT(7)
+
+/* RCC_XBAR48CFGR register fields */
+#define RCC_XBAR48CFGR_XBAR48SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR48CFGR_XBAR48SEL_SHIFT 0
+#define RCC_XBAR48CFGR_XBAR48EN BIT(6)
+#define RCC_XBAR48CFGR_XBAR48STS BIT(7)
+
+/* RCC_XBAR49CFGR register fields */
+#define RCC_XBAR49CFGR_XBAR49SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR49CFGR_XBAR49SEL_SHIFT 0
+#define RCC_XBAR49CFGR_XBAR49EN BIT(6)
+#define RCC_XBAR49CFGR_XBAR49STS BIT(7)
+
+/* RCC_XBAR50CFGR register fields */
+#define RCC_XBAR50CFGR_XBAR50SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR50CFGR_XBAR50SEL_SHIFT 0
+#define RCC_XBAR50CFGR_XBAR50EN BIT(6)
+#define RCC_XBAR50CFGR_XBAR50STS BIT(7)
+
+/* RCC_XBAR51CFGR register fields */
+#define RCC_XBAR51CFGR_XBAR51SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR51CFGR_XBAR51SEL_SHIFT 0
+#define RCC_XBAR51CFGR_XBAR51EN BIT(6)
+#define RCC_XBAR51CFGR_XBAR51STS BIT(7)
+
+/* RCC_XBAR52CFGR register fields */
+#define RCC_XBAR52CFGR_XBAR52SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR52CFGR_XBAR52SEL_SHIFT 0
+#define RCC_XBAR52CFGR_XBAR52EN BIT(6)
+#define RCC_XBAR52CFGR_XBAR52STS BIT(7)
+
+/* RCC_XBAR53CFGR register fields */
+#define RCC_XBAR53CFGR_XBAR53SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR53CFGR_XBAR53SEL_SHIFT 0
+#define RCC_XBAR53CFGR_XBAR53EN BIT(6)
+#define RCC_XBAR53CFGR_XBAR53STS BIT(7)
+
+/* RCC_XBAR54CFGR register fields */
+#define RCC_XBAR54CFGR_XBAR54SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR54CFGR_XBAR54SEL_SHIFT 0
+#define RCC_XBAR54CFGR_XBAR54EN BIT(6)
+#define RCC_XBAR54CFGR_XBAR54STS BIT(7)
+
+/* RCC_XBAR55CFGR register fields */
+#define RCC_XBAR55CFGR_XBAR55SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR55CFGR_XBAR55SEL_SHIFT 0
+#define RCC_XBAR55CFGR_XBAR55EN BIT(6)
+#define RCC_XBAR55CFGR_XBAR55STS BIT(7)
+
+/* RCC_XBAR56CFGR register fields */
+#define RCC_XBAR56CFGR_XBAR56SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR56CFGR_XBAR56SEL_SHIFT 0
+#define RCC_XBAR56CFGR_XBAR56EN BIT(6)
+#define RCC_XBAR56CFGR_XBAR56STS BIT(7)
+
+/* RCC_XBAR57CFGR register fields */
+#define RCC_XBAR57CFGR_XBAR57SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR57CFGR_XBAR57SEL_SHIFT 0
+#define RCC_XBAR57CFGR_XBAR57EN BIT(6)
+#define RCC_XBAR57CFGR_XBAR57STS BIT(7)
+
+/* RCC_XBAR58CFGR register fields */
+#define RCC_XBAR58CFGR_XBAR58SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR58CFGR_XBAR58SEL_SHIFT 0
+#define RCC_XBAR58CFGR_XBAR58EN BIT(6)
+#define RCC_XBAR58CFGR_XBAR58STS BIT(7)
+
+/* RCC_XBAR59CFGR register fields */
+#define RCC_XBAR59CFGR_XBAR59SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR59CFGR_XBAR59SEL_SHIFT 0
+#define RCC_XBAR59CFGR_XBAR59EN BIT(6)
+#define RCC_XBAR59CFGR_XBAR59STS BIT(7)
+
+/* RCC_XBAR60CFGR register fields */
+#define RCC_XBAR60CFGR_XBAR60SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR60CFGR_XBAR60SEL_SHIFT 0
+#define RCC_XBAR60CFGR_XBAR60EN BIT(6)
+#define RCC_XBAR60CFGR_XBAR60STS BIT(7)
+
+/* RCC_XBAR61CFGR register fields */
+#define RCC_XBAR61CFGR_XBAR61SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR61CFGR_XBAR61SEL_SHIFT 0
+#define RCC_XBAR61CFGR_XBAR61EN BIT(6)
+#define RCC_XBAR61CFGR_XBAR61STS BIT(7)
+
+/* RCC_XBAR62CFGR register fields */
+#define RCC_XBAR62CFGR_XBAR62SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR62CFGR_XBAR62SEL_SHIFT 0
+#define RCC_XBAR62CFGR_XBAR62EN BIT(6)
+#define RCC_XBAR62CFGR_XBAR62STS BIT(7)
+
+/* RCC_XBAR63CFGR register fields */
+#define RCC_XBAR63CFGR_XBAR63SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR63CFGR_XBAR63SEL_SHIFT 0
+#define RCC_XBAR63CFGR_XBAR63EN BIT(6)
+#define RCC_XBAR63CFGR_XBAR63STS BIT(7)
+
+/* RCC_XBARxCFGR register fields */
+#define RCC_XBARxCFGR_XBARxSEL_MASK GENMASK_32(3, 0)
+#define RCC_XBARxCFGR_XBARxSEL_SHIFT 0
+#define RCC_XBARxCFGR_XBARxEN BIT(6)
+#define RCC_XBARxCFGR_XBARxSTS BIT(7)
+
+/* RCC_PREDIV0CFGR register fields */
+#define RCC_PREDIV0CFGR_PREDIV0_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV0CFGR_PREDIV0_SHIFT 0
+
+/* RCC_PREDIV1CFGR register fields */
+#define RCC_PREDIV1CFGR_PREDIV1_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV1CFGR_PREDIV1_SHIFT 0
+
+/* RCC_PREDIV2CFGR register fields */
+#define RCC_PREDIV2CFGR_PREDIV2_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV2CFGR_PREDIV2_SHIFT 0
+
+/* RCC_PREDIV3CFGR register fields */
+#define RCC_PREDIV3CFGR_PREDIV3_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV3CFGR_PREDIV3_SHIFT 0
+
+/* RCC_PREDIV4CFGR register fields */
+#define RCC_PREDIV4CFGR_PREDIV4_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV4CFGR_PREDIV4_SHIFT 0
+
+/* RCC_PREDIV5CFGR register fields */
+#define RCC_PREDIV5CFGR_PREDIV5_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV5CFGR_PREDIV5_SHIFT 0
+
+/* RCC_PREDIV6CFGR register fields */
+#define RCC_PREDIV6CFGR_PREDIV6_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV6CFGR_PREDIV6_SHIFT 0
+
+/* RCC_PREDIV7CFGR register fields */
+#define RCC_PREDIV7CFGR_PREDIV7_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV7CFGR_PREDIV7_SHIFT 0
+
+/* RCC_PREDIV8CFGR register fields */
+#define RCC_PREDIV8CFGR_PREDIV8_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV8CFGR_PREDIV8_SHIFT 0
+
+/* RCC_PREDIV9CFGR register fields */
+#define RCC_PREDIV9CFGR_PREDIV9_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV9CFGR_PREDIV9_SHIFT 0
+
+/* RCC_PREDIV10CFGR register fields */
+#define RCC_PREDIV10CFGR_PREDIV10_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV10CFGR_PREDIV10_SHIFT 0
+
+/* RCC_PREDIV11CFGR register fields */
+#define RCC_PREDIV11CFGR_PREDIV11_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV11CFGR_PREDIV11_SHIFT 0
+
+/* RCC_PREDIV12CFGR register fields */
+#define RCC_PREDIV12CFGR_PREDIV12_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV12CFGR_PREDIV12_SHIFT 0
+
+/* RCC_PREDIV13CFGR register fields */
+#define RCC_PREDIV13CFGR_PREDIV13_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV13CFGR_PREDIV13_SHIFT 0
+
+/* RCC_PREDIV14CFGR register fields */
+#define RCC_PREDIV14CFGR_PREDIV14_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV14CFGR_PREDIV14_SHIFT 0
+
+/* RCC_PREDIV15CFGR register fields */
+#define RCC_PREDIV15CFGR_PREDIV15_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV15CFGR_PREDIV15_SHIFT 0
+
+/* RCC_PREDIV16CFGR register fields */
+#define RCC_PREDIV16CFGR_PREDIV16_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV16CFGR_PREDIV16_SHIFT 0
+
+/* RCC_PREDIV17CFGR register fields */
+#define RCC_PREDIV17CFGR_PREDIV17_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV17CFGR_PREDIV17_SHIFT 0
+
+/* RCC_PREDIV18CFGR register fields */
+#define RCC_PREDIV18CFGR_PREDIV18_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV18CFGR_PREDIV18_SHIFT 0
+
+/* RCC_PREDIV19CFGR register fields */
+#define RCC_PREDIV19CFGR_PREDIV19_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV19CFGR_PREDIV19_SHIFT 0
+
+/* RCC_PREDIV20CFGR register fields */
+#define RCC_PREDIV20CFGR_PREDIV20_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV20CFGR_PREDIV20_SHIFT 0
+
+/* RCC_PREDIV21CFGR register fields */
+#define RCC_PREDIV21CFGR_PREDIV21_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV21CFGR_PREDIV21_SHIFT 0
+
+/* RCC_PREDIV22CFGR register fields */
+#define RCC_PREDIV22CFGR_PREDIV22_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV22CFGR_PREDIV22_SHIFT 0
+
+/* RCC_PREDIV23CFGR register fields */
+#define RCC_PREDIV23CFGR_PREDIV23_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV23CFGR_PREDIV23_SHIFT 0
+
+/* RCC_PREDIV24CFGR register fields */
+#define RCC_PREDIV24CFGR_PREDIV24_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV24CFGR_PREDIV24_SHIFT 0
+
+/* RCC_PREDIV25CFGR register fields */
+#define RCC_PREDIV25CFGR_PREDIV25_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV25CFGR_PREDIV25_SHIFT 0
+
+/* RCC_PREDIV26CFGR register fields */
+#define RCC_PREDIV26CFGR_PREDIV26_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV26CFGR_PREDIV26_SHIFT 0
+
+/* RCC_PREDIV27CFGR register fields */
+#define RCC_PREDIV27CFGR_PREDIV27_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV27CFGR_PREDIV27_SHIFT 0
+
+/* RCC_PREDIV28CFGR register fields */
+#define RCC_PREDIV28CFGR_PREDIV28_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV28CFGR_PREDIV28_SHIFT 0
+
+/* RCC_PREDIV29CFGR register fields */
+#define RCC_PREDIV29CFGR_PREDIV29_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV29CFGR_PREDIV29_SHIFT 0
+
+/* RCC_PREDIV30CFGR register fields */
+#define RCC_PREDIV30CFGR_PREDIV30_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV30CFGR_PREDIV30_SHIFT 0
+
+/* RCC_PREDIV31CFGR register fields */
+#define RCC_PREDIV31CFGR_PREDIV31_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV31CFGR_PREDIV31_SHIFT 0
+
+/* RCC_PREDIV32CFGR register fields */
+#define RCC_PREDIV32CFGR_PREDIV32_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV32CFGR_PREDIV32_SHIFT 0
+
+/* RCC_PREDIV33CFGR register fields */
+#define RCC_PREDIV33CFGR_PREDIV33_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV33CFGR_PREDIV33_SHIFT 0
+
+/* RCC_PREDIV34CFGR register fields */
+#define RCC_PREDIV34CFGR_PREDIV34_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV34CFGR_PREDIV34_SHIFT 0
+
+/* RCC_PREDIV35CFGR register fields */
+#define RCC_PREDIV35CFGR_PREDIV35_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV35CFGR_PREDIV35_SHIFT 0
+
+/* RCC_PREDIV36CFGR register fields */
+#define RCC_PREDIV36CFGR_PREDIV36_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV36CFGR_PREDIV36_SHIFT 0
+
+/* RCC_PREDIV37CFGR register fields */
+#define RCC_PREDIV37CFGR_PREDIV37_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV37CFGR_PREDIV37_SHIFT 0
+
+/* RCC_PREDIV38CFGR register fields */
+#define RCC_PREDIV38CFGR_PREDIV38_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV38CFGR_PREDIV38_SHIFT 0
+
+/* RCC_PREDIV39CFGR register fields */
+#define RCC_PREDIV39CFGR_PREDIV39_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV39CFGR_PREDIV39_SHIFT 0
+
+/* RCC_PREDIV40CFGR register fields */
+#define RCC_PREDIV40CFGR_PREDIV40_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV40CFGR_PREDIV40_SHIFT 0
+
+/* RCC_PREDIV41CFGR register fields */
+#define RCC_PREDIV41CFGR_PREDIV41_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV41CFGR_PREDIV41_SHIFT 0
+
+/* RCC_PREDIV42CFGR register fields */
+#define RCC_PREDIV42CFGR_PREDIV42_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV42CFGR_PREDIV42_SHIFT 0
+
+/* RCC_PREDIV43CFGR register fields */
+#define RCC_PREDIV43CFGR_PREDIV43_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV43CFGR_PREDIV43_SHIFT 0
+
+/* RCC_PREDIV44CFGR register fields */
+#define RCC_PREDIV44CFGR_PREDIV44_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV44CFGR_PREDIV44_SHIFT 0
+
+/* RCC_PREDIV45CFGR register fields */
+#define RCC_PREDIV45CFGR_PREDIV45_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV45CFGR_PREDIV45_SHIFT 0
+
+/* RCC_PREDIV46CFGR register fields */
+#define RCC_PREDIV46CFGR_PREDIV46_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV46CFGR_PREDIV46_SHIFT 0
+
+/* RCC_PREDIV47CFGR register fields */
+#define RCC_PREDIV47CFGR_PREDIV47_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV47CFGR_PREDIV47_SHIFT 0
+
+/* RCC_PREDIV48CFGR register fields */
+#define RCC_PREDIV48CFGR_PREDIV48_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV48CFGR_PREDIV48_SHIFT 0
+
+/* RCC_PREDIV49CFGR register fields */
+#define RCC_PREDIV49CFGR_PREDIV49_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV49CFGR_PREDIV49_SHIFT 0
+
+/* RCC_PREDIV50CFGR register fields */
+#define RCC_PREDIV50CFGR_PREDIV50_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV50CFGR_PREDIV50_SHIFT 0
+
+/* RCC_PREDIV51CFGR register fields */
+#define RCC_PREDIV51CFGR_PREDIV51_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV51CFGR_PREDIV51_SHIFT 0
+
+/* RCC_PREDIV52CFGR register fields */
+#define RCC_PREDIV52CFGR_PREDIV52_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV52CFGR_PREDIV52_SHIFT 0
+
+/* RCC_PREDIV53CFGR register fields */
+#define RCC_PREDIV53CFGR_PREDIV53_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV53CFGR_PREDIV53_SHIFT 0
+
+/* RCC_PREDIV54CFGR register fields */
+#define RCC_PREDIV54CFGR_PREDIV54_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV54CFGR_PREDIV54_SHIFT 0
+
+/* RCC_PREDIV55CFGR register fields */
+#define RCC_PREDIV55CFGR_PREDIV55_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV55CFGR_PREDIV55_SHIFT 0
+
+/* RCC_PREDIV56CFGR register fields */
+#define RCC_PREDIV56CFGR_PREDIV56_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV56CFGR_PREDIV56_SHIFT 0
+
+/* RCC_PREDIV57CFGR register fields */
+#define RCC_PREDIV57CFGR_PREDIV57_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV57CFGR_PREDIV57_SHIFT 0
+
+/* RCC_PREDIV58CFGR register fields */
+#define RCC_PREDIV58CFGR_PREDIV58_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV58CFGR_PREDIV58_SHIFT 0
+
+/* RCC_PREDIV59CFGR register fields */
+#define RCC_PREDIV59CFGR_PREDIV59_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV59CFGR_PREDIV59_SHIFT 0
+
+/* RCC_PREDIV60CFGR register fields */
+#define RCC_PREDIV60CFGR_PREDIV60_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV60CFGR_PREDIV60_SHIFT 0
+
+/* RCC_PREDIV61CFGR register fields */
+#define RCC_PREDIV61CFGR_PREDIV61_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV61CFGR_PREDIV61_SHIFT 0
+
+/* RCC_PREDIV62CFGR register fields */
+#define RCC_PREDIV62CFGR_PREDIV62_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV62CFGR_PREDIV62_SHIFT 0
+
+/* RCC_PREDIV63CFGR register fields */
+#define RCC_PREDIV63CFGR_PREDIV63_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV63CFGR_PREDIV63_SHIFT 0
+
+/* RCC_PREDIVxCFGR register fields */
+#define RCC_PREDIVxCFGR_PREDIVx_MASK GENMASK_32(9, 0)
+#define RCC_PREDIVxCFGR_PREDIVx_SHIFT 0
+
+/* RCC_FINDIV0CFGR register fields */
+#define RCC_FINDIV0CFGR_FINDIV0_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV0CFGR_FINDIV0_SHIFT 0
+#define RCC_FINDIV0CFGR_FINDIV0EN BIT(6)
+
+/* RCC_FINDIV1CFGR register fields */
+#define RCC_FINDIV1CFGR_FINDIV1_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV1CFGR_FINDIV1_SHIFT 0
+#define RCC_FINDIV1CFGR_FINDIV1EN BIT(6)
+
+/* RCC_FINDIV2CFGR register fields */
+#define RCC_FINDIV2CFGR_FINDIV2_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV2CFGR_FINDIV2_SHIFT 0
+#define RCC_FINDIV2CFGR_FINDIV2EN BIT(6)
+
+/* RCC_FINDIV3CFGR register fields */
+#define RCC_FINDIV3CFGR_FINDIV3_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV3CFGR_FINDIV3_SHIFT 0
+#define RCC_FINDIV3CFGR_FINDIV3EN BIT(6)
+
+/* RCC_FINDIV4CFGR register fields */
+#define RCC_FINDIV4CFGR_FINDIV4_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV4CFGR_FINDIV4_SHIFT 0
+#define RCC_FINDIV4CFGR_FINDIV4EN BIT(6)
+
+/* RCC_FINDIV5CFGR register fields */
+#define RCC_FINDIV5CFGR_FINDIV5_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV5CFGR_FINDIV5_SHIFT 0
+#define RCC_FINDIV5CFGR_FINDIV5EN BIT(6)
+
+/* RCC_FINDIV6CFGR register fields */
+#define RCC_FINDIV6CFGR_FINDIV6_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV6CFGR_FINDIV6_SHIFT 0
+#define RCC_FINDIV6CFGR_FINDIV6EN BIT(6)
+
+/* RCC_FINDIV7CFGR register fields */
+#define RCC_FINDIV7CFGR_FINDIV7_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV7CFGR_FINDIV7_SHIFT 0
+#define RCC_FINDIV7CFGR_FINDIV7EN BIT(6)
+
+/* RCC_FINDIV8CFGR register fields */
+#define RCC_FINDIV8CFGR_FINDIV8_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV8CFGR_FINDIV8_SHIFT 0
+#define RCC_FINDIV8CFGR_FINDIV8EN BIT(6)
+
+/* RCC_FINDIV9CFGR register fields */
+#define RCC_FINDIV9CFGR_FINDIV9_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV9CFGR_FINDIV9_SHIFT 0
+#define RCC_FINDIV9CFGR_FINDIV9EN BIT(6)
+
+/* RCC_FINDIV10CFGR register fields */
+#define RCC_FINDIV10CFGR_FINDIV10_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV10CFGR_FINDIV10_SHIFT 0
+#define RCC_FINDIV10CFGR_FINDIV10EN BIT(6)
+
+/* RCC_FINDIV11CFGR register fields */
+#define RCC_FINDIV11CFGR_FINDIV11_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV11CFGR_FINDIV11_SHIFT 0
+#define RCC_FINDIV11CFGR_FINDIV11EN BIT(6)
+
+/* RCC_FINDIV12CFGR register fields */
+#define RCC_FINDIV12CFGR_FINDIV12_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV12CFGR_FINDIV12_SHIFT 0
+#define RCC_FINDIV12CFGR_FINDIV12EN BIT(6)
+
+/* RCC_FINDIV13CFGR register fields */
+#define RCC_FINDIV13CFGR_FINDIV13_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV13CFGR_FINDIV13_SHIFT 0
+#define RCC_FINDIV13CFGR_FINDIV13EN BIT(6)
+
+/* RCC_FINDIV14CFGR register fields */
+#define RCC_FINDIV14CFGR_FINDIV14_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV14CFGR_FINDIV14_SHIFT 0
+#define RCC_FINDIV14CFGR_FINDIV14EN BIT(6)
+
+/* RCC_FINDIV15CFGR register fields */
+#define RCC_FINDIV15CFGR_FINDIV15_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV15CFGR_FINDIV15_SHIFT 0
+#define RCC_FINDIV15CFGR_FINDIV15EN BIT(6)
+
+/* RCC_FINDIV16CFGR register fields */
+#define RCC_FINDIV16CFGR_FINDIV16_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV16CFGR_FINDIV16_SHIFT 0
+#define RCC_FINDIV16CFGR_FINDIV16EN BIT(6)
+
+/* RCC_FINDIV17CFGR register fields */
+#define RCC_FINDIV17CFGR_FINDIV17_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV17CFGR_FINDIV17_SHIFT 0
+#define RCC_FINDIV17CFGR_FINDIV17EN BIT(6)
+
+/* RCC_FINDIV18CFGR register fields */
+#define RCC_FINDIV18CFGR_FINDIV18_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV18CFGR_FINDIV18_SHIFT 0
+#define RCC_FINDIV18CFGR_FINDIV18EN BIT(6)
+
+/* RCC_FINDIV19CFGR register fields */
+#define RCC_FINDIV19CFGR_FINDIV19_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV19CFGR_FINDIV19_SHIFT 0
+#define RCC_FINDIV19CFGR_FINDIV19EN BIT(6)
+
+/* RCC_FINDIV20CFGR register fields */
+#define RCC_FINDIV20CFGR_FINDIV20_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV20CFGR_FINDIV20_SHIFT 0
+#define RCC_FINDIV20CFGR_FINDIV20EN BIT(6)
+
+/* RCC_FINDIV21CFGR register fields */
+#define RCC_FINDIV21CFGR_FINDIV21_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV21CFGR_FINDIV21_SHIFT 0
+#define RCC_FINDIV21CFGR_FINDIV21EN BIT(6)
+
+/* RCC_FINDIV22CFGR register fields */
+#define RCC_FINDIV22CFGR_FINDIV22_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV22CFGR_FINDIV22_SHIFT 0
+#define RCC_FINDIV22CFGR_FINDIV22EN BIT(6)
+
+/* RCC_FINDIV23CFGR register fields */
+#define RCC_FINDIV23CFGR_FINDIV23_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV23CFGR_FINDIV23_SHIFT 0
+#define RCC_FINDIV23CFGR_FINDIV23EN BIT(6)
+
+/* RCC_FINDIV24CFGR register fields */
+#define RCC_FINDIV24CFGR_FINDIV24_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV24CFGR_FINDIV24_SHIFT 0
+#define RCC_FINDIV24CFGR_FINDIV24EN BIT(6)
+
+/* RCC_FINDIV25CFGR register fields */
+#define RCC_FINDIV25CFGR_FINDIV25_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV25CFGR_FINDIV25_SHIFT 0
+#define RCC_FINDIV25CFGR_FINDIV25EN BIT(6)
+
+/* RCC_FINDIV26CFGR register fields */
+#define RCC_FINDIV26CFGR_FINDIV26_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV26CFGR_FINDIV26_SHIFT 0
+#define RCC_FINDIV26CFGR_FINDIV26EN BIT(6)
+
+/* RCC_FINDIV27CFGR register fields */
+#define RCC_FINDIV27CFGR_FINDIV27_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV27CFGR_FINDIV27_SHIFT 0
+#define RCC_FINDIV27CFGR_FINDIV27EN BIT(6)
+
+/* RCC_FINDIV28CFGR register fields */
+#define RCC_FINDIV28CFGR_FINDIV28_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV28CFGR_FINDIV28_SHIFT 0
+#define RCC_FINDIV28CFGR_FINDIV28EN BIT(6)
+
+/* RCC_FINDIV29CFGR register fields */
+#define RCC_FINDIV29CFGR_FINDIV29_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV29CFGR_FINDIV29_SHIFT 0
+#define RCC_FINDIV29CFGR_FINDIV29EN BIT(6)
+
+/* RCC_FINDIV30CFGR register fields */
+#define RCC_FINDIV30CFGR_FINDIV30_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV30CFGR_FINDIV30_SHIFT 0
+#define RCC_FINDIV30CFGR_FINDIV30EN BIT(6)
+
+/* RCC_FINDIV31CFGR register fields */
+#define RCC_FINDIV31CFGR_FINDIV31_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV31CFGR_FINDIV31_SHIFT 0
+#define RCC_FINDIV31CFGR_FINDIV31EN BIT(6)
+
+/* RCC_FINDIV32CFGR register fields */
+#define RCC_FINDIV32CFGR_FINDIV32_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV32CFGR_FINDIV32_SHIFT 0
+#define RCC_FINDIV32CFGR_FINDIV32EN BIT(6)
+
+/* RCC_FINDIV33CFGR register fields */
+#define RCC_FINDIV33CFGR_FINDIV33_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV33CFGR_FINDIV33_SHIFT 0
+#define RCC_FINDIV33CFGR_FINDIV33EN BIT(6)
+
+/* RCC_FINDIV34CFGR register fields */
+#define RCC_FINDIV34CFGR_FINDIV34_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV34CFGR_FINDIV34_SHIFT 0
+#define RCC_FINDIV34CFGR_FINDIV34EN BIT(6)
+
+/* RCC_FINDIV35CFGR register fields */
+#define RCC_FINDIV35CFGR_FINDIV35_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV35CFGR_FINDIV35_SHIFT 0
+#define RCC_FINDIV35CFGR_FINDIV35EN BIT(6)
+
+/* RCC_FINDIV36CFGR register fields */
+#define RCC_FINDIV36CFGR_FINDIV36_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV36CFGR_FINDIV36_SHIFT 0
+#define RCC_FINDIV36CFGR_FINDIV36EN BIT(6)
+
+/* RCC_FINDIV37CFGR register fields */
+#define RCC_FINDIV37CFGR_FINDIV37_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV37CFGR_FINDIV37_SHIFT 0
+#define RCC_FINDIV37CFGR_FINDIV37EN BIT(6)
+
+/* RCC_FINDIV38CFGR register fields */
+#define RCC_FINDIV38CFGR_FINDIV38_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV38CFGR_FINDIV38_SHIFT 0
+#define RCC_FINDIV38CFGR_FINDIV38EN BIT(6)
+
+/* RCC_FINDIV39CFGR register fields */
+#define RCC_FINDIV39CFGR_FINDIV39_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV39CFGR_FINDIV39_SHIFT 0
+#define RCC_FINDIV39CFGR_FINDIV39EN BIT(6)
+
+/* RCC_FINDIV40CFGR register fields */
+#define RCC_FINDIV40CFGR_FINDIV40_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV40CFGR_FINDIV40_SHIFT 0
+#define RCC_FINDIV40CFGR_FINDIV40EN BIT(6)
+
+/* RCC_FINDIV41CFGR register fields */
+#define RCC_FINDIV41CFGR_FINDIV41_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV41CFGR_FINDIV41_SHIFT 0
+#define RCC_FINDIV41CFGR_FINDIV41EN BIT(6)
+
+/* RCC_FINDIV42CFGR register fields */
+#define RCC_FINDIV42CFGR_FINDIV42_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV42CFGR_FINDIV42_SHIFT 0
+#define RCC_FINDIV42CFGR_FINDIV42EN BIT(6)
+
+/* RCC_FINDIV43CFGR register fields */
+#define RCC_FINDIV43CFGR_FINDIV43_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV43CFGR_FINDIV43_SHIFT 0
+#define RCC_FINDIV43CFGR_FINDIV43EN BIT(6)
+
+/* RCC_FINDIV44CFGR register fields */
+#define RCC_FINDIV44CFGR_FINDIV44_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV44CFGR_FINDIV44_SHIFT 0
+#define RCC_FINDIV44CFGR_FINDIV44EN BIT(6)
+
+/* RCC_FINDIV45CFGR register fields */
+#define RCC_FINDIV45CFGR_FINDIV45_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV45CFGR_FINDIV45_SHIFT 0
+#define RCC_FINDIV45CFGR_FINDIV45EN BIT(6)
+
+/* RCC_FINDIV46CFGR register fields */
+#define RCC_FINDIV46CFGR_FINDIV46_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV46CFGR_FINDIV46_SHIFT 0
+#define RCC_FINDIV46CFGR_FINDIV46EN BIT(6)
+
+/* RCC_FINDIV47CFGR register fields */
+#define RCC_FINDIV47CFGR_FINDIV47_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV47CFGR_FINDIV47_SHIFT 0
+#define RCC_FINDIV47CFGR_FINDIV47EN BIT(6)
+
+/* RCC_FINDIV48CFGR register fields */
+#define RCC_FINDIV48CFGR_FINDIV48_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV48CFGR_FINDIV48_SHIFT 0
+#define RCC_FINDIV48CFGR_FINDIV48EN BIT(6)
+
+/* RCC_FINDIV49CFGR register fields */
+#define RCC_FINDIV49CFGR_FINDIV49_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV49CFGR_FINDIV49_SHIFT 0
+#define RCC_FINDIV49CFGR_FINDIV49EN BIT(6)
+
+/* RCC_FINDIV50CFGR register fields */
+#define RCC_FINDIV50CFGR_FINDIV50_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV50CFGR_FINDIV50_SHIFT 0
+#define RCC_FINDIV50CFGR_FINDIV50EN BIT(6)
+
+/* RCC_FINDIV51CFGR register fields */
+#define RCC_FINDIV51CFGR_FINDIV51_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV51CFGR_FINDIV51_SHIFT 0
+#define RCC_FINDIV51CFGR_FINDIV51EN BIT(6)
+
+/* RCC_FINDIV52CFGR register fields */
+#define RCC_FINDIV52CFGR_FINDIV52_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV52CFGR_FINDIV52_SHIFT 0
+#define RCC_FINDIV52CFGR_FINDIV52EN BIT(6)
+
+/* RCC_FINDIV53CFGR register fields */
+#define RCC_FINDIV53CFGR_FINDIV53_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV53CFGR_FINDIV53_SHIFT 0
+#define RCC_FINDIV53CFGR_FINDIV53EN BIT(6)
+
+/* RCC_FINDIV54CFGR register fields */
+#define RCC_FINDIV54CFGR_FINDIV54_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV54CFGR_FINDIV54_SHIFT 0
+#define RCC_FINDIV54CFGR_FINDIV54EN BIT(6)
+
+/* RCC_FINDIV55CFGR register fields */
+#define RCC_FINDIV55CFGR_FINDIV55_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV55CFGR_FINDIV55_SHIFT 0
+#define RCC_FINDIV55CFGR_FINDIV55EN BIT(6)
+
+/* RCC_FINDIV56CFGR register fields */
+#define RCC_FINDIV56CFGR_FINDIV56_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV56CFGR_FINDIV56_SHIFT 0
+#define RCC_FINDIV56CFGR_FINDIV56EN BIT(6)
+
+/* RCC_FINDIV57CFGR register fields */
+#define RCC_FINDIV57CFGR_FINDIV57_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV57CFGR_FINDIV57_SHIFT 0
+#define RCC_FINDIV57CFGR_FINDIV57EN BIT(6)
+
+/* RCC_FINDIV58CFGR register fields */
+#define RCC_FINDIV58CFGR_FINDIV58_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV58CFGR_FINDIV58_SHIFT 0
+#define RCC_FINDIV58CFGR_FINDIV58EN BIT(6)
+
+/* RCC_FINDIV59CFGR register fields */
+#define RCC_FINDIV59CFGR_FINDIV59_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV59CFGR_FINDIV59_SHIFT 0
+#define RCC_FINDIV59CFGR_FINDIV59EN BIT(6)
+
+/* RCC_FINDIV60CFGR register fields */
+#define RCC_FINDIV60CFGR_FINDIV60_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV60CFGR_FINDIV60_SHIFT 0
+#define RCC_FINDIV60CFGR_FINDIV60EN BIT(6)
+
+/* RCC_FINDIV61CFGR register fields */
+#define RCC_FINDIV61CFGR_FINDIV61_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV61CFGR_FINDIV61_SHIFT 0
+#define RCC_FINDIV61CFGR_FINDIV61EN BIT(6)
+
+/* RCC_FINDIV62CFGR register fields */
+#define RCC_FINDIV62CFGR_FINDIV62_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV62CFGR_FINDIV62_SHIFT 0
+#define RCC_FINDIV62CFGR_FINDIV62EN BIT(6)
+
+/* RCC_FINDIV63CFGR register fields */
+#define RCC_FINDIV63CFGR_FINDIV63_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV63CFGR_FINDIV63_SHIFT 0
+#define RCC_FINDIV63CFGR_FINDIV63EN BIT(6)
+
+/* RCC_FINDIVxCFGR register fields */
+#define RCC_FINDIVxCFGR_FINDIVx_MASK GENMASK_32(5, 0)
+#define RCC_FINDIVxCFGR_FINDIVx_SHIFT 0
+#define RCC_FINDIVxCFGR_FINDIVxEN BIT(6)
+
+/* RCC_FCALCOBS0CFGR register fields */
+#define RCC_FCALCOBS0CFGR_CKINTSEL_MASK GENMASK_32(7, 0)
+#define RCC_FCALCOBS0CFGR_CKINTSEL_SHIFT 0
+#define RCC_FCALCOBS0CFGR_CKEXTSEL_MASK GENMASK_32(10, 8)
+#define RCC_FCALCOBS0CFGR_CKEXTSEL_SHIFT 8
+#define RCC_FCALCOBS0CFGR_FCALCCKEXTSEL BIT(15)
+#define RCC_FCALCOBS0CFGR_CKOBSEXTSEL BIT(16)
+#define RCC_FCALCOBS0CFGR_FCALCCKINV BIT(17)
+#define RCC_FCALCOBS0CFGR_CKOBSINV BIT(18)
+#define RCC_FCALCOBS0CFGR_CKOBSDIV_MASK GENMASK_32(24, 22)
+#define RCC_FCALCOBS0CFGR_CKOBSDIV_SHIFT 22
+#define RCC_FCALCOBS0CFGR_FCALCCKEN BIT(25)
+#define RCC_FCALCOBS0CFGR_CKOBSEN BIT(26)
+
+/* RCC_FCALCOBS1CFGR register fields */
+#define RCC_FCALCOBS1CFGR_CKINTSEL_MASK GENMASK_32(7, 0)
+#define RCC_FCALCOBS1CFGR_CKINTSEL_SHIFT 0
+#define RCC_FCALCOBS1CFGR_CKEXTSEL_MASK GENMASK_32(10, 8)
+#define RCC_FCALCOBS1CFGR_CKEXTSEL_SHIFT 8
+#define RCC_FCALCOBS1CFGR_CKOBSEXTSEL BIT(16)
+#define RCC_FCALCOBS1CFGR_CKOBSINV BIT(18)
+#define RCC_FCALCOBS1CFGR_CKOBSDIV_MASK GENMASK_32(24, 22)
+#define RCC_FCALCOBS1CFGR_CKOBSDIV_SHIFT 22
+#define RCC_FCALCOBS1CFGR_CKOBSEN BIT(26)
+#define RCC_FCALCOBS1CFGR_FCALCRSTN BIT(27)
+
+/* RCC_FCALCREFCFGR register fields */
+#define RCC_FCALCREFCFGR_FCALCREFCKSEL_MASK GENMASK_32(2, 0)
+#define RCC_FCALCREFCFGR_FCALCREFCKSEL_SHIFT 0
+
+/* RCC_FCALCCR1 register fields */
+#define RCC_FCALCCR1_FCALCRUN BIT(0)
+
+/* RCC_FCALCCR2 register fields */
+#define RCC_FCALCCR2_FCALCMD_MASK GENMASK_32(4, 3)
+#define RCC_FCALCCR2_FCALCMD_SHIFT 3
+#define RCC_FCALCCR2_FCALCTWC_MASK GENMASK_32(14, 11)
+#define RCC_FCALCCR2_FCALCTWC_SHIFT 11
+#define RCC_FCALCCR2_FCALCTYP_MASK GENMASK_32(21, 17)
+#define RCC_FCALCCR2_FCALCTYP_SHIFT 17
+
+/* RCC_FCALCSR register fields */
+#define RCC_FCALCSR_FVAL_MASK GENMASK_32(16, 0)
+#define RCC_FCALCSR_FVAL_SHIFT 0
+#define RCC_FCALCSR_FCALCSTS BIT(19)
+
+/* RCC_PLL4CFGR1 register fields */
+#define RCC_PLL4CFGR1_SSMODRST BIT(0)
+#define RCC_PLL4CFGR1_PLLEN BIT(8)
+#define RCC_PLL4CFGR1_PLLRDY BIT(24)
+#define RCC_PLL4CFGR1_CKREFST BIT(28)
+
+/* RCC_PLL4CFGR2 register fields */
+#define RCC_PLL4CFGR2_FREFDIV_MASK GENMASK_32(5, 0)
+#define RCC_PLL4CFGR2_FREFDIV_SHIFT 0
+#define RCC_PLL4CFGR2_FBDIV_MASK GENMASK_32(27, 16)
+#define RCC_PLL4CFGR2_FBDIV_SHIFT 16
+
+/* RCC_PLL4CFGR3 register fields */
+#define RCC_PLL4CFGR3_FRACIN_MASK GENMASK_32(23, 0)
+#define RCC_PLL4CFGR3_FRACIN_SHIFT 0
+#define RCC_PLL4CFGR3_DOWNSPREAD BIT(24)
+#define RCC_PLL4CFGR3_DACEN BIT(25)
+#define RCC_PLL4CFGR3_SSCGDIS BIT(26)
+
+/* RCC_PLL4CFGR4 register fields */
+#define RCC_PLL4CFGR4_DSMEN BIT(8)
+#define RCC_PLL4CFGR4_FOUTPOSTDIVEN BIT(9)
+#define RCC_PLL4CFGR4_BYPASS BIT(10)
+
+/* RCC_PLL4CFGR5 register fields */
+#define RCC_PLL4CFGR5_DIVVAL_MASK GENMASK_32(3, 0)
+#define RCC_PLL4CFGR5_DIVVAL_SHIFT 0
+#define RCC_PLL4CFGR5_SPREAD_MASK GENMASK_32(20, 16)
+#define RCC_PLL4CFGR5_SPREAD_SHIFT 16
+
+/* RCC_PLL4CFGR6 register fields */
+#define RCC_PLL4CFGR6_POSTDIV1_MASK GENMASK_32(2, 0)
+#define RCC_PLL4CFGR6_POSTDIV1_SHIFT 0
+
+/* RCC_PLL4CFGR7 register fields */
+#define RCC_PLL4CFGR7_POSTDIV2_MASK GENMASK_32(2, 0)
+#define RCC_PLL4CFGR7_POSTDIV2_SHIFT 0
+
+/* RCC_PLL5CFGR1 register fields */
+#define RCC_PLL5CFGR1_SSMODRST BIT(0)
+#define RCC_PLL5CFGR1_PLLEN BIT(8)
+#define RCC_PLL5CFGR1_PLLRDY BIT(24)
+#define RCC_PLL5CFGR1_CKREFST BIT(28)
+
+/* RCC_PLL5CFGR2 register fields */
+#define RCC_PLL5CFGR2_FREFDIV_MASK GENMASK_32(5, 0)
+#define RCC_PLL5CFGR2_FREFDIV_SHIFT 0
+#define RCC_PLL5CFGR2_FBDIV_MASK GENMASK_32(27, 16)
+#define RCC_PLL5CFGR2_FBDIV_SHIFT 16
+
+/* RCC_PLL5CFGR3 register fields */
+#define RCC_PLL5CFGR3_FRACIN_MASK GENMASK_32(23, 0)
+#define RCC_PLL5CFGR3_FRACIN_SHIFT 0
+#define RCC_PLL5CFGR3_DOWNSPREAD BIT(24)
+#define RCC_PLL5CFGR3_DACEN BIT(25)
+#define RCC_PLL5CFGR3_SSCGDIS BIT(26)
+
+/* RCC_PLL5CFGR4 register fields */
+#define RCC_PLL5CFGR4_DSMEN BIT(8)
+#define RCC_PLL5CFGR4_FOUTPOSTDIVEN BIT(9)
+#define RCC_PLL5CFGR4_BYPASS BIT(10)
+
+/* RCC_PLL5CFGR5 register fields */
+#define RCC_PLL5CFGR5_DIVVAL_MASK GENMASK_32(3, 0)
+#define RCC_PLL5CFGR5_DIVVAL_SHIFT 0
+#define RCC_PLL5CFGR5_SPREAD_MASK GENMASK_32(20, 16)
+#define RCC_PLL5CFGR5_SPREAD_SHIFT 16
+
+/* RCC_PLL5CFGR6 register fields */
+#define RCC_PLL5CFGR6_POSTDIV1_MASK GENMASK_32(2, 0)
+#define RCC_PLL5CFGR6_POSTDIV1_SHIFT 0
+
+/* RCC_PLL5CFGR7 register fields */
+#define RCC_PLL5CFGR7_POSTDIV2_MASK GENMASK_32(2, 0)
+#define RCC_PLL5CFGR7_POSTDIV2_SHIFT 0
+
+/* RCC_PLL6CFGR1 register fields */
+#define RCC_PLL6CFGR1_SSMODRST BIT(0)
+#define RCC_PLL6CFGR1_PLLEN BIT(8)
+#define RCC_PLL6CFGR1_PLLRDY BIT(24)
+#define RCC_PLL6CFGR1_CKREFST BIT(28)
+
+/* RCC_PLL6CFGR2 register fields */
+#define RCC_PLL6CFGR2_FREFDIV_MASK GENMASK_32(5, 0)
+#define RCC_PLL6CFGR2_FREFDIV_SHIFT 0
+#define RCC_PLL6CFGR2_FBDIV_MASK GENMASK_32(27, 16)
+#define RCC_PLL6CFGR2_FBDIV_SHIFT 16
+
+/* RCC_PLL6CFGR3 register fields */
+#define RCC_PLL6CFGR3_FRACIN_MASK GENMASK_32(23, 0)
+#define RCC_PLL6CFGR3_FRACIN_SHIFT 0
+#define RCC_PLL6CFGR3_DOWNSPREAD BIT(24)
+#define RCC_PLL6CFGR3_DACEN BIT(25)
+#define RCC_PLL6CFGR3_SSCGDIS BIT(26)
+
+/* RCC_PLL6CFGR4 register fields */
+#define RCC_PLL6CFGR4_DSMEN BIT(8)
+#define RCC_PLL6CFGR4_FOUTPOSTDIVEN BIT(9)
+#define RCC_PLL6CFGR4_BYPASS BIT(10)
+
+/* RCC_PLL6CFGR5 register fields */
+#define RCC_PLL6CFGR5_DIVVAL_MASK GENMASK_32(3, 0)
+#define RCC_PLL6CFGR5_DIVVAL_SHIFT 0
+#define RCC_PLL6CFGR5_SPREAD_MASK GENMASK_32(20, 16)
+#define RCC_PLL6CFGR5_SPREAD_SHIFT 16
+
+/* RCC_PLL6CFGR6 register fields */
+#define RCC_PLL6CFGR6_POSTDIV1_MASK GENMASK_32(2, 0)
+#define RCC_PLL6CFGR6_POSTDIV1_SHIFT 0
+
+/* RCC_PLL6CFGR7 register fields */
+#define RCC_PLL6CFGR7_POSTDIV2_MASK GENMASK_32(2, 0)
+#define RCC_PLL6CFGR7_POSTDIV2_SHIFT 0
+
+/* RCC_PLL7CFGR1 register fields */
+#define RCC_PLL7CFGR1_SSMODRST BIT(0)
+#define RCC_PLL7CFGR1_PLLEN BIT(8)
+#define RCC_PLL7CFGR1_PLLRDY BIT(24)
+#define RCC_PLL7CFGR1_CKREFST BIT(28)
+
+/* RCC_PLL7CFGR2 register fields */
+#define RCC_PLL7CFGR2_FREFDIV_MASK GENMASK_32(5, 0)
+#define RCC_PLL7CFGR2_FREFDIV_SHIFT 0
+#define RCC_PLL7CFGR2_FBDIV_MASK GENMASK_32(27, 16)
+#define RCC_PLL7CFGR2_FBDIV_SHIFT 16
+
+/* RCC_PLL7CFGR3 register fields */
+#define RCC_PLL7CFGR3_FRACIN_MASK GENMASK_32(23, 0)
+#define RCC_PLL7CFGR3_FRACIN_SHIFT 0
+#define RCC_PLL7CFGR3_DOWNSPREAD BIT(24)
+#define RCC_PLL7CFGR3_DACEN BIT(25)
+#define RCC_PLL7CFGR3_SSCGDIS BIT(26)
+
+/* RCC_PLL7CFGR4 register fields */
+#define RCC_PLL7CFGR4_DSMEN BIT(8)
+#define RCC_PLL7CFGR4_FOUTPOSTDIVEN BIT(9)
+#define RCC_PLL7CFGR4_BYPASS BIT(10)
+
+/* RCC_PLL7CFGR5 register fields */
+#define RCC_PLL7CFGR5_DIVVAL_MASK GENMASK_32(3, 0)
+#define RCC_PLL7CFGR5_DIVVAL_SHIFT 0
+#define RCC_PLL7CFGR5_SPREAD_MASK GENMASK_32(20, 16)
+#define RCC_PLL7CFGR5_SPREAD_SHIFT 16
+
+/* RCC_PLL7CFGR6 register fields */
+#define RCC_PLL7CFGR6_POSTDIV1_MASK GENMASK_32(2, 0)
+#define RCC_PLL7CFGR6_POSTDIV1_SHIFT 0
+
+/* RCC_PLL7CFGR7 register fields */
+#define RCC_PLL7CFGR7_POSTDIV2_MASK GENMASK_32(2, 0)
+#define RCC_PLL7CFGR7_POSTDIV2_SHIFT 0
+
+/* RCC_PLL8CFGR1 register fields */
+#define RCC_PLL8CFGR1_SSMODRST BIT(0)
+#define RCC_PLL8CFGR1_PLLEN BIT(8)
+#define RCC_PLL8CFGR1_PLLRDY BIT(24)
+#define RCC_PLL8CFGR1_CKREFST BIT(28)
+
+/* RCC_PLL8CFGR2 register fields */
+#define RCC_PLL8CFGR2_FREFDIV_MASK GENMASK_32(5, 0)
+#define RCC_PLL8CFGR2_FREFDIV_SHIFT 0
+#define RCC_PLL8CFGR2_FBDIV_MASK GENMASK_32(27, 16)
+#define RCC_PLL8CFGR2_FBDIV_SHIFT 16
+
+/* RCC_PLL8CFGR3 register fields */
+#define RCC_PLL8CFGR3_FRACIN_MASK GENMASK_32(23, 0)
+#define RCC_PLL8CFGR3_FRACIN_SHIFT 0
+#define RCC_PLL8CFGR3_DOWNSPREAD BIT(24)
+#define RCC_PLL8CFGR3_DACEN BIT(25)
+#define RCC_PLL8CFGR3_SSCGDIS BIT(26)
+
+/* RCC_PLL8CFGR4 register fields */
+#define RCC_PLL8CFGR4_DSMEN BIT(8)
+#define RCC_PLL8CFGR4_FOUTPOSTDIVEN BIT(9)
+#define RCC_PLL8CFGR4_BYPASS BIT(10)
+
+/* RCC_PLL8CFGR5 register fields */
+#define RCC_PLL8CFGR5_DIVVAL_MASK GENMASK_32(3, 0)
+#define RCC_PLL8CFGR5_DIVVAL_SHIFT 0
+#define RCC_PLL8CFGR5_SPREAD_MASK GENMASK_32(20, 16)
+#define RCC_PLL8CFGR5_SPREAD_SHIFT 16
+
+/* RCC_PLL8CFGR6 register fields */
+#define RCC_PLL8CFGR6_POSTDIV1_MASK GENMASK_32(2, 0)
+#define RCC_PLL8CFGR6_POSTDIV1_SHIFT 0
+
+/* RCC_PLL8CFGR7 register fields */
+#define RCC_PLL8CFGR7_POSTDIV2_MASK GENMASK_32(2, 0)
+#define RCC_PLL8CFGR7_POSTDIV2_SHIFT 0
+
+/* RCC_PLLxCFGR1 register fields */
+#define RCC_PLLxCFGR1_SSMODRST BIT(0)
+#define RCC_PLLxCFGR1_PLLEN BIT(8)
+#define RCC_PLLxCFGR1_PLLRDY BIT(24)
+#define RCC_PLLxCFGR1_CKREFST BIT(28)
+
+/* RCC_PLLxCFGR2 register fields */
+#define RCC_PLLxCFGR2_FREFDIV_MASK GENMASK_32(5, 0)
+#define RCC_PLLxCFGR2_FREFDIV_SHIFT 0
+#define RCC_PLLxCFGR2_FBDIV_MASK GENMASK_32(27, 16)
+#define RCC_PLLxCFGR2_FBDIV_SHIFT 16
+
+/* RCC_PLLxCFGR3 register fields */
+#define RCC_PLLxCFGR3_FRACIN_MASK GENMASK_32(23, 0)
+#define RCC_PLLxCFGR3_FRACIN_SHIFT 0
+#define RCC_PLLxCFGR3_DOWNSPREAD BIT(24)
+#define RCC_PLLxCFGR3_DACEN BIT(25)
+#define RCC_PLLxCFGR3_SSCGDIS BIT(26)
+
+/* RCC_PLLxCFGR4 register fields */
+#define RCC_PLLxCFGR4_DSMEN BIT(8)
+#define RCC_PLLxCFGR4_FOUTPOSTDIVEN BIT(9)
+#define RCC_PLLxCFGR4_BYPASS BIT(10)
+
+/* RCC_PLLxCFGR5 register fields */
+#define RCC_PLLxCFGR5_DIVVAL_MASK GENMASK_32(3, 0)
+#define RCC_PLLxCFGR5_DIVVAL_SHIFT 0
+#define RCC_PLLxCFGR5_SPREAD_MASK GENMASK_32(20, 16)
+#define RCC_PLLxCFGR5_SPREAD_SHIFT 16
+
+/* RCC_PLLxCFGR6 register fields */
+#define RCC_PLLxCFGR6_POSTDIV1_MASK GENMASK_32(2, 0)
+#define RCC_PLLxCFGR6_POSTDIV1_SHIFT 0
+
+/* RCC_PLLxCFGR7 register fields */
+#define RCC_PLLxCFGR7_POSTDIV2_MASK GENMASK_32(2, 0)
+#define RCC_PLLxCFGR7_POSTDIV2_SHIFT 0
+
+/* RCC_VERR register fields */
+#define RCC_VERR_MINREV_MASK GENMASK_32(3, 0)
+#define RCC_VERR_MINREV_SHIFT 0
+#define RCC_VERR_MAJREV_MASK GENMASK_32(7, 4)
+#define RCC_VERR_MAJREV_SHIFT 4
+
+#endif /* STM32MP2_RCC_H */
diff --git a/include/dt-bindings/clock/stm32mp25-clks.h b/include/dt-bindings/clock/stm32mp25-clks.h
new file mode 100644
index 0000000..c4ff9cf
--- /dev/null
+++ b/include/dt-bindings/clock/stm32mp25-clks.h
@@ -0,0 +1,494 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */
+/*
+ * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
+ * Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics.
+ */
+
+#ifndef _DT_BINDINGS_STM32MP25_CLKS_H_
+#define _DT_BINDINGS_STM32MP25_CLKS_H_
+
+/* INTERNAL/EXTERNAL OSCILLATORS */
+#define HSI_CK 0
+#define HSE_CK 1
+#define MSI_CK 2
+#define LSI_CK 3
+#define LSE_CK 4
+#define I2S_CK 5
+#define RTC_CK 6
+#define SPDIF_CK_SYMB 7
+
+/* PLL CLOCKS */
+#define PLL1_CK 8
+#define PLL2_CK 9
+#define PLL3_CK 10
+#define PLL4_CK 11
+#define PLL5_CK 12
+#define PLL6_CK 13
+#define PLL7_CK 14
+#define PLL8_CK 15
+
+#define CK_CPU1 16
+
+/* APB DIV CLOCKS */
+#define CK_ICN_APB1 17
+#define CK_ICN_APB2 18
+#define CK_ICN_APB3 19
+#define CK_ICN_APB4 20
+#define CK_ICN_APBDBG 21
+
+/* GLOBAL TIMER */
+#define TIMG1_CK 22
+#define TIMG2_CK 23
+
+/* FLEXGEN CLOCKS */
+#define CK_ICN_HS_MCU 24
+#define CK_ICN_SDMMC 25
+#define CK_ICN_DDR 26
+#define CK_ICN_DISPLAY 27
+#define CK_ICN_HSL 28
+#define CK_ICN_NIC 29
+#define CK_ICN_VID 30
+#define CK_FLEXGEN_07 31
+#define CK_FLEXGEN_08 32
+#define CK_FLEXGEN_09 33
+#define CK_FLEXGEN_10 34
+#define CK_FLEXGEN_11 35
+#define CK_FLEXGEN_12 36
+#define CK_FLEXGEN_13 37
+#define CK_FLEXGEN_14 38
+#define CK_FLEXGEN_15 39
+#define CK_FLEXGEN_16 40
+#define CK_FLEXGEN_17 41
+#define CK_FLEXGEN_18 42
+#define CK_FLEXGEN_19 43
+#define CK_FLEXGEN_20 44
+#define CK_FLEXGEN_21 45
+#define CK_FLEXGEN_22 46
+#define CK_FLEXGEN_23 47
+#define CK_FLEXGEN_24 48
+#define CK_FLEXGEN_25 49
+#define CK_FLEXGEN_26 50
+#define CK_FLEXGEN_27 51
+#define CK_FLEXGEN_28 52
+#define CK_FLEXGEN_29 53
+#define CK_FLEXGEN_30 54
+#define CK_FLEXGEN_31 55
+#define CK_FLEXGEN_32 56
+#define CK_FLEXGEN_33 57
+#define CK_FLEXGEN_34 58
+#define CK_FLEXGEN_35 59
+#define CK_FLEXGEN_36 60
+#define CK_FLEXGEN_37 61
+#define CK_FLEXGEN_38 62
+#define CK_FLEXGEN_39 63
+#define CK_FLEXGEN_40 64
+#define CK_FLEXGEN_41 65
+#define CK_FLEXGEN_42 66
+#define CK_FLEXGEN_43 67
+#define CK_FLEXGEN_44 68
+#define CK_FLEXGEN_45 69
+#define CK_FLEXGEN_46 70
+#define CK_FLEXGEN_47 71
+#define CK_FLEXGEN_48 72
+#define CK_FLEXGEN_49 73
+#define CK_FLEXGEN_50 74
+#define CK_FLEXGEN_51 75
+#define CK_FLEXGEN_52 76
+#define CK_FLEXGEN_53 77
+#define CK_FLEXGEN_54 78
+#define CK_FLEXGEN_55 79
+#define CK_FLEXGEN_56 80
+#define CK_FLEXGEN_57 81
+#define CK_FLEXGEN_58 82
+#define CK_FLEXGEN_59 83
+#define CK_FLEXGEN_60 84
+#define CK_FLEXGEN_61 85
+#define CK_FLEXGEN_62 86
+#define CK_FLEXGEN_63 87
+
+/* LOW SPEED MCU CLOCK */
+#define CK_ICN_LS_MCU 88
+
+#define CK_BUS_STM500 89
+#define CK_BUS_FMC 90
+#define CK_BUS_GPU 91
+#define CK_BUS_ETH1 92
+#define CK_BUS_ETH2 93
+#define CK_BUS_PCIE 94
+#define CK_BUS_DDRPHYC 95
+#define CK_BUS_SYSCPU1 96
+#define CK_BUS_ETHSW 97
+#define CK_BUS_HPDMA1 98
+#define CK_BUS_HPDMA2 99
+#define CK_BUS_HPDMA3 100
+#define CK_BUS_ADC12 101
+#define CK_BUS_ADC3 102
+#define CK_BUS_IPCC1 103
+#define CK_BUS_CCI 104
+#define CK_BUS_CRC 105
+#define CK_BUS_MDF1 106
+#define CK_BUS_OSPIIOM 107
+#define CK_BUS_BKPSRAM 108
+#define CK_BUS_HASH 109
+#define CK_BUS_RNG 110
+#define CK_BUS_CRYP1 111
+#define CK_BUS_CRYP2 112
+#define CK_BUS_SAES 113
+#define CK_BUS_PKA 114
+#define CK_BUS_GPIOA 115
+#define CK_BUS_GPIOB 116
+#define CK_BUS_GPIOC 117
+#define CK_BUS_GPIOD 118
+#define CK_BUS_GPIOE 119
+#define CK_BUS_GPIOF 120
+#define CK_BUS_GPIOG 121
+#define CK_BUS_GPIOH 122
+#define CK_BUS_GPIOI 123
+#define CK_BUS_GPIOJ 124
+#define CK_BUS_GPIOK 125
+#define CK_BUS_LPSRAM1 126
+#define CK_BUS_LPSRAM2 127
+#define CK_BUS_LPSRAM3 128
+#define CK_BUS_GPIOZ 129
+#define CK_BUS_LPDMA 130
+#define CK_BUS_HSEM 131
+#define CK_BUS_IPCC2 132
+#define CK_BUS_RTC 133
+#define CK_BUS_SPI8 134
+#define CK_BUS_LPUART1 135
+#define CK_BUS_I2C8 136
+#define CK_BUS_LPTIM3 137
+#define CK_BUS_LPTIM4 138
+#define CK_BUS_LPTIM5 139
+#define CK_BUS_IWDG5 140
+#define CK_BUS_WWDG2 141
+#define CK_BUS_I3C4 142
+#define CK_BUS_TIM2 143
+#define CK_BUS_TIM3 144
+#define CK_BUS_TIM4 145
+#define CK_BUS_TIM5 146
+#define CK_BUS_TIM6 147
+#define CK_BUS_TIM7 148
+#define CK_BUS_TIM10 149
+#define CK_BUS_TIM11 150
+#define CK_BUS_TIM12 151
+#define CK_BUS_TIM13 152
+#define CK_BUS_TIM14 153
+#define CK_BUS_LPTIM1 154
+#define CK_BUS_LPTIM2 155
+#define CK_BUS_SPI2 156
+#define CK_BUS_SPI3 157
+#define CK_BUS_SPDIFRX 158
+#define CK_BUS_USART2 159
+#define CK_BUS_USART3 160
+#define CK_BUS_UART4 161
+#define CK_BUS_UART5 162
+#define CK_BUS_I2C1 163
+#define CK_BUS_I2C2 164
+#define CK_BUS_I2C3 165
+#define CK_BUS_I2C4 166
+#define CK_BUS_I2C5 167
+#define CK_BUS_I2C6 168
+#define CK_BUS_I2C7 169
+#define CK_BUS_I3C1 170
+#define CK_BUS_I3C2 171
+#define CK_BUS_I3C3 172
+#define CK_BUS_TIM1 173
+#define CK_BUS_TIM8 174
+#define CK_BUS_TIM15 175
+#define CK_BUS_TIM16 176
+#define CK_BUS_TIM17 177
+#define CK_BUS_TIM20 178
+#define CK_BUS_SAI1 179
+#define CK_BUS_SAI2 180
+#define CK_BUS_SAI3 181
+#define CK_BUS_SAI4 182
+#define CK_BUS_USART1 183
+#define CK_BUS_USART6 184
+#define CK_BUS_UART7 185
+#define CK_BUS_UART8 186
+#define CK_BUS_UART9 187
+#define CK_BUS_FDCAN 188
+#define CK_BUS_SPI1 189
+#define CK_BUS_SPI4 190
+#define CK_BUS_SPI5 191
+#define CK_BUS_SPI6 192
+#define CK_BUS_SPI7 193
+#define CK_BUS_BSEC 194
+#define CK_BUS_IWDG1 195
+#define CK_BUS_IWDG2 196
+#define CK_BUS_IWDG3 197
+#define CK_BUS_IWDG4 198
+#define CK_BUS_WWDG1 199
+#define CK_BUS_VREF 200
+#define CK_BUS_DTS 201
+#define CK_BUS_SERC 202
+#define CK_BUS_HDP 203
+#define CK_BUS_IS2M 204
+#define CK_BUS_DSI 205
+#define CK_BUS_LTDC 206
+#define CK_BUS_CSI 207
+#define CK_BUS_DCMIPP 208
+#define CK_BUS_DDRC 209
+#define CK_BUS_DDRCFG 210
+#define CK_BUS_GICV2M 211
+#define CK_BUS_USBTC 212
+#define CK_BUS_BUSPERFM 213
+#define CK_BUS_USB3PCIEPHY 214
+#define CK_BUS_STGEN 215
+#define CK_BUS_VDEC 216
+#define CK_BUS_VENC 217
+#define CK_SYSDBG 218
+#define CK_KER_TIM2 219
+#define CK_KER_TIM3 220
+#define CK_KER_TIM4 221
+#define CK_KER_TIM5 222
+#define CK_KER_TIM6 223
+#define CK_KER_TIM7 224
+#define CK_KER_TIM10 225
+#define CK_KER_TIM11 226
+#define CK_KER_TIM12 227
+#define CK_KER_TIM13 228
+#define CK_KER_TIM14 229
+#define CK_KER_TIM1 230
+#define CK_KER_TIM8 231
+#define CK_KER_TIM15 232
+#define CK_KER_TIM16 233
+#define CK_KER_TIM17 234
+#define CK_KER_TIM20 235
+#define CK_BUS_SYSRAM 236
+#define CK_BUS_VDERAM 237
+#define CK_BUS_RETRAM 238
+#define CK_BUS_OSPI1 239
+#define CK_BUS_OSPI2 240
+#define CK_BUS_OTFD1 241
+#define CK_BUS_OTFD2 242
+#define CK_BUS_SRAM1 243
+#define CK_BUS_SRAM2 244
+#define CK_BUS_SDMMC1 245
+#define CK_BUS_SDMMC2 246
+#define CK_BUS_SDMMC3 247
+#define CK_BUS_DDR 248
+#define CK_BUS_RISAF4 249
+#define CK_BUS_USB2OHCI 250
+#define CK_BUS_USB2EHCI 251
+#define CK_BUS_USB3DRD 252
+#define CK_KER_LPTIM1 253
+#define CK_KER_LPTIM2 254
+#define CK_KER_USART2 255
+#define CK_KER_UART4 256
+#define CK_KER_USART3 257
+#define CK_KER_UART5 258
+#define CK_KER_SPI2 259
+#define CK_KER_SPI3 260
+#define CK_KER_SPDIFRX 261
+#define CK_KER_I2C1 262
+#define CK_KER_I2C2 263
+#define CK_KER_I3C1 264
+#define CK_KER_I3C2 265
+#define CK_KER_I2C3 266
+#define CK_KER_I2C5 267
+#define CK_KER_I3C3 268
+#define CK_KER_I2C4 269
+#define CK_KER_I2C6 270
+#define CK_KER_I2C7 271
+#define CK_KER_SPI1 272
+#define CK_KER_SPI4 273
+#define CK_KER_SPI5 274
+#define CK_KER_SPI6 275
+#define CK_KER_SPI7 276
+#define CK_KER_USART1 277
+#define CK_KER_USART6 278
+#define CK_KER_UART7 279
+#define CK_KER_UART8 280
+#define CK_KER_UART9 281
+#define CK_KER_MDF1 282
+#define CK_KER_SAI1 283
+#define CK_KER_SAI2 284
+#define CK_KER_SAI3 285
+#define CK_KER_SAI4 286
+#define CK_KER_FDCAN 287
+#define CK_KER_DSIBLANE 288
+#define CK_KER_DSIPHY 289
+#define CK_KER_CSI 290
+#define CK_KER_CSITXESC 291
+#define CK_KER_CSIPHY 292
+#define CK_KER_LVDSPHY 293
+#define CK_KER_STGEN 294
+#define CK_KER_USB3PCIEPHY 295
+#define CK_KER_USB2PHY2EN 296
+#define CK_KER_I3C4 297
+#define CK_KER_SPI8 298
+#define CK_KER_I2C8 299
+#define CK_KER_LPUART1 300
+#define CK_KER_LPTIM3 301
+#define CK_KER_LPTIM4 302
+#define CK_KER_LPTIM5 303
+#define CK_KER_TSDBG 304
+#define CK_KER_TPIU 305
+#define CK_BUS_ETR 306
+#define CK_BUS_SYSATB 307
+#define CK_KER_ADC12 308
+#define CK_KER_ADC3 309
+#define CK_KER_OSPI1 310
+#define CK_KER_OSPI2 311
+#define CK_KER_FMC 312
+#define CK_KER_SDMMC1 313
+#define CK_KER_SDMMC2 314
+#define CK_KER_SDMMC3 315
+#define CK_KER_ETH1 316
+#define CK_KER_ETH2 317
+#define CK_KER_ETH1PTP 318
+#define CK_KER_ETH2PTP 319
+#define CK_KER_USB2PHY1 320
+#define CK_KER_USB2PHY2 321
+#define CK_KER_ETHSW 322
+#define CK_KER_ETHSWREF 323
+#define CK_MCO1 324
+#define CK_MCO2 325
+#define CK_KER_DTS 326
+#define CK_ETH1_RX 327
+#define CK_ETH1_TX 328
+#define CK_ETH1_MAC 329
+#define CK_ETH2_RX 330
+#define CK_ETH2_TX 331
+#define CK_ETH2_MAC 332
+#define CK_ETH1_STP 333
+#define CK_ETH2_STP 334
+#define CK_KER_USBTC 335
+#define CK_BUS_ADF1 336
+#define CK_KER_ADF1 337
+#define CK_BUS_LVDS 338
+#define CK_KER_LTDC 339
+#define CK_KER_GPU 340
+#define CK_BUS_ETHSWACMCFG 341
+#define CK_BUS_ETHSWACMMSG 342
+#define HSE_DIV2_CK 343
+
+#define STM32MP25_LAST_CLK 344
+
+#define CK_SCMI_ICN_HS_MCU 0
+#define CK_SCMI_ICN_SDMMC 1
+#define CK_SCMI_ICN_DDR 2
+#define CK_SCMI_ICN_DISPLAY 3
+#define CK_SCMI_ICN_HSL 4
+#define CK_SCMI_ICN_NIC 5
+#define CK_SCMI_ICN_VID 6
+#define CK_SCMI_FLEXGEN_07 7
+#define CK_SCMI_FLEXGEN_08 8
+#define CK_SCMI_FLEXGEN_09 9
+#define CK_SCMI_FLEXGEN_10 10
+#define CK_SCMI_FLEXGEN_11 11
+#define CK_SCMI_FLEXGEN_12 12
+#define CK_SCMI_FLEXGEN_13 13
+#define CK_SCMI_FLEXGEN_14 14
+#define CK_SCMI_FLEXGEN_15 15
+#define CK_SCMI_FLEXGEN_16 16
+#define CK_SCMI_FLEXGEN_17 17
+#define CK_SCMI_FLEXGEN_18 18
+#define CK_SCMI_FLEXGEN_19 19
+#define CK_SCMI_FLEXGEN_20 20
+#define CK_SCMI_FLEXGEN_21 21
+#define CK_SCMI_FLEXGEN_22 22
+#define CK_SCMI_FLEXGEN_23 23
+#define CK_SCMI_FLEXGEN_24 24
+#define CK_SCMI_FLEXGEN_25 25
+#define CK_SCMI_FLEXGEN_26 26
+#define CK_SCMI_FLEXGEN_27 27
+#define CK_SCMI_FLEXGEN_28 28
+#define CK_SCMI_FLEXGEN_29 29
+#define CK_SCMI_FLEXGEN_30 30
+#define CK_SCMI_FLEXGEN_31 31
+#define CK_SCMI_FLEXGEN_32 32
+#define CK_SCMI_FLEXGEN_33 33
+#define CK_SCMI_FLEXGEN_34 34
+#define CK_SCMI_FLEXGEN_35 35
+#define CK_SCMI_FLEXGEN_36 36
+#define CK_SCMI_FLEXGEN_37 37
+#define CK_SCMI_FLEXGEN_38 38
+#define CK_SCMI_FLEXGEN_39 39
+#define CK_SCMI_FLEXGEN_40 40
+#define CK_SCMI_FLEXGEN_41 41
+#define CK_SCMI_FLEXGEN_42 42
+#define CK_SCMI_FLEXGEN_43 43
+#define CK_SCMI_FLEXGEN_44 44
+#define CK_SCMI_FLEXGEN_45 45
+#define CK_SCMI_FLEXGEN_46 46
+#define CK_SCMI_FLEXGEN_47 47
+#define CK_SCMI_FLEXGEN_48 48
+#define CK_SCMI_FLEXGEN_49 49
+#define CK_SCMI_FLEXGEN_50 50
+#define CK_SCMI_FLEXGEN_51 51
+#define CK_SCMI_FLEXGEN_52 52
+#define CK_SCMI_FLEXGEN_53 53
+#define CK_SCMI_FLEXGEN_54 54
+#define CK_SCMI_FLEXGEN_55 55
+#define CK_SCMI_FLEXGEN_56 56
+#define CK_SCMI_FLEXGEN_57 57
+#define CK_SCMI_FLEXGEN_58 58
+#define CK_SCMI_FLEXGEN_59 59
+#define CK_SCMI_FLEXGEN_60 60
+#define CK_SCMI_FLEXGEN_61 61
+#define CK_SCMI_FLEXGEN_62 62
+#define CK_SCMI_FLEXGEN_63 63
+#define CK_SCMI_ICN_LS_MCU 64
+#define CK_SCMI_HSE 65
+#define CK_SCMI_LSE 66
+#define CK_SCMI_HSI 67
+#define CK_SCMI_LSI 68
+#define CK_SCMI_MSI 69
+#define CK_SCMI_HSE_DIV2 70
+#define CK_SCMI_CPU1 71
+#define CK_SCMI_SYSCPU1 72
+#define CK_SCMI_PLL2 73
+#define CK_SCMI_PLL3 74
+#define CK_SCMI_RTC 75
+#define CK_SCMI_RTCCK 76
+#define CK_SCMI_ICN_APB1 77
+#define CK_SCMI_ICN_APB2 78
+#define CK_SCMI_ICN_APB3 79
+#define CK_SCMI_ICN_APB4 80
+#define CK_SCMI_ICN_APBDBG 81
+#define CK_SCMI_TIMG1 82
+#define CK_SCMI_TIMG2 83
+#define CK_SCMI_BKPSRAM 84
+#define CK_SCMI_BSEC 85
+#define CK_SCMI_BUSPERFM 86
+#define CK_SCMI_ETR 87
+#define CK_SCMI_FMC 88
+#define CK_SCMI_GPIOA 89
+#define CK_SCMI_GPIOB 90
+#define CK_SCMI_GPIOC 91
+#define CK_SCMI_GPIOD 92
+#define CK_SCMI_GPIOE 93
+#define CK_SCMI_GPIOF 94
+#define CK_SCMI_GPIOG 95
+#define CK_SCMI_GPIOH 96
+#define CK_SCMI_GPIOI 97
+#define CK_SCMI_GPIOJ 98
+#define CK_SCMI_GPIOK 99
+#define CK_SCMI_GPIOZ 100
+#define CK_SCMI_HPDMA1 101
+#define CK_SCMI_HPDMA2 102
+#define CK_SCMI_HPDMA3 103
+#define CK_SCMI_HSEM 104
+#define CK_SCMI_IPCC1 105
+#define CK_SCMI_IPCC2 106
+#define CK_SCMI_LPDMA 107
+#define CK_SCMI_RETRAM 108
+#define CK_SCMI_SRAM1 109
+#define CK_SCMI_SRAM2 110
+#define CK_SCMI_LPSRAM1 111
+#define CK_SCMI_LPSRAM2 112
+#define CK_SCMI_LPSRAM3 113
+#define CK_SCMI_VDERAM 114
+#define CK_SCMI_SYSRAM 115
+#define CK_SCMI_OSPI1 116
+#define CK_SCMI_OSPI2 117
+#define CK_SCMI_TPIU 118
+#define CK_SCMI_SYSDBG 119
+#define CK_SCMI_SYSATB 120
+#define CK_SCMI_TSDBG 121
+#define CK_SCMI_STM500 122
+
+#endif /* _DT_BINDINGS_STM32MP25_CLKS_H_ */
diff --git a/include/dt-bindings/clock/stm32mp25-clksrc.h b/include/dt-bindings/clock/stm32mp25-clksrc.h
new file mode 100644
index 0000000..e6f7154
--- /dev/null
+++ b/include/dt-bindings/clock/stm32mp25-clksrc.h
@@ -0,0 +1,226 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause */
+/*
+ * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_STM32MP25_CLKSRC_H_
+#define _DT_BINDINGS_CLOCK_STM32MP25_CLKSRC_H_
+
+#define CMD_DIV 0
+#define CMD_MUX 1
+#define CMD_CLK 2
+#define CMD_FLEXGEN 3
+
+#define CMD_ADDR_BIT 0x80000000
+
+#define CMD_SHIFT 26
+#define CMD_MASK 0xFC000000
+#define CMD_DATA_MASK 0x03FFFFFF
+
+#define DIV_ID_SHIFT 8
+#define DIV_ID_MASK 0x0000FF00
+
+#define DIV_DIVN_SHIFT 0
+#define DIV_DIVN_MASK 0x000000FF
+
+#define MUX_ID_SHIFT 4
+#define MUX_ID_MASK 0x00000FF0
+
+#define MUX_SEL_SHIFT 0
+#define MUX_SEL_MASK 0x0000000F
+
+/* CLK define */
+#define CLK_ON_MASK BIT(21)
+#define CLK_ON_SHIFT 21
+
+#define CLK_ID_MASK GENMASK_32(20, 12)
+#define CLK_ID_SHIFT 12
+
+#define CLK_NO_DIV_MASK 0x0000080
+#define CLK_DIV_MASK GENMASK_32(10, 5)
+#define CLK_DIV_SHIFT 5
+
+#define CLK_NO_SEL_MASK 0x00000010
+#define CLK_SEL_MASK GENMASK_32(3, 0)
+#define CLK_SEL_SHIFT 0
+
+#define CLK_CFG(clk_id, sel, div, state) ((CMD_CLK << CMD_SHIFT) |\
+ ((state) << CLK_ON_SHIFT) |\
+ ((clk_id) << CLK_ID_SHIFT) |\
+ ((div) << CLK_DIV_SHIFT) |\
+ ((sel) << CLK_SEL_SHIFT))
+
+#define CLK_OFF 0
+#define CLK_ON 1
+#define CLK_NODIV 0x00000040
+#define CLK_NOMUX 0x00000010
+
+/* Flexgen define */
+#define FLEX_ID_SHIFT 13
+#define FLEX_SEL_SHIFT 9
+#define FLEX_PDIV_SHIFT 6
+#define FLEX_FDIV_SHIFT 0
+
+#define FLEX_ID_MASK GENMASK_32(18, 13)
+#define FLEX_SEL_MASK GENMASK_32(12, 9)
+#define FLEX_PDIV_MASK GENMASK_32(8, 6)
+#define FLEX_FDIV_MASK GENMASK_32(5, 0)
+
+#define DIV_CFG(div_id, div) ((CMD_DIV << CMD_SHIFT) |\
+ ((div_id) << DIV_ID_SHIFT |\
+ (div)))
+
+#define MUX_CFG(mux_id, sel) ((CMD_MUX << CMD_SHIFT) |\
+ ((mux_id) << MUX_ID_SHIFT |\
+ (sel)))
+
+#define CLK_ADDR_SHIFT 16
+#define CLK_ADDR_MASK 0x7FFF0000
+#define CLK_ADDR_VAL_MASK 0xFFFF
+
+#define DIV_LSMCU 0
+#define DIV_APB1 1
+#define DIV_APB2 2
+#define DIV_APB3 3
+#define DIV_APB4 4
+#define DIV_APBDBG 5
+#define DIV_RTC 6
+#define DIV_NB 7
+
+#define MUX_MUXSEL0 0
+#define MUX_MUXSEL1 1
+#define MUX_MUXSEL2 2
+#define MUX_MUXSEL3 3
+#define MUX_MUXSEL4 4
+#define MUX_MUXSEL5 5
+#define MUX_MUXSEL6 6
+#define MUX_MUXSEL7 7
+#define MUX_XBARSEL 8
+#define MUX_RTC 9
+#define MUX_MCO1 10
+#define MUX_MCO2 11
+#define MUX_ADC12 12
+#define MUX_ADC3 13
+#define MUX_USB2PHY1 14
+#define MUX_USB2PHY2 15
+#define MUX_USB3PCIEPHY 16
+#define MUX_DSIBLANE 17
+#define MUX_DSIPHY 18
+#define MUX_LVDSPHY 19
+#define MUX_DTS 20
+#define MUX_CPU1 21
+#define MUX_D3PER 22
+#define MUX_NB 23
+
+#define MUXSEL_HSI 0
+#define MUXSEL_HSE 1
+#define MUXSEL_MSI 2
+
+/* KERNEL source clocks */
+#define MUX_RTC_DISABLED 0x0
+#define MUX_RTC_LSE 0x1
+#define MUX_RTC_LSI 0x2
+#define MUX_RTC_HSE 0x3
+
+#define MUX_MCO1_FLEX61 0x0
+#define MUX_MCO1_OBSER0 0x1
+
+#define MUX_MCO2_FLEX62 0x0
+#define MUX_MCO2_OBSER1 0x1
+
+#define MUX_ADC12_FLEX46 0x0
+#define MUX_ADC12_LSMCU 0x1
+
+#define MUX_ADC3_FLEX47 0x0
+#define MUX_ADC3_LSMCU 0x1
+#define MUX_ADC3_FLEX46 0x2
+
+#define MUX_USB2PHY1_FLEX57 0x0
+#define MUX_USB2PHY1_HSE 0x1
+
+#define MUX_USB2PHY2_FLEX58 0x0
+#define MUX_USB2PHY2_HSE 0x1
+
+#define MUX_USB3PCIEPHY_FLEX34 0x0
+#define MUX_USB3PCIEPHY_HSE 0x1
+
+#define MUX_DSIBLANE_FLEX28 0x0
+#define MUX_DSIBLANE_FLEX27 0x1
+
+#define MUX_DSIPHY_FLEX28 0x0
+#define MUX_DSIPHY_HSE 0x1
+
+#define MUX_LVDSPHY_FLEX32 0x0
+#define MUX_LVDSPHY_HSE 0x1
+
+#define MUX_DTS_HSI 0x0
+#define MUX_DTS_HSE 0x1
+#define MUX_DTS_MSI 0x2
+
+#define MUX_D3PER_MSI 0x0
+#define MUX_D3PER_LSI 0x1
+#define MUX_D3PER_LSE 0x2
+
+/* PLLs source clocks */
+#define PLL_SRC_HSI 0x0
+#define PLL_SRC_HSE 0x1
+#define PLL_SRC_MSI 0x2
+#define PLL_SRC_DISABLED 0x3
+
+/* XBAR source clocks */
+#define XBAR_SRC_PLL4 0x0
+#define XBAR_SRC_PLL5 0x1
+#define XBAR_SRC_PLL6 0x2
+#define XBAR_SRC_PLL7 0x3
+#define XBAR_SRC_PLL8 0x4
+#define XBAR_SRC_HSI 0x5
+#define XBAR_SRC_HSE 0x6
+#define XBAR_SRC_MSI 0x7
+#define XBAR_SRC_HSI_KER 0x8
+#define XBAR_SRC_HSE_KER 0x9
+#define XBAR_SRC_MSI_KER 0xA
+#define XBAR_SRC_SPDIF_SYMB 0xB
+#define XBAR_SRC_I2S 0xC
+#define XBAR_SRC_LSI 0xD
+#define XBAR_SRC_LSE 0xE
+
+/*
+ * Configure a XBAR channel with its clock source
+ * channel_nb: XBAR channel number from 0 to 63
+ * channel_src: one of the 15 previous XBAR source clocks defines
+ * channel_prediv: value of the PREDIV in channel RCC_PREDIVxCFGR register
+ * can be either 1, 2, 4 or 1024
+ * channel_findiv: value of the FINDIV in channel RCC_FINDIVxCFGR register
+ * from 1 to 64
+ */
+
+#define FLEXGEN_CFG(ch, sel, pdiv, fdiv) ((CMD_FLEXGEN << CMD_SHIFT) |\
+ ((ch) << FLEX_ID_SHIFT) |\
+ ((sel) << FLEX_SEL_SHIFT) |\
+ ((pdiv) << FLEX_PDIV_SHIFT) |\
+ ((fdiv) << FLEX_FDIV_SHIFT))
+
+/* Register addresses of MCO1 & MCO2 */
+#define MCO1 0x494
+#define MCO2 0x498
+
+#define MCO_OFF 0
+#define MCO_ON 1
+#define MCO_STATUS_SHIFT 8
+
+#define MCO_CFG(addr, sel, status) (CMD_ADDR_BIT |\
+ ((addr) << CLK_ADDR_SHIFT) |\
+ ((status) << MCO_STATUS_SHIFT) |\
+ (sel))
+
+/* define for st,pll /csg */
+#define SSCG_MODE_CENTER_SPREAD 0
+#define SSCG_MODE_DOWN_SPREAD 1
+
+/* define for st,drive */
+#define LSEDRV_LOWEST 0
+#define LSEDRV_MEDIUM_LOW 1
+#define LSEDRV_MEDIUM_HIGH 2
+#define LSEDRV_HIGHEST 3
+
+#endif /* _DT_BINDINGS_CLOCK_STM32MP25_CLKSRC_H_ */
diff --git a/include/dt-bindings/reset/stm32mp25-resets.h b/include/dt-bindings/reset/stm32mp25-resets.h
new file mode 100644
index 0000000..c34fe2a
--- /dev/null
+++ b/include/dt-bindings/reset/stm32mp25-resets.h
@@ -0,0 +1,164 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later or BSD-3-Clause */
+/*
+ * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
+ * Author(s): Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics.
+ */
+
+#ifndef _DT_BINDINGS_STM32MP25_RESET_H_
+#define _DT_BINDINGS_STM32MP25_RESET_H_
+
+#define SYS_R 8192
+#define C1_R 8224
+#define C1P1POR_R 8256
+#define C1P1_R 8257
+#define C2_R 8288
+#define C2_HOLDBOOT_R 8608
+#define C1_HOLDBOOT_R 8609
+#define VSW_R 8703
+#define C1MS_R 8808
+#define IWDG2_KER_R 9074
+#define IWDG4_KER_R 9202
+#define C3_R 9312
+#define DDRCP_R 9856
+#define DDRCAPB_R 9888
+#define DDRPHYCAPB_R 9920
+#define DDRCFG_R 9984
+#define DDR_R 10016
+#define OSPI1_R 10400
+#define OSPI1DLL_R 10416
+#define OSPI2_R 10432
+#define OSPI2DLL_R 10448
+#define FMC_R 10464
+#define DBG_R 10508
+#define GPIOA_R 10592
+#define GPIOB_R 10624
+#define GPIOC_R 10656
+#define GPIOD_R 10688
+#define GPIOE_R 10720
+#define GPIOF_R 10752
+#define GPIOG_R 10784
+#define GPIOH_R 10816
+#define GPIOI_R 10848
+#define GPIOJ_R 10880
+#define GPIOK_R 10912
+#define GPIOZ_R 10944
+#define HPDMA1_R 10976
+#define HPDMA2_R 11008
+#define HPDMA3_R 11040
+#define LPDMA_R 11072
+#define HSEM_R 11104
+#define IPCC1_R 11136
+#define IPCC2_R 11168
+#define IS2M_R 11360
+#define SSMOD_R 11392
+#define TIM1_R 14336
+#define TIM2_R 14368
+#define TIM3_R 14400
+#define TIM4_R 14432
+#define TIM5_R 14464
+#define TIM6_R 14496
+#define TIM7_R 14528
+#define TIM8_R 14560
+#define TIM10_R 14592
+#define TIM11_R 14624
+#define TIM12_R 14656
+#define TIM13_R 14688
+#define TIM14_R 14720
+#define TIM15_R 14752
+#define TIM16_R 14784
+#define TIM17_R 14816
+#define TIM20_R 14848
+#define LPTIM1_R 14880
+#define LPTIM2_R 14912
+#define LPTIM3_R 14944
+#define LPTIM4_R 14976
+#define LPTIM5_R 15008
+#define SPI1_R 15040
+#define SPI2_R 15072
+#define SPI3_R 15104
+#define SPI4_R 15136
+#define SPI5_R 15168
+#define SPI6_R 15200
+#define SPI7_R 15232
+#define SPI8_R 15264
+#define SPDIFRX_R 15296
+#define USART1_R 15328
+#define USART2_R 15360
+#define USART3_R 15392
+#define UART4_R 15424
+#define UART5_R 15456
+#define USART6_R 15488
+#define UART7_R 15520
+#define UART8_R 15552
+#define UART9_R 15584
+#define LPUART1_R 15616
+#define I2C1_R 15648
+#define I2C2_R 15680
+#define I2C3_R 15712
+#define I2C4_R 15744
+#define I2C5_R 15776
+#define I2C6_R 15808
+#define I2C7_R 15840
+#define I2C8_R 15872
+#define SAI1_R 15904
+#define SAI2_R 15936
+#define SAI3_R 15968
+#define SAI4_R 16000
+#define MDF1_R 16064
+#define MDF2_R 16096
+#define FDCAN_R 16128
+#define HDP_R 16160
+#define ADC12_R 16192
+#define ADC3_R 16224
+#define ETH1_R 16256
+#define ETH2_R 16288
+#define USB2_R 16352
+#define USB2PHY1_R 16384
+#define USB2PHY2_R 16416
+#define USB3DRD_R 16448
+#define USB3PCIEPHY_R 16480
+#define PCIE_R 16512
+#define USBTC_R 16544
+#define ETHSW_R 16576
+#define SDMMC1_R 16768
+#define SDMMC1DLL_R 16784
+#define SDMMC2_R 16800
+#define SDMMC2DLL_R 16816
+#define SDMMC3_R 16832
+#define SDMMC3DLL_R 16848
+#define GPU_R 16864
+#define LTDC_R 16896
+#define DSI_R 16928
+#define LVDS_R 17024
+#define CSI_R 17088
+#define DCMIPP_R 17120
+#define CCI_R 17152
+#define VDEC_R 17184
+#define VENC_R 17216
+#define RNG_R 17280
+#define PKA_R 17312
+#define SAES_R 17344
+#define HASH_R 17376
+#define CRYP1_R 17408
+#define CRYP2_R 17440
+#define WWDG1_R 17632
+#define WWDG2_R 17664
+#define BUSPERFM_R 17696
+#define VREF_R 17728
+#define DTS_R 17760
+#define CRC_R 17824
+#define SERC_R 17856
+#define OSPIIOM_R 17888
+#define I3C1_R 17984
+#define I3C2_R 18016
+#define I3C3_R 18048
+#define I3C4_R 18080
+
+#define RST_SCMI_C1_R 0
+#define RST_SCMI_C2_R 1
+#define RST_SCMI_C1_HOLDBOOT_R 2
+#define RST_SCMI_C2_HOLDBOOT_R 3
+#define RST_SCMI_FMC 4
+#define RST_SCMI_PCIE 5
+
+#endif /* _DT_BINDINGS_STM32MP25_RESET_H_ */
diff --git a/include/lib/bootmarker_capture.h b/include/lib/bootmarker_capture.h
new file mode 100644
index 0000000..31fe048
--- /dev/null
+++ b/include/lib/bootmarker_capture.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2023, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef BOOTMARKER_CAPTURE_H
+#define BOOTMARKER_CAPTURE_H
+
+#define BL1_ENTRY U(0)
+#define BL1_EXIT U(1)
+#define BL2_ENTRY U(2)
+#define BL2_EXIT U(3)
+#define BL31_ENTRY U(4)
+#define BL31_EXIT U(5)
+#define BL_TOTAL_IDS U(6)
+
+#ifdef __ASSEMBLER__
+PMF_DECLARE_CAPTURE_TIMESTAMP(bl_svc)
+#endif /*__ASSEMBLER__*/
+
+#endif /*BOOTMARKER_CAPTURE_H*/
diff --git a/include/lib/cpus/aarch64/cortex_x3.h b/include/lib/cpus/aarch64/cortex_x3.h
index ceafe66..e648734 100644
--- a/include/lib/cpus/aarch64/cortex_x3.h
+++ b/include/lib/cpus/aarch64/cortex_x3.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -31,4 +31,11 @@
#define CORTEX_X3_CPUACTLR2_EL1 S3_0_C15_C1_1
#define CORTEX_X3_CPUACTLR2_EL1_BIT_36 (ULL(1) << 36)
+/*******************************************************************************
+ * CPU Auxiliary Control register 5 specific definitions.
+ ******************************************************************************/
+#define CORTEX_X3_CPUACTLR5_EL1 S3_0_C15_C8_0
+#define CORTEX_X3_CPUACTLR5_EL1_BIT_55 (ULL(1) << 55)
+#define CORTEX_X3_CPUACTLR5_EL1_BIT_56 (ULL(1) << 56)
+
#endif /* CORTEX_X3_H */
diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h
index 9426ac7..0ab0e82 100644
--- a/include/plat/arm/common/arm_def.h
+++ b/include/plat/arm/common/arm_def.h
@@ -593,15 +593,15 @@
* As the BL31 image size appears to be increased when built with the ENABLE_PIE
* option, set BL2 base address to have enough space for BL31 in Trusted SRAM.
*/
-#define BL2_BASE (ARM_TRUSTED_SRAM_BASE + \
- (PLAT_ARM_TRUSTED_SRAM_SIZE >> 1) + \
- 0x3000)
+#define BL2_OFFSET (0x5000)
#else
/* Put BL2 towards the middle of the Trusted SRAM */
-#define BL2_BASE (ARM_TRUSTED_SRAM_BASE + \
- (PLAT_ARM_TRUSTED_SRAM_SIZE >> 1) + \
- 0x2000)
+#define BL2_OFFSET (0x2000)
#endif /* ENABLE_PIE */
+
+#define BL2_BASE (ARM_TRUSTED_SRAM_BASE + \
+ (PLAT_ARM_TRUSTED_SRAM_SIZE >> 1) + \
+ BL2_OFFSET)
#define BL2_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
#else
diff --git a/include/plat/arm/common/plat_arm.h b/include/plat/arm/common/plat_arm.h
index e8461f5..2fdbfb7 100644
--- a/include/plat/arm/common/plat_arm.h
+++ b/include/plat/arm/common/plat_arm.h
@@ -39,6 +39,20 @@
* - Region 1 with secure access only;
* - the remaining DRAM regions access from the given Non-Secure masters.
******************************************************************************/
+
+#if ENABLE_RME
+#define ARM_TZC_RME_REGIONS_DEF \
+ {ARM_AP_TZC_DRAM1_BASE, ARM_AP_TZC_DRAM1_END, TZC_REGION_S_RDWR, 0},\
+ {ARM_EL3_TZC_DRAM1_BASE, ARM_L1_GPT_END, TZC_REGION_S_RDWR, 0}, \
+ {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \
+ PLAT_ARM_TZC_NS_DEV_ACCESS}, \
+ /* Realm and Shared area share the same PAS */ \
+ {ARM_REALM_BASE, ARM_EL3_RMM_SHARED_END, ARM_TZC_NS_DRAM_S_ACCESS, \
+ PLAT_ARM_TZC_NS_DEV_ACCESS}, \
+ {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \
+ PLAT_ARM_TZC_NS_DEV_ACCESS}
+#endif
+
#if SPM_MM
#define ARM_TZC_REGIONS_DEF \
{ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END + ARM_L1_GPT_SIZE,\
@@ -52,16 +66,16 @@
PLAT_ARM_TZC_NS_DEV_ACCESS}
#elif ENABLE_RME
-#define ARM_TZC_REGIONS_DEF \
- {ARM_AP_TZC_DRAM1_BASE, ARM_AP_TZC_DRAM1_END, TZC_REGION_S_RDWR, 0},\
- {ARM_EL3_TZC_DRAM1_BASE, ARM_L1_GPT_END, TZC_REGION_S_RDWR, 0}, \
- {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \
- PLAT_ARM_TZC_NS_DEV_ACCESS}, \
- /* Realm and Shared area share the same PAS */ \
- {ARM_REALM_BASE, ARM_EL3_RMM_SHARED_END, ARM_TZC_NS_DRAM_S_ACCESS, \
- PLAT_ARM_TZC_NS_DEV_ACCESS}, \
- {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \
- PLAT_ARM_TZC_NS_DEV_ACCESS}
+#if (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd)) && \
+MEASURED_BOOT
+#define ARM_TZC_REGIONS_DEF \
+ ARM_TZC_RME_REGIONS_DEF, \
+ {ARM_EVENT_LOG_DRAM1_BASE, ARM_EVENT_LOG_DRAM1_END, \
+ TZC_REGION_S_RDWR, 0}
+#else
+#define ARM_TZC_REGIONS_DEF \
+ ARM_TZC_RME_REGIONS_DEF
+#endif
#else
#define ARM_TZC_REGIONS_DEF \
diff --git a/lib/cpus/aarch64/cortex_x3.S b/lib/cpus/aarch64/cortex_x3.S
index c781d38..98d148e 100644
--- a/lib/cpus/aarch64/cortex_x3.S
+++ b/lib/cpus/aarch64/cortex_x3.S
@@ -42,6 +42,14 @@
check_erratum_ls cortex_x3, ERRATUM(2615812), CPU_REV(1, 1)
+workaround_reset_start cortex_x3, ERRATUM(2742421), ERRATA_X3_2742421
+ /* Set CPUACTLR5_EL1[56:55] to 2'b01 */
+ sysreg_bit_set CORTEX_X3_CPUACTLR5_EL1, CORTEX_X3_CPUACTLR5_EL1_BIT_55
+ sysreg_bit_clear CORTEX_X3_CPUACTLR5_EL1, CORTEX_X3_CPUACTLR5_EL1_BIT_56
+workaround_reset_end cortex_x3, ERRATUM(2742421)
+
+check_erratum_ls cortex_x3, ERRATUM(2742421), CPU_REV(1, 1)
+
workaround_reset_start cortex_x3, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
#if IMAGE_BL31
override_vector_table wa_cve_vbar_cortex_x3
diff --git a/lib/cpus/aarch64/neoverse_n2.S b/lib/cpus/aarch64/neoverse_n2.S
index acf8dee..ead3908 100644
--- a/lib/cpus/aarch64/neoverse_n2.S
+++ b/lib/cpus/aarch64/neoverse_n2.S
@@ -68,6 +68,22 @@
check_erratum_ls neoverse_n2, ERRATUM(2067956), CPU_REV(0, 0)
+workaround_runtime_start neoverse_n2, ERRATUM(2009478), ERRATA_N2_2009478
+ /* Stash ERRSELR_EL1 in x2 */
+ mrs x2, ERRSELR_EL1
+
+ /* Select error record 0 and clear ED bit */
+ msr ERRSELR_EL1, xzr
+ mrs x1, ERXCTLR_EL1
+ bfi x1, xzr, #ERXCTLR_ED_SHIFT, #1
+ msr ERXCTLR_EL1, x1
+
+ /* Restore ERRSELR_EL1 from x2 */
+ msr ERRSELR_EL1, x2
+workaround_runtime_end neoverse_n2, ERRATUM(2009478), NO_ISB
+
+check_erratum_ls neoverse_n2, ERRATUM(2009478), CPU_REV(0, 0)
+
workaround_reset_start neoverse_n2, ERRATUM(2138953), ERRATA_N2_2138953
/* Apply instruction patching sequence */
mrs x1, NEOVERSE_N2_CPUECTLR2_EL1
@@ -233,7 +249,9 @@
func neoverse_n2_core_pwr_dwn
- apply_erratum neoverse_n2, ERRATUM(2326639), ERRATA_N2_2326639
+ apply_erratum neoverse_n2, ERRATUM(2009478), ERRATA_N2_2009478
+ apply_erratum neoverse_n2, ERRATUM(2326639), ERRATA_N2_2326639, NO_GET_CPU_REV
+
/* ---------------------------------------------------
* Enable CPU power down bit in power control register
* No need to do cache maintenance here.
diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index 8df0a29..0d8f4d4 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -615,6 +615,10 @@
# to revisions r0p0 of the Neoverse-N2 cpu and is fixed in r0p1.
CPU_FLAG_LIST += ERRATA_N2_2002655
+# Flag to apply erratum 2009478 workaround during powerdown. This erratum
+# applies to revision r0p0 of the Neoverse N2 cpu, it is fixed in r0p1.
+CPU_FLAG_LIST += ERRATA_N2_2009478
+
# Flag to apply erratum 2067956 workaround during reset. This erratum applies
# to revision r0p0 of the Neoverse N2 cpu and is fixed in r0p1.
CPU_FLAG_LIST += ERRATA_N2_2067956
@@ -738,6 +742,10 @@
# to revisions r0p0, r1p0, r1p1 of the Cortex-X3 cpu, it is still open.
CPU_FLAG_LIST += ERRATA_X3_2615812
+# Flag to apply erratum 2742421 workaround on reset. This erratum applies
+# to revisions r0p0, r1p0 and r1p1 of the Cortex-X3 cpu, it is fixed in r1p2.
+CPU_FLAG_LIST += ERRATA_X3_2742421
+
# Flag to apply erratum 1922240 workaround during reset. This erratum applies
# to revision r0p0 of the Cortex-A510 cpu and is fixed in r0p1.
CPU_FLAG_LIST += ERRATA_A510_1922240
diff --git a/make_helpers/arch_features.mk b/make_helpers/arch_features.mk
index b799697..5cd89f0 100644
--- a/make_helpers/arch_features.mk
+++ b/make_helpers/arch_features.mk
@@ -1,41 +1,324 @@
#
-# Copyright (c) 2022, Arm Limited. All rights reserved.
+# Copyright (c) 2022-2023, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
-# This file lists all the checks related to the Architectural Feature
-# Enablement flags, based on the Architectural version.
+# This file lists all of the architectural features, and initializes
+# and enables them based on the configured architecture version.
+
+# This file follows the following format:
+# - By default disable any mandatory features.
+# - Then Enable mandatory feature if applicable to an Arch Version.
+# - Disable or enable any optional feature this would be enabled/disabled if needed by platform.
+
+#
+################################################################################
+# Set mandatory features by default to zero.
+################################################################################
+#
+
+#----
+# 8.1
+#----
+
+# Flag to enable access to Privileged Access Never bit of PSTATE.
+ENABLE_FEAT_PAN := 0
+
+# Flag to enable Virtualization Host Extensions.
+ENABLE_FEAT_VHE := 0
+
+#----
+# 8.2
+#----
+
+# Enable RAS Support.
+ENABLE_FEAT_RAS := 0
+
+#----
+# 8.3
+#----
+
+# Flag to enable Pointer Authentication. Internal flag not meant for
+# direct setting. Use BRANCH_PROTECTION to enable PAUTH.
+ENABLE_PAUTH := 0
+
+# Include pointer authentication (ARMv8.3-PAuth) registers in cpu context. This
+# must be set to 1 if the platform wants to use this feature in the Secure
+# world. It is not necessary for use in the Non-secure world.
+CTX_INCLUDE_PAUTH_REGS := 0
+
+#----
+# 8.4
+#----
+
+# Flag to enable Secure EL-2 feature.
+ENABLE_FEAT_SEL2 := 0
+
+# Include nested virtualization control (Armv8.4-NV) registers in cpu context.
+# This must be set to 1 if architecture implements Nested Virtualization
+# Extension and platform wants to use this feature in the Secure world.
+CTX_INCLUDE_NEVE_REGS := 0
+
+# By default, disable trace filter control register access to lower non-secure
+# exception levels, i.e. NS-EL2, or NS-EL1 if NS-EL2 is implemented, but
+# trace filter control register access is unused if FEAT_TRF is implemented.
+ENABLE_TRF_FOR_NS := 0
+
+# Flag to enable Data Independent Timing instructions.
+ENABLE_FEAT_DIT := 0
+
+#----
+# 8.5
+#----
+
+# Flag to enable access to the Random Number Generator registers.
+ENABLE_FEAT_RNG := 0
+
+# Flag to enable Speculation Barrier Instruction.
+ENABLE_FEAT_SB := 0
+
+# Flag to enable Branch Target Identification.
+# Internal flag not meant for direct setting.
+# Use BRANCH_PROTECTION to enable BTI.
+ENABLE_BTI := 0
+
+#----
+# 8.6
+#----
+
+# Flag to enable access to the CNTPOFF_EL2 register.
+ENABLE_FEAT_ECV := 0
+
+# Flag to enable access to the HDFGRTR_EL2 register.
+ENABLE_FEAT_FGT := 0
+
+#----
+# 8.7
+#----
+
+# Flag to enable access to the HCRX_EL2 register by setting SCR_EL3.HXEn.
+ENABLE_FEAT_HCX := 0
+
+#----
+# 8.9
+#----
+
+# Flag to enable access to TCR2 (FEAT_TCR2).
+ENABLE_FEAT_TCR2 := 0
+
+#
+################################################################################
+# Enable Mandatory features based on Arch versions.
+################################################################################
+#
# Enable the features which are mandatory from ARCH version 8.1 and upwards.
ifeq "8.1" "$(word 1, $(sort 8.1 $(ARM_ARCH_MAJOR).$(ARM_ARCH_MINOR)))"
-ENABLE_FEAT_PAN = 1
-ENABLE_FEAT_VHE = 1
+ENABLE_FEAT_PAN := 1
+ENABLE_FEAT_VHE := 1
endif
# Enable the features which are mandatory from ARCH version 8.2 and upwards.
ifeq "8.2" "$(word 1, $(sort 8.2 $(ARM_ARCH_MAJOR).$(ARM_ARCH_MINOR)))"
-ENABLE_FEAT_RAS = 1
+ENABLE_FEAT_RAS := 1
endif
# Enable the features which are mandatory from ARCH version 8.4 and upwards.
ifeq "8.4" "$(word 1, $(sort 8.4 $(ARM_ARCH_MAJOR).$(ARM_ARCH_MINOR)))"
-ENABLE_FEAT_DIT = 1
-ENABLE_FEAT_SEL2 = 1
+ENABLE_FEAT_SEL2 := 1
+CTX_INCLUDE_NEVE_REGS := 1
+ENABLE_TRF_FOR_NS := 1
+ENABLE_FEAT_DIT := 1
endif
# Enable the features which are mandatory from ARCH version 8.5 and upwards.
ifeq "8.5" "$(word 1, $(sort 8.5 $(ARM_ARCH_MAJOR).$(ARM_ARCH_MINOR)))"
-ENABLE_FEAT_SB = 1
+ENABLE_FEAT_RNG := 1
+ENABLE_FEAT_SB := 1
+
+# Enable Memory tagging, Branch Target Identification for aarch64 only.
+ifeq ($(ARCH), aarch64)
+ mem_tag_arch_support := yes
+endif #(ARCH=aarch64)
+
endif
# Enable the features which are mandatory from ARCH version 8.6 and upwards.
ifeq "8.6" "$(word 1, $(sort 8.6 $(ARM_ARCH_MAJOR).$(ARM_ARCH_MINOR)))"
-ENABLE_FEAT_FGT = 1
-ENABLE_FEAT_ECV = 1
+ENABLE_FEAT_ECV := 1
+ENABLE_FEAT_FGT := 1
endif
# Enable the features which are mandatory from ARCH version 8.7 and upwards.
ifeq "8.7" "$(word 1, $(sort 8.7 $(ARM_ARCH_MAJOR).$(ARM_ARCH_MINOR)))"
-ENABLE_FEAT_HCX = 1
+ENABLE_FEAT_HCX := 1
endif
+
+# Enable the features which are mandatory from ARCH version 8.9 and upwards.
+ifeq "8.9" "$(word 1, $(sort 8.9 $(ARM_ARCH_MAJOR).$(ARM_ARCH_MINOR)))"
+ENABLE_FEAT_TCR2 := 1
+endif
+
+#
+################################################################################
+# Optional Features defaulted to 0 or 2, if they are not enabled from
+# build option. Can also be disabled or enabled by platform if needed.
+################################################################################
+#
+
+#----
+# 8.0
+#----
+
+# Flag to enable CSV2_2 extension.
+ENABLE_FEAT_CSV2_2 ?= 0
+
+# By default, disable access of trace system registers from NS lower
+# ELs i.e. NS-EL2, or NS-EL1 if NS-EL2 implemented but unused if
+# system register trace is implemented. This feature is available if
+# trace unit such as ETMv4.x, This feature is OPTIONAL and is only
+# permitted in Armv8 implementations.
+ENABLE_SYS_REG_TRACE_FOR_NS ?= 0
+
+#----
+# 8.2
+#----
+
+# Build option to enable/disable the Statistical Profiling Extension,
+# keep it enabled by default for AArch64.
+ifeq (${ARCH},aarch64)
+ ENABLE_SPE_FOR_NS ?= 2
+else ifeq (${ARCH},aarch32)
+ ifdef ENABLE_SPE_FOR_NS
+ $(error ENABLE_SPE_FOR_NS is not supported for AArch32)
+ else
+ ENABLE_SPE_FOR_NS := 0
+ endif
+endif
+
+# Enable SVE for non-secure world by default.
+ifeq (${ARCH},aarch64)
+ ENABLE_SVE_FOR_NS ?= 2
+# SVE is only supported on AArch64 so disable it on AArch32.
+else ifeq (${ARCH},aarch32)
+ ifdef ENABLE_SVE_FOR_NS
+ $(error ENABLE_SVE_FOR_NS is not supported for AArch32)
+ else
+ ENABLE_SVE_FOR_NS := 0
+ endif
+endif
+
+#----
+# 8.4
+#----
+
+# Feature flags for supporting Activity monitor extensions.
+ENABLE_FEAT_AMU ?= 0
+ENABLE_AMU_AUXILIARY_COUNTERS ?= 0
+ENABLE_AMU_FCONF ?= 0
+AMU_RESTRICT_COUNTERS ?= 0
+
+# Build option to enable MPAM for lower ELs.
+ENABLE_MPAM_FOR_LOWER_ELS ?= 0
+
+#----
+# 8.5
+#----
+
+# Flag to enable support for EL3 trapping of reads of the RNDR and RNDRRS
+# registers, by setting SCR_EL3.TRNDR.
+ENABLE_FEAT_RNG_TRAP ?= 0
+
+# Include Memory Tagging Extension registers in cpu context. This must be set
+# to 1 if the platform wants to use this feature in the Secure world and MTE is
+# enabled at ELX.
+CTX_INCLUDE_MTE_REGS ?= 0
+
+#----
+# 8.6
+#----
+
+# Flag to enable AMUv1p1 extension.
+ENABLE_FEAT_AMUv1p1 ?= 0
+
+# Flag to enable delayed trapping of WFE instruction (FEAT_TWED).
+ENABLE_FEAT_TWED ?= 0
+
+# In v8.6+ platforms with delayed trapping of WFE being supported
+# via FEAT_TWED, this flag takes the delay value to be set in the
+# SCR_EL3.TWEDEL(4bit) field, when FEAT_TWED is implemented.
+# By default it takes 0, and need to be updated by the platforms.
+TWED_DELAY ?= 0
+
+# Disable MTPMU if FEAT_MTPMU is supported.
+DISABLE_MTPMU ?= 0
+
+#----
+# 8.9
+#----
+
+# Flag to enable NoTagAccess memory region attribute for stage 2 of translation.
+ENABLE_FEAT_MTE_PERM ?= 0
+
+# Flag to enable access to Stage 2 Permission Indirection (FEAT_S2PIE).
+ENABLE_FEAT_S2PIE ?= 0
+
+# Flag to enable access to Stage 1 Permission Indirection (FEAT_S1PIE).
+ENABLE_FEAT_S1PIE ?= 0
+
+# Flag to enable access to Stage 2 Permission Overlay (FEAT_S2POE).
+ENABLE_FEAT_S2POE ?= 0
+
+# Flag to enable access to Stage 1 Permission Overlay (FEAT_S1POE).
+ENABLE_FEAT_S1POE ?= 0
+
+#----
+# 9.0
+#----
+
+# Flag to enable Realm Management Extension (FEAT_RME).
+ENABLE_RME ?= 0
+
+# Scalable Matrix Extension for non-secure world.
+ENABLE_SME_FOR_NS ?= 0
+
+# Scalable Vector Extension for secure world.
+ENABLE_SVE_FOR_SWD ?= 0
+
+# By default, disable access of trace buffer control registers from NS
+# lower ELs i.e. NS-EL2, or NS-EL1 if NS-EL2 implemented but unused
+# if FEAT_TRBE is implemented.
+# Note FEAT_TRBE is only supported on AArch64 - therefore do not enable in
+# AArch32.
+ifeq (${ARCH},aarch64)
+ ENABLE_TRBE_FOR_NS ?= 0
+else ifeq (${ARCH},aarch32)
+ ifdef ENABLE_TRBE_FOR_NS
+ $(error ENABLE_TRBE_FOR_NS is not supported for AArch32)
+ else
+ ENABLE_TRBE_FOR_NS := 0
+ endif
+endif
+
+#----
+# 9.2
+#----
+
+# Scalable Matrix Extension version 2 for non-secure world.
+ENABLE_SME2_FOR_NS ?= 0
+
+# Scalable Matrix Extension for secure world.
+ENABLE_SME_FOR_SWD ?= 0
+
+# By default, disable access to branch record buffer control registers from NS
+# lower ELs i.e. NS-EL2, or NS-EL1 if NS-EL2 implemented but unused
+# if FEAT_BRBE is implemented.
+ENABLE_BRBE_FOR_NS ?= 0
+
+#----
+#9.4
+#----
+
+# Flag to enable access to Guarded Control Stack (FEAT_GCS).
+ENABLE_FEAT_GCS ?= 0
diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk
index 964e0f9..aaabb27 100644
--- a/make_helpers/defaults.mk
+++ b/make_helpers/defaults.mk
@@ -63,16 +63,6 @@
# Include FP registers in cpu context
CTX_INCLUDE_FPREGS := 0
-# Include pointer authentication (ARMv8.3-PAuth) registers in cpu context. This
-# must be set to 1 if the platform wants to use this feature in the Secure
-# world. It is not needed to use it in the Non-secure world.
-CTX_INCLUDE_PAUTH_REGS := 0
-
-# Include Nested virtualization control (Armv8.4-NV) registers in cpu context.
-# This must be set to 1 if architecture implements Nested Virtualization
-# Extension and platform wants to use this feature in the Secure world
-CTX_INCLUDE_NEVE_REGS := 0
-
# Debug build
DEBUG := 0
@@ -85,17 +75,10 @@
# Disable the generation of the binary image (ELF only).
DISABLE_BIN_GENERATION := 0
-# Disable MTPMU if FEAT_MTPMU is supported. Default is 0 to keep backwards
-# compatibility.
-DISABLE_MTPMU := 0
-
# Enable capability to disable authentication dynamically. Only meant for
# development platforms.
DYN_DISABLE_AUTH := 0
-# Build option to enable MPAM for lower ELs
-ENABLE_MPAM_FOR_LOWER_ELS := 0
-
# Enable the Maximum Power Mitigation Mechanism on supporting cores.
ENABLE_MPMM := 0
@@ -111,9 +94,6 @@
# Flag to enable PSCI STATs functionality
ENABLE_PSCI_STAT := 0
-# Flag to enable Realm Management Extension (FEAT_RME)
-ENABLE_RME := 0
-
# Flag to enable runtime instrumentation using PMF
ENABLE_RUNTIME_INSTRUMENTATION := 0
@@ -123,77 +103,6 @@
# Flag to enable exception handling in EL3
EL3_EXCEPTION_HANDLING := 0
-# Flag to enable Branch Target Identification.
-# Internal flag not meant for direct setting.
-# Use BRANCH_PROTECTION to enable BTI.
-ENABLE_BTI := 0
-
-# Flag to enable Pointer Authentication.
-# Internal flag not meant for direct setting.
-# Use BRANCH_PROTECTION to enable PAUTH.
-ENABLE_PAUTH := 0
-
-# Flag to enable AMUv1p1 extension.
-ENABLE_FEAT_AMUv1p1 := 0
-
-# Flag to enable CSV2_2 extension.
-ENABLE_FEAT_CSV2_2 := 0
-
-# Flag to enable access to the HCRX_EL2 register by setting SCR_EL3.HXEn.
-ENABLE_FEAT_HCX := 0
-
-# Flag to enable access to the HDFGRTR_EL2 register
-ENABLE_FEAT_FGT := 0
-
-# Flag to enable access to the CNTPOFF_EL2 register
-ENABLE_FEAT_ECV := 0
-
-# Flag to enable use of the DIT feature.
-ENABLE_FEAT_DIT := 0
-
-# Flag to enable access to Privileged Access Never bit of PSTATE.
-ENABLE_FEAT_PAN := 0
-
-# Flag to enable access to the Random Number Generator registers
-ENABLE_FEAT_RNG := 0
-
-# Flag to enable support for EL3 trapping of reads of the RNDR and RNDRRS
-# registers, by setting SCR_EL3.TRNDR.
-ENABLE_FEAT_RNG_TRAP := 0
-
-# Flag to enable Speculation Barrier Instruction
-ENABLE_FEAT_SB := 0
-
-# Flag to enable Secure EL-2 feature.
-ENABLE_FEAT_SEL2 := 0
-
-# Flag to enable Virtualization Host Extensions
-ENABLE_FEAT_VHE := 0
-
-# Flag to enable delayed trapping of WFE instruction (FEAT_TWED)
-ENABLE_FEAT_TWED := 0
-
-# Flag to enable access to TCR2 (FEAT_TCR2)
-ENABLE_FEAT_TCR2 := 0
-
-# Flag to enable access to Stage 2 Permission Indirection (FEAT_S2PIE)
-ENABLE_FEAT_S2PIE := 0
-
-# Flag to enable access to Stage 1 Permission Indirection (FEAT_S1PIE)
-ENABLE_FEAT_S1PIE := 0
-
-# Flag to enable access to Stage 2 Permission Overlay (FEAT_S2POE)
-ENABLE_FEAT_S2POE := 0
-
-# Flag to enable access to Stage 1 Permission Overlay (FEAT_S1POE)
-ENABLE_FEAT_S1POE := 0
-
-# Flag to enable access to Guarded Control Stack (FEAT_GCS)
-ENABLE_FEAT_GCS := 0
-
-# Flag to enable NoTagAccess memory region attribute for stage 2 of translation.
-ENABLE_FEAT_MTE_PERM := 0
-
# By default BL31 encryption disabled
ENCRYPT_BL31 := 0
@@ -279,8 +188,7 @@
# Enable PSCI OS-initiated mode support
PSCI_OS_INIT_MODE := 0
-# Enable RAS Support
-ENABLE_FEAT_RAS := 0
+# Enable RAS Firmware First Handling Support
RAS_FFH_SUPPORT := 0
# By default, BL1 acts as the reset handler, not BL31
@@ -379,40 +287,9 @@
# platforms).
WARMBOOT_ENABLE_DCACHE_EARLY := 0
-# Build option to enable/disable the Statistical Profiling Extensions
-ENABLE_SPE_FOR_NS := 2
-
-# SPE is only supported on AArch64 so disable it on AArch32.
-ifeq (${ARCH},aarch32)
- override ENABLE_SPE_FOR_NS := 0
-endif
-
-# Include Memory Tagging Extension registers in cpu context. This must be set
-# to 1 if the platform wants to use this feature in the Secure world and MTE is
-# enabled at ELX.
-CTX_INCLUDE_MTE_REGS := 0
-
-ENABLE_FEAT_AMU := 0
-ENABLE_AMU_AUXILIARY_COUNTERS := 0
-ENABLE_AMU_FCONF := 0
-AMU_RESTRICT_COUNTERS := 0
-
-# Enable SVE for non-secure world by default
-ENABLE_SVE_FOR_NS := 2
-# SVE is only supported on AArch64 so disable it on AArch32.
-ifeq (${ARCH},aarch32)
- override ENABLE_SVE_FOR_NS := 0
-endif
-ENABLE_SVE_FOR_SWD := 0
-
# Default SVE vector length to maximum architected value
SVE_VECTOR_LEN := 2048
-# SME defaults to disabled
-ENABLE_SME_FOR_NS := 0
-ENABLE_SME_FOR_SWD := 0
-ENABLE_SME2_FOR_NS := 0
-
SANITIZE_UB := off
# For ARMv8.1 (AArch64) platforms, enabling this option selects the spinlock
@@ -467,38 +344,6 @@
# Disable Firmware update support by default
PSA_FWU_SUPPORT := 0
-# By default, disable access of trace buffer control registers from NS
-# lower ELs i.e. NS-EL2, or NS-EL1 if NS-EL2 implemented but unused
-# if FEAT_TRBE is implemented.
-# Note FEAT_TRBE is only supported on AArch64 - therefore do not enable in
-# AArch32.
-ifneq (${ARCH},aarch32)
- ENABLE_TRBE_FOR_NS := 0
-else
- override ENABLE_TRBE_FOR_NS := 0
-endif
-
-# By default, disable access to branch record buffer control registers from NS
-# lower ELs i.e. NS-EL2, or NS-EL1 if NS-EL2 implemented but unused
-# if FEAT_BRBE is implemented.
-ENABLE_BRBE_FOR_NS := 0
-
-# By default, disable access of trace system registers from NS lower
-# ELs i.e. NS-EL2, or NS-EL1 if NS-EL2 implemented but unused if
-# system register trace is implemented.
-ENABLE_SYS_REG_TRACE_FOR_NS := 0
-
-# By default, disable trace filter control registers access to NS
-# lower ELs, i.e. NS-EL2, or NS-EL1 if NS-EL2 implemented but unused
-# if FEAT_TRF is implemented.
-ENABLE_TRF_FOR_NS := 0
-
-# In v8.6+ platforms with delayed trapping of WFE being supported
-# via FEAT_TWED, this flag takes the delay value to be set in the
-# SCR_EL3.TWEDEL(4bit) field, when FEAT_TWED is implemented.
-# By default it takes 0, and need to be updated by the platforms.
-TWED_DELAY := 0
-
# By default, disable the mocking of RSS provided services
PLAT_RSS_NOT_SUPPORTED := 0
diff --git a/make_helpers/tbbr/tbbr_tools.mk b/make_helpers/tbbr/tbbr_tools.mk
index a3351eb..3a2c53f 100644
--- a/make_helpers/tbbr/tbbr_tools.mk
+++ b/make_helpers/tbbr/tbbr_tools.mk
@@ -118,8 +118,10 @@
ifeq (${NEED_BL32},yes)
$(if ${BL32_KEY},$(eval $(call CERT_ADD_CMD_OPT,${BL32_KEY},--tos-fw-key)))
$(eval $(call TOOL_ADD_PAYLOAD,${BUILD_PLAT}/tos_fw_content.crt,--tos-fw-cert))
+ifneq (${COT},cca)
$(eval $(call TOOL_ADD_PAYLOAD,${BUILD_PLAT}/tos_fw_key.crt,--tos-fw-key-cert))
endif
+endif
# Add the BL33 CoT (key cert + img cert)
ifneq (${BL33},)
diff --git a/package-lock.json b/package-lock.json
index 89ebd51..e23f9a4 100644
--- a/package-lock.json
+++ b/package-lock.json
@@ -3894,9 +3894,9 @@
}
},
"node_modules/word-wrap": {
- "version": "1.2.3",
- "resolved": "https://registry.npmjs.org/word-wrap/-/word-wrap-1.2.3.tgz",
- "integrity": "sha512-Hz/mrNwitNRh/HUAtM/VT/5VH+ygD6DV7mYKZAtHOrbs8U7lvPS6xf7EJKMF0uW1KJCl0H701g3ZGus+muE5vQ==",
+ "version": "1.2.4",
+ "resolved": "https://registry.npmjs.org/word-wrap/-/word-wrap-1.2.4.tgz",
+ "integrity": "sha512-2V81OA4ugVo5pRo46hAoD2ivUJx8jXmWXfUkY4KFNw0hEptvN0QfH3K4nHiwzGeKl5rFKedV48QVoqYavy4YpA==",
"dev": true,
"engines": {
"node": ">=0.10.0"
@@ -4022,7 +4022,7 @@
}
},
"tools/conventional-changelog-tf-a": {
- "version": "2.7.0",
+ "version": "2.9.0",
"dev": true,
"license": "BSD-3-Clause",
"dependencies": {
@@ -6978,9 +6978,9 @@
}
},
"word-wrap": {
- "version": "1.2.3",
- "resolved": "https://registry.npmjs.org/word-wrap/-/word-wrap-1.2.3.tgz",
- "integrity": "sha512-Hz/mrNwitNRh/HUAtM/VT/5VH+ygD6DV7mYKZAtHOrbs8U7lvPS6xf7EJKMF0uW1KJCl0H701g3ZGus+muE5vQ==",
+ "version": "1.2.4",
+ "resolved": "https://registry.npmjs.org/word-wrap/-/word-wrap-1.2.4.tgz",
+ "integrity": "sha512-2V81OA4ugVo5pRo46hAoD2ivUJx8jXmWXfUkY4KFNw0hEptvN0QfH3K4nHiwzGeKl5rFKedV48QVoqYavy4YpA==",
"dev": true
},
"wordwrap": {
diff --git a/plat/arm/board/common/board_common.mk b/plat/arm/board/common/board_common.mk
index 777784d..4665827 100644
--- a/plat/arm/board/common/board_common.mk
+++ b/plat/arm/board/common/board_common.mk
@@ -52,8 +52,6 @@
# Force generation of the new hash if ROT_KEY is specified
ifdef ROT_KEY
HASH_PREREQUISITES = $(ROT_KEY) FORCE
-else
- HASH_PREREQUISITES = $(ROT_KEY)
endif
$(ARM_ROTPK_HASH) : $(HASH_PREREQUISITES)
diff --git a/plat/arm/board/fvp/fvp_pm.c b/plat/arm/board/fvp/fvp_pm.c
index 534a175..51dda9e 100644
--- a/plat/arm/board/fvp/fvp_pm.c
+++ b/plat/arm/board/fvp/fvp_pm.c
@@ -65,25 +65,6 @@
/* Disable coherency if this cluster is to be turned off */
fvp_interconnect_disable();
-#if HW_ASSISTED_COHERENCY
- uint32_t reg;
-
- /*
- * If we have determined this core to be the last man standing and we
- * intend to power down the cluster proactively, we provide a hint to
- * the power controller that cluster power is not required when all
- * cores are powered down.
- * Note that this is only an advisory to power controller and is supported
- * by SoCs with DynamIQ Shared Units only.
- */
- reg = read_clusterpwrdn();
-
- /* Clear and set bit 0 : Cluster power not required */
- reg &= ~DSU_CLUSTER_PWR_MASK;
- reg |= DSU_CLUSTER_PWR_OFF;
- write_clusterpwrdn(reg);
-#endif
-
/* Program the power controller to turn the cluster off */
fvp_pwrc_write_pcoffr(mpidr);
}
diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h
index df04617..826fca2 100644
--- a/plat/arm/board/fvp/include/platform_def.h
+++ b/plat/arm/board/fvp/include/platform_def.h
@@ -168,8 +168,13 @@
# define MAX_XLAT_TABLES 6
# endif
#elif !USE_ROMLIB
-# define PLAT_ARM_MMAP_ENTRIES 11
-# define MAX_XLAT_TABLES 5
+# if ENABLE_RME && defined(IMAGE_BL2)
+# define PLAT_ARM_MMAP_ENTRIES 12
+# define MAX_XLAT_TABLES 6
+# else
+# define PLAT_ARM_MMAP_ENTRIES 11
+# define MAX_XLAT_TABLES 5
+# endif /* (IMAGE_BL2 && ENABLE_RME) */
#else
# define PLAT_ARM_MMAP_ENTRIES 12
# if (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd)) && \
@@ -437,7 +442,12 @@
/*
* Maximum size of Event Log buffer used in Measured Boot Event Log driver
*/
+#if ENABLE_RME && (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd))
+/* Account for additional measurements of secure partitions and SPM. */
+#define PLAT_ARM_EVENT_LOG_MAX_SIZE UL(0x800)
+#else
#define PLAT_ARM_EVENT_LOG_MAX_SIZE UL(0x400)
+#endif
/*
* Maximum size of Event Log buffer used for DRTM
diff --git a/plat/arm/board/morello/platform.mk b/plat/arm/board/morello/platform.mk
index 0ae7693..12ffb5a 100644
--- a/plat/arm/board/morello/platform.mk
+++ b/plat/arm/board/morello/platform.mk
@@ -89,6 +89,9 @@
override ARM_BL31_IN_DRAM := 1
+override PSCI_EXTENDED_STATE_ID := 1
+override ARM_RECOM_STATE_ID_ENC := 1
+
# Errata workarounds:
ERRATA_N1_1868343 := 1
diff --git a/plat/arm/css/common/css_pm.c b/plat/arm/css/common/css_pm.c
index 3222226..bb64e73 100644
--- a/plat/arm/css/common/css_pm.c
+++ b/plat/arm/css/common/css_pm.c
@@ -131,28 +131,8 @@
plat_arm_gic_cpuif_disable();
/* Cluster is to be turned off, so disable coherency */
- if (CSS_CLUSTER_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF) {
+ if (CSS_CLUSTER_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF)
plat_arm_interconnect_exit_coherency();
-
-#if HW_ASSISTED_COHERENCY
- uint32_t reg;
-
- /*
- * If we have determined this core to be the last man standing and we
- * intend to power down the cluster proactively, we provide a hint to
- * the power controller that cluster power is not required when all
- * cores are powered down.
- * Note that this is only an advisory to power controller and is supported
- * by SoCs with DynamIQ Shared Units only.
- */
- reg = read_clusterpwrdn();
-
- /* Clear and set bit 0 : Cluster power not required */
- reg &= ~DSU_CLUSTER_PWR_MASK;
- reg |= DSU_CLUSTER_PWR_OFF;
- write_clusterpwrdn(reg);
-#endif
- }
}
/*******************************************************************************
diff --git a/plat/qemu/common/common.mk b/plat/qemu/common/common.mk
index b8b57d2..b23f7fd 100644
--- a/plat/qemu/common/common.mk
+++ b/plat/qemu/common/common.mk
@@ -17,15 +17,30 @@
else
QEMU_CPU_LIBS := lib/cpus/aarch64/aem_generic.S \
lib/cpus/aarch64/cortex_a53.S \
+ lib/cpus/aarch64/cortex_a55.S \
lib/cpus/aarch64/cortex_a57.S \
lib/cpus/aarch64/cortex_a72.S \
lib/cpus/aarch64/cortex_a76.S \
+ lib/cpus/aarch64/cortex_a710.S \
lib/cpus/aarch64/neoverse_n_common.S \
lib/cpus/aarch64/neoverse_n1.S \
lib/cpus/aarch64/neoverse_v1.S \
+ lib/cpus/aarch64/neoverse_n2.S \
lib/cpus/aarch64/qemu_max.S
PLAT_INCLUDES += -Iinclude/plat/arm/common/${ARCH}
+
+# Cpu core architecture level:
+# v8.0: a53, a57, a72
+# v8.2: a76, n1
+# v8.4: v1
+# v9.0: a710, n2
+#
+# let treat v9.0 as v8.5 as they share cpu features
+# https://developer.arm.com/documentation/102378/0201/Armv8-x-and-Armv9-x-extensions-and-features
+
+ARM_ARCH_MAJOR := 8
+ARM_ARCH_MINOR := 5
endif
PLAT_BL_COMMON_SOURCES := ${PLAT_QEMU_COMMON_PATH}/qemu_common.c \
diff --git a/plat/qemu/qemu/qemu_bl1_measured_boot.c b/plat/qemu/qemu/qemu_bl1_measured_boot.c
index 3d20f97..7984781 100644
--- a/plat/qemu/qemu/qemu_bl1_measured_boot.c
+++ b/plat/qemu/qemu/qemu_bl1_measured_boot.c
@@ -26,3 +26,9 @@
{
return 0;
}
+
+int plat_mboot_measure_key(const void *pk_oid, const void *pk_ptr,
+ size_t pk_len)
+{
+ return 0;
+}
diff --git a/plat/qemu/qemu_sbsa/include/platform_def.h b/plat/qemu/qemu_sbsa/include/platform_def.h
index deaf16e..14030e3 100644
--- a/plat/qemu/qemu_sbsa/include/platform_def.h
+++ b/plat/qemu/qemu_sbsa/include/platform_def.h
@@ -199,7 +199,7 @@
#define QEMU_FLASH1_BASE 0x10000000
#define QEMU_FLASH1_SIZE 0x10000000
-#define PLAT_QEMU_FIP_BASE 0x00008000
+#define PLAT_QEMU_FIP_BASE BL1_SIZE
#define PLAT_QEMU_FIP_MAX_SIZE 0x00400000
/* This is map from GIC_DIST up to last CPU (255) GIC_REDISTR */
diff --git a/plat/st/common/bl2_io_storage.c b/plat/st/common/bl2_io_storage.c
index 5b0a171..0bcfece 100644
--- a/plat/st/common/bl2_io_storage.c
+++ b/plat/st/common/bl2_io_storage.c
@@ -191,13 +191,13 @@
case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC:
INFO("Using EMMC\n");
break;
- case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_QSPI:
- INFO("Using QSPI NOR\n");
+ case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_SPI:
+ INFO("Using SPI NOR\n");
break;
case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC:
INFO("Using FMC NAND\n");
break;
- case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_QSPI:
+ case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_SPI:
INFO("Using SPI NAND\n");
break;
case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART:
@@ -433,7 +433,7 @@
break;
#endif
#if STM32MP_SPI_NOR
- case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_QSPI:
+ case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_SPI:
dmbsy();
boot_spi_nor(boot_context);
break;
@@ -445,7 +445,7 @@
break;
#endif
#if STM32MP_SPI_NAND
- case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_QSPI:
+ case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_SPI:
dmbsy();
boot_spi_nand(boot_context);
break;
@@ -530,14 +530,14 @@
case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC:
#endif
#if STM32MP_SPI_NAND
- case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_QSPI:
+ case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_SPI:
#endif
image_block_spec.offset = STM32MP_NAND_FIP_OFFSET;
break;
#endif
#if STM32MP_SPI_NOR
- case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_QSPI:
+ case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_SPI:
/*
* With FWU Multi Bank feature enabled, the selection of
* the image to boot will be done by fwu_init calling the
@@ -694,7 +694,7 @@
break;
#endif
#if STM32MP_SPI_NOR
- case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_QSPI:
+ case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_SPI:
if (guidcmp(img_uuid, &STM32MP_NOR_FIP_A_GUID) == 0) {
image_spec->offset = STM32MP_NOR_FIP_A_OFFSET;
} else if (guidcmp(img_uuid, &STM32MP_NOR_FIP_B_GUID) == 0) {
@@ -747,7 +747,7 @@
#endif
#if STM32MP_SPI_NOR
- case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_QSPI:
+ case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_SPI:
if (image_id == FWU_METADATA_IMAGE_ID) {
spec->offset = STM32MP_NOR_METADATA1_OFFSET;
} else {
diff --git a/plat/st/common/common.mk b/plat/st/common/common.mk
index f69c901..d10f185 100644
--- a/plat/st/common/common.mk
+++ b/plat/st/common/common.mk
@@ -146,6 +146,7 @@
BL2_SOURCES += drivers/io/io_fip.c \
plat/st/common/bl2_io_storage.c \
+ plat/st/common/plat_image_load.c \
plat/st/common/stm32mp_fconf_io.c
BL2_SOURCES += drivers/io/io_block.c \
diff --git a/plat/st/common/include/stm32mp_common.h b/plat/st/common/include/stm32mp_common.h
index bb3401f..e334f22 100644
--- a/plat/st/common/include/stm32mp_common.h
+++ b/plat/st/common/include/stm32mp_common.h
@@ -14,6 +14,9 @@
#define JEDEC_ST_BKID U(0x0)
#define JEDEC_ST_MFID U(0x20)
+/* FWU configuration (max supported value is 15) */
+#define FWU_MAX_TRIAL_REBOOT U(3)
+
/* Functions to save and get boot context address given by ROM code */
void stm32mp_save_boot_ctx_address(uintptr_t address);
uintptr_t stm32mp_get_boot_ctx_address(void);
diff --git a/plat/st/common/include/stm32mp_io_storage.h b/plat/st/common/include/stm32mp_io_storage.h
index 3c04c47..ce0d647 100644
--- a/plat/st/common/include/stm32mp_io_storage.h
+++ b/plat/st/common/include/stm32mp_io_storage.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2022, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2021-2023, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -10,6 +10,55 @@
#include <drivers/io/io_storage.h>
+/*******************************************************************************
+ * STM32MP1 RAW partition offset for devices without GPT
+ ******************************************************************************/
+#define STM32MP_EMMC_BOOT_FIP_OFFSET U(0x00040000)
+#if PSA_FWU_SUPPORT
+#define STM32MP_NOR_METADATA1_OFFSET U(0x00080000)
+#define STM32MP_NOR_METADATA2_OFFSET U(0x000C0000)
+#define STM32MP_NOR_FIP_A_OFFSET U(0x00100000)
+#define STM32MP_NOR_FIP_A_GUID (const struct efi_guid)EFI_GUID(0x4fd84c93, \
+ 0x54ef, 0x463f, 0xa7, 0xef, 0xae, 0x25, 0xff,\
+ 0x88, 0x70, 0x87)
+
+#define STM32MP_NOR_FIP_B_OFFSET U(0x00500000)
+#define STM32MP_NOR_FIP_B_GUID (const struct efi_guid)EFI_GUID(0x09c54952, \
+ 0xd5bf, 0x45af, 0xac, 0xee, 0x33, 0x53, 0x03,\
+ 0x76, 0x6f, 0xb3)
+
+#define STM32MP_NAND_METADATA1_OFFSET U(0x00100000)
+#define STM32MP_NAND_METADATA2_OFFSET U(0x00180000)
+#define STM32MP_NAND_FIP_A_OFFSET U(0x00200000)
+#define STM32MP_NAND_FIP_A_GUID (const struct efi_guid)EFI_GUID(0x4fd84c93, \
+ 0x54ef, 0x463f, 0xa7, 0xef, 0xae, 0x25, 0xff,\
+ 0x88, 0x70, 0x87)
+
+#define STM32MP_NAND_FIP_B_OFFSET U(0x00A00000)
+#define STM32MP_NAND_FIP_B_GUID (const struct efi_guid)EFI_GUID(0x09c54952, \
+ 0xd5bf, 0x45af, 0xac, 0xee, 0x33, 0x53, 0x03,\
+ 0x76, 0x6f, 0xb3)
+
+#define STM32MP_NAND_FIP_B_MAX_OFFSET U(0x01200000)
+#else /* PSA_FWU_SUPPORT */
+#ifndef STM32MP_NOR_FIP_OFFSET
+#define STM32MP_NOR_FIP_OFFSET U(0x00080000)
+#endif
+#ifndef STM32MP_NAND_FIP_OFFSET
+#define STM32MP_NAND_FIP_OFFSET U(0x00200000)
+#endif
+#endif /* PSA_FWU_SUPPORT */
+
+/*
+ * Only used for MTD devices that need some backup blocks.
+ * Must define a maximum size for a partition.
+ */
+#define PLATFORM_MTD_MAX_PART_SIZE U(0x00400000)
+
+#define FIP_IMAGE_NAME "fip"
+#define METADATA_PART_1 "metadata1"
+#define METADATA_PART_2 "metadata2"
+
/* IO devices handle */
extern uintptr_t storage_dev_handle;
extern uintptr_t fip_dev_handle;
diff --git a/plat/st/stm32mp1/plat_image_load.c b/plat/st/common/plat_image_load.c
similarity index 94%
rename from plat/st/stm32mp1/plat_image_load.c
rename to plat/st/common/plat_image_load.c
index c455544..4644168 100644
--- a/plat/st/stm32mp1/plat_image_load.c
+++ b/plat/st/common/plat_image_load.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/plat/st/common/stm32mp_common.c b/plat/st/common/stm32mp_common.c
index f842e16..2163aaf 100644
--- a/plat/st/common/stm32mp_common.c
+++ b/plat/st/common/stm32mp_common.c
@@ -113,7 +113,11 @@
const uint32_t c_m_bits = SCTLR_M_BIT | SCTLR_C_BIT;
/* The spinlocks are used only when MMU and data cache are enabled */
+#ifdef __aarch64__
+ return (read_sctlr_el3() & c_m_bits) == c_m_bits;
+#else
return (read_sctlr() & c_m_bits) == c_m_bits;
+#endif
}
int stm32mp_map_ddr_non_cacheable(void)
diff --git a/plat/st/stm32mp1/include/boot_api.h b/plat/st/stm32mp1/include/boot_api.h
index 1054609..1340633 100644
--- a/plat/st/stm32mp1/include/boot_api.h
+++ b/plat/st/stm32mp1/include/boot_api.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2022, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2017-2023, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -47,7 +47,7 @@
#define BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC 0x3U
/* Boot occurred on QSPI NOR */
-#define BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_QSPI 0x4U
+#define BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_SPI 0x4U
/* Boot occurred on UART */
#define BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART 0x5U
@@ -56,7 +56,7 @@
#define BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_USB 0x6U
/* Boot occurred on QSPI NAND */
-#define BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_QSPI 0x7U
+#define BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_SPI 0x7U
/**
* @brief Possible value of boot context field 'EmmcXferStatus'
diff --git a/plat/st/stm32mp1/include/platform_def.h b/plat/st/stm32mp1/include/platform_def.h
index 61b847f..75c8219 100644
--- a/plat/st/stm32mp1/include/platform_def.h
+++ b/plat/st/stm32mp1/include/platform_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -25,10 +25,6 @@
#define PLATFORM_STACK_SIZE 0xC00
#endif
-#define FIP_IMAGE_NAME "fip"
-#define METADATA_PART_1 "metadata1"
-#define METADATA_PART_2 "metadata2"
-
#define STM32MP_PRIMARY_CPU U(0x0)
#define STM32MP_SECONDARY_CPU U(0x1)
diff --git a/plat/st/stm32mp1/platform.mk b/plat/st/stm32mp1/platform.mk
index 55423ae..194672e 100644
--- a/plat/st/stm32mp1/platform.mk
+++ b/plat/st/stm32mp1/platform.mk
@@ -277,8 +277,6 @@
BL2_SOURCES += drivers/st/ddr/stm32mp1_ddr.c \
drivers/st/ddr/stm32mp1_ram.c
-BL2_SOURCES += plat/st/stm32mp1/plat_image_load.c
-
ifeq ($(AARCH32_SP),sp_min)
# Create DTB file for BL32
${BUILD_PLAT}/fdts/%-bl32.dts: fdts/%.dts fdts/${BL32_DTSI} | ${BUILD_PLAT} fdt_dirs
diff --git a/plat/st/stm32mp1/stm32mp1_def.h b/plat/st/stm32mp1/stm32mp1_def.h
index df5593a..0fa6c73 100644
--- a/plat/st/stm32mp1/stm32mp1_def.h
+++ b/plat/st/stm32mp1/stm32mp1_def.h
@@ -195,6 +195,7 @@
SRAM1_SIZE - \
PLATFORM_MTD_MAX_PAGE_SIZE)
#endif
+
/*******************************************************************************
* STM32MP1 device/io map related constants (used for MMU)
******************************************************************************/
@@ -416,12 +417,6 @@
#define STM32MP_SDMMC2_BASE U(0x58007000)
#define STM32MP_SDMMC3_BASE U(0x48004000)
-#define STM32MP_MMC_INIT_FREQ U(400000) /*400 KHz*/
-#define STM32MP_SD_NORMAL_SPEED_MAX_FREQ U(25000000) /*25 MHz*/
-#define STM32MP_SD_HIGH_SPEED_MAX_FREQ U(50000000) /*50 MHz*/
-#define STM32MP_EMMC_NORMAL_SPEED_MAX_FREQ U(26000000) /*26 MHz*/
-#define STM32MP_EMMC_HIGH_SPEED_MAX_FREQ U(52000000) /*52 MHz*/
-
/*******************************************************************************
* STM32MP1 BSEC / OTP
******************************************************************************/
@@ -540,9 +535,6 @@
/* UID OTP */
#define UID_WORD_NB U(3)
-/* FWU configuration (max supported value is 15) */
-#define FWU_MAX_TRIAL_REBOOT U(3)
-
/*******************************************************************************
* STM32MP1 TAMP
******************************************************************************/
@@ -642,7 +634,7 @@
/* 3 PWR + 1 VREFBUF + 14 PMIC regulators + 1 FIXED */
#define PLAT_NB_RDEVS U(19)
/* 2 FIXED */
-#define PLAT_NB_FIXED_REGS U(2)
+#define PLAT_NB_FIXED_REGUS U(2)
/*******************************************************************************
* Device Tree defines
diff --git a/plat/st/stm32mp1/stm32mp1_fip_def.h b/plat/st/stm32mp1/stm32mp1_fip_def.h
index fa2d20e..e37e2e6 100644
--- a/plat/st/stm32mp1/stm32mp1_fip_def.h
+++ b/plat/st/stm32mp1/stm32mp1_fip_def.h
@@ -124,30 +124,4 @@
#define MAX_MMAP_REGIONS 10
#endif
-/*******************************************************************************
- * STM32MP1 RAW partition offset for devices without GPT
- ******************************************************************************/
-#define STM32MP_EMMC_BOOT_FIP_OFFSET U(0x00040000)
-#if PSA_FWU_SUPPORT
-#define STM32MP_NOR_METADATA1_OFFSET U(0x00080000)
-#define STM32MP_NOR_METADATA2_OFFSET U(0x000C0000)
-#define STM32MP_NOR_FIP_A_OFFSET U(0x00100000)
-#define STM32MP_NOR_FIP_A_GUID (const struct efi_guid)EFI_GUID(0x4fd84c93, \
- 0x54ef, 0x463f, 0xa7, 0xef, 0xae, 0x25, 0xff,\
- 0x88, 0x70, 0x87)
-
-#define STM32MP_NOR_FIP_B_OFFSET U(0x00500000)
-#define STM32MP_NOR_FIP_B_GUID (const struct efi_guid)EFI_GUID(0x09c54952, \
- 0xd5bf, 0x45af, 0xac, 0xee, 0x33, 0x53, 0x03,\
- 0x76, 0x6f, 0xb3)
-
-#else /* PSA_FWU_SUPPORT */
-#ifndef STM32MP_NOR_FIP_OFFSET
-#define STM32MP_NOR_FIP_OFFSET U(0x00080000)
-#endif
-#ifndef STM32MP_NAND_FIP_OFFSET
-#define STM32MP_NAND_FIP_OFFSET U(0x00200000)
-#endif
-#endif /* PSA_FWU_SUPPORT */
-
#endif /* STM32MP1_FIP_DEF_H */
diff --git a/plat/st/stm32mp2/aarch64/stm32mp2.S b/plat/st/stm32mp2/aarch64/stm32mp2.S
new file mode 100644
index 0000000..1866b8b
--- /dev/null
+++ b/plat/st/stm32mp2/aarch64/stm32mp2.S
@@ -0,0 +1,11 @@
+/*
+ * Copyright (c) 2023, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+.section .bl2_image
+.incbin BL2_BIN_PATH
+
+.section .dtb_image
+.incbin DTB_BIN_PATH
diff --git a/plat/st/stm32mp2/aarch64/stm32mp2.ld.S b/plat/st/stm32mp2/aarch64/stm32mp2.ld.S
new file mode 100644
index 0000000..48bf424
--- /dev/null
+++ b/plat/st/stm32mp2/aarch64/stm32mp2.ld.S
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2023, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef STM32MP2_LD_S
+#define STM32MP2_LD_S
+
+#include <lib/xlat_tables/xlat_tables_defs.h>
+#include <platform_def.h>
+
+OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
+OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
+
+ENTRY(__BL2_IMAGE_START__)
+
+MEMORY {
+ HEADER (rw) : ORIGIN = 0x00000000, LENGTH = STM32MP_HEADER_RESERVED_SIZE
+ RAM (rwx) : ORIGIN = STM32MP_BINARY_BASE, LENGTH = STM32MP_BINARY_SIZE
+}
+
+SECTIONS
+{
+ /*
+ * TF mapping must conform to ROM code specification.
+ */
+ .header : {
+ __HEADER_START__ = .;
+ KEEP(*(.header))
+ . = ALIGN(4);
+ __HEADER_END__ = .;
+ } >HEADER
+
+ . = STM32MP_BINARY_BASE;
+ .data . : {
+ . = ALIGN(PAGE_SIZE);
+ __DATA_START__ = .;
+ *(.data*)
+
+ /*
+ * dtb.
+ * The strongest and only alignment contraint is MMU 4K page.
+ * Indeed as images below will be removed, 4K pages will be re-used.
+ */
+ . = ( STM32MP_BL2_DTB_BASE - STM32MP_BINARY_BASE );
+ __DTB_IMAGE_START__ = .;
+ *(.dtb_image*)
+ __DTB_IMAGE_END__ = .;
+
+ /*
+ * bl2.
+ * The strongest and only alignment contraint is MMU 4K page.
+ * Indeed as images below will be removed, 4K pages will be re-used.
+ */
+#if SEPARATE_CODE_AND_RODATA
+ . = ( STM32MP_BL2_RO_BASE - STM32MP_BINARY_BASE );
+#else
+ . = ( STM32MP_BL2_BASE - STM32MP_BINARY_BASE );
+#endif
+ __BL2_IMAGE_START__ = .;
+ *(.bl2_image*)
+ __BL2_IMAGE_END__ = .;
+
+ __DATA_END__ = .;
+ } >RAM
+
+ __TF_END__ = .;
+
+}
+#endif /* STM32MP2_LD_S */
diff --git a/plat/st/stm32mp2/aarch64/stm32mp2_helper.S b/plat/st/stm32mp2/aarch64/stm32mp2_helper.S
new file mode 100644
index 0000000..66333ad
--- /dev/null
+++ b/plat/st/stm32mp2/aarch64/stm32mp2_helper.S
@@ -0,0 +1,194 @@
+/*
+ * Copyright (c) 2023, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <asm_macros.S>
+#include <drivers/st/stm32_gpio.h>
+
+#include <platform_def.h>
+
+#define GPIO_TX_SHIFT (DEBUG_UART_TX_GPIO_PORT << 1)
+
+ .globl platform_mem_init
+ .globl plat_secondary_cold_boot_setup
+ .globl plat_is_my_cpu_primary
+ .globl plat_crash_console_init
+ .globl plat_crash_console_flush
+ .globl plat_crash_console_putc
+ .globl plat_report_exception
+
+func platform_mem_init
+ /* Nothing to do, don't need to init SYSRAM */
+ ret
+endfunc platform_mem_init
+
+ /* ---------------------------------------------
+ * void plat_secondary_cold_boot_setup (void);
+ *
+ * Set secondary core in WFI waiting for core reset.
+ * ---------------------------------------------
+ */
+func plat_secondary_cold_boot_setup
+ dsb sy
+ wfi
+ /* This shouldn't be reached */
+ b .
+endfunc plat_secondary_cold_boot_setup
+
+ /* ----------------------------------------------
+ * unsigned int plat_is_my_cpu_primary(void);
+ * This function checks if this is the primary CPU
+ * ----------------------------------------------
+ */
+func plat_is_my_cpu_primary
+ mrs x0, mpidr_el1
+ and x0, x0, #(MPIDR_CPU_MASK)
+ cmp x0, #STM32MP_PRIMARY_CPU
+ cset x0, eq
+ ret
+endfunc plat_is_my_cpu_primary
+
+ /* ---------------------------------------------
+ * int plat_crash_console_init(void)
+ *
+ * Initialize the crash console without a C Runtime stack.
+ * ---------------------------------------------
+ */
+func plat_crash_console_init
+ /* Reset UART peripheral */
+ mov_imm x1, (RCC_BASE + DEBUG_UART_RST_REG)
+ ldr x2, =DEBUG_UART_RST_BIT
+ ldr x0, [x1]
+ orr x0, x0, x2
+ str x0, [x1]
+1:
+ ldr x0, [x1]
+ ands x2, x0, x2
+ beq 1b
+ bic x2, x2, #DEBUG_UART_RST_BIT
+ str x2, [x1]
+2:
+ ldr x0, [x1]
+ ands x2, x0, x2
+ bne 2b
+ /* Enable GPIOs for UART TX */
+ mov_imm x1, (RCC_BASE + DEBUG_UART_TX_GPIO_BANK_CLK_REG)
+ ldr w2, [x1]
+ /* Configure GPIO */
+ orr w2, w2, #DEBUG_UART_TX_GPIO_BANK_CLK_EN
+ str w2, [x1]
+ mov_imm x1, DEBUG_UART_TX_GPIO_BANK_ADDRESS
+ /* Set GPIO mode alternate */
+ ldr w2, [x1, #GPIO_MODE_OFFSET]
+ bic w2, w2, #(GPIO_MODE_MASK << GPIO_TX_SHIFT)
+ orr w2, w2, #(GPIO_MODE_ALTERNATE << GPIO_TX_SHIFT)
+ str w2, [x1, #GPIO_MODE_OFFSET]
+ /* Set GPIO speed low */
+ ldr w2, [x1, #GPIO_SPEED_OFFSET]
+ bic w2, w2, #(GPIO_SPEED_MASK << GPIO_TX_SHIFT)
+ str w2, [x1, #GPIO_SPEED_OFFSET]
+ /* Set no-pull */
+ ldr w2, [x1, #GPIO_PUPD_OFFSET]
+ bic w2, w2, #(GPIO_PULL_MASK << GPIO_TX_SHIFT)
+ str w2, [x1, #GPIO_PUPD_OFFSET]
+ /* Set alternate */
+#if DEBUG_UART_TX_GPIO_PORT >= GPIO_ALT_LOWER_LIMIT
+ ldr w2, [x1, #GPIO_AFRH_OFFSET]
+ bic w2, w2, #(GPIO_ALTERNATE_MASK << \
+ ((DEBUG_UART_TX_GPIO_PORT - GPIO_ALT_LOWER_LIMIT) << 2))
+ orr w2, w2, #(DEBUG_UART_TX_GPIO_ALTERNATE << \
+ ((DEBUG_UART_TX_GPIO_PORT - GPIO_ALT_LOWER_LIMIT) << 2))
+ str w2, [x1, #GPIO_AFRH_OFFSET]
+#else
+ ldr w2, [x1, #GPIO_AFRL_OFFSET]
+ bic w2, w2, #(GPIO_ALTERNATE_MASK << (DEBUG_UART_TX_GPIO_PORT << 2))
+ orr w2, w2, #(DEBUG_UART_TX_GPIO_ALTERNATE << (DEBUG_UART_TX_GPIO_PORT << 2))
+ str w2, [x1, #GPIO_AFRL_OFFSET]
+#endif
+ /* Clear UART clock flexgen divisors, keep enable bit */
+ mov_imm x1, (RCC_BASE + DEBUG_UART_PREDIV_CFGR)
+ mov x2, #0
+ str w2, [x1]
+ mov_imm x1, (RCC_BASE + DEBUG_UART_FINDIV_CFGR)
+ mov x2, #0x40
+ str w2, [x1]
+ /* Enable UART clock, with its source */
+ mov_imm x1, (RCC_BASE + DEBUG_UART_TX_CLKSRC_REG)
+ mov_imm w2, (DEBUG_UART_TX_CLKSRC | RCC_XBARxCFGR_XBARxEN)
+ str w2, [x1]
+ mov_imm x1, (RCC_BASE + DEBUG_UART_TX_EN_REG)
+ ldr w2, [x1]
+ orr w2, w2, #DEBUG_UART_TX_EN
+ str w2, [x1]
+
+ mov_imm x0, STM32MP_DEBUG_USART_BASE
+ mov_imm x1, STM32MP_DEBUG_USART_CLK_FRQ
+ mov_imm x2, STM32MP_UART_BAUDRATE
+ b console_stm32_core_init
+endfunc plat_crash_console_init
+
+func plat_crash_console_flush
+ mov_imm x0, STM32MP_DEBUG_USART_BASE
+ b console_stm32_core_flush
+endfunc plat_crash_console_flush
+
+func plat_crash_console_putc
+ mov_imm x1, STM32MP_DEBUG_USART_BASE
+ cmp x0, #'\n'
+ b.ne 1f
+ mov x15, x30
+ mov x0, #'\r'
+ bl console_stm32_core_putc
+ mov x30, x15
+ mov x0, #'\n'
+1:
+ b console_stm32_core_putc
+endfunc plat_crash_console_putc
+
+#ifdef IMAGE_BL2
+ /* ---------------------------------------------
+ * void plat_report_exception(unsigned int type)
+ * Function to report an unhandled exception
+ * with platform-specific means.
+ * ---------------------------------------------
+ */
+func plat_report_exception
+ mov x8, x30
+
+ adr x4, plat_err_str
+ bl asm_print_str
+
+ adr x4, esr_el3_str
+ bl asm_print_str
+
+ mrs x4, esr_el3
+ bl asm_print_hex
+
+ adr x4, elr_el3_str
+ bl asm_print_str
+
+ mrs x4, elr_el3
+ bl asm_print_hex
+
+ adr x4, far_el3_str
+ bl asm_print_str
+
+ mrs x4, far_el3
+ bl asm_print_hex
+
+ mov x30, x8
+ ret
+endfunc plat_report_exception
+
+.section .rodata.rev_err_str, "aS"
+plat_err_str:
+ .asciz "\nPlatform exception reporting:"
+esr_el3_str:
+ .asciz "\nESR_EL3: "
+elr_el3_str:
+ .asciz "\nELR_EL3: "
+far_el3_str:
+ .asciz "\nFAR_EL3: "
+#endif /* IMAGE_BL2 */
diff --git a/plat/st/stm32mp2/bl2_plat_setup.c b/plat/st/stm32mp2/bl2_plat_setup.c
new file mode 100644
index 0000000..0805756
--- /dev/null
+++ b/plat/st/stm32mp2/bl2_plat_setup.c
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2023, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <cdefs.h>
+#include <stdint.h>
+
+#include <stm32mp_common.h>
+
+void bl2_el3_early_platform_setup(u_register_t arg0 __unused,
+ u_register_t arg1 __unused,
+ u_register_t arg2 __unused,
+ u_register_t arg3 __unused)
+{
+ stm32mp_setup_early_console();
+}
+
+void bl2_platform_setup(void)
+{
+}
+
+void bl2_el3_plat_arch_setup(void)
+{
+}
diff --git a/plat/st/stm32mp2/include/boot_api.h b/plat/st/stm32mp2/include/boot_api.h
new file mode 100644
index 0000000..d3bed76
--- /dev/null
+++ b/plat/st/stm32mp2/include/boot_api.h
@@ -0,0 +1,406 @@
+/*
+ * Copyright (c) 2023, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef BOOT_API_H
+#define BOOT_API_H
+
+#include <stdint.h>
+#include <stdio.h>
+
+/*
+ * Exported constants
+ */
+
+/*
+ * Boot Context related definitions
+ */
+
+/*
+ * Possible value of boot context field 'auth_status'
+ */
+/* No authentication done */
+#define BOOT_API_CTX_AUTH_NO 0x0U
+/* Authentication done and failed */
+#define BOOT_API_CTX_AUTH_FAILED 0x1U
+/* Authentication done and succeeded */
+#define BOOT_API_CTX_AUTH_SUCCESS 0x2U
+
+/*
+ * Possible value of boot context field 'boot_interface_sel'
+ */
+
+/* Value of field 'boot_interface_sel' when no boot occurred */
+#define BOOT_API_CTX_BOOT_INTERFACE_SEL_NO 0x0U
+
+/* Boot occurred on SD */
+#define BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD 0x1U
+
+/* Boot occurred on EMMC */
+#define BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC 0x2U
+
+/* Boot occurred on FMC */
+#define BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC 0x3U
+
+/* Boot occurred on OSPI NOR */
+#define BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_SPI 0x4U
+
+/* Boot occurred on UART */
+#define BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART 0x5U
+
+/* Boot occurred on USB */
+#define BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_USB 0x6U
+
+/* Boot occurred on OSPI NAND */
+#define BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_SPI 0x7U
+
+/* Boot occurred on HyperFlash QSPI */
+#define BOOT_API_CTX_BOOT_INTERFACE_SEL_HYPERFLASH_OSPI 0x8U
+
+/*
+ * Possible value of boot context field 'emmc_xfer_status'
+ */
+#define BOOT_API_CTX_EMMC_XFER_STATUS_NOT_STARTED 0x0U
+#define BOOT_API_CTX_EMMC_XFER_STATUS_DATAEND_DETECTED 0x1U
+#define BOOT_API_CTX_EMMC_XFER_STATUS_XFER_DATA_TIMEOUT 0x2U
+
+/*
+ * Possible value of boot context field 'emmc_error_status'
+ */
+#define BOOT_API_CTX_EMMC_ERROR_STATUS_NONE 0x0U
+#define BOOT_API_CTX_EMMC_ERROR_STATUS_CMD_TIMEOUT 0x1U
+#define BOOT_API_CTX_EMMC_ERROR_STATUS_ACK_TIMEOUT 0x2U
+#define BOOT_API_CTX_EMMC_ERROR_STATUS_DATA_CRC_FAIL 0x3U
+#define BOOT_API_CTX_EMMC_ERROR_STATUS_NOT_ENOUGH_BOOT_DATA_RX 0x4U
+#define BOOT_API_CTX_EMMC_ERROR_STATUS_HEADER_NOT_FOUND 0x5U
+#define BOOT_API_CTX_EMMC_ERROR_STATUS_HEADER_SIZE_ZERO 0x6U
+#define BOOT_API_CTX_EMMC_ERROR_STATUS_IMAGE_NOT_COMPLETE 0x7U
+#define BOOT_API_CTX_EMMC_ERROR_STATUS_ACK_ERROR 0x8U
+
+/* Definitions relative to 'p_rom_version_info->platform_type_ver' field */
+#define BOOT_API_CTX_ROM_VERSION_PLAT_VER_IC_EMU_FPGA 0xAA
+#define BOOT_API_CTX_ROM_VERSION_PLAT_VER_FPGA_ONLY 0xBB
+
+/* Image Header related definitions */
+
+/* Definition of header version */
+#define BOOT_API_HEADER_VERSION 0x00020000U
+
+/*
+ * Magic number used to detect header in memory
+ * Its value must be 'S' 'T' 'M' 0x32, i.e 0x324D5453 as field
+ * 'bootapi_image_header_t.magic'
+ * This identifies the start of a boot image.
+ */
+#define BOOT_API_IMAGE_HEADER_MAGIC_NB 0x324D5453U
+
+/* Definitions related to Authentication used in image header structure */
+#define BOOT_API_ECDSA_PUB_KEY_LEN_IN_BYTES 64
+#define BOOT_API_ECDSA_SIGNATURE_LEN_IN_BYTES 64
+#define BOOT_API_SHA256_DIGEST_SIZE_IN_BYTES 32
+
+/* Possible values of the field 'boot_api_image_header_t.ecc_algo_type' */
+#define BOOT_API_ECDSA_ALGO_TYPE_P256NIST 1
+#define BOOT_API_ECDSA_ALGO_TYPE_BRAINPOOL256 2
+
+/*
+ * Extension headers related definitions
+ */
+/* 'bootapi_image_header_t.extension_flag' used for authentication feature */
+#define BOOT_API_AUTHENTICATION_EXTENSION_BIT BIT(0)
+/* 'bootapi_image_header_t.extension_flag' used for FSBL decryption feature */
+#define BOOT_API_FSBL_DECRYPTION_EXTENSION_BIT BIT(1)
+/* 'bootapi_image_header_t.extension_flag' used for padding header feature */
+#define BOOT_API_PADDING_EXTENSION_BIT BIT(31)
+/*
+ * mask of bits of field 'bootapi_image_header_t.extension_flag'
+ * used for extension headers
+ */
+#define BOOT_API_ALL_EXTENSIONS_MASK \
+ (BOOT_API_AUTHENTICATION_EXTENSION_BIT | \
+ BOOT_API_FSBL_DECRYPTION_EXTENSION_BIT | \
+ BOOT_API_PADDING_EXTENSION_BIT)
+/*
+ * Magic number of FSBL decryption extension header
+ * The value shall gives the four bytes 'S','T',0x00,0x01 in memory
+ */
+#define BOOT_API_FSBL_DECRYPTION_HEADER_MAGIC_NB 0x01005453U
+
+/*
+ * Magic number of PKH revocation extension header
+ * The value shall gives the four bytes 'S','T',0x00,0x02 in memory
+ */
+#define BOOT_API_AUTHENTICATION_HEADER_MAGIC_NB 0x02005453U
+
+/* Max number of ECDSA public key hash in table */
+#define BOOT_API_AUTHENTICATION_NB_PKH_MAX 8U
+
+/* ECDSA public key hash table size in bytes */
+#define BOOT_API_AUTHENTICATION_TABLE_SIZE_BYTES \
+ (BOOT_API_AUTHENTICATION_NB_PKH_MAX * \
+ BOOT_API_SHA256_DIGEST_SIZE_IN_BYTES)
+
+/*
+ * Magic number of padding extension header
+ * The value shall gives the four bytes 'S','T',0xFF,0xFF in memory
+ */
+#define BOOT_API_PADDING_HEADER_MAGIC_NB 0xFFFF5453U
+
+/*
+ * Related to binaryType
+ * 0x00: U-Boot
+ * 0x10-0x1F: TF-A
+ * 0x20-0X2F: OPTEE
+ * 0x30: CM33 image
+ */
+#define BOOT_API_IMAGE_TYPE_UBOOT 0x0
+#define BOOT_API_IMAGE_TYPE_M33 0x30
+
+/*
+ * Cores secure magic numbers
+ * Constant to be stored in bakcup register
+ * BOOT_API_MAGIC_NUMBER_TAMP_BCK_REG_IDX
+ */
+#define BOOT_API_A35_CORE0_MAGIC_NUMBER 0xCA7FACE0U
+#define BOOT_API_A35_CORE1_MAGIC_NUMBER 0xCA7FACE1U
+
+/*
+ * TAMP_BCK9R register index
+ * This register is used to write a Magic Number in order to restart
+ * Cortex A35 Core 1 and make it execute @ branch address from TAMP_BCK5R
+ */
+#define BOOT_API_CORE1_MAGIC_NUMBER_TAMP_BCK_REG_IDX 9U
+
+/*
+ * TAMP_BCK10R register index
+ * This register is used to contain the branch address of
+ * Cortex A35 Core 1 when restarted by a TAMP_BCK4R magic number writing
+ */
+#define BOOT_API_CORE1_BRANCH_ADDRESS_TAMP_BCK_REG_IDX 10U
+
+/*
+ * Possible value of boot context field 'hse_clock_value_in_hz'
+ */
+#define BOOT_API_CTX_HSE_CLOCK_VALUE_UNDEFINED 0U
+#define BOOT_API_CTX_HSE_CLOCK_VALUE_19_2_MHZ 19200000U
+#define BOOT_API_CTX_HSE_CLOCK_VALUE_24_MHZ 24000000U
+#define BOOT_API_CTX_HSE_CLOCK_VALUE_25_MHZ 25000000U
+#define BOOT_API_CTX_HSE_CLOCK_VALUE_26_MHZ 26000000U
+#define BOOT_API_CTX_HSE_CLOCK_VALUE_40_MHZ 40000000U
+#define BOOT_API_CTX_HSE_CLOCK_VALUE_48_MHZ 48000000U
+
+/*
+ * Possible value of boot context field 'boot_partition_used_toboot'
+ */
+#define BOOT_API_CTX_BOOT_PARTITION_UNDEFINED 0U
+
+/* Used FSBL1 to boot */
+#define BOOT_API_CTX_BOOT_PARTITION_FSBL1 1U
+
+/* Used FSBL2 to boot */
+#define BOOT_API_CTX_BOOT_PARTITION_FSBL2 2U
+
+#define BOOT_API_RETURN_OK 0x66U
+
+/*
+ * Possible values of boot context field
+ * 'ssp_config_ptr_in->ssp_cmd'
+ */
+/* 'K' 'B' 'U' 'P' -.> 'PUBK' */
+#define BOOT_API_CTX_SSP_CMD_CALC_CHIP_PUBK 0x4B425550
+
+/*
+ * Exported types
+ */
+
+/*
+ * bootROM version information structure definition
+ * Total size = 24 bytes = 6 uint32_t
+ */
+typedef struct {
+ /* Chip Version */
+ uint32_t chip_ver;
+
+ /* Cut version within a fixed chip version */
+ uint32_t cut_ver;
+
+ /* Version of ROM Mask within a fixed cut version */
+ uint32_t rom_mask_ver;
+
+ /* Internal Version of bootROM code */
+ uint32_t bootrom_ver;
+
+ /* Version of bootROM adapted */
+ uint32_t for_chip_design_rtl_ver;
+
+ /* Restriction on compiled platform when it applies */
+ uint32_t platform_type_ver;
+} boot_api_rom_version_info_t;
+
+/*
+ * Boot Context related definitions
+ */
+
+/*
+ * Boot core boot configuration structure
+ * Specifies all items of the secure boot configuration
+ * Memory and peripheral part.
+ */
+typedef struct {
+ /* Boot partition: ie FSBL partition on which the boot was successful */
+ uint32_t boot_partition_used_toboot;
+
+ uint32_t reserved1[3];
+
+ /*
+ * Information specific to an SD boot
+ * Updated each time an SD boot is at least attempted,
+ * even if not successful
+ * Note : This is useful to understand why an SD boot failed
+ * in particular
+ */
+ uint32_t sd_err_internal_timeout_cnt;
+ uint32_t sd_err_dcrc_fail_cnt;
+ uint32_t sd_err_dtimeout_cnt;
+ uint32_t sd_err_ctimeout_cnt;
+ uint32_t sd_err_ccrc_fail_cnt;
+ uint32_t sd_overall_retry_cnt;
+ /*
+ * Information specific to an eMMC boot
+ * Updated each time an eMMC boot is at least attempted,
+ * even if not successful
+ * Note : This is useful to understand why an eMMC boot failed
+ * in particular
+ */
+ uint32_t emmc_xfer_status;
+ uint32_t emmc_error_status;
+ uint32_t emmc_nbbytes_rxcopied_tosysram_download_area;
+
+ uint32_t reserved[4];
+ /*
+ * Boot interface used to boot : take values from defines
+ * BOOT_API_CTX_BOOT_INTERFACE_SEL_XXX above
+ */
+ uint16_t boot_interface_selected;
+ uint16_t boot_interface_instance;
+
+ uint32_t hse_clock_value_in_hz;
+
+ uint32_t nand_fsbl_first_block;
+
+ /*
+ * Returned authentication status : take values from defines
+ * BOOT_API_CTX_AUTH_XXX above
+ */
+ uint32_t auth_status;
+
+ /* Pointer on ROM constant containing ROM information */
+ const boot_api_rom_version_info_t *p_rom_version_info;
+} __packed boot_api_context_t;
+
+/*
+ * Image Header related definitions
+ */
+
+/*
+ * Structure used to define the common Header format used for FSBL, xloader,
+ * ... and in particular used by bootROM for FSBL header readout.
+ * FSBL header size is 256 Bytes = 0x100
+ */
+typedef struct {
+ /* BOOT_API_IMAGE_HEADER_MAGIC_NB */
+ uint32_t magic;
+ uint8_t image_signature[BOOT_API_ECDSA_SIGNATURE_LEN_IN_BYTES];
+ /*
+ * Checksum of payload
+ * 32-bit sum all payload bytes considered as 8 bit unsigned
+ * numbers, discarding any overflow bits.
+ * Use to check UART/USB downloaded image integrity when signature
+ * is not used
+ */
+ uint32_t payload_checksum;
+ /* Image header version : should have value BOOT_API_HEADER_VERSION */
+ uint32_t header_version;
+ /* Image length in bytes */
+ uint32_t image_length;
+ /*
+ * Image Entry point address : should be in the SYSRAM area
+ * and at least within the download area range
+ */
+ uint32_t image_entry_point;
+ /* Reserved */
+ uint32_t reserved1;
+ /*
+ * Image load address : not used by bootROM but to be consistent
+ * with header format for other packages (xloader, ...)
+ */
+ uint32_t load_address;
+ /* Reserved */
+ uint32_t reserved2;
+ /* Image version to be compared by bootROM with FSBL_A or FSBL_M version
+ * counter value in OTP prior executing the downloaded image
+ */
+ uint32_t image_version;
+ /*
+ * Extension flags :
+ *
+ * Bit 0 : Authentication extension header
+ * value 0 : No signature check request
+ * Bit 1 : Encryption extension header
+ * Bit 2 : Padding extension header
+ */
+ uint32_t extension_flags;
+ /* Length in bytes of all extension headers */
+ uint32_t extension_headers_length;
+ /* Add binary type information */
+ uint32_t binary_type;
+ /* Pad up to 128 byte total size */
+ uint8_t pad[16];
+ /* Followed by extension header */
+ uint8_t ext_header[];
+} __packed boot_api_image_header_t;
+
+typedef uint8_t boot_api_sha256_t[BOOT_API_SHA256_DIGEST_SIZE_IN_BYTES];
+
+typedef struct {
+ /* Extension header type:
+ * BOOT_API_FSBL_DECRYPTION_HEADER_MAGIC_NB or
+ * BOOT_API_AUTHENTICATION_HEADER_MAGIC_NB
+ * BOOT_API_PADDING_HEADER_MAGIC_NB
+ */
+ uint32_t type;
+ /* Extension header len in byte */
+ uint32_t len;
+ /* parameters of this extension */
+ uint8_t params[];
+} __packed boot_extension_header_t;
+
+typedef struct {
+ /* Idx of ECDSA public key to be used in table */
+ uint32_t pk_idx;
+ /* Number of ECDSA public key in table */
+ uint32_t nb_pk;
+ /*
+ * Type of ECC algorithm to use :
+ * value 1 : for P-256 NIST algorithm
+ * value 2 : for Brainpool 256 algorithm
+ * See definitions 'BOOT_API_ECDSA_ALGO_TYPE_XXX' above.
+ */
+ uint32_t ecc_algo_type;
+ /* ECDSA public key to be used to check signature. */
+ uint8_t ecc_pubk[BOOT_API_ECDSA_PUB_KEY_LEN_IN_BYTES];
+ /* table of Hash of Algo+ECDSA public key */
+ boot_api_sha256_t pk_hashes[];
+} __packed boot_ext_header_params_authentication_t;
+
+typedef struct {
+ /* Size of encryption key (128 or 256) */
+ uint32_t key_size;
+ uint32_t derivation_cont;
+ /* 128 msb bits of plain payload SHA256 */
+ uint32_t hash[4];
+} __packed boot_ext_header_params_encrypted_fsbl_t;
+
+#endif /* BOOT_API_H */
diff --git a/plat/st/stm32mp2/include/plat_macros.S b/plat/st/stm32mp2/include/plat_macros.S
new file mode 100644
index 0000000..e5be2c8
--- /dev/null
+++ b/plat/st/stm32mp2/include/plat_macros.S
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2023, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLAT_MACROS_S
+#define PLAT_MACROS_S
+
+ .macro plat_crash_print_regs
+ .endm
+
+#endif /* PLAT_MACROS_S */
diff --git a/plat/st/stm32mp2/include/platform_def.h b/plat/st/stm32mp2/include/platform_def.h
new file mode 100644
index 0000000..404c384
--- /dev/null
+++ b/plat/st/stm32mp2/include/platform_def.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2023, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
+
+#include <arch.h>
+#include <lib/utils_def.h>
+#include <plat/common/common_def.h>
+
+#include "../stm32mp2_def.h"
+
+/*******************************************************************************
+ * Generic platform constants
+ ******************************************************************************/
+
+/* Size of cacheable stacks */
+#define PLATFORM_STACK_SIZE 0xC00
+
+#define STM32MP_PRIMARY_CPU U(0x0)
+#define STM32MP_SECONDARY_CPU U(0x1)
+
+#define MAX_IO_DEVICES U(4)
+#define MAX_IO_HANDLES U(4)
+#define MAX_IO_BLOCK_DEVICES U(1)
+#define MAX_IO_MTD_DEVICES U(1)
+
+#define PLATFORM_CLUSTER_COUNT U(1)
+#define PLATFORM_CORE_COUNT U(2)
+#define PLATFORM_MAX_CPUS_PER_CLUSTER U(2)
+
+#define PLAT_MAX_PWR_LVL U(5)
+#define PLAT_MAX_CPU_SUSPEND_PWR_LVL U(5)
+#define PLAT_NUM_PWR_DOMAINS U(7)
+
+/* Local power state for power domains in Run state. */
+#define STM32MP_LOCAL_STATE_RUN U(0)
+/* Local power state for retention. */
+#define STM32MP_LOCAL_STATE_RET U(1)
+#define STM32MP_LOCAL_STATE_LP U(2)
+#define PLAT_MAX_RET_STATE STM32MP_LOCAL_STATE_LP
+/* Local power state for OFF/power-down. */
+#define STM32MP_LOCAL_STATE_OFF U(3)
+#define PLAT_MAX_OFF_STATE STM32MP_LOCAL_STATE_OFF
+
+/* Macros to parse the state information from State-ID (recommended encoding) */
+#define PLAT_LOCAL_PSTATE_WIDTH U(4)
+#define PLAT_LOCAL_PSTATE_MASK GENMASK(PLAT_LOCAL_PSTATE_WIDTH - 1U, 0)
+
+/*******************************************************************************
+ * BL2 specific defines.
+ ******************************************************************************/
+/*
+ * Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug
+ * size plus a little space for growth.
+ */
+#define BL2_BASE STM32MP_BL2_BASE
+#define BL2_LIMIT (STM32MP_BL2_BASE + \
+ STM32MP_BL2_SIZE)
+
+/*******************************************************************************
+ * BL33 specific defines.
+ ******************************************************************************/
+#define BL33_BASE STM32MP_BL33_BASE
+
+/*******************************************************************************
+ * Platform specific page table and MMU setup constants
+ ******************************************************************************/
+#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 33)
+#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 33)
+
+/*******************************************************************************
+ * Declarations and constants to access the mailboxes safely. Each mailbox is
+ * aligned on the biggest cache line size in the platform. This is known only
+ * to the platform as it might have a combination of integrated and external
+ * caches. Such alignment ensures that two maiboxes do not sit on the same cache
+ * line at any cache level. They could belong to different cpus/clusters &
+ * get written while being protected by different locks causing corruption of
+ * a valid mailbox address.
+ ******************************************************************************/
+#define CACHE_WRITEBACK_SHIFT 6
+#define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT)
+
+#endif /* PLATFORM_DEF_H */
diff --git a/plat/st/stm32mp2/plat_bl2_mem_params_desc.c b/plat/st/stm32mp2/plat_bl2_mem_params_desc.c
new file mode 100644
index 0000000..630cc84
--- /dev/null
+++ b/plat/st/stm32mp2/plat_bl2_mem_params_desc.c
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2023, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/desc_image_load.h>
+
+/*******************************************************************************
+ * Following descriptor provides BL image/ep information that gets used
+ * by BL2 to load the images and also subset of this information is
+ * passed to next BL image. The image loading sequence is managed by
+ * populating the images in required loading order. The image execution
+ * sequence is managed by populating the `next_handoff_image_id` with
+ * the next executable image id.
+ ******************************************************************************/
+static bl_mem_params_node_t bl2_mem_params_descs[] = {
+};
+
+REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs)
diff --git a/plat/st/stm32mp2/platform.mk b/plat/st/stm32mp2/platform.mk
new file mode 100644
index 0000000..6ea4638
--- /dev/null
+++ b/plat/st/stm32mp2/platform.mk
@@ -0,0 +1,52 @@
+#
+# Copyright (c) 2023, STMicroelectronics - All Rights Reserved
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+include plat/st/common/common.mk
+
+CRASH_REPORTING := 1
+ENABLE_PIE := 1
+PROGRAMMABLE_RESET_ADDRESS := 1
+
+# Default Device tree
+DTB_FILE_NAME ?= stm32mp257f-ev1.dtb
+
+STM32MP25 := 1
+
+# STM32 image header version v2.2
+STM32_HEADER_VERSION_MAJOR := 2
+STM32_HEADER_VERSION_MINOR := 2
+
+# Number of TF-A copies in the device
+STM32_TF_A_COPIES := 2
+
+# PLAT_PARTITION_MAX_ENTRIES must take care of STM32_TF-A_COPIES and other partitions
+# such as metadata (2) and fsbl-m (2) to find all the FIP partitions (default is 2).
+PLAT_PARTITION_MAX_ENTRIES := $(shell echo $$(($(STM32_TF_A_COPIES) + 6)))
+
+# Device tree
+BL2_DTSI := stm32mp25-bl2.dtsi
+FDT_SOURCES := $(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl2.dts,$(DTB_FILE_NAME)))
+
+# Macros and rules to build TF binary
+STM32_TF_STM32 := $(addprefix ${BUILD_PLAT}/tf-a-, $(patsubst %.dtb,%.stm32,$(DTB_FILE_NAME)))
+STM32_LD_FILE := plat/st/stm32mp2/${ARCH}/stm32mp2.ld.S
+STM32_BINARY_MAPPING := plat/st/stm32mp2/${ARCH}/stm32mp2.S
+
+# STM32MP2x is based on Cortex-A35, which is Armv8.0, and does not support BTI
+# Disable mbranch-protection to avoid adding useless code
+TF_CFLAGS += -mbranch-protection=none
+
+# Include paths and source files
+PLAT_INCLUDES += -Iplat/st/stm32mp2/include/
+
+PLAT_BL_COMMON_SOURCES += lib/cpus/${ARCH}/cortex_a35.S
+PLAT_BL_COMMON_SOURCES += drivers/st/uart/${ARCH}/stm32_console.S
+PLAT_BL_COMMON_SOURCES += plat/st/stm32mp2/${ARCH}/stm32mp2_helper.S
+
+BL2_SOURCES += plat/st/stm32mp2/plat_bl2_mem_params_desc.c
+BL2_SOURCES += plat/st/stm32mp2/bl2_plat_setup.c
+
+include plat/st/common/common_rules.mk
diff --git a/plat/st/stm32mp2/stm32mp2_def.h b/plat/st/stm32mp2/stm32mp2_def.h
new file mode 100644
index 0000000..66514fc
--- /dev/null
+++ b/plat/st/stm32mp2/stm32mp2_def.h
@@ -0,0 +1,222 @@
+/*
+ * Copyright (c) 2023, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef STM32MP2_DEF_H
+#define STM32MP2_DEF_H
+
+#include <common/tbbr/tbbr_img_def.h>
+#ifndef __ASSEMBLER__
+#include <drivers/st/bsec.h>
+#endif
+#include <drivers/st/stm32mp25_rcc.h>
+#include <dt-bindings/clock/stm32mp25-clks.h>
+#include <dt-bindings/clock/stm32mp25-clksrc.h>
+#include <dt-bindings/reset/stm32mp25-resets.h>
+
+#ifndef __ASSEMBLER__
+#include <boot_api.h>
+#include <stm32mp_common.h>
+#include <stm32mp_dt.h>
+#include <stm32mp_shared_resources.h>
+#endif
+
+/*******************************************************************************
+ * STM32MP2 memory map related constants
+ ******************************************************************************/
+#define STM32MP_SYSRAM_BASE U(0x0E000000)
+#define STM32MP_SYSRAM_SIZE U(0x00040000)
+
+#define STM32MP_SEC_SYSRAM_BASE STM32MP_SYSRAM_BASE
+#define STM32MP_SEC_SYSRAM_SIZE STM32MP_SYSRAM_SIZE
+
+/* DDR configuration */
+#define STM32MP_DDR_BASE U(0x80000000)
+#define STM32MP_DDR_MAX_SIZE UL(0x100000000) /* Max 4GB */
+
+/* DDR power initializations */
+#ifndef __ASSEMBLER__
+enum ddr_type {
+ STM32MP_DDR3,
+ STM32MP_DDR4,
+ STM32MP_LPDDR4
+};
+#endif
+
+/* Section used inside TF binaries */
+#define STM32MP_PARAM_LOAD_SIZE U(0x00002400) /* 9 KB for param */
+/* 512 Octets reserved for header */
+#define STM32MP_HEADER_SIZE U(0x00000200)
+#define STM32MP_HEADER_BASE (STM32MP_SEC_SYSRAM_BASE + \
+ STM32MP_PARAM_LOAD_SIZE)
+
+/* round_up(STM32MP_PARAM_LOAD_SIZE + STM32MP_HEADER_SIZE, PAGE_SIZE) */
+#define STM32MP_HEADER_RESERVED_SIZE U(0x3000)
+
+#define STM32MP_BINARY_BASE (STM32MP_SEC_SYSRAM_BASE + \
+ STM32MP_PARAM_LOAD_SIZE + \
+ STM32MP_HEADER_SIZE)
+
+#define STM32MP_BINARY_SIZE (STM32MP_SEC_SYSRAM_SIZE - \
+ (STM32MP_PARAM_LOAD_SIZE + \
+ STM32MP_HEADER_SIZE))
+
+#define STM32MP_BL2_SIZE U(0x0002A000) /* 168 KB for BL2 */
+
+#define STM32MP_BL2_BASE (STM32MP_SEC_SYSRAM_BASE + \
+ STM32MP_SEC_SYSRAM_SIZE - \
+ STM32MP_BL2_SIZE)
+
+/* BL2 and BL32/sp_min require 4 tables */
+#define MAX_XLAT_TABLES U(4) /* 16 KB for mapping */
+
+/*
+ * MAX_MMAP_REGIONS is usually:
+ * BL stm32mp2_mmap size + mmap regions in *_plat_arch_setup
+ */
+#define MAX_MMAP_REGIONS 6
+
+/* DTB initialization value */
+#define STM32MP_BL2_DTB_SIZE U(0x00005000) /* 20 KB for DTB */
+
+#define STM32MP_BL2_DTB_BASE (STM32MP_BL2_BASE - \
+ STM32MP_BL2_DTB_SIZE)
+
+#define STM32MP_BL33_BASE (STM32MP_DDR_BASE + U(0x04000000))
+#define STM32MP_BL33_MAX_SIZE U(0x400000)
+
+/*******************************************************************************
+ * STM32MP2 RCC
+ ******************************************************************************/
+#define RCC_BASE U(0x44200000)
+
+/*******************************************************************************
+ * STM32MP2 PWR
+ ******************************************************************************/
+#define PWR_BASE U(0x44210000)
+
+/*******************************************************************************
+ * STM32MP2 GPIO
+ ******************************************************************************/
+#define GPIOA_BASE U(0x44240000)
+#define GPIOB_BASE U(0x44250000)
+#define GPIOC_BASE U(0x44260000)
+#define GPIOD_BASE U(0x44270000)
+#define GPIOE_BASE U(0x44280000)
+#define GPIOF_BASE U(0x44290000)
+#define GPIOG_BASE U(0x442A0000)
+#define GPIOH_BASE U(0x442B0000)
+#define GPIOI_BASE U(0x442C0000)
+#define GPIOJ_BASE U(0x442D0000)
+#define GPIOK_BASE U(0x442E0000)
+#define GPIOZ_BASE U(0x46200000)
+#define GPIO_BANK_OFFSET U(0x10000)
+
+#define STM32MP_GPIOS_PIN_MAX_COUNT 16
+#define STM32MP_GPIOZ_PIN_MAX_COUNT 8
+
+/*******************************************************************************
+ * STM32MP2 UART
+ ******************************************************************************/
+#define USART1_BASE U(0x40330000)
+#define USART2_BASE U(0x400E0000)
+#define USART3_BASE U(0x400F0000)
+#define UART4_BASE U(0x40100000)
+#define UART5_BASE U(0x40110000)
+#define USART6_BASE U(0x40220000)
+#define UART7_BASE U(0x40370000)
+#define UART8_BASE U(0x40380000)
+#define UART9_BASE U(0x402C0000)
+#define STM32MP_NB_OF_UART U(9)
+
+/* For UART crash console */
+#define STM32MP_DEBUG_USART_CLK_FRQ 64000000
+/* USART2 on HSI@64MHz, TX on GPIOA4 Alternate 6 */
+#define STM32MP_DEBUG_USART_BASE USART2_BASE
+#define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOA_BASE
+#define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_GPIOACFGR
+#define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_GPIOxCFGR_GPIOxEN
+#define DEBUG_UART_TX_GPIO_PORT 4
+#define DEBUG_UART_TX_GPIO_ALTERNATE 6
+#define DEBUG_UART_TX_CLKSRC_REG RCC_XBAR8CFGR
+#define DEBUG_UART_TX_CLKSRC XBAR_SRC_HSI
+#define DEBUG_UART_TX_EN_REG RCC_USART2CFGR
+#define DEBUG_UART_TX_EN RCC_UARTxCFGR_UARTxEN
+#define DEBUG_UART_RST_REG RCC_USART2CFGR
+#define DEBUG_UART_RST_BIT RCC_UARTxCFGR_UARTxRST
+#define DEBUG_UART_PREDIV_CFGR RCC_PREDIV8CFGR
+#define DEBUG_UART_FINDIV_CFGR RCC_FINDIV8CFGR
+
+/*******************************************************************************
+ * STM32MP2 SDMMC
+ ******************************************************************************/
+#define STM32MP_SDMMC1_BASE U(0x48220000)
+#define STM32MP_SDMMC2_BASE U(0x48230000)
+#define STM32MP_SDMMC3_BASE U(0x48240000)
+
+/*******************************************************************************
+ * STM32MP2 TAMP
+ ******************************************************************************/
+#define PLAT_MAX_TAMP_INT U(5)
+#define PLAT_MAX_TAMP_EXT U(3)
+#define TAMP_BASE U(0x46010000)
+#define TAMP_SMCR (TAMP_BASE + U(0x20))
+#define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100))
+#define TAMP_BKP_REG_CLK CK_BUS_RTC
+#define TAMP_BKP_SEC_NUMBER U(10)
+#define TAMP_COUNTR U(0x40)
+
+#if !(defined(__LINKER__) || defined(__ASSEMBLER__))
+static inline uintptr_t tamp_bkpr(uint32_t idx)
+{
+ return TAMP_BKP_REGISTER_BASE + (idx << 2);
+}
+#endif
+
+/*******************************************************************************
+ * STM32MP2 DDRCTRL
+ ******************************************************************************/
+#define DDRCTRL_BASE U(0x48040000)
+
+/*******************************************************************************
+ * STM32MP2 DDRDBG
+ ******************************************************************************/
+#define DDRDBG_BASE U(0x48050000)
+
+/*******************************************************************************
+ * STM32MP2 DDRPHYC
+ ******************************************************************************/
+#define DDRPHYC_BASE U(0x48C00000)
+
+/*******************************************************************************
+ * Miscellaneous STM32MP1 peripherals base address
+ ******************************************************************************/
+#define BSEC_BASE U(0x44000000)
+#define DBGMCU_BASE U(0x4A010000)
+#define HASH_BASE U(0x42010000)
+#define RTC_BASE U(0x46000000)
+#define STGEN_BASE U(0x48080000)
+#define SYSCFG_BASE U(0x44230000)
+
+/*******************************************************************************
+ * REGULATORS
+ ******************************************************************************/
+/* 3 PWR + 1 VREFBUF + 14 PMIC regulators + 1 FIXED */
+#define PLAT_NB_RDEVS U(19)
+/* 2 FIXED */
+#define PLAT_NB_FIXED_REGUS U(2)
+/* No GPIO regu */
+#define PLAT_NB_GPIO_REGUS U(0)
+
+/*******************************************************************************
+ * Device Tree defines
+ ******************************************************************************/
+#define DT_BSEC_COMPAT "st,stm32mp25-bsec"
+#define DT_DDR_COMPAT "st,stm32mp2-ddr"
+#define DT_PWR_COMPAT "st,stm32mp25-pwr"
+#define DT_RCC_CLK_COMPAT "st,stm32mp25-rcc"
+#define DT_UART_COMPAT "st,stm32h7-uart"
+
+#endif /* STM32MP2_DEF_H */
diff --git a/plat/xilinx/common/plat_fdt.c b/plat/xilinx/common/plat_fdt.c
index 7f93340..911f664 100644
--- a/plat/xilinx/common/plat_fdt.c
+++ b/plat/xilinx/common/plat_fdt.c
@@ -8,6 +8,7 @@
#include <common/fdt_fixup.h>
#include <common/fdt_wrappers.h>
#include <libfdt.h>
+#include <lib/xlat_tables/xlat_tables_v2.h>
#include <plat_fdt.h>
#include <platform_def.h>
@@ -24,6 +25,17 @@
if (IS_TFA_IN_OCM(BL31_BASE))
return;
+#if defined(PLAT_XLAT_TABLES_DYNAMIC)
+ ret = mmap_add_dynamic_region((unsigned long long)dtb,
+ (uintptr_t)dtb,
+ XILINX_OF_BOARD_DTB_MAX_SIZE,
+ MT_MEMORY | MT_RW | MT_NS);
+ if (ret != 0) {
+ WARN("Failed to add dynamic region for dtb: error %d\n", ret);
+ return;
+ }
+#endif
+
/* Return if no device tree is detected */
if (fdt_check_header(dtb) != 0) {
NOTICE("Can't read DT at %p\n", dtb);
@@ -37,7 +49,7 @@
}
/* Reserve memory used by Trusted Firmware. */
- if (fdt_add_reserved_memory(dtb, "tf-a", BL31_BASE, BL31_LIMIT - BL31_BASE + 1)) {
+ if (fdt_add_reserved_memory(dtb, "tf-a", BL31_BASE, BL31_LIMIT - BL31_BASE)) {
WARN("Failed to add reserved memory nodes for BL31 to DT.\n");
return;
}
@@ -48,6 +60,16 @@
return;
}
+ flush_dcache_range((uintptr_t)dtb, fdt_blob_size(dtb));
+
+#if defined(PLAT_XLAT_TABLES_DYNAMIC)
+ ret = mmap_remove_dynamic_region((uintptr_t)dtb,
+ XILINX_OF_BOARD_DTB_MAX_SIZE);
+ if (ret != 0) {
+ WARN("Failed to remove dynamic region for dtb: error %d\n", ret);
+ return;
+ }
+#endif
+
- clean_dcache_range((uintptr_t)dtb, fdt_blob_size(dtb));
INFO("Changed device tree to advertise PSCI and reserved memories.\n");
}
diff --git a/plat/xilinx/versal/bl31_versal_setup.c b/plat/xilinx/versal/bl31_versal_setup.c
index 6cb529b..c50f06f 100644
--- a/plat/xilinx/versal/bl31_versal_setup.c
+++ b/plat/xilinx/versal/bl31_versal_setup.c
@@ -224,7 +224,8 @@
plat_arm_interconnect_enter_coherency();
const mmap_region_t bl_regions[] = {
-#if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE))
+#if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE) && \
+ (!defined(PLAT_XLAT_TABLES_DYNAMIC)))
MAP_REGION_FLAT(XILINX_OF_BOARD_DTB_ADDR, XILINX_OF_BOARD_DTB_MAX_SIZE,
MT_MEMORY | MT_RW | MT_NS),
#endif
diff --git a/plat/xilinx/versal/platform.mk b/plat/xilinx/versal/platform.mk
index c936220..a052713 100644
--- a/plat/xilinx/versal/platform.mk
+++ b/plat/xilinx/versal/platform.mk
@@ -49,6 +49,11 @@
$(eval $(call add_define,XILINX_OF_BOARD_DTB_ADDR))
endif
+PLAT_XLAT_TABLES_DYNAMIC := 0
+ifeq (${PLAT_XLAT_TABLES_DYNAMIC},1)
+$(eval $(call add_define,PLAT_XLAT_TABLES_DYNAMIC))
+endif
+
PLAT_INCLUDES := -Iinclude/plat/arm/common/ \
-Iplat/xilinx/common/include/ \
-Iplat/xilinx/common/ipi_mailbox_service/ \
diff --git a/poetry.lock b/poetry.lock
index 12d546a..08b2b37 100644
--- a/poetry.lock
+++ b/poetry.lock
@@ -1,4 +1,4 @@
-# This file is automatically @generated by Poetry 1.5.0 and should not be changed by hand.
+# This file is automatically @generated by Poetry 1.6.1 and should not be changed by hand.
[[package]]
name = "alabaster"
@@ -556,13 +556,13 @@
[[package]]
name = "requests"
-version = "2.30.0"
+version = "2.31.0"
description = "Python HTTP for Humans."
optional = false
python-versions = ">=3.7"
files = [
- {file = "requests-2.30.0-py3-none-any.whl", hash = "sha256:10e94cc4f3121ee6da529d358cdaeaff2f1c409cd377dbc72b825852f2f7e294"},
- {file = "requests-2.30.0.tar.gz", hash = "sha256:239d7d4458afcb28a692cdd298d87542235f4ca8d36d03a15bfc128a6559a2f4"},
+ {file = "requests-2.31.0-py3-none-any.whl", hash = "sha256:58cd2187c01e70e6e26505bca751777aa9f2ee0b7f4300988b709f44e013003f"},
+ {file = "requests-2.31.0.tar.gz", hash = "sha256:942c5a758f98d790eaed1a29cb6eefc7ffb0d1cf7af05c3d2791656dbd6ad1e1"},
]
[package.dependencies]
diff --git a/services/std_svc/errata_abi/cpu_errata_info.h b/services/std_svc/errata_abi/cpu_errata_info.h
index 9906fac..e24a621 100644
--- a/services/std_svc/errata_abi/cpu_errata_info.h
+++ b/services/std_svc/errata_abi/cpu_errata_info.h
@@ -28,6 +28,7 @@
#include <cortex_a715.h>
#include <cortex_x1.h>
#include <cortex_x2.h>
+#include <cortex_x3.h>
#include <neoverse_n1.h>
#include <neoverse_n2.h>
#include <neoverse_v1.h>
diff --git a/services/std_svc/errata_abi/errata_abi_main.c b/services/std_svc/errata_abi/errata_abi_main.c
index 71a907b..8fee6ac 100644
--- a/services/std_svc/errata_abi/errata_abi_main.c
+++ b/services/std_svc/errata_abi/errata_abi_main.c
@@ -332,24 +332,25 @@
.cpu_partnumber = NEOVERSE_N2_MIDR,
.cpu_errata_list = {
[0] = {2002655, 0x00, 0x00, ERRATA_N2_2002655},
- [1] = {2025414, 0x00, 0x00, ERRATA_N2_2025414},
- [2] = {2067956, 0x00, 0x00, ERRATA_N2_2067956},
- [3] = {2138953, 0x00, 0x00, ERRATA_N2_2138953},
- [4] = {2138956, 0x00, 0x00, ERRATA_N2_2138956},
- [5] = {2138958, 0x00, 0x00, ERRATA_N2_2138958},
- [6] = {2189731, 0x00, 0x00, ERRATA_N2_2189731},
- [7] = {2242400, 0x00, 0x00, ERRATA_N2_2242400},
- [8] = {2242415, 0x00, 0x00, ERRATA_N2_2242415},
- [9] = {2280757, 0x00, 0x00, ERRATA_N2_2280757},
- [10] = {2326639, 0x00, 0x00, ERRATA_N2_2326639},
- [11] = {2376738, 0x00, 0x00, ERRATA_N2_2376738},
- [12] = {2388450, 0x00, 0x00, ERRATA_N2_2388450},
- [13] = {2728475, 0x00, 0x02, ERRATA_N2_2728475, \
+ [1] = {2009478, 0x00, 0x00, ERRATA_N2_2009478},
+ [2] = {2025414, 0x00, 0x00, ERRATA_N2_2025414},
+ [3] = {2067956, 0x00, 0x00, ERRATA_N2_2067956},
+ [4] = {2138953, 0x00, 0x00, ERRATA_N2_2138953},
+ [5] = {2138956, 0x00, 0x00, ERRATA_N2_2138956},
+ [6] = {2138958, 0x00, 0x00, ERRATA_N2_2138958},
+ [7] = {2189731, 0x00, 0x00, ERRATA_N2_2189731},
+ [8] = {2242400, 0x00, 0x00, ERRATA_N2_2242400},
+ [9] = {2242415, 0x00, 0x00, ERRATA_N2_2242415},
+ [10] = {2280757, 0x00, 0x00, ERRATA_N2_2280757},
+ [11] = {2326639, 0x00, 0x00, ERRATA_N2_2326639},
+ [12] = {2376738, 0x00, 0x00, ERRATA_N2_2376738},
+ [13] = {2388450, 0x00, 0x00, ERRATA_N2_2388450},
+ [14] = {2728475, 0x00, 0x02, ERRATA_N2_2728475, \
ERRATA_NON_ARM_INTERCONNECT},
- [14] = {2743014, 0x00, 0x02, ERRATA_N2_2743014},
- [15] = {2743089, 0x00, 0x02, ERRATA_N2_2743089},
- [16] = {2779511, 0x00, 0x02, ERRATA_N2_2779511},
- [17 ... ERRATA_LIST_END] = UNDEF_ERRATA,
+ [15] = {2743014, 0x00, 0x02, ERRATA_N2_2743014},
+ [16] = {2743089, 0x00, 0x02, ERRATA_N2_2743089},
+ [17] = {2779511, 0x00, 0x02, ERRATA_N2_2779511},
+ [18 ... ERRATA_LIST_END] = UNDEF_ERRATA,
}
},
#endif /* NEOVERSE_N2_H_INC */
@@ -417,6 +418,18 @@
}
},
#endif /* CORTEX_A715_H_INC */
+
+#if CORTEX_X3_H_INC
+{
+ .cpu_partnumber = CORTEX_X3_MIDR,
+ .cpu_errata_list = {
+ [0] = {2313909, 0x00, 0x10, ERRATA_X3_2313909},
+ [1] = {2615812, 0x00, 0x11, ERRATA_X3_2615812},
+ [2] = {2742421, 0x00, 0x11, ERRATA_X3_2742421},
+ [3 ... ERRATA_LIST_END] = UNDEF_ERRATA,
+ }
+},
+#endif /* CORTEX_X3_H_INC */
};
/*