tree ce33ce311c4b377bc2b4bb8067ee9b8850659e90
parent 7cbd469dc0fd430f35722bdc37812a127bf15313
parent aa3b816f8ccd7a2a5cfc572d20596cf7146bcc2b
author Madhukar Pappireddy <madhukar.pappireddy@arm.com> 1718371222 +0200
committer TrustedFirmware Code Review <review@review.trustedfirmware.org> 1718371222 +0200

Merge changes from topic "st_clk_update" into integration

* changes:
  feat(st-clock): use early traces
  fix(st-clock): adapt order of CSS on LSE and HSE
  refactor(st-clock): remove unused struct
  feat(stm32mp1-fdts): remove RTC clock configuration
  refactor(st-clock): move stm32mp1_clk_rcc_regs_*lock
  refactor(st-clock): driver size optimization
  refactor(st-clock): remove BL32 support on STM32MP13
  feat(st-clock): don't gate/ungate an oscillator if it is not wired
  feat(dt-bindings): add missing SPIx bus clocks
  feat(stm32mp1-fdts): remove PLL1 settings
  feat(st-clock): update with new bindings
  feat(stm32mp1-fdts): new RCC DT bindings for STM32MP1
  feat(dt-bindings): new RCC DT bindings
  feat(stm32mp1): always boot at 650MHz
  refactor(st-clock): remove LSEDRV_MEDIUM_HIGH for STM32MP13
  fix(st-clock): display proper PLL number for STM32MP13
  fix(st-clock): do not reconfigure LSE
  feat(stm32mp1-fdts): move RNG1 to CSI to improve random generation
  refactor(st-clock): remove unused clk function in API
  refactor(st-clock): support deactivated STGEN in stm32mp_stgen_config
  feat(st-clock): add function to restore generic timer rate