Merge "smccc: add get smc function id num macro" into integration
diff --git a/Makefile b/Makefile
index 073c2ed..42fdb73 100644
--- a/Makefile
+++ b/Makefile
@@ -736,6 +736,7 @@
 $(eval $(call assert_boolean,RESET_TO_BL31))
 $(eval $(call assert_boolean,SAVE_KEYS))
 $(eval $(call assert_boolean,SEPARATE_CODE_AND_RODATA))
+$(eval $(call assert_boolean,SEPARATE_NOBITS_REGION))
 $(eval $(call assert_boolean,SPIN_ON_BL1_EXIT))
 $(eval $(call assert_boolean,SPM_MM))
 $(eval $(call assert_boolean,TRUSTED_BOARD_BOOT))
@@ -800,6 +801,7 @@
 $(eval $(call add_define,RAS_EXTENSION))
 $(eval $(call add_define,RESET_TO_BL31))
 $(eval $(call add_define,SEPARATE_CODE_AND_RODATA))
+$(eval $(call add_define,SEPARATE_NOBITS_REGION))
 $(eval $(call add_define,RECLAIM_INIT_CODE))
 $(eval $(call add_define,SPD_${SPD}))
 $(eval $(call add_define,SPIN_ON_BL1_EXIT))
diff --git a/bl31/bl31.ld.S b/bl31/bl31.ld.S
index a598e59..42227f0 100644
--- a/bl31/bl31.ld.S
+++ b/bl31/bl31.ld.S
@@ -15,6 +15,11 @@
 
 MEMORY {
     RAM (rwx): ORIGIN = BL31_BASE, LENGTH = BL31_LIMIT - BL31_BASE
+#if SEPARATE_NOBITS_REGION
+    NOBITS (rw!a): ORIGIN = BL31_NOBITS_BASE, LENGTH = BL31_NOBITS_LIMIT - BL31_NOBITS_BASE
+#else
+#define NOBITS RAM
+#endif
 }
 
 #ifdef PLAT_EXTRA_LD_SCRIPT
@@ -198,11 +203,28 @@
     ASSERT(. <= BL31_PROGBITS_LIMIT, "BL31 progbits has exceeded its limit.")
 #endif
 
+#if SEPARATE_NOBITS_REGION
+    /*
+     * Define a linker symbol to mark end of the RW memory area for this
+     * image.
+     */
+    __RW_END__ = .;
+    __BL31_END__ = .;
+
+    ASSERT(. <= BL31_LIMIT, "BL31 image has exceeded its limit.")
+
+    . = BL31_NOBITS_BASE;
+    ASSERT(. == ALIGN(PAGE_SIZE),
+           "BL31 NOBITS base address is not aligned on a page boundary.")
+
+    __NOBITS_START__ = .;
+#endif
+
     stacks (NOLOAD) : {
         __STACKS_START__ = .;
         *(tzfw_normal_stacks)
         __STACKS_END__ = .;
-    } >RAM
+    } >NOBITS
 
     /*
      * The .bss section gets initialised to 0 at runtime.
@@ -262,7 +284,7 @@
         __PMF_TIMESTAMP_END__ = .;
 #endif /* ENABLE_PMF */
         __BSS_END__ = .;
-    } >RAM
+    } >NOBITS
 
     /*
      * The xlat_table section is for full, aligned page tables (4K).
@@ -272,7 +294,7 @@
      */
     xlat_table (NOLOAD) : {
         *(xlat_table)
-    } >RAM
+    } >NOBITS
 
 #if USE_COHERENT_MEM
     /*
@@ -298,9 +320,18 @@
          */
         . = ALIGN(PAGE_SIZE);
         __COHERENT_RAM_END__ = .;
-    } >RAM
+    } >NOBITS
 #endif
 
+#if SEPARATE_NOBITS_REGION
+    /*
+     * Define a linker symbol to mark end of the NOBITS memory area for this
+     * image.
+     */
+    __NOBITS_END__ = .;
+
+    ASSERT(. <= BL31_NOBITS_LIMIT, "BL31 NOBITS region has exceeded its limit.")
+#else
     /*
      * Define a linker symbol to mark end of the RW memory area for this
      * image.
@@ -309,4 +340,5 @@
     __BL31_END__ = .;
 
     ASSERT(. <= BL31_LIMIT, "BL31 image has exceeded its limit.")
+#endif
 }
diff --git a/docs/design/firmware-design.rst b/docs/design/firmware-design.rst
index cae94b5..5fc1335 100644
--- a/docs/design/firmware-design.rst
+++ b/docs/design/firmware-design.rst
@@ -1500,6 +1500,11 @@
 this NOBITS section, making the image unnecessarily bigger. Smaller images
 allow faster loading from the FIP to the main memory.
 
+For BL31, a platform can specify an alternate location for NOBITS sections
+(other than immediately following PROGBITS sections) by setting
+``SEPARATE_NOBITS_REGION`` to 1 and defining ``BL31_NOBITS_BASE`` and
+``BL31_NOBITS_LIMIT``.
+
 Linker scripts and symbols
 ~~~~~~~~~~~~~~~~~~~~~~~~~~
 
diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst
index 37c28a5..d7bb044 100644
--- a/docs/getting_started/build-options.rst
+++ b/docs/getting_started/build-options.rst
@@ -491,6 +491,13 @@
    pages" section in :ref:`Firmware Design`. This flag is disabled by default and
    affects all BL images.
 
+-  ``SEPARATE_NOBITS_REGION``: Setting this option to ``1`` allows the NOBITS
+   sections of BL31 (.bss, stacks, page tables, and coherent memory) to be
+   allocated in RAM discontiguous from the loaded firmware image. When set, the
+   platform is expected to provide definitons for ``BL31_NOBITS_BASE`` and
+   ``BL31_NOBITS_LIMIT``. When the option is ``0`` (the default), NOBITS
+   sections are placed in RAM immediately following the loaded firmware image.
+
 -  ``SPD``: Choose a Secure Payload Dispatcher component to be built into TF-A.
    This build option is only valid if ``ARCH=aarch64``. The value should be
    the path to the directory containing the SPD source, relative to
diff --git a/docs/getting_started/initial-build.rst b/docs/getting_started/initial-build.rst
index 41cd4d1..893aba2 100644
--- a/docs/getting_started/initial-build.rst
+++ b/docs/getting_started/initial-build.rst
@@ -8,13 +8,13 @@
 
    .. code:: shell
 
-       export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
+       export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-none-elf-
 
    For AArch32:
 
    .. code:: shell
 
-       export CROSS_COMPILE=<path-to-aarch32-gcc>/bin/arm-eabi-
+       export CROSS_COMPILE=<path-to-aarch32-gcc>/bin/arm-none-eabi-
 
    It is possible to build TF-A using Clang or Arm Compiler 6. To do so
    ``CC`` needs to point to the clang or armclang binary, which will
@@ -32,7 +32,7 @@
 
    .. code:: shell
 
-       export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
+       export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-none-elf-
        make CC=<path-to-armclang>/bin/armclang PLAT=<platform> all
 
    Clang will be selected when the base name of the path assigned to ``CC``
@@ -43,7 +43,7 @@
 
    .. code:: shell
 
-       export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
+       export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-none-elf-
        make CC=<path-to-clang>/bin/clang PLAT=<platform> all
 
 -  Change to the root directory of the TF-A source tree and build.
diff --git a/docs/getting_started/prerequisites.rst b/docs/getting_started/prerequisites.rst
index 27ad0ed..3e0c8ff 100644
--- a/docs/getting_started/prerequisites.rst
+++ b/docs/getting_started/prerequisites.rst
@@ -26,7 +26,7 @@
 |TF-A| can be built with any of the following *cross-compiler* toolchains that
 target the Armv7-A or Armv8-A architectures:
 
-- GCC >= 8.3-2019.03 (from the `Arm Developer website`_)
+- GCC >= 9.2-2019.12 (from the `Arm Developer website`_)
 - Clang >= 4.0
 - Arm Compiler >= 6.0
 
diff --git a/docs/plat/allwinner.rst b/docs/plat/allwinner.rst
index a1e0659..5c905d8 100644
--- a/docs/plat/allwinner.rst
+++ b/docs/plat/allwinner.rst
@@ -26,13 +26,13 @@
 
 .. code:: shell
 
-    make CROSS_COMPILE=aarch64-linux-gnu- PLAT=sun50i_a64 DEBUG=1 bl31
+    make CROSS_COMPILE=aarch64-none-elf- PLAT=sun50i_a64 DEBUG=1 bl31
 
 To build for machines with an H6 SoC:
 
 .. code:: shell
 
-    make CROSS_COMPILE=aarch64-linux-gnu- PLAT=sun50i_h6 DEBUG=1 bl31
+    make CROSS_COMPILE=aarch64-none-elf- PLAT=sun50i_h6 DEBUG=1 bl31
 
 .. _U-Boot documentation: http://git.denx.de/?p=u-boot.git;f=board/sunxi/README.sunxi64;hb=HEAD
 
diff --git a/docs/plat/arm/fvp/index.rst b/docs/plat/arm/fvp/index.rst
index b6396b9..37010e1 100644
--- a/docs/plat/arm/fvp/index.rst
+++ b/docs/plat/arm/fvp/index.rst
@@ -223,7 +223,7 @@
 
 .. code:: shell
 
-    CROSS_COMPILE=aarch64-linux-gnu-  \
+    CROSS_COMPILE=aarch64-none-elf-  \
     make PLAT=fvp DEBUG=1             \
     RESET_TO_BL31=1                   \
     ARM_LINUX_KERNEL_AS_BL33=1        \
diff --git a/docs/plat/arm/juno/index.rst b/docs/plat/arm/juno/index.rst
index 6429ede..cf328fa 100644
--- a/docs/plat/arm/juno/index.rst
+++ b/docs/plat/arm/juno/index.rst
@@ -136,7 +136,7 @@
 
       .. code:: shell
 
-          export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
+          export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-none-elf-
 
    -  The following parameters should be used to build BL1 and BL2 in AArch64
       and point to the BL32 file.
diff --git a/docs/plat/hikey.rst b/docs/plat/hikey.rst
index 372d388..d7a01a8 100644
--- a/docs/plat/hikey.rst
+++ b/docs/plat/hikey.rst
@@ -78,7 +78,7 @@
        EDK2_OUTPUT_DIR=${EDK2_DIR}/Build/HiKey/${BUILD_OPTION}_${AARCH64_TOOLCHAIN}
        # Build fastboot for Trusted Firmware-A. It's used for recovery mode.
        cd ${BUILD_PATH}/atf-fastboot
-       CROSS_COMPILE=aarch64-linux-gnu- make PLAT=hikey DEBUG=1
+       CROSS_COMPILE=aarch64-none-elf- make PLAT=hikey DEBUG=1
        # Convert DEBUG/RELEASE to debug/release
        FASTBOOT_BUILD_OPTION=$(echo ${BUILD_OPTION} | tr '[A-Z]' '[a-z]')
        cd ${EDK2_DIR}
diff --git a/docs/plat/imx8.rst b/docs/plat/imx8.rst
index 49ba374..cec1a39 100644
--- a/docs/plat/imx8.rst
+++ b/docs/plat/imx8.rst
@@ -40,7 +40,7 @@
 
    .. code:: shell
 
-       CROSS_COMPILE=aarch64-linux-gnu- make PLAT=<Target_SoC> bl31
+       CROSS_COMPILE=aarch64-none-elf- make PLAT=<Target_SoC> bl31
 
    Target_SoC should be "imx8qm" for i.MX8QM SoC.
    Target_SoC should be "imx8qx" for i.MX8QX SoC.
diff --git a/docs/plat/imx8m.rst b/docs/plat/imx8m.rst
index 8acd13c..0116b34 100644
--- a/docs/plat/imx8m.rst
+++ b/docs/plat/imx8m.rst
@@ -28,7 +28,7 @@
 
    .. code:: shell
 
-       CROSS_COMPILE=aarch64-linux-gnu- make PLAT=<Target_SoC> bl31
+       CROSS_COMPILE=aarch64-none-elf- make PLAT=<Target_SoC> bl31
 
    Target_SoC should be "imx8mq" for i.MX8MQ SoC.
    Target_SoC should be "imx8mm" for i.MX8MM SoC.
diff --git a/docs/plat/intel-agilex.rst b/docs/plat/intel-agilex.rst
index ff27b6b..f60bf14 100644
--- a/docs/plat/intel-agilex.rst
+++ b/docs/plat/intel-agilex.rst
@@ -41,7 +41,7 @@
 
 .. code:: bash
 
-       make CROSS_COMPILE=aarch64-linux-gnu- bl2 fip PLAT=agilex
+       make CROSS_COMPILE=aarch64-none-elf- bl2 fip PLAT=agilex
        BL33=PEI.ROM
 
 Install Procedure
diff --git a/docs/plat/intel-stratix10.rst b/docs/plat/intel-stratix10.rst
index 7f8d18e..5f33d12 100644
--- a/docs/plat/intel-stratix10.rst
+++ b/docs/plat/intel-stratix10.rst
@@ -41,7 +41,7 @@
 
 .. code:: bash
 
-       make CROSS_COMPILE=aarch64-linux-gnu- bl2 fip PLAT=stratix10
+       make CROSS_COMPILE=aarch64-none-elf- bl2 fip PLAT=stratix10
        BL33=PEI.ROM
 
 Install Procedure
diff --git a/docs/plat/ls1043a.rst b/docs/plat/ls1043a.rst
index 72a51f3..5a8f755 100644
--- a/docs/plat/ls1043a.rst
+++ b/docs/plat/ls1043a.rst
@@ -59,13 +59,13 @@
 
    .. code:: shell
 
-       CROSS_COMPILE=aarch64-linux-gnu- make PLAT=ls1043 bl1
+       CROSS_COMPILE=aarch64-none-elf- make PLAT=ls1043 bl1
 
    Build fip:
 
    .. code:: shell
 
-       CROSS_COMPILE=aarch64-linux-gnu- make PLAT=ls1043 fip \
+       CROSS_COMPILE=aarch64-none-elf- make PLAT=ls1043 fip \
        BL33=u-boot.bin NEED_BL32=yes BL32=tee.bin SPD=opteed
 
 Deploy TF-A Images
diff --git a/docs/plat/marvell/build.rst b/docs/plat/marvell/build.rst
index c10bcff..d0e37c6 100644
--- a/docs/plat/marvell/build.rst
+++ b/docs/plat/marvell/build.rst
@@ -9,7 +9,7 @@
 
     .. code:: shell
 
-        > export CROSS_COMPILE=/path/to/toolchain/aarch64-linux-gnu-
+        > export CROSS_COMPILE=/path/to/toolchain/aarch64-none-elf-
 
 (2) Set path for FIP images:
 
diff --git a/docs/plat/meson-g12a.rst b/docs/plat/meson-g12a.rst
index 7cd1bf7..8b06cc2 100644
--- a/docs/plat/meson-g12a.rst
+++ b/docs/plat/meson-g12a.rst
@@ -17,7 +17,7 @@
 
 .. code:: shell
 
-    CROSS_COMPILE=aarch64-linux-gnu- make DEBUG=1 PLAT=g12a
+    CROSS_COMPILE=aarch64-none-elf- make DEBUG=1 PLAT=g12a
 
 This port has been tested on a SEI510 board. After building it, follow the
 instructions in the `gxlimg repository` or `U-Boot repository`_, replacing the
diff --git a/docs/plat/meson-gxbb.rst b/docs/plat/meson-gxbb.rst
index 2cd8342..f891ecd 100644
--- a/docs/plat/meson-gxbb.rst
+++ b/docs/plat/meson-gxbb.rst
@@ -17,7 +17,7 @@
 
 .. code:: shell
 
-    CROSS_COMPILE=aarch64-linux-gnu- make DEBUG=1 PLAT=gxbb bl31
+    CROSS_COMPILE=aarch64-none-elf- make DEBUG=1 PLAT=gxbb bl31
 
 This port has been tested in a ODROID-C2. After building it, follow the
 instructions in the `U-Boot repository`_, replacing the mentioned **bl31.bin**
diff --git a/docs/plat/meson-gxl.rst b/docs/plat/meson-gxl.rst
index c6d8504..170d7c7 100644
--- a/docs/plat/meson-gxl.rst
+++ b/docs/plat/meson-gxl.rst
@@ -17,7 +17,7 @@
 
 .. code:: shell
 
-    CROSS_COMPILE=aarch64-linux-gnu- make DEBUG=1 PLAT=gxl
+    CROSS_COMPILE=aarch64-none-elf- make DEBUG=1 PLAT=gxl
 
 This port has been tested on a Lepotato. After building it, follow the
 instructions in the `gxlimg repository` or `U-Boot repository`_, replacing the
diff --git a/docs/plat/mt8183.rst b/docs/plat/mt8183.rst
index c639be1..7a0830f 100644
--- a/docs/plat/mt8183.rst
+++ b/docs/plat/mt8183.rst
@@ -17,4 +17,4 @@
 
 .. code:: shell
 
-    make CROSS_COMPILE=aarch64-linux-gnu- PLAT=mt8183 DEBUG=1
+    make CROSS_COMPILE=aarch64-none-elf- PLAT=mt8183 DEBUG=1
diff --git a/docs/plat/poplar.rst b/docs/plat/poplar.rst
index 215f551..040b593 100644
--- a/docs/plat/poplar.rst
+++ b/docs/plat/poplar.rst
@@ -68,7 +68,7 @@
 
 .. code:: bash
 
-       make CROSS_COMPILE=aarch64-linux-gnu-  all fip SPD=none PLAT=poplar
+       make CROSS_COMPILE=aarch64-none-elf- all fip SPD=none PLAT=poplar
        BL33=u-boot.bin
 
 -  Build l-loader (generated the final fastboot.bin)
diff --git a/docs/plat/qemu-sbsa.rst b/docs/plat/qemu-sbsa.rst
index 51fe414..5e8535c 100644
--- a/docs/plat/qemu-sbsa.rst
+++ b/docs/plat/qemu-sbsa.rst
@@ -27,7 +27,7 @@
 
     git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git tfa
     cd tfa
-    export CROSS_COMPILE=aarch64-linux-gnu-
+    export CROSS_COMPILE=aarch64-none-elf-
     make PLAT=qemu_sbsa all fip
 
 Images will be placed at build/qemu_sbsa/release (bl1.bin and fip.bin).
diff --git a/docs/plat/rockchip.rst b/docs/plat/rockchip.rst
index b7c43fb..2c3c38f 100644
--- a/docs/plat/rockchip.rst
+++ b/docs/plat/rockchip.rst
@@ -35,7 +35,7 @@
 
 For AARCH64 architectures the build command looks like
 
-    make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3399 bl32
+    make CROSS_COMPILE=aarch64-none-elf- PLAT=rk3399 bl32
 
 while AARCH32 needs a slightly different command
 
diff --git a/docs/plat/rpi3.rst b/docs/plat/rpi3.rst
index 38c3dfa..5c7b6d5 100644
--- a/docs/plat/rpi3.rst
+++ b/docs/plat/rpi3.rst
@@ -315,7 +315,7 @@
 
 .. code:: shell
 
-    CROSS_COMPILE=aarch64-linux-gnu- make PLAT=rpi3             \
+    CROSS_COMPILE=aarch64-none-elf- make PLAT=rpi3             \
     RPI3_BL33_IN_AARCH32=1                                      \
     BL33=../rpi3-arm-tf-bootstrap/aarch32/el2-bootstrap.bin
 
@@ -323,7 +323,7 @@
 
 .. code:: shell
 
-    CROSS_COMPILE=aarch64-linux-gnu- make PLAT=rpi3             \
+    CROSS_COMPILE=aarch64-none-elf- make PLAT=rpi3             \
     BL33=../rpi3-arm-tf-bootstrap/aarch64/el2-bootstrap.bin
 
 However, enabling PSCI support in a 64-bit kernel is really easy. In the
@@ -340,7 +340,7 @@
 
 .. code:: shell
 
-    CROSS_COMPILE=aarch64-linux-gnu- make PLAT=rpi3             \
+    CROSS_COMPILE=aarch64-none-elf- make PLAT=rpi3             \
     PRELOADED_BL33_BASE=0x02000000                              \
     RPI3_PRELOADED_DTB_BASE=0x01000000                          \
     RPI3_DIRECT_LINUX_BOOT=1
@@ -349,7 +349,7 @@
 
 .. code:: shell
 
-    CROSS_COMPILE=aarch64-linux-gnu- make PLAT=rpi3             \
+    CROSS_COMPILE=aarch64-none-elf- make PLAT=rpi3             \
     PRELOADED_BL33_BASE=0x02000000                              \
     RPI3_PRELOADED_DTB_BASE=0x01000000                          \
     RPI3_DIRECT_LINUX_BOOT=1                                    \
diff --git a/docs/plat/rpi4.rst b/docs/plat/rpi4.rst
index 0f529c1..e87aef7 100644
--- a/docs/plat/rpi4.rst
+++ b/docs/plat/rpi4.rst
@@ -22,7 +22,7 @@
 
 .. code:: shell
 
-    CROSS_COMPILE=aarch64-linux-gnu- make PLAT=rpi4 DEBUG=1
+    CROSS_COMPILE=aarch64-none-elf- make PLAT=rpi4 DEBUG=1
 
 Copy the generated build/rpi4/debug/bl31.bin to the SD card, either
 renaming it to ``armstub8.bin`` or adding an entry starting with ``armstub=``,
diff --git a/docs/plat/ti-k3.rst b/docs/plat/ti-k3.rst
index 4843227..2626e67 100644
--- a/docs/plat/ti-k3.rst
+++ b/docs/plat/ti-k3.rst
@@ -27,7 +27,7 @@
 
 .. code:: shell
 
-    make CROSS_COMPILE=aarch64-linux-gnu- PLAT=k3 SPD=opteed all
+    make CROSS_COMPILE=aarch64-none-elf- PLAT=k3 SPD=opteed all
 
 OP-TEE:
 
diff --git a/drivers/arm/scu/scu.c b/drivers/arm/scu/scu.c
new file mode 100644
index 0000000..aceac92
--- /dev/null
+++ b/drivers/arm/scu/scu.c
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2019, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <drivers/arm/scu.h>
+#include <lib/mmio.h>
+#include <plat/common/platform.h>
+#include <stdint.h>
+
+/*******************************************************************************
+ * Turn ON snoop control unit. This is needed to synchronize the data between
+ * CPU's.
+ ******************************************************************************/
+void enable_snoop_ctrl_unit(uintptr_t base)
+{
+	uint32_t scu_ctrl;
+
+	INFO("[SCU]: enabling snoop control unit ... \n");
+
+	assert(base != 0U);
+	scu_ctrl = mmio_read_32(base + SCU_CTRL_REG);
+
+	/* already enabled? */
+	if ((scu_ctrl & SCU_ENABLE_BIT) != 0) {
+		return;
+	}
+
+	scu_ctrl |= SCU_ENABLE_BIT;
+	mmio_write_32(base + SCU_CTRL_REG, scu_ctrl);
+}
+
+/*******************************************************************************
+ * Snoop Control Unit configuration register. This is read-only register and
+ * contains information such as
+ * - number of CPUs present
+ * - is a particular CPU operating in SMP mode or AMP mode
+ * - data cache size of a particular CPU
+ * - does SCU has ACP port
+ * - is L2CPRESENT
+ * NOTE: user of this API should interpert the bits in this register according
+ * to the TRM
+ ******************************************************************************/
+uint32_t read_snoop_ctrl_unit_cfg(uintptr_t base)
+{
+	assert(base != 0U);
+
+	return mmio_read_32(base + SCU_CFG_REG);
+}
diff --git a/drivers/auth/auth_mod.c b/drivers/auth/auth_mod.c
index a6538c4..3fb2d1a 100644
--- a/drivers/auth/auth_mod.c
+++ b/drivers/auth/auth_mod.c
@@ -30,9 +30,6 @@
 
 #pragma weak plat_set_nv_ctr2
 
-/* Pointer to CoT */
-extern const auth_img_desc_t *const *const cot_desc_ptr;
-extern unsigned int auth_img_flags[MAX_NUMBER_IDS];
 
 static int cmp_auth_param_type_desc(const auth_param_type_desc_t *a,
 		const auth_param_type_desc_t *b)
diff --git a/drivers/renesas/rcar/io/io_rcar.c b/drivers/renesas/rcar/io/io_rcar.c
index 650931b..b82c510 100644
--- a/drivers/renesas/rcar/io/io_rcar.c
+++ b/drivers/renesas/rcar/io/io_rcar.c
@@ -28,9 +28,6 @@
 extern int32_t plat_get_drv_source(uint32_t id, uintptr_t *dev,
 				   uintptr_t *image_spec);
 
-extern int auth_mod_verify_img(unsigned int img_id, void *ptr,
-				unsigned int len);
-
 static int32_t rcar_dev_open(const uintptr_t dev_spec __attribute__ ((unused)),
 			     io_dev_info_t **dev_info);
 static int32_t rcar_dev_close(io_dev_info_t *dev_info);
diff --git a/fdts/a5ds.dts b/fdts/a5ds.dts
index fc8783d..31d635a 100644
--- a/fdts/a5ds.dts
+++ b/fdts/a5ds.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019, Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2020, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -64,13 +64,20 @@
 		arm,tag-latency = <1 1 1>;
 	};
 
-	refclk100mhz: refclk100mhz {
+	refclk7500khz: refclk7500khz {
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
-		clock-frequency = <100000000>;
+		clock-frequency = <7500000>;
 		clock-output-names = "apb_pclk";
 	};
 
+	refclk24mhz: refclk24mhz {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <24000000>;
+		clock-output-names = "apb_pclk";
+	};
+
 	smbclk: refclk24mhzx2 {
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
@@ -82,7 +89,7 @@
 	rtc@1a220000 {
 		compatible = "arm,pl031", "arm,primecell";
 		reg = <0x1a220000 0x1000>;
-		clocks = <&refclk100mhz>;
+		clocks = <&refclk24mhz>;
 		interrupts = <0 6 0xf04>;
 		clock-names = "apb_pclk";
 	};
@@ -102,7 +109,7 @@
 		reg = <0x1a200000 0x1000>;
 		interrupt-parent = <&gic>;
 		interrupts = <0 8 0xf04>;
-		clocks = <&refclk100mhz>;
+		clocks = <&refclk7500khz>;
 		clock-names = "apb_pclk";
 	};
 
@@ -111,7 +118,7 @@
 		reg = <0x1a210000 0x1000>;
 		interrupt-parent = <&gic>;
 		interrupts = <0 9 0xf04>;
-		clocks = <&refclk100mhz>;
+		clocks = <&refclk7500khz>;
 		clock-names = "apb_pclk";
 	};
 
diff --git a/include/arch/aarch64/el3_common_macros.S b/include/arch/aarch64/el3_common_macros.S
index b14b7b6..156b18a 100644
--- a/include/arch/aarch64/el3_common_macros.S
+++ b/include/arch/aarch64/el3_common_macros.S
@@ -382,6 +382,14 @@
 		add	x1, x1, :lo12:__RW_END__
 		sub	x1, x1, x0
 		bl	inv_dcache_range
+#if defined(IMAGE_BL31) && SEPARATE_NOBITS_REGION
+		adrp	x0, __NOBITS_START__
+		add	x0, x0, :lo12:__NOBITS_START__
+		adrp	x1, __NOBITS_END__
+		add	x1, x1, :lo12:__NOBITS_END__
+		sub	x1, x1, x0
+		bl	inv_dcache_range
+#endif
 #endif
 		adrp	x0, __BSS_START__
 		add	x0, x0, :lo12:__BSS_START__
diff --git a/include/drivers/arm/scu.h b/include/drivers/arm/scu.h
new file mode 100644
index 0000000..992539f
--- /dev/null
+++ b/include/drivers/arm/scu.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2019, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SCU_H
+#define SCU_H
+
+#include <stdint.h>
+
+#define SCU_CTRL_REG	0x00
+#define SCU_CFG_REG	0x04
+
+#define SCU_ENABLE_BIT	(1 << 0)
+
+void enable_snoop_ctrl_unit(uintptr_t base);
+uint32_t read_snoop_ctrl_unit_cfg(uintptr_t base);
+
+#endif /* SCU_H */
diff --git a/include/lib/pmf/pmf.h b/include/lib/pmf/pmf.h
index df7c9ff..3fc8e38 100644
--- a/include/lib/pmf/pmf.h
+++ b/include/lib/pmf/pmf.h
@@ -54,108 +54,6 @@
 #define PMF_PSCI_STAT_SVC_ID	0
 #define PMF_RT_INSTR_SVC_ID	1
 
-#if ENABLE_PMF
-/*
- * Convenience macros for capturing time-stamp.
- */
-#define PMF_DECLARE_CAPTURE_TIMESTAMP(_name)			\
-	void pmf_capture_timestamp_with_cache_maint_ ## _name(	\
-				unsigned int tid,		\
-				unsigned long long ts);		\
-	void pmf_capture_timestamp_ ## _name(			\
-				unsigned int tid,		\
-				unsigned long long ts);
-
-#define PMF_CAPTURE_TIMESTAMP(_name, _tid, _flags)			\
-	do {								\
-		unsigned long long ts = read_cntpct_el0();		\
-		if (((_flags) & PMF_CACHE_MAINT) != 0U)			\
-			pmf_capture_timestamp_with_cache_maint_ ## _name((_tid), ts);\
-		else							\
-			pmf_capture_timestamp_ ## _name((_tid), ts);	\
-	} while (0)
-
-#define PMF_CAPTURE_AND_GET_TIMESTAMP(_name, _tid, _flags, _tsval)	\
-	do {								\
-		(_tsval) = read_cntpct_el0();				\
-		CASSERT(sizeof(_tsval) == sizeof(unsigned long long), invalid_tsval_size);\
-		if (((_flags) & PMF_CACHE_MAINT) != 0U)			\
-			pmf_capture_timestamp_with_cache_maint_ ## _name((_tid), (_tsval));\
-		else							\
-			pmf_capture_timestamp_ ## _name((_tid), (_tsval));\
-	} while (0)
-
-#define PMF_WRITE_TIMESTAMP(_name, _tid, _flags, _wrval)		\
-	do {								\
-		CASSERT(sizeof(_wrval) == sizeof(unsigned long long), invalid_wrval_size);\
-		if (((_flags) & PMF_CACHE_MAINT) != 0U)			\
-			pmf_capture_timestamp_with_cache_maint_ ## _name((_tid), (_wrval));\
-		else							\
-			pmf_capture_timestamp_ ## _name((_tid), (_wrval));\
-	} while (0)
-
-/*
- * Convenience macros for retrieving time-stamp.
- */
-#define PMF_DECLARE_GET_TIMESTAMP(_name)			\
-	unsigned long long pmf_get_timestamp_by_index_ ## _name(\
-		unsigned int tid,				\
-		unsigned int cpuid,				\
-		unsigned int flags);				\
-	unsigned long long pmf_get_timestamp_by_mpidr_ ## _name(\
-		unsigned int tid,				\
-		u_register_t mpidr,				\
-		unsigned int flags);
-
-#define PMF_GET_TIMESTAMP_BY_MPIDR(_name, _tid, _mpidr, _flags, _tsval)\
-	_tsval = pmf_get_timestamp_by_mpidr_ ## _name(_tid, _mpidr, _flags)
-
-#define PMF_GET_TIMESTAMP_BY_INDEX(_name, _tid, _cpuid, _flags, _tsval)\
-	_tsval = pmf_get_timestamp_by_index_ ## _name(_tid, _cpuid, _flags)
-
-/* Convenience macros to register a PMF service.*/
-/*
- * This macro is used to register a PMF Service. It allocates PMF memory
- * and defines default service-specific PMF functions.
- */
-#define PMF_REGISTER_SERVICE(_name, _svcid, _totalid, _flags)	\
-	PMF_ALLOCATE_TIMESTAMP_MEMORY(_name, _totalid)		\
-	PMF_DEFINE_CAPTURE_TIMESTAMP(_name, _flags)		\
-	PMF_DEFINE_GET_TIMESTAMP(_name)
-
-/*
- * This macro is used to register a PMF service, including an
- * SMC interface to that service.
- */
-#define PMF_REGISTER_SERVICE_SMC(_name, _svcid, _totalid, _flags)\
-	PMF_REGISTER_SERVICE(_name, _svcid, _totalid, _flags)	\
-	PMF_DEFINE_SERVICE_DESC(_name, PMF_ARM_TIF_IMPL_ID,	\
-			_svcid, _totalid, NULL,			\
-			pmf_get_timestamp_by_mpidr_ ## _name)
-
-/*
- * This macro is used to register a PMF service that has an SMC interface
- * but provides its own service-specific PMF functions.
- */
-#define PMF_REGISTER_SERVICE_SMC_OWN(_name, _implid, _svcid, _totalid,	\
-		 _init, _getts)						\
-	PMF_DEFINE_SERVICE_DESC(_name, _implid, _svcid, _totalid,	\
-		 _init, _getts)
-
-#else
-
-#define PMF_REGISTER_SERVICE(_name, _svcid, _totalid, _flags)
-#define PMF_REGISTER_SERVICE_SMC(_name, _svcid, _totalid, _flags)
-#define PMF_REGISTER_SERVICE_SMC_OWN(_name, _implid, _svcid, _totalid,	\
-				_init, _getts)
-#define PMF_DECLARE_CAPTURE_TIMESTAMP(_name)
-#define PMF_DECLARE_GET_TIMESTAMP(_name)
-#define PMF_CAPTURE_TIMESTAMP(_name, _tid, _flags)
-#define PMF_GET_TIMESTAMP_BY_MPIDR(_name, _tid, _mpidr, _flags, _tsval)
-#define PMF_GET_TIMESTAMP_BY_INDEX(_name, _tid, _cpuid, _flags, _tsval)
-
-#endif /* ENABLE_PMF */
-
 /*******************************************************************************
  * Function & variable prototypes
  ******************************************************************************/
diff --git a/include/lib/pmf/pmf_helpers.h b/include/lib/pmf/pmf_helpers.h
index e6798a7..db38e55 100644
--- a/include/lib/pmf/pmf_helpers.h
+++ b/include/lib/pmf/pmf_helpers.h
@@ -43,6 +43,108 @@
 	pmf_svc_get_ts_t get_ts;
 } pmf_svc_desc_t;
 
+#if ENABLE_PMF
+/*
+ * Convenience macros for capturing time-stamp.
+ */
+#define PMF_DECLARE_CAPTURE_TIMESTAMP(_name)			\
+	void pmf_capture_timestamp_with_cache_maint_ ## _name(	\
+				unsigned int tid,		\
+				unsigned long long ts);		\
+	void pmf_capture_timestamp_ ## _name(			\
+				unsigned int tid,		\
+				unsigned long long ts);
+
+#define PMF_CAPTURE_TIMESTAMP(_name, _tid, _flags)			\
+	do {								\
+		unsigned long long ts = read_cntpct_el0();		\
+		if (((_flags) & PMF_CACHE_MAINT) != 0U)			\
+			pmf_capture_timestamp_with_cache_maint_ ## _name((_tid), ts);\
+		else							\
+			pmf_capture_timestamp_ ## _name((_tid), ts);	\
+	} while (0)
+
+#define PMF_CAPTURE_AND_GET_TIMESTAMP(_name, _tid, _flags, _tsval)	\
+	do {								\
+		(_tsval) = read_cntpct_el0();				\
+		CASSERT(sizeof(_tsval) == sizeof(unsigned long long), invalid_tsval_size);\
+		if (((_flags) & PMF_CACHE_MAINT) != 0U)			\
+			pmf_capture_timestamp_with_cache_maint_ ## _name((_tid), (_tsval));\
+		else							\
+			pmf_capture_timestamp_ ## _name((_tid), (_tsval));\
+	} while (0)
+
+#define PMF_WRITE_TIMESTAMP(_name, _tid, _flags, _wrval)		\
+	do {								\
+		CASSERT(sizeof(_wrval) == sizeof(unsigned long long), invalid_wrval_size);\
+		if (((_flags) & PMF_CACHE_MAINT) != 0U)			\
+			pmf_capture_timestamp_with_cache_maint_ ## _name((_tid), (_wrval));\
+		else							\
+			pmf_capture_timestamp_ ## _name((_tid), (_wrval));\
+	} while (0)
+
+/*
+ * Convenience macros for retrieving time-stamp.
+ */
+#define PMF_DECLARE_GET_TIMESTAMP(_name)			\
+	unsigned long long pmf_get_timestamp_by_index_ ## _name(\
+		unsigned int tid,				\
+		unsigned int cpuid,				\
+		unsigned int flags);				\
+	unsigned long long pmf_get_timestamp_by_mpidr_ ## _name(\
+		unsigned int tid,				\
+		u_register_t mpidr,				\
+		unsigned int flags);
+
+#define PMF_GET_TIMESTAMP_BY_MPIDR(_name, _tid, _mpidr, _flags, _tsval)\
+	_tsval = pmf_get_timestamp_by_mpidr_ ## _name(_tid, _mpidr, _flags)
+
+#define PMF_GET_TIMESTAMP_BY_INDEX(_name, _tid, _cpuid, _flags, _tsval)\
+	_tsval = pmf_get_timestamp_by_index_ ## _name(_tid, _cpuid, _flags)
+
+/* Convenience macros to register a PMF service.*/
+/*
+ * This macro is used to register a PMF Service. It allocates PMF memory
+ * and defines default service-specific PMF functions.
+ */
+#define PMF_REGISTER_SERVICE(_name, _svcid, _totalid, _flags)	\
+	PMF_ALLOCATE_TIMESTAMP_MEMORY(_name, _totalid)		\
+	PMF_DEFINE_CAPTURE_TIMESTAMP(_name, _flags)		\
+	PMF_DEFINE_GET_TIMESTAMP(_name)
+
+/*
+ * This macro is used to register a PMF service, including an
+ * SMC interface to that service.
+ */
+#define PMF_REGISTER_SERVICE_SMC(_name, _svcid, _totalid, _flags)\
+	PMF_REGISTER_SERVICE(_name, _svcid, _totalid, _flags)	\
+	PMF_DEFINE_SERVICE_DESC(_name, PMF_ARM_TIF_IMPL_ID,	\
+			_svcid, _totalid, NULL,			\
+			pmf_get_timestamp_by_mpidr_ ## _name)
+
+/*
+ * This macro is used to register a PMF service that has an SMC interface
+ * but provides its own service-specific PMF functions.
+ */
+#define PMF_REGISTER_SERVICE_SMC_OWN(_name, _implid, _svcid, _totalid,	\
+		 _init, _getts)						\
+	PMF_DEFINE_SERVICE_DESC(_name, _implid, _svcid, _totalid,	\
+		 _init, _getts)
+
+#else
+
+#define PMF_REGISTER_SERVICE(_name, _svcid, _totalid, _flags)
+#define PMF_REGISTER_SERVICE_SMC(_name, _svcid, _totalid, _flags)
+#define PMF_REGISTER_SERVICE_SMC_OWN(_name, _implid, _svcid, _totalid,	\
+				_init, _getts)
+#define PMF_DECLARE_CAPTURE_TIMESTAMP(_name)
+#define PMF_DECLARE_GET_TIMESTAMP(_name)
+#define PMF_CAPTURE_TIMESTAMP(_name, _tid, _flags)
+#define PMF_GET_TIMESTAMP_BY_MPIDR(_name, _tid, _mpidr, _flags, _tsval)
+#define PMF_GET_TIMESTAMP_BY_INDEX(_name, _tid, _cpuid, _flags, _tsval)
+
+#endif /* ENABLE_PMF */
+
 /*
  * Convenience macro to allocate memory for a PMF service.
  *
@@ -69,9 +171,6 @@
 #define PMF_DEFINE_CAPTURE_TIMESTAMP(_name, _flags)			\
 	void pmf_capture_timestamp_ ## _name(				\
 			unsigned int tid,				\
-			unsigned long long ts);				\
-	void pmf_capture_timestamp_ ## _name(				\
-			unsigned int tid,				\
 			unsigned long long ts)				\
 	{								\
 		CASSERT(_flags, select_proper_config);			\
@@ -84,9 +183,6 @@
 	}								\
 	void pmf_capture_timestamp_with_cache_maint_ ## _name(		\
 			unsigned int tid,				\
-			unsigned long long ts);				\
-	void pmf_capture_timestamp_with_cache_maint_ ## _name(		\
-			unsigned int tid,				\
 			unsigned long long ts)				\
 	{								\
 		CASSERT(_flags, select_proper_config);			\
@@ -105,8 +201,6 @@
  */
 #define PMF_DEFINE_GET_TIMESTAMP(_name)					\
 	unsigned long long pmf_get_timestamp_by_index_ ## _name(	\
-		unsigned int tid, unsigned int cpuid, unsigned int flags);\
-	unsigned long long pmf_get_timestamp_by_index_ ## _name(	\
 		unsigned int tid, unsigned int cpuid, unsigned int flags)\
 	{								\
 		PMF_VALIDATE_TID(_name, tid);				\
@@ -114,8 +208,6 @@
 		return __pmf_get_timestamp(base_addr, tid, cpuid, flags);\
 	}								\
 	unsigned long long pmf_get_timestamp_by_mpidr_ ## _name(	\
-		unsigned int tid, u_register_t mpidr, unsigned int flags);\
-	unsigned long long pmf_get_timestamp_by_mpidr_ ## _name(	\
 		unsigned int tid, u_register_t mpidr, unsigned int flags)\
 	{								\
 		PMF_VALIDATE_TID(_name, tid);				\
diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk
index a1f9db9..53832c5 100644
--- a/make_helpers/defaults.mk
+++ b/make_helpers/defaults.mk
@@ -171,6 +171,10 @@
 # platform Makefile is free to override this value.
 SEPARATE_CODE_AND_RODATA	:= 0
 
+# Put NOBITS sections (.bss, stacks, page tables, and coherent memory) in a
+# separate memory region, which may be discontiguous from the rest of BL31.
+SEPARATE_NOBITS_REGION		:= 0
+
 # If the BL31 image initialisation code is recalimed after use for the secondary
 # cores stack
 RECLAIM_INIT_CODE		:= 0
diff --git a/plat/allwinner/common/allwinner-common.mk b/plat/allwinner/common/allwinner-common.mk
index 5e8885d..d281011 100644
--- a/plat/allwinner/common/allwinner-common.mk
+++ b/plat/allwinner/common/allwinner-common.mk
@@ -8,8 +8,7 @@
 
 AW_PLAT			:=	plat/allwinner
 
-PLAT_INCLUDES		:=	-Iinclude/plat/arm/common		\
-				-Iinclude/plat/arm/common/aarch64	\
+PLAT_INCLUDES		:=	-Iinclude/plat/arm/common/aarch64	\
 				-I${AW_PLAT}/common/include		\
 				-I${AW_PLAT}/${PLAT}/include
 
diff --git a/plat/arm/board/a5ds/a5ds_common.c b/plat/arm/board/a5ds/a5ds_common.c
index e462fa1..a4a0cff 100644
--- a/plat/arm/board/a5ds/a5ds_common.c
+++ b/plat/arm/board/a5ds/a5ds_common.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019, Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2020, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -23,18 +23,18 @@
 #ifdef IMAGE_BL1
 const mmap_region_t plat_arm_mmap[] = {
 	ARM_MAP_SHARED_RAM,
-	MAP_FLASH1_RW,
 	MAP_PERIPHBASE,
 	MAP_A5_PERIPHERALS,
+	MAP_BOOT_RW,
 	{0}
 };
 #endif
 #ifdef IMAGE_BL2
 const mmap_region_t plat_arm_mmap[] = {
 	ARM_MAP_SHARED_RAM,
-	MAP_FLASH1_RW,
 	MAP_PERIPHBASE,
 	MAP_A5_PERIPHERALS,
+	MAP_BOOT_RW,
 	ARM_MAP_NS_DRAM1,
 	{0}
 };
diff --git a/plat/arm/board/a5ds/a5ds_pm.c b/plat/arm/board/a5ds/a5ds_pm.c
index cc734b0..7774002 100644
--- a/plat/arm/board/a5ds/a5ds_pm.c
+++ b/plat/arm/board/a5ds/a5ds_pm.c
@@ -4,11 +4,10 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 #include <assert.h>
-
+#include <drivers/arm/gicv2.h>
 #include <lib/psci/psci.h>
 #include <plat/arm/common/plat_arm.h>
 #include <plat/common/platform.h>
-#include <drivers/arm/gicv2.h>
 
 /*******************************************************************************
  * Platform handler called when a power domain is about to be turned on. The
diff --git a/plat/arm/board/a5ds/fdts/a5ds_tb_fw_config.dts b/plat/arm/board/a5ds/fdts/a5ds_tb_fw_config.dts
index 9ab2d96..7b3aa11 100644
--- a/plat/arm/board/a5ds/fdts/a5ds_tb_fw_config.dts
+++ b/plat/arm/board/a5ds/fdts/a5ds_tb_fw_config.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019, Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2020, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -10,7 +10,7 @@
 	/* Platform Config */
 	plat_arm_bl2 {
 		compatible = "arm,tb_fw";
-		hw_config_addr = <0x0 0x82000000>;
+		hw_config_addr = <0x0 0x83000000>;
 		hw_config_max_size = <0x01000000>;
 		/* Disable authentication for development */
 		disable_auth = <0x0>;
diff --git a/plat/arm/board/a5ds/include/platform_def.h b/plat/arm/board/a5ds/include/platform_def.h
index e9e4b9a..4c87c22 100644
--- a/plat/arm/board/a5ds/include/platform_def.h
+++ b/plat/arm/board/a5ds/include/platform_def.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019, Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2020, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -21,14 +21,6 @@
 #define ARM_DRAM1_END			(ARM_DRAM1_BASE +		\
 					 ARM_DRAM1_SIZE - 1)
 
-#define ARM_NS_DRAM1_BASE		ARM_DRAM1_BASE
-/*
- * The last 2MB is meant to be NOLOAD and will not be zero
- * initialized.
- */
-#define ARM_NS_DRAM1_SIZE		(ARM_DRAM1_SIZE -		\
-					 0x00200000)
-
 #define SRAM_BASE	0x2000000
 #define SRAM_SIZE	0x200000
 
@@ -47,7 +39,7 @@
 #define A5_PERIPHERALS_BASE 0x1c000000
 #define A5_PERIPHERALS_SIZE  0x10000
 
-#define ARM_CACHE_WRITEBACK_SHIFT	6
+#define ARM_CACHE_WRITEBACK_SHIFT	5
 
 #define ARM_IRQ_SEC_PHY_TIMER		29
 
@@ -101,16 +93,22 @@
 
 #define A5DS_PRIMARY_CPU	0x0
 
-#define FLASH1_BASE			UL(0x8000000)
-#define FLASH1_SIZE			UL(0x2800000)
+#define BOOT_BASE			ARM_DRAM1_BASE
+#define BOOT_SIZE			UL(0x2800000)
 
-#define MAP_FLASH1_RW		MAP_REGION_FLAT(FLASH1_BASE,\
-						FLASH1_SIZE,	\
-						MT_DEVICE | MT_RW | MT_SECURE)
+#define ARM_NS_DRAM1_BASE		(ARM_DRAM1_BASE + BOOT_SIZE)
+/*
+ * The last 2MB is meant to be NOLOAD and will not be zero
+ * initialized.
+ */
+#define ARM_NS_DRAM1_SIZE		(ARM_DRAM1_SIZE -		\
+					 BOOT_SIZE -			\
+					 0x00200000)
 
-#define MAP_FLASH1_RO		MAP_REGION_FLAT(FLASH1_BASE,\
-						FLASH1_SIZE,	\
-						MT_RO_DATA | MT_SECURE)
+#define MAP_BOOT_RW          		MAP_REGION_FLAT(		\
+						BOOT_BASE,		\
+						BOOT_SIZE,    		\
+						MT_DEVICE | MT_RW | MT_SECURE)
 
 #define ARM_MAP_SHARED_RAM		MAP_REGION_FLAT(		\
 						A5DS_SHARED_RAM_BASE,	\
@@ -122,9 +120,9 @@
 						ARM_NS_DRAM1_SIZE,	\
 						MT_MEMORY | MT_RW | MT_NS)
 
-#define ARM_MAP_SRAM		MAP_REGION_FLAT(		\
-						SRAM_BASE,	\
-						SRAM_SIZE,	\
+#define ARM_MAP_SRAM			MAP_REGION_FLAT(		\
+						SRAM_BASE,		\
+						SRAM_SIZE,		\
 						MT_MEMORY | MT_RW | MT_NS)
 
 /*
@@ -162,7 +160,7 @@
 					 ARM_BL_REGIONS)
 
 /* Memory mapped Generic timer interfaces  */
-#define A5DS_TIMER_BASE_FREQUENCY		UL(24000000)
+#define A5DS_TIMER_BASE_FREQUENCY		UL(7500000)
 
 #define ARM_CONSOLE_BAUDRATE		115200
 
@@ -300,25 +298,25 @@
 #define MAX_IO_HANDLES			4
 
 /* Reserve the last block of flash for PSCI MEM PROTECT flag */
-#define PLAT_ARM_FIP_BASE		FLASH1_BASE
-#define PLAT_ARM_FIP_MAX_SIZE		(FLASH1_SIZE - V2M_FLASH_BLOCK_SIZE)
+#define PLAT_ARM_FIP_BASE		BOOT_BASE
+#define PLAT_ARM_FIP_MAX_SIZE		(BOOT_SIZE - V2M_FLASH_BLOCK_SIZE)
 
-#define PLAT_ARM_NVM_BASE		FLASH1_BASE
-#define PLAT_ARM_NVM_SIZE		(FLASH1_SIZE - V2M_FLASH_BLOCK_SIZE)
+#define PLAT_ARM_NVM_BASE		BOOT_BASE
+#define PLAT_ARM_NVM_SIZE		(BOOT_SIZE - V2M_FLASH_BLOCK_SIZE)
 
 /*
  * PL011 related constants
  */
 #define PLAT_ARM_BOOT_UART_BASE		0x1A200000
-#define PLAT_ARM_BOOT_UART_CLK_IN_HZ	24000000
+#define PLAT_ARM_BOOT_UART_CLK_IN_HZ	UL(7500000)
 
 #define PLAT_ARM_RUN_UART_BASE		0x1A210000
-#define PLAT_ARM_RUN_UART_CLK_IN_HZ	24000000
+#define PLAT_ARM_RUN_UART_CLK_IN_HZ	UL(7500000)
 
 #define PLAT_ARM_CRASH_UART_BASE	PLAT_ARM_RUN_UART_BASE
 #define PLAT_ARM_CRASH_UART_CLK_IN_HZ	PLAT_ARM_RUN_UART_CLK_IN_HZ
 
-#define A5DS_TIMER_BASE_FREQUENCY	UL(24000000)
+#define A5DS_TIMER_BASE_FREQUENCY	UL(7500000)
 
 /* System timer related constants */
 #define PLAT_ARM_NSTIMER_FRAME_ID		1
@@ -334,6 +332,9 @@
 #define A5DS_HOLD_STATE_WAIT	0
 #define A5DS_HOLD_STATE_GO	1
 
+/* Snoop Control Unit base address */
+#define A5DS_SCU_BASE			0x1C000000
+
 /*
  * GIC related constants to cater for GICv2
  */
diff --git a/plat/arm/board/a5ds/sp_min/a5ds_sp_min_setup.c b/plat/arm/board/a5ds/sp_min/a5ds_sp_min_setup.c
index 8b45af8..a951dc7 100644
--- a/plat/arm/board/a5ds/sp_min/a5ds_sp_min_setup.c
+++ b/plat/arm/board/a5ds/sp_min/a5ds_sp_min_setup.c
@@ -4,12 +4,17 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
+#include <drivers/arm/scu.h>
 #include <plat/arm/common/plat_arm.h>
 
+
 void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1,
 			u_register_t arg2, u_register_t arg3)
 {
 	arm_sp_min_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
+
+	/* enable snoop control unit */
+	enable_snoop_ctrl_unit(A5DS_SCU_BASE);
 }
 
 /*
diff --git a/plat/arm/board/a5ds/sp_min/sp_min-a5ds.mk b/plat/arm/board/a5ds/sp_min/sp_min-a5ds.mk
index da1d785..4b0c97d 100644
--- a/plat/arm/board/a5ds/sp_min/sp_min-a5ds.mk
+++ b/plat/arm/board/a5ds/sp_min/sp_min-a5ds.mk
@@ -5,7 +5,8 @@
 #
 
 # SP_MIN source files specific to A5DS platform
-BL32_SOURCES	+=	drivers/cfi/v2m/v2m_flash.c			\
+BL32_SOURCES	+=	drivers/arm/scu/scu.c                           \
+			drivers/cfi/v2m/v2m_flash.c			\
 			lib/utils/mem_region.c				\
 			lib/aarch32/arm32_aeabi_divmod.c		\
 			lib/aarch32/arm32_aeabi_divmod_a32.S		\
diff --git a/plat/common/plat_psci_common.c b/plat/common/plat_psci_common.c
index 16bec79..a756d5e 100644
--- a/plat/common/plat_psci_common.c
+++ b/plat/common/plat_psci_common.c
@@ -31,6 +31,8 @@
 #define PSCI_STAT_ID_EXIT_LOW_PWR		1
 #define PSCI_STAT_TOTAL_IDS			2
 
+PMF_DECLARE_CAPTURE_TIMESTAMP(psci_svc)
+PMF_DECLARE_GET_TIMESTAMP(psci_svc)
 PMF_REGISTER_SERVICE(psci_svc, PMF_PSCI_STAT_SVC_ID, PSCI_STAT_TOTAL_IDS,
 	PMF_STORE_ENABLE)
 
diff --git a/plat/imx/imx8m/include/imx8m_psci.h b/plat/imx/imx8m/include/imx8m_psci.h
index 4966403..c33d25e 100644
--- a/plat/imx/imx8m/include/imx8m_psci.h
+++ b/plat/imx/imx8m/include/imx8m_psci.h
@@ -15,13 +15,9 @@
 void imx_pwr_domain_on_finish(const psci_power_state_t *target_state);
 void imx_pwr_domain_off(const psci_power_state_t *target_state);
 int imx_validate_ns_entrypoint(uintptr_t ns_entrypoint);
-int imx_validate_power_state(unsigned int power_state, psci_power_state_t *rq_state);
 void imx_cpu_standby(plat_local_state_t cpu_state);
 void imx_domain_suspend(const psci_power_state_t *target_state);
 void imx_domain_suspend_finish(const psci_power_state_t *target_state);
-void imx_get_sys_suspend_power_state(psci_power_state_t *req_state);
-void __dead2 imx_system_reset(void);
-void __dead2 imx_system_off(void);
 void __dead2 imx_pwr_domain_pwr_down_wfi(const psci_power_state_t *target_state);
 
 #endif /* IMX8M_PSCI_H */
diff --git a/plat/intel/soc/agilex/include/agilex_system_manager.h b/plat/intel/soc/agilex/include/agilex_system_manager.h
index 381c2d3..be29536 100644
--- a/plat/intel/soc/agilex/include/agilex_system_manager.h
+++ b/plat/intel/soc/agilex/include/agilex_system_manager.h
@@ -73,7 +73,6 @@
 #define DISABLE_BRIDGE_FIREWALL			0x0ffe0101
 #define DISABLE_L4_FIREWALL	(BIT(0) | BIT(16) | BIT(24))
 
-void enable_nonsecure_access(void);
 void enable_ns_bridge_access(void);
 
 #endif
diff --git a/plat/intel/soc/stratix10/include/s10_system_manager.h b/plat/intel/soc/stratix10/include/s10_system_manager.h
index a67d689..4abfedb 100644
--- a/plat/intel/soc/stratix10/include/s10_system_manager.h
+++ b/plat/intel/soc/stratix10/include/s10_system_manager.h
@@ -69,5 +69,3 @@
 
 #define DISABLE_L4_FIREWALL	(BIT(0) | BIT(16) | BIT(24))
 
-void enable_nonsecure_access(void);
-
diff --git a/plat/mediatek/mt8173/drivers/spm/spm.h b/plat/mediatek/mt8173/drivers/spm/spm.h
index 403303a..0c05410 100644
--- a/plat/mediatek/mt8173/drivers/spm/spm.h
+++ b/plat/mediatek/mt8173/drivers/spm/spm.h
@@ -320,7 +320,6 @@
 void spm_go_to_hotplug(void);
 void spm_init_event_vector(const struct pcm_desc *pcmdesc);
 void spm_kick_im_to_fetch(const struct pcm_desc *pcmdesc);
-void spm_set_sysclk_settle(void);
 int is_mcdi_ready(void);
 int is_hotplug_ready(void);
 int is_suspend_ready(void);
diff --git a/plat/mediatek/mt8183/drivers/spm/spm.c b/plat/mediatek/mt8183/drivers/spm/spm.c
index 547af57..d6d2344 100644
--- a/plat/mediatek/mt8183/drivers/spm/spm.c
+++ b/plat/mediatek/mt8183/drivers/spm/spm.c
@@ -12,6 +12,12 @@
 
 DEFINE_BAKERY_LOCK(spm_lock);
 
+/* SPM_DVS_LEVEL */
+#define SPM_VMODEM_LEVEL_MASK	(0xff << 16)
+#define SPM_VMODEM_LEVEL	(1U << 18)
+#define SPM_VCORE_LEVEL_MASK	(0xff)
+#define SPM_VCORE_LEVEL		(1U << 1)
+
 /* CLK_SCP_CFG_0 */
 #define SPM_CK_OFF_CONTROL	(0x3FF)
 
@@ -339,6 +345,11 @@
 	spm_lock_init();
 	mt_spm_pmic_wrap_set_phase(PMIC_WRAP_PHASE_ALLINONE);
 
+	/* Set Vmodem / Vcore DVS init level */
+	mmio_clrsetbits_32(SPM_DVS_LEVEL,
+			   SPM_VMODEM_LEVEL_MASK | SPM_VCORE_LEVEL_MASK,
+			   SPM_VMODEM_LEVEL | SPM_VCORE_LEVEL);
+
 	/* switch ck_off/axi_26m control to SPM */
 	mmio_setbits_32(CLK_SCP_CFG_0, SPM_CK_OFF_CONTROL);
 	mmio_setbits_32(CLK_SCP_CFG_1, SPM_AXI_26M_SEL);
diff --git a/plat/nvidia/tegra/include/tegra_private.h b/plat/nvidia/tegra/include/tegra_private.h
index cd2f773..761acde 100644
--- a/plat/nvidia/tegra/include/tegra_private.h
+++ b/plat/nvidia/tegra/include/tegra_private.h
@@ -137,7 +137,6 @@
 void tegra_delay_timer_init(void);
 
 void tegra_secure_entrypoint(void);
-void tegra186_cpu_reset_handler(void);
 
 /* Declarations for tegra_sip_calls.c */
 uintptr_t tegra_sip_handler(uint32_t smc_fid,
diff --git a/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h b/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h
index 3994b2d..7dcfd84 100644
--- a/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h
+++ b/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h
@@ -66,7 +66,6 @@
 uint64_t nvg_cache_clean(void);
 uint64_t nvg_cache_clean_inval(void);
 uint64_t nvg_cache_inval_all(void);
-int32_t nvg_roc_clean_cache_trbits(void);
 void nvg_enable_strict_checking_mode(void);
 
 /* MCE helper functions */
diff --git a/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c b/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c
index 1dd1f51..536ed57 100644
--- a/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c
+++ b/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -165,7 +165,7 @@
 	/* sanity check the core ID value */
 	if (core > (uint32_t)PLATFORM_CORE_COUNT) {
 		ERROR("%s: unknown core id (%d)\n", __func__, core);
-		ret = EINVAL;
+		ret = -EINVAL;
 	} else {
 		/* get a core online */
 		nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_ONLINE_CORE,
@@ -183,15 +183,15 @@
  */
 int32_t nvg_update_ccplex_gsc(uint32_t gsc_idx)
 {
-	int32_t ret;
+	int32_t ret = 0;
 
 	/* sanity check GSC ID */
 	if (gsc_idx > (uint32_t)TEGRA_NVG_CHANNEL_UPDATE_GSC_VPR) {
 		ERROR("%s: unknown gsc_idx (%u)\n", __func__, gsc_idx);
-		ret = EINVAL;
+		ret = -EINVAL;
 	} else {
 		nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_UPDATE_CCPLEX_GSC,
-								(uint64_t)gsc_idx);
+				     (uint64_t)gsc_idx);
 	}
 
 	return ret;
@@ -209,11 +209,12 @@
 			ID_AFR0_EL1_CACHE_OPS_MASK) == 1U) {
 		if (nvg_cache_clean() == 0U) {
 			ERROR("%s: failed\n", __func__);
-			ret = EINVAL;
+			ret = -ENODEV;
 		}
 	} else {
-		ret = EINVAL;
+		ret = -ENOTSUP;
 	}
+
 	return ret;
 }
 
@@ -229,11 +230,12 @@
 			ID_AFR0_EL1_CACHE_OPS_MASK) == 1U) {
 		if (nvg_cache_clean_inval() == 0U) {
 			ERROR("%s: failed\n", __func__);
-			ret = EINVAL;
+			ret = -ENODEV;
 		}
 	} else {
-		ret = EINVAL;
+		ret = -ENOTSUP;
 	}
+
 	return ret;
 }
 
@@ -249,11 +251,12 @@
 			ID_AFR0_EL1_CACHE_OPS_MASK) == 1U) {
 		if (nvg_cache_inval_all() == 0U) {
 			ERROR("%s: failed\n", __func__);
-			ret = EINVAL;
+			ret = -ENODEV;
 		}
 	} else {
-		ret = EINVAL;
+		ret = -ENOTSUP;
 	}
+
 	return ret;
 }
 
@@ -271,8 +274,8 @@
 	    (state != (uint32_t)TEGRA_NVG_CORE_C6) &&
 		(state != (uint32_t)TEGRA_NVG_CORE_C7))
 	{
-		ERROR("%s: unknown cstate (%d)\n", __func__, state);
-		ret = EINVAL;
+		ERROR("%s: unknown cstate (%u)\n", __func__, state);
+		ret = -EINVAL;
 	} else {
 		/* time (TSC ticks) until the core is expected to get a wake event */
 		nvg_set_wake_time(wake_time);
diff --git a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c
index 1188a3b..fa5ba62 100644
--- a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c
+++ b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c
@@ -26,7 +26,6 @@
 #include <tegra_platform.h>
 #include <tegra_private.h>
 
-extern void tegra194_cpu_reset_handler(void);
 extern uint32_t __tegra194_cpu_reset_handler_data,
 		__tegra194_cpu_reset_handler_end;
 
diff --git a/plat/rockchip/rk3328/drivers/soc/soc.h b/plat/rockchip/rk3328/drivers/soc/soc.h
index a1f35b2..e8cbc09 100644
--- a/plat/rockchip/rk3328/drivers/soc/soc.h
+++ b/plat/rockchip/rk3328/drivers/soc/soc.h
@@ -16,8 +16,6 @@
 #define TIMER_INTSTATUS		0x18
 #define TIMER_EN		0x1
 
-extern const unsigned char rockchip_power_domain_tree_desc[];
-
 /**************************** read/write **************************************/
 #ifndef BITS_WMSK
 #define BITS_WMSK(msk, shift)	((msk) << (shift + REG_MSK_SHIFT))
diff --git a/plat/rockchip/rk3328/platform.mk b/plat/rockchip/rk3328/platform.mk
index 0c5cfae..0219422 100644
--- a/plat/rockchip/rk3328/platform.mk
+++ b/plat/rockchip/rk3328/platform.mk
@@ -59,6 +59,9 @@
 include lib/coreboot/coreboot.mk
 include lib/libfdt/libfdt.mk
 
+# Enable workarounds for selected Cortex-A53 errata
+ERRATA_A53_855873	:=	1
+
 $(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT))
 $(eval $(call add_define,PLAT_SKIP_OPTEE_S_EL1_INT_REGISTER))