fix(versal-net): explicitly check operators precedence
This corrects the MISRA violation C2012-12.1:
The precedence of operators within expressions should be
made explicit.
Enclosed the subexpression in parentheses to maintain
the precedence.
Change-Id: I3c30f5029628f8b297c08443a2c6c8bbf2063d29
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
diff --git a/plat/xilinx/versal_net/bl31_versal_net_setup.c b/plat/xilinx/versal_net/bl31_versal_net_setup.c
index ebde49f..12d3e3b 100644
--- a/plat/xilinx/versal_net/bl31_versal_net_setup.c
+++ b/plat/xilinx/versal_net/bl31_versal_net_setup.c
@@ -179,7 +179,7 @@
uint32_t i;
/* Validate 'handler' and 'id' parameters */
- if (handler == NULL || index >= MAX_INTR_EL3) {
+ if ((handler == NULL) || (index >= MAX_INTR_EL3)) {
return -EINVAL;
}
diff --git a/plat/xilinx/versal_net/plat_psci_pm.c b/plat/xilinx/versal_net/plat_psci_pm.c
index 7a653d4..e89af71 100644
--- a/plat/xilinx/versal_net/plat_psci_pm.c
+++ b/plat/xilinx/versal_net/plat_psci_pm.c
@@ -162,7 +162,7 @@
plat_arm_gic_save();
}
- state = target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE ?
+ state = (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) ?
PM_STATE_SUSPEND_TO_RAM : PM_STATE_CPU_IDLE;
/* Send request to PMC to suspend this core */