Merge "fix(intel): fix print out ERROR when encounter SEU_Err" into integration
diff --git a/docs/about/release-information.rst b/docs/about/release-information.rst
index dead4f7..ddfc081 100644
--- a/docs/about/release-information.rst
+++ b/docs/about/release-information.rst
@@ -67,10 +67,7 @@
| | Date | after | |
| | | Release | |
+================================+=============+=========+=========================================================+
-| plat_convert_pk() function | Nov'22 | Next | Platform conversion to manage specific PK hash |
-| | | release | |
-| | | after | |
-| | | 2.8 | |
+| plat_convert_pk() function | Nov'22 | 2.9 | Platform conversion to manage specific PK hash |
+--------------------------------+-------------+---------+---------------------------------------------------------+
--------------
diff --git a/include/lib/psa/measured_boot.h b/include/lib/psa/measured_boot.h
index bdb79d5..47aa0b9 100644
--- a/include/lib/psa/measured_boot.h
+++ b/include/lib/psa/measured_boot.h
@@ -34,14 +34,14 @@
*
* index Slot number in which measurement is to be stored
* signer_id Pointer to signer_id buffer.
- * signer_id_size Size of the signer_id buffer in bytes.
+ * signer_id_size Size of the signer_id in bytes.
* version Pointer to version buffer.
- * version_size Size of the version buffer in bytes.
+ * version_size Size of the version string in bytes (with \0).
* measurement_algo Algorithm identifier used for measurement.
* sw_type Pointer to sw_type buffer.
- * sw_type_size Size of the sw_type buffer in bytes.
+ * sw_type_size Size of the sw_type string in bytes (with \0).
* measurement_value Pointer to measurement_value buffer.
- * measurement_value_size Size of the measurement_value buffer in bytes.
+ * measurement_value_size Size of the measurement_value in bytes.
* lock_measurement Boolean flag requesting whether the measurement
* is to be locked.
*
diff --git a/lib/psa/measured_boot.c b/lib/psa/measured_boot.c
index 6e9ff78..61747f2 100644
--- a/lib/psa/measured_boot.c
+++ b/lib/psa/measured_boot.c
@@ -80,22 +80,24 @@
.lock_measurement = lock_measurement,
.measurement_algo = measurement_algo,
.sw_type = {0},
- .sw_type_size = sw_type_size,
+ /* Removing \0 */
+ .sw_type_size = (sw_type_size > 0) ? (sw_type_size - 1) : 0,
};
psa_invec in_vec[] = {
{.base = &extend_iov,
.len = sizeof(struct measured_boot_extend_iovec_t)},
{.base = signer_id, .len = signer_id_size},
- {.base = version, .len = version_size},
+ {.base = version,
+ .len = (version_size > 0) ? (version_size - 1) : 0},
{.base = measurement_value, .len = measurement_value_size}
};
if (sw_type != NULL) {
- if (sw_type_size > SW_TYPE_MAX_SIZE) {
+ if (extend_iov.sw_type_size > SW_TYPE_MAX_SIZE) {
return PSA_ERROR_INVALID_ARGUMENT;
}
- memcpy(extend_iov.sw_type, sw_type, sw_type_size);
+ memcpy(extend_iov.sw_type, sw_type, extend_iov.sw_type_size);
}
log_measurement(index, signer_id, signer_id_size,
diff --git a/plat/intel/soc/agilex/include/agilex_pinmux.h b/plat/intel/soc/agilex/include/agilex_pinmux.h
index fe01062..0701208 100644
--- a/plat/intel/soc/agilex/include/agilex_pinmux.h
+++ b/plat/intel/soc/agilex/include/agilex_pinmux.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, Intel Corporation. All rights reserved.
+ * Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,10 +7,25 @@
#ifndef AGX_PINMUX_H
#define AGX_PINMUX_H
-#define AGX_PINMUX_PIN0SEL 0xffd13000
-#define AGX_PINMUX_IO0CTRL 0xffd13130
-#define AGX_PINMUX_PINMUX_EMAC0_USEFPGA 0xffd13300
-#define AGX_PINMUX_IO0_DELAY 0xffd13400
+#define AGX_PINMUX_BASE 0xffd13000
+#define AGX_PINMUX_PIN0SEL (AGX_PINMUX_BASE + 0x000)
+#define AGX_PINMUX_IO0CTRL (AGX_PINMUX_BASE + 0x130)
+#define AGX_PINMUX_EMAC0_USEFPGA (AGX_PINMUX_BASE + 0x300)
+#define AGX_PINMUX_EMAC1_USEFPGA (AGX_PINMUX_BASE + 0x304)
+#define AGX_PINMUX_EMAC2_USEFPGA (AGX_PINMUX_BASE + 0x308)
+#define AGX_PINMUX_NAND_USEFPGA (AGX_PINMUX_BASE + 0x320)
+#define AGX_PINMUX_SPIM0_USEFPGA (AGX_PINMUX_BASE + 0x328)
+#define AGX_PINMUX_SPIM1_USEFPGA (AGX_PINMUX_BASE + 0x32c)
+#define AGX_PINMUX_SDMMC_USEFPGA (AGX_PINMUX_BASE + 0x354)
+#define AGX_PINMUX_IO0_DELAY (AGX_PINMUX_BASE + 0x400)
+
+#define AGX_PINMUX_NAND_USEFPGA_VAL BIT(4)
+#define AGX_PINMUX_SDMMC_USEFPGA_VAL BIT(8)
+#define AGX_PINMUX_SPIM0_USEFPGA_VAL BIT(16)
+#define AGX_PINMUX_SPIM1_USEFPGA_VAL BIT(24)
+#define AGX_PINMUX_EMAC0_USEFPGA_VAL BIT(0)
+#define AGX_PINMUX_EMAC1_USEFPGA_VAL BIT(8)
+#define AGX_PINMUX_EMAC2_USEFPGA_VAL BIT(16)
#include "socfpga_handoff.h"
diff --git a/plat/intel/soc/agilex/soc/agilex_pinmux.c b/plat/intel/soc/agilex/soc/agilex_pinmux.c
index 0b908cf..96e1ade 100644
--- a/plat/intel/soc/agilex/soc/agilex_pinmux.c
+++ b/plat/intel/soc/agilex/soc/agilex_pinmux.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, Intel Corporation. All rights reserved.
+ * Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -188,7 +188,27 @@
void config_fpgaintf_mod(void)
{
- mmio_write_32(SOCFPGA_SYSMGR(FPGAINTF_EN_2), 1<<8);
+ uint32_t val;
+
+ val = 0;
+ if (mmio_read_32(AGX_PINMUX_NAND_USEFPGA) & 1)
+ val |= AGX_PINMUX_NAND_USEFPGA_VAL;
+ if (mmio_read_32(AGX_PINMUX_SDMMC_USEFPGA) & 1)
+ val |= AGX_PINMUX_SDMMC_USEFPGA_VAL;
+ if (mmio_read_32(AGX_PINMUX_SPIM0_USEFPGA) & 1)
+ val |= AGX_PINMUX_SPIM0_USEFPGA_VAL;
+ if (mmio_read_32(AGX_PINMUX_SPIM1_USEFPGA) & 1)
+ val |= AGX_PINMUX_SPIM1_USEFPGA_VAL;
+ mmio_write_32(SOCFPGA_SYSMGR(FPGAINTF_EN_2), val);
+
+ val = 0;
+ if (mmio_read_32(AGX_PINMUX_EMAC0_USEFPGA) & 1)
+ val |= AGX_PINMUX_EMAC0_USEFPGA_VAL;
+ if (mmio_read_32(AGX_PINMUX_EMAC1_USEFPGA) & 1)
+ val |= AGX_PINMUX_EMAC1_USEFPGA_VAL;
+ if (mmio_read_32(AGX_PINMUX_EMAC2_USEFPGA) & 1)
+ val |= AGX_PINMUX_EMAC2_USEFPGA_VAL;
+ mmio_write_32(SOCFPGA_SYSMGR(FPGAINTF_EN_3), val);
}
@@ -208,8 +228,8 @@
hoff_ptr->pinmux_io_array[i+1]);
}
- for (i = 0; i < 42; i += 2) {
- mmio_write_32(AGX_PINMUX_PINMUX_EMAC0_USEFPGA +
+ for (i = 0; i < 40; i += 2) {
+ mmio_write_32(AGX_PINMUX_EMAC0_USEFPGA +
hoff_ptr->pinmux_fpga_array[i],
hoff_ptr->pinmux_fpga_array[i+1]);
}
diff --git a/plat/intel/soc/common/soc/socfpga_firewall.c b/plat/intel/soc/common/soc/socfpga_firewall.c
index 515784b..fc3889c 100644
--- a/plat/intel/soc/common/soc/socfpga_firewall.c
+++ b/plat/intel/soc/common/soc/socfpga_firewall.c
@@ -60,6 +60,7 @@
mmio_write_32(SOCFPGA_L4_PER_SCR(I2C3), DISABLE_L4_FIREWALL);
mmio_write_32(SOCFPGA_L4_PER_SCR(I2C4), DISABLE_L4_FIREWALL);
+ mmio_write_32(SOCFPGA_L4_PER_SCR(SP_TIMER0), DISABLE_L4_FIREWALL);
mmio_write_32(SOCFPGA_L4_PER_SCR(SP_TIMER1), DISABLE_L4_FIREWALL);
mmio_write_32(SOCFPGA_L4_PER_SCR(UART0), DISABLE_L4_FIREWALL);
diff --git a/plat/intel/soc/common/socfpga_sip_svc.c b/plat/intel/soc/common/socfpga_sip_svc.c
index f079349..b57ab92 100644
--- a/plat/intel/soc/common/socfpga_sip_svc.c
+++ b/plat/intel/soc/common/socfpga_sip_svc.c
@@ -469,10 +469,6 @@
/* Intel HWMON services */
static uint32_t intel_hwmon_readtemp(uint32_t chan, uint32_t *retval)
{
- if (chan > TEMP_CHANNEL_MAX) {
- return INTEL_SIP_SMC_STATUS_ERROR;
- }
-
if (mailbox_hwmon_readtemp(chan, retval) < 0) {
return INTEL_SIP_SMC_STATUS_ERROR;
}
@@ -482,10 +478,6 @@
static uint32_t intel_hwmon_readvolt(uint32_t chan, uint32_t *retval)
{
- if (chan > VOLT_CHANNEL_MAX) {
- return INTEL_SIP_SMC_STATUS_ERROR;
- }
-
if (mailbox_hwmon_readvolt(chan, retval) < 0) {
return INTEL_SIP_SMC_STATUS_ERROR;
}
diff --git a/plat/qemu/qemu/include/platform_def.h b/plat/qemu/qemu/include/platform_def.h
index c9ed640..a22fbe5 100644
--- a/plat/qemu/qemu/include/platform_def.h
+++ b/plat/qemu/qemu/include/platform_def.h
@@ -137,7 +137,7 @@
* Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug
* size plus a little space for growth.
*/
-#define BL2_BASE (BL31_BASE - 0x25000)
+#define BL2_BASE (BL31_BASE - 0x35000)
#define BL2_LIMIT BL31_BASE
/*
diff --git a/plat/xilinx/versal/pm_service/pm_client.c b/plat/xilinx/versal/pm_service/pm_client.c
index ce5e533..54f4eb2 100644
--- a/plat/xilinx/versal/pm_service/pm_client.c
+++ b/plat/xilinx/versal/pm_service/pm_client.c
@@ -120,11 +120,9 @@
{
uint32_t reg_num;
uint32_t device_id;
- uint8_t pm_wakeup_nodes_set[XPM_NODEIDX_DEV_MAX];
+ uint8_t pm_wakeup_nodes_set[XPM_NODEIDX_DEV_MAX] = { 0U };
uintptr_t isenabler1 = PLAT_VERSAL_GICD_BASE + GICD_ISENABLER + 4;
- zeromem(&pm_wakeup_nodes_set, (u_register_t)sizeof(pm_wakeup_nodes_set));
-
for (reg_num = 0U; reg_num < NUM_GICD_ISENABLER; reg_num++) {
uint32_t base_irq = reg_num << ISENABLER_SHIFT;
uint32_t reg = mmio_read_32(isenabler1 + (reg_num << 2));
diff --git a/plat/xilinx/versal/pm_service/pm_svc_main.c b/plat/xilinx/versal/pm_service/pm_svc_main.c
index 9eb426a..c90f9e1 100644
--- a/plat/xilinx/versal/pm_service/pm_svc_main.c
+++ b/plat/xilinx/versal/pm_service/pm_svc_main.c
@@ -160,7 +160,7 @@
case PM_IOCTL:
{
- uint32_t value;
+ uint32_t value = 0U;
ret = pm_api_ioctl(pm_arg[0], pm_arg[1], pm_arg[2],
pm_arg[3], pm_arg[4],
diff --git a/plat/xilinx/zynqmp/pm_service/pm_svc_main.c b/plat/xilinx/zynqmp/pm_service/pm_svc_main.c
index 03fa316..b45ce6c 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_svc_main.c
+++ b/plat/xilinx/zynqmp/pm_service/pm_svc_main.c
@@ -207,10 +207,16 @@
*/
int32_t pm_setup(void)
{
+ enum pm_ret_status err;
pm_ipi_init(primary_proc);
- pm_get_api_version(&pm_ctx.api_version);
+ err = pm_get_api_version(&pm_ctx.api_version);
+ if (err != PM_RET_SUCCESS) {
+ ERROR("BL31: Failed to read Platform Management API version. "
+ "Return: %d\n", err);
+ return -EINVAL;
+ }
if (pm_ctx.api_version < PM_VERSION) {
ERROR("BL31: Platform Management API version error. Expected: "
"v%d.%d - Found: v%d.%d\n", PM_VERSION_MAJOR,