Merge "DSU: Apply erratum 936184 for Neoverse N1/E1" into integration
diff --git a/docs/getting_started/user-guide.rst b/docs/getting_started/user-guide.rst
index 1a4df03..02f8c5f 100644
--- a/docs/getting_started/user-guide.rst
+++ b/docs/getting_started/user-guide.rst
@@ -401,6 +401,8 @@
for development platforms. ``TRUSTED_BOARD_BOOT`` flag must be set if this
flag has to be enabled. 0 is the default.
+- ``E``: Boolean option to make warnings into errors. Default is 1.
+
- ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of
the normal boot flow. It must specify the entry point address of the EL3
payload. Please refer to the "Booting an EL3 payload" section for more
@@ -785,6 +787,10 @@
Defaults to a string formed by concatenating the version number, build type
and build string.
+- ``W``: Warning level. Some compiler warning options of interest have been
+ regrouped and put in the root Makefile. This flag can take the values 0 to 3,
+ each level enabling more warning options. Default is 0.
+
- ``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on
the CPU after warm boot. This is applicable for platforms which do not
require interconnect programming to enable cache coherency (eg: single
diff --git a/docs/maintainers.rst b/docs/maintainers.rst
index 5449faa..098fc5f 100644
--- a/docs/maintainers.rst
+++ b/docs/maintainers.rst
@@ -11,10 +11,16 @@
----------------
:M: Dan Handley <dan.handley@arm.com>
:G: `danh-arm`_
-:M: Dimitris Papastamos <dimitrs.papastamos@arm.com>
-:G: `dp-arm`_
:M: Soby Mathew <soby.mathew@arm.com>
:G: `soby-mathew`_
+:M: Sandrine Bailleux <sandrine.bailleux@arm.com>
+:G: `sandrine-bailleux-arm`_
+:M: Alexei Fedorov <alexei.fedorov@arm.com>
+:G: `AlexeiFedorov`_
+:M: Paul Beesley <paul.beesley@arm.com>
+:G: `pbeesley-arm`_
+:M: John Tsichritzis <john.tsichritzis@arm.com>
+:G: `jts-arm`_
Allwinner ARMv8 platform port
-----------------------------
@@ -260,28 +266,33 @@
:F: docs/plat/xilinx-zynqmp.rst
:F: plat/xilinx/
+.. _AlexeiFedorov: https://github.com/AlexeiFedorov
.. _Andre-ARM: https://github.com/Andre-ARM
.. _Anson-Huang: https://github.com/Anson-Huang
.. _bryanodonoghue: https://github.com/bryanodonoghue
.. _b49020: https://github.com/b49020
.. _danh-arm: https://github.com/danh-arm
-.. _dp-arm: https://github.com/dp-arm
.. _etienne-lms: https://github.com/etienne-lms
.. _glneo: https://github.com/glneo
+.. _grandpaul: https://github.com/grandpaul
.. _hzhuang1: https://github.com/hzhuang1
.. _JackyBai: https://github.com/JackyBai
.. _jenswi-linaro: https://github.com/jenswi-linaro
+.. _jts-arm: https://github.com/jts-arm
+.. _jwerner-chromium: https://github.com/jwerner-chromium
+.. _kostapr: https://github.com/kostapr
.. _ldts: https://github.com/ldts
.. _marex: https://github.com/marex
-.. _niej: https://github.com/niej
-.. _kostapr: https://github.com/kostapr
.. _masahir0y: https://github.com/masahir0y
.. _mmind: https://github.com/mmind
.. _mtk09422: https://github.com/mtk09422
+.. _niej: https://github.com/niej
.. _npoushin: https://github.com/npoushin
+.. _pbeesley-arm: https://github.com/pbeesley-arm
.. _qoriq-open-source: https://github.com/qoriq-open-source
.. _remi-triplefault: https://github.com/repk
.. _rockchip-linux: https://github.com/rockchip-linux
+.. _sandrine-bailleux-arm: https://github.com/sandrine-bailleux-arm
.. _shawnguo2: https://github.com/shawnguo2
.. _sivadur: https://github.com/sivadur
.. _smaeul: https://github.com/smaeul
@@ -290,5 +301,3 @@
.. _TonyXie06: https://github.com/TonyXie06
.. _vwadekar: https://github.com/vwadekar
.. _Yann-lms: https://github.com/Yann-lms
-.. _grandpaul: https://github.com/grandpaul
-.. _jwerner-chromium: https://github.com/jwerner-chromium
diff --git a/lib/cpus/aarch64/cortex_a53.S b/lib/cpus/aarch64/cortex_a53.S
index 6fd3c53..b105de2 100644
--- a/lib/cpus/aarch64/cortex_a53.S
+++ b/lib/cpus/aarch64/cortex_a53.S
@@ -279,13 +279,11 @@
func cortex_a53_core_pwr_dwn
mov x18, x30
-#if !TI_AM65X_WORKAROUND
/* ---------------------------------------------
* Turn off caches.
* ---------------------------------------------
*/
bl cortex_a53_disable_dcache
-#endif
/* ---------------------------------------------
* Flush L1 caches.
@@ -305,13 +303,11 @@
func cortex_a53_cluster_pwr_dwn
mov x18, x30
-#if !TI_AM65X_WORKAROUND
/* ---------------------------------------------
* Turn off caches.
* ---------------------------------------------
*/
bl cortex_a53_disable_dcache
-#endif
/* ---------------------------------------------
* Flush L1 caches.
diff --git a/lib/psci/psci_common.c b/lib/psci/psci_common.c
index 2928c33..3f5e989 100644
--- a/lib/psci/psci_common.c
+++ b/lib/psci/psci_common.c
@@ -568,35 +568,35 @@
}
/*******************************************************************************
- * This function is passed a cpu_index and the highest level in the topology
- * tree that the operation should be applied to. It picks up locks in order of
- * increasing power domain level in the range specified.
+ * This function is passed the highest level in the topology tree that the
+ * operation should be applied to and a list of node indexes. It picks up locks
+ * from the node index list in order of increasing power domain level in the
+ * range specified.
******************************************************************************/
-void psci_acquire_pwr_domain_locks(unsigned int end_pwrlvl, int cpu_idx)
+void psci_acquire_pwr_domain_locks(unsigned int end_pwrlvl,
+ const unsigned int *parent_nodes)
{
- unsigned int parent_idx = psci_cpu_pd_nodes[cpu_idx].parent_node;
+ unsigned int parent_idx;
unsigned int level;
/* No locking required for level 0. Hence start locking from level 1 */
for (level = PSCI_CPU_PWR_LVL + 1U; level <= end_pwrlvl; level++) {
+ parent_idx = parent_nodes[level - 1U];
psci_lock_get(&psci_non_cpu_pd_nodes[parent_idx]);
- parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node;
}
}
/*******************************************************************************
- * This function is passed a cpu_index and the highest level in the topology
- * tree that the operation should be applied to. It releases the locks in order
- * of decreasing power domain level in the range specified.
+ * This function is passed the highest level in the topology tree that the
+ * operation should be applied to and a list of node indexes. It releases the
+ * locks in order of decreasing power domain level in the range specified.
******************************************************************************/
-void psci_release_pwr_domain_locks(unsigned int end_pwrlvl, int cpu_idx)
+void psci_release_pwr_domain_locks(unsigned int end_pwrlvl,
+ const unsigned int *parent_nodes)
{
- unsigned int parent_idx, parent_nodes[PLAT_MAX_PWR_LVL] = {0};
+ unsigned int parent_idx;
unsigned int level;
- /* Get the parent nodes */
- psci_get_parent_pwr_domain_nodes(cpu_idx, end_pwrlvl, parent_nodes);
-
/* Unlock top down. No unlocking required for level 0. */
for (level = end_pwrlvl; level >= PSCI_CPU_PWR_LVL + 1U; level--) {
parent_idx = parent_nodes[level - 1U];
@@ -764,6 +764,7 @@
{
unsigned int end_pwrlvl;
int cpu_idx = (int) plat_my_core_pos();
+ unsigned int parent_nodes[PLAT_MAX_PWR_LVL] = {0};
psci_power_state_t state_info = { {PSCI_LOCAL_STATE_RUN} };
/*
@@ -781,12 +782,15 @@
*/
end_pwrlvl = get_power_on_target_pwrlvl();
+ /* Get the parent nodes */
+ psci_get_parent_pwr_domain_nodes(cpu_idx, end_pwrlvl, parent_nodes);
+
/*
* This function acquires the lock corresponding to each power level so
* that by the time all locks are taken, the system topology is snapshot
* and state management can be done safely.
*/
- psci_acquire_pwr_domain_locks(end_pwrlvl, cpu_idx);
+ psci_acquire_pwr_domain_locks(end_pwrlvl, parent_nodes);
psci_get_target_local_pwr_states(end_pwrlvl, &state_info);
@@ -831,7 +835,7 @@
* This loop releases the lock corresponding to each power level
* in the reverse order to which they were acquired.
*/
- psci_release_pwr_domain_locks(end_pwrlvl, cpu_idx);
+ psci_release_pwr_domain_locks(end_pwrlvl, parent_nodes);
}
/*******************************************************************************
diff --git a/lib/psci/psci_off.c b/lib/psci/psci_off.c
index ac03e05..e8cd8fe 100644
--- a/lib/psci/psci_off.c
+++ b/lib/psci/psci_off.c
@@ -45,6 +45,7 @@
int rc = PSCI_E_SUCCESS;
int idx = (int) plat_my_core_pos();
psci_power_state_t state_info;
+ unsigned int parent_nodes[PLAT_MAX_PWR_LVL] = {0};
/*
* This function must only be called on platforms where the
@@ -56,11 +57,20 @@
psci_set_power_off_state(&state_info);
/*
+ * Get the parent nodes here, this is important to do before we
+ * initiate the power down sequence as after that point the core may
+ * have exited coherency and its cache may be disabled, any access to
+ * shared memory after that (such as the parent node lookup in
+ * psci_cpu_pd_nodes) can cause coherency issues on some platforms.
+ */
+ psci_get_parent_pwr_domain_nodes(idx, end_pwrlvl, parent_nodes);
+
+ /*
* This function acquires the lock corresponding to each power
* level so that by the time all locks are taken, the system topology
* is snapshot and state management can be done safely.
*/
- psci_acquire_pwr_domain_locks(end_pwrlvl, idx);
+ psci_acquire_pwr_domain_locks(end_pwrlvl, parent_nodes);
/*
* Call the cpu off handler registered by the Secure Payload Dispatcher
@@ -122,7 +132,7 @@
* Release the locks corresponding to each power level in the
* reverse order to which they were acquired.
*/
- psci_release_pwr_domain_locks(end_pwrlvl, idx);
+ psci_release_pwr_domain_locks(end_pwrlvl, parent_nodes);
/*
* Check if all actions needed to safely power down this cpu have
diff --git a/lib/psci/psci_private.h b/lib/psci/psci_private.h
index 68ec7fb..bbcc5cf 100644
--- a/lib/psci/psci_private.h
+++ b/lib/psci/psci_private.h
@@ -274,8 +274,10 @@
unsigned int *node_index);
void psci_do_state_coordination(unsigned int end_pwrlvl,
psci_power_state_t *state_info);
-void psci_acquire_pwr_domain_locks(unsigned int end_pwrlvl, int cpu_idx);
-void psci_release_pwr_domain_locks(unsigned int end_pwrlvl, int cpu_idx);
+void psci_acquire_pwr_domain_locks(unsigned int end_pwrlvl,
+ const unsigned int *parent_nodes);
+void psci_release_pwr_domain_locks(unsigned int end_pwrlvl,
+ const unsigned int *parent_nodes);
int psci_validate_suspend_req(const psci_power_state_t *state_info,
unsigned int is_power_down_state);
unsigned int psci_find_max_off_lvl(const psci_power_state_t *state_info);
diff --git a/lib/psci/psci_suspend.c b/lib/psci/psci_suspend.c
index 8a752c1..6d5c099 100644
--- a/lib/psci/psci_suspend.c
+++ b/lib/psci/psci_suspend.c
@@ -28,10 +28,13 @@
static void psci_suspend_to_standby_finisher(int cpu_idx,
unsigned int end_pwrlvl)
{
+ unsigned int parent_nodes[PLAT_MAX_PWR_LVL] = {0};
psci_power_state_t state_info;
- psci_acquire_pwr_domain_locks(end_pwrlvl,
- cpu_idx);
+ /* Get the parent nodes */
+ psci_get_parent_pwr_domain_nodes(cpu_idx, end_pwrlvl, parent_nodes);
+
+ psci_acquire_pwr_domain_locks(end_pwrlvl, parent_nodes);
/*
* Find out which retention states this CPU has exited from until the
@@ -57,8 +60,7 @@
*/
psci_set_pwr_domains_to_run(end_pwrlvl);
- psci_release_pwr_domain_locks(end_pwrlvl,
- cpu_idx);
+ psci_release_pwr_domain_locks(end_pwrlvl, parent_nodes);
}
/*******************************************************************************
@@ -156,6 +158,7 @@
{
int skip_wfi = 0;
int idx = (int) plat_my_core_pos();
+ unsigned int parent_nodes[PLAT_MAX_PWR_LVL] = {0};
/*
* This function must only be called on platforms where the
@@ -164,13 +167,15 @@
assert((psci_plat_pm_ops->pwr_domain_suspend != NULL) &&
(psci_plat_pm_ops->pwr_domain_suspend_finish != NULL));
+ /* Get the parent nodes */
+ psci_get_parent_pwr_domain_nodes(idx, end_pwrlvl, parent_nodes);
+
/*
* This function acquires the lock corresponding to each power
* level so that by the time all locks are taken, the system topology
* is snapshot and state management can be done safely.
*/
- psci_acquire_pwr_domain_locks(end_pwrlvl,
- idx);
+ psci_acquire_pwr_domain_locks(end_pwrlvl, parent_nodes);
/*
* We check if there are any pending interrupts after the delay
@@ -214,8 +219,8 @@
* Release the locks corresponding to each power level in the
* reverse order to which they were acquired.
*/
- psci_release_pwr_domain_locks(end_pwrlvl,
- idx);
+ psci_release_pwr_domain_locks(end_pwrlvl, parent_nodes);
+
if (skip_wfi == 1)
return;
diff --git a/plat/allwinner/common/allwinner-common.mk b/plat/allwinner/common/allwinner-common.mk
index f20f515..585079b 100644
--- a/plat/allwinner/common/allwinner-common.mk
+++ b/plat/allwinner/common/allwinner-common.mk
@@ -38,6 +38,12 @@
# The bootloader is guaranteed to only run on CPU 0 by the boot ROM.
COLD_BOOT_SINGLE_CPU := 1
+# Do not enable SPE (not supported on ARM v8.0).
+ENABLE_SPE_FOR_LOWER_ELS := 0
+
+# Do not enable SVE (not supported on ARM v8.0).
+ENABLE_SVE_FOR_NS := 0
+
# Enable workarounds for Cortex-A53 errata. Allwinner uses at least r0p4.
ERRATA_A53_835769 := 1
ERRATA_A53_843419 := 1
@@ -56,3 +62,6 @@
# We are short on memory, so save 3.5KB by not having an extra coherent page.
USE_COHERENT_MEM := 0
+
+# This platform is single-cluster and does not require coherency setup.
+WARMBOOT_ENABLE_DCACHE_EARLY := 1
diff --git a/plat/arm/common/sp_min/arm_sp_min.mk b/plat/arm/common/sp_min/arm_sp_min.mk
index edab884..dbd451c 100644
--- a/plat/arm/common/sp_min/arm_sp_min.mk
+++ b/plat/arm/common/sp_min/arm_sp_min.mk
@@ -1,15 +1,16 @@
#
-# Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
# SP MIN source files common to ARM standard platforms
-# Skip building BL1 and BL2 if RESET_TO_SP_MIN flag is set.
+# Skip building BL1, BL2 and BL2U if RESET_TO_SP_MIN flag is set.
ifeq (${RESET_TO_SP_MIN},1)
BL1_SOURCES =
BL2_SOURCES =
+ BL2U_SOURCES =
endif
BL32_SOURCES += plat/arm/common/arm_pm.c \
@@ -17,4 +18,3 @@
plat/arm/common/sp_min/arm_sp_min_setup.c \
plat/common/aarch32/platform_mp_stack.S \
plat/common/plat_psci_common.c
-
diff --git a/plat/ti/k3/common/k3_psci.c b/plat/ti/k3/common/k3_psci.c
index c7754e9..de9cefe 100644
--- a/plat/ti/k3/common/k3_psci.c
+++ b/plat/ti/k3/common/k3_psci.c
@@ -17,11 +17,6 @@
#include <k3_gicv3.h>
#include <ti_sci.h>
-#ifdef TI_AM65X_WORKAROUND
-/* Need to flush psci internal locks before shutdown or their values are lost */
-#include "../../../../lib/psci/psci_private.h"
-#endif
-
uintptr_t k3_sec_entrypoint;
static void k3_cpu_standby(plat_local_state_t cpu_state)
@@ -114,16 +109,6 @@
k3_gic_pcpu_init();
k3_gic_cpuif_enable();
}
-
-#ifdef TI_AM65X_WORKAROUND
-static void __dead2 k3_pwr_domain_pwr_down_wfi(const psci_power_state_t
- *target_state)
-{
- flush_cpu_data(psci_svc_cpu_data);
- flush_dcache_range((uintptr_t) psci_locks, sizeof(psci_locks));
- psci_power_down_wfi();
-}
-#endif
static void __dead2 k3_system_reset(void)
{
@@ -154,9 +139,6 @@
.pwr_domain_on = k3_pwr_domain_on,
.pwr_domain_off = k3_pwr_domain_off,
.pwr_domain_on_finish = k3_pwr_domain_on_finish,
-#ifdef TI_AM65X_WORKAROUND
- .pwr_domain_pwr_down_wfi = k3_pwr_domain_pwr_down_wfi,
-#endif
.system_reset = k3_system_reset,
.validate_power_state = k3_validate_power_state,
.validate_ns_entrypoint = k3_validate_ns_entrypoint
diff --git a/plat/ti/k3/common/plat_common.mk b/plat/ti/k3/common/plat_common.mk
index 2e5f584..83e9c62 100644
--- a/plat/ti/k3/common/plat_common.mk
+++ b/plat/ti/k3/common/plat_common.mk
@@ -12,8 +12,8 @@
PROGRAMMABLE_RESET_ADDRESS:= 1
# System coherency is managed in hardware
-HW_ASSISTED_COHERENCY := 1
-USE_COHERENT_MEM := 0
+WARMBOOT_ENABLE_DCACHE_EARLY := 1
+USE_COHERENT_MEM := 1
# A53 erratum for SoC. (enable them all)
ERRATA_A53_826319 := 1
@@ -28,10 +28,6 @@
# Split out RO data into a non-executable section
SEPARATE_CODE_AND_RODATA := 1
-# Leave the caches enabled on core powerdown path
-TI_AM65X_WORKAROUND := 1
-$(eval $(call add_define,TI_AM65X_WORKAROUND))
-
MULTI_CONSOLE_API := 1
TI_16550_MDR_QUIRK := 1
$(eval $(call add_define,TI_16550_MDR_QUIRK))
diff --git a/readme.rst b/readme.rst
index 6846419..84c8020 100644
--- a/readme.rst
+++ b/readme.rst
@@ -222,7 +222,7 @@
This release also contains the following platform support:
-- Allwinner sun50i_a64 and sun50i_h6
+- Allwinner sun50i (A64, H5, and H6) SoCs
- Amlogic Meson S905 (GXBB)
- Amlogic Meson S905x (GXL)
- Arm Juno Software Development Platform