Merge changes from topic "el3_direct_msg" into integration
* changes:
docs(spm): document new build option
feat(fvp): spmd logical partition smc handler
feat(fvp): add spmd logical partition
feat(spmd): get logical partitions info
feat(spmd): add partition info get regs
refactor(ff-a): move structure definitions
feat(spmd): el3 direct message API
feat(spmd): add spmd logical partitions
diff --git a/.gitignore b/.gitignore
index ac9a11d..e07d997 100644
--- a/.gitignore
+++ b/.gitignore
@@ -22,6 +22,7 @@
tools/renesas/rzg_layout_create/*.elf
tools/fiptool/fiptool
tools/fiptool/fiptool.exe
+tools/memory/memory/__pycache__/
tools/cert_create/src/*.o
tools/cert_create/src/**/*.o
tools/cert_create/cert_create
diff --git a/.readthedocs.yaml b/.readthedocs.yaml
index e3a7ebf..7b6a1f5 100644
--- a/.readthedocs.yaml
+++ b/.readthedocs.yaml
@@ -15,6 +15,7 @@
python: "3.10"
apt_packages:
- plantuml
+ - librsvg2-bin
jobs:
post_create_environment:
- pip install poetry=="1.3.2"
diff --git a/Makefile b/Makefile
index f3ab71a..0c35120 100644
--- a/Makefile
+++ b/Makefile
@@ -139,6 +139,7 @@
SPTOOLPATH ?= tools/sptool
SPTOOL ?= ${SPTOOLPATH}/sptool.py
SP_MK_GEN ?= ${SPTOOLPATH}/sp_mk_generator.py
+SP_DTS_LIST_FRAGMENT ?= ${BUILD_PLAT}/sp_list_fragment.dts
# Variables for use with ROMLIB
ROMLIBPATH ?= lib/romlib
@@ -1553,8 +1554,8 @@
# Add Secure Partition packages
ifeq (${NEED_SP_PKG},yes)
-$(BUILD_PLAT)/sp_gen.mk: ${SP_MK_GEN} ${SP_LAYOUT_FILE} | ${BUILD_PLAT}
- ${Q}${PYTHON} "$<" "$@" $(filter-out $<,$^) $(BUILD_PLAT) ${COT}
+$(BUILD_PLAT)/sp_gen.mk : ${SP_MK_GEN} ${SP_LAYOUT_FILE} | ${BUILD_PLAT}
+ ${PYTHON} "$<" "$@" $(filter-out $<,$^) $(BUILD_PLAT) ${COT} ${SP_DTS_LIST_FRAGMENT}
sp: $(DTBS) $(BUILD_PLAT)/sp_gen.mk $(SP_PKGS)
@${ECHO_BLANK_LINE}
@echo "Built SP Images successfully"
diff --git a/bl32/sp_min/aarch32/entrypoint.S b/bl32/sp_min/aarch32/entrypoint.S
index f102967..693dd4b 100644
--- a/bl32/sp_min/aarch32/entrypoint.S
+++ b/bl32/sp_min/aarch32/entrypoint.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -62,11 +62,8 @@
* The Cold boot/Reset entrypoint for SP_MIN
*/
func sp_min_entrypoint
-#if !RESET_TO_SP_MIN
/* ---------------------------------------------------------------
- * Preceding bootloader has populated r0 with a pointer to a
- * 'bl_params_t' structure & r1 with a pointer to platform
- * specific structure
+ * Stash the previous bootloader arguments r0 - r3 for later use.
* ---------------------------------------------------------------
*/
mov r9, r0
@@ -74,6 +71,7 @@
mov r11, r2
mov r12, r3
+#if !RESET_TO_SP_MIN
/* ---------------------------------------------------------------------
* For !RESET_TO_SP_MIN systems, only the primary CPU ever reaches
* sp_min_entrypoint() during the cold boot flow, so the cold/warm boot
@@ -91,11 +89,6 @@
_init_c_runtime=1 \
_exception_vectors=sp_min_vector_table \
_pie_fixup_size=FIXUP_SIZE
-
- /* ---------------------------------------------------------------------
- * Relay the previous bootloader's arguments to the platform layer
- * ---------------------------------------------------------------------
- */
#else
/* ---------------------------------------------------------------------
* For RESET_TO_SP_MIN systems which have a programmable reset address,
@@ -111,24 +104,16 @@
_init_c_runtime=1 \
_exception_vectors=sp_min_vector_table \
_pie_fixup_size=FIXUP_SIZE
-
- /* ---------------------------------------------------------------------
- * For RESET_TO_SP_MIN systems, BL32 (SP_MIN) is the first bootloader
- * to run so there's no argument to relay from a previous bootloader.
- * Zero the arguments passed to the platform layer to reflect that.
- * ---------------------------------------------------------------------
- */
- mov r9, #0
- mov r10, #0
- mov r11, #0
- mov r12, #0
-
#endif /* RESET_TO_SP_MIN */
#if SP_MIN_WITH_SECURE_FIQ
route_fiq_to_sp_min r4
#endif
+ /* ---------------------------------------------------------------------
+ * Relay the previous bootloader's arguments to the platform layer
+ * ---------------------------------------------------------------------
+ */
mov r0, r9
mov r1, r10
mov r2, r11
diff --git a/bl32/sp_min/sp_min.mk b/bl32/sp_min/sp_min.mk
index 0b7bc57..065468c 100644
--- a/bl32/sp_min/sp_min.mk
+++ b/bl32/sp_min/sp_min.mk
@@ -17,6 +17,7 @@
bl32/sp_min/aarch32/entrypoint.S \
common/runtime_svc.c \
plat/common/aarch32/plat_sp_min_common.c\
+ services/arm_arch_svc/arm_arch_svc_setup.c \
services/std_svc/std_svc_setup.c \
${PSCI_LIB_SOURCES}
diff --git a/bl32/sp_min/sp_min_main.c b/bl32/sp_min/sp_min_main.c
index f050160..26cf207 100644
--- a/bl32/sp_min/sp_min_main.c
+++ b/bl32/sp_min/sp_min_main.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -134,6 +134,7 @@
assert(NON_SECURE == GET_SECURITY_STATE(next_image_info->h.attr));
INFO("SP_MIN: Preparing exit to normal world\n");
+ print_entry_point_info(next_image_info);
psci_prepare_next_non_secure_ctx(next_image_info);
smc_set_next_ctx(NON_SECURE);
diff --git a/docs/components/realm-management-extension.rst b/docs/components/realm-management-extension.rst
index 919eea5..f228e6b 100644
--- a/docs/components/realm-management-extension.rst
+++ b/docs/components/realm-management-extension.rst
@@ -157,7 +157,7 @@
git clone https://git.trustedfirmware.org/TF-A/tf-a-tests.git
cd tf-a-tests
- make CROSS_COMPILE=aarch64-none-elf- PLAT=fvp DEBUG=1 all pack_realm
+ make CROSS_COMPILE=aarch64-none-elf- PLAT=fvp DEBUG=1 ENABLE_REALM_PAYLOAD_TESTS=1 all
This produces a TF-A Tests binary (**tftf.bin**) with Realm payload packaged
and **sp_layout.json** in the **build/fvp/debug** directory.
diff --git a/docs/conf.py b/docs/conf.py
index 345f53b..9e7a5f8 100644
--- a/docs/conf.py
+++ b/docs/conf.py
@@ -26,7 +26,7 @@
"myst_parser",
"sphinx.ext.autosectionlabel",
"sphinxcontrib.plantuml",
- "sphinxcontrib.inkscapeconverter",
+ "sphinxcontrib.rsvgconverter",
]
# Add any paths that contain templates here, relative to this directory.
@@ -108,4 +108,5 @@
latex_elements = {
"maxlistdepth": "10",
"pointsize": "11pt",
+ "extraclassoptions": "openany"
}
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index df0cfc0..bb12d7d 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -601,47 +601,50 @@
For Neoverse N2, the following errata build flags are defined :
- ``ERRATA_N2_2002655``: This applies errata 2002655 workaround to Neoverse-N2
- CPU. This needs to be enabled for revision r0p0 of the CPU, it is still open.
+ CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
- ``ERRATA_N2_2067956``: This applies errata 2067956 workaround to Neoverse-N2
- CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
+ CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
- ``ERRATA_N2_2025414``: This applies errata 2025414 workaround to Neoverse-N2
- CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
+ CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
- ``ERRATA_N2_2189731``: This applies errata 2189731 workaround to Neoverse-N2
- CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
+ CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
- ``ERRATA_N2_2138956``: This applies errata 2138956 workaround to Neoverse-N2
- CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
+ CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
- ``ERRATA_N2_2138953``: This applies errata 2138953 workaround to Neoverse-N2
- CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
+ CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, r0p3 and is still open.
- ``ERRATA_N2_2242415``: This applies errata 2242415 workaround to Neoverse-N2
- CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
+ CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
- ``ERRATA_N2_2138958``: This applies errata 2138958 workaround to Neoverse-N2
- CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
+ CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
- ``ERRATA_N2_2242400``: This applies errata 2242400 workaround to Neoverse-N2
- CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
+ CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
- ``ERRATA_N2_2280757``: This applies errata 2280757 workaround to Neoverse-N2
- CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
+ CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
- ``ERRATA_N2_2326639``: This applies errata 2326639 workaround to Neoverse-N2
CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in
r0p1.
- ``ERRATA_N2_2376738``: This applies errata 2376738 workaround to Neoverse-N2
- CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in
- r0p1.
+ CPU. This needs to be enabled for revision r0p0, r0p1, r0p2, r0p3 and is still open.
- ``ERRATA_N2_2388450``: This applies errata 2388450 workaround to Neoverse-N2
CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in
r0p1.
+- ``ERRATA_N2_2743014``: This applies errata 2743014 workaround to Neoverse-N2
+ CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is fixed
+ in r0p3.
+
- ``ERRATA_N2_2743089``: This applies errata 2743089 workaround to Neoverse-N2
CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is fixed
in r0p3.
@@ -651,6 +654,10 @@
interconnect IP. This needs to be enabled for revisions r0p0, r0p1 and r0p2.
It is fixed in r0p3.
+- ``ERRATA_N2_2779511``: This applies errata 2779511 workaround to Neoverse-N2
+ CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is fixed
+ in r0p3.
+
For Cortex-X2, the following errata build flags are defined :
- ``ERRATA_X2_2002765``: This applies errata 2002765 workaround to Cortex-X2
diff --git a/docs/design_documents/measured_boot.rst b/docs/design_documents/measured_boot.rst
index 8130d7d..c4e5213 100644
--- a/docs/design_documents/measured_boot.rst
+++ b/docs/design_documents/measured_boot.rst
@@ -204,6 +204,28 @@
In FVP, Non volatile counters get measured and recorded as Critical data
using the backend via this interface.
+#. **Function : plat_mboot_measure_key()**
+
+ .. code-block:: c
+
+ int plat_mboot_measure_key(const void *pk_oid, const void *pk_ptr,
+ size_t pk_len);
+
+ - This function is used by the platform to measure the passed key and
+ publicise it using any of the supported backends.
+ - The authentication module within the trusted boot framework calls this
+ function for every ROTPK involved in verifying the signature of a root
+ certificate and for every subsidiary key that gets extracted from a key
+ certificate for later authentication of a content certificate.
+ - A cookie, passed as the first argument, serves as a key-OID pointer
+ associated with the public key data, passed as the second argument.
+ - Public key data size is passed as the third argument to this function.
+ - This function must return 0 on success, a signed integer error code
+ otherwise.
+ - In FVP platform, this function is used to calculate the hash of the given
+ key and forward this hash to RSS alongside the measurement of the image
+ which the key signs.
+
--------------
*Copyright (c) 2023, Arm Limited. All rights reserved.*
diff --git a/docs/design_documents/rss.rst b/docs/design_documents/rss.rst
index 2be8067..2ad2ee7 100644
--- a/docs/design_documents/rss.rst
+++ b/docs/design_documents/rss.rst
@@ -262,7 +262,8 @@
- ``SW type``: Optional. Short text description (e.g.: BL1, BL2, BL31, etc.)
.. Note::
- Signer-id and version info is not implemented in TF-A yet.
+ Version info is not implemented in TF-A yet.
+
The caller must specify in which measurement slot to extend a certain
measurement and metadata. A measurement slot can be extended by multiple
@@ -321,9 +322,38 @@
size_t version_size;
uint8_t sw_type[SW_TYPE_MAX_SIZE];
size_t sw_type_size;
+ void *pk_oid;
bool lock_measurement;
};
+Signer-ID API
+^^^^^^^^^^^^^
+
+This function calculates the hash of a public key (signer-ID) using the
+``Measurement algorithm`` and stores it in the ``rss_mboot_metadata`` field
+named ``signer_id``.
+Prior to calling this function, the caller must ensure that the ``signer_id``
+field points to the zero-filled buffer.
+
+Defined here:
+
+- ``include/drivers/measured_boot/rss/rss_measured_boot.h``
+
+.. code-block:: c
+
+ int rss_mboot_set_signer_id(struct rss_mboot_metadata *metadata_ptr,
+ const void *pk_oid,
+ const void *pk_ptr,
+ size_t pk_len)
+
+
+- First parameter is the pointer to the ``rss_mboot_metadata`` structure.
+- Second parameter is the pointer to the key-OID of the public key.
+- Third parameter is the pointer to the public key buffer.
+- Fourth parameter is the size of public key buffer.
+- This function returns 0 on success, a signed integer error code
+ otherwise.
+
Build time config options
^^^^^^^^^^^^^^^^^^^^^^^^^
@@ -361,8 +391,8 @@
INFO: Image id=24 loaded: 0x4001300 - 0x400153a
INFO: Measured boot extend measurement:
INFO: - slot : 7
- INFO: - signer_id : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
- INFO: : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+ INFO: - signer_id : b0 f3 82 09 12 97 d8 3a 37 7a 72 47 1b ec 32 73
+ INFO: : e9 92 32 e2 49 59 f6 5e 8b 4a 4a 46 d8 22 9a da
INFO: - version :
INFO: - version_size: 0
INFO: - sw_type : TB_FW_CONFIG
@@ -377,8 +407,8 @@
INFO: Image id=1 loaded: 0x404d000 - 0x406412a
INFO: Measured boot extend measurement:
INFO: - slot : 8
- INFO: - signer_id : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
- INFO: : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+ INFO: - signer_id : b0 f3 82 09 12 97 d8 3a 37 7a 72 47 1b ec 32 73
+ INFO: : e9 92 32 e2 49 59 f6 5e 8b 4a 4a 46 d8 22 9a da
INFO: - version :
INFO: - version_size: 0
INFO: - sw_type : BL_2
@@ -483,31 +513,31 @@
INFO: a2 6a df 34 c3 29 48 9a dc 38 04 67 31 2e 35 2e
INFO: 30 2b 30 01 60 02 58 20 b8 01 65 a7 78 8b c6 59
INFO: 42 8d 33 10 85 d1 49 0a dc 9e c3 ee df 85 1b d2
- INFO: f0 73 73 6a 0c 07 11 b8 a4 05 58 20 00 00 00 00
- INFO: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
- INFO: 00 00 00 00 00 00 00 00 00 00 00 00 04 60 01 6a
+ INFO: f0 73 73 6a 0c 07 11 b8 a4 05 58 20 b0 f3 82 09
+ INFO: 12 97 d8 3a 37 7a 72 47 1b ec 32 73 e9 92 32 e2
+ INFO: 49 59 f6 5e 8b 4a 4a 46 d8 22 9a da 04 60 01 6a
INFO: 46 57 5f 43 4f 4e 46 49 47 00 02 58 20 21 9e a0
INFO: 13 82 e6 d7 97 5a 11 13 a3 5f 45 39 68 b1 d9 a3
INFO: ea 6a ab 84 23 3b 8c 06 16 98 20 ba b9 a4 05 58
- INFO: 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
- INFO: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
- INFO: 00 04 60 01 6d 54 42 5f 46 57 5f 43 4f 4e 46 49
+ INFO: 20 b0 f3 82 09 12 97 d8 3a 37 7a 72 47 1b ec 32
+ INFO: 73 e9 92 32 e2 49 59 f6 5e 8b 4a 4a 46 d8 22 9a
+ INFO: da 04 60 01 6d 54 42 5f 46 57 5f 43 4f 4e 46 49
INFO: 47 00 02 58 20 41 39 f6 c2 10 84 53 c5 17 ae 9a
INFO: e5 be c1 20 7b cc 24 24 f3 9d 20 a8 fb c7 b3 10
- INFO: e3 ee af 1b 05 a4 05 58 20 00 00 00 00 00 00 00
- INFO: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
- INFO: 00 00 00 00 00 00 00 00 00 04 60 01 65 42 4c 5f
+ INFO: e3 ee af 1b 05 a4 05 58 20 b0 f3 82 09 12 97 d8
+ INFO: 3a 37 7a 72 47 1b ec 32 73 e9 92 32 e2 49 59 f6
+ INFO: 5e 8b 4a 4a 46 d8 22 9a da 04 60 01 65 42 4c 5f
INFO: 32 00 02 58 20 5c 96 20 e1 e3 3b 0f 2c eb c1 8e
INFO: 1a 02 a6 65 86 dd 34 97 a7 4c 98 13 bf 74 14 45
- INFO: 2d 30 28 05 c3 a4 05 58 20 00 00 00 00 00 00 00
- INFO: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
- INFO: 00 00 00 00 00 00 00 00 00 04 60 01 6e 53 45 43
+ INFO: 2d 30 28 05 c3 a4 05 58 20 b0 f3 82 09 12 97 d8
+ INFO: 3a 37 7a 72 47 1b ec 32 73 e9 92 32 e2 49 59 f6
+ INFO: 5e 8b 4a 4a 46 d8 22 9a da 04 60 01 6e 53 45 43
INFO: 55 52 45 5f 52 54 5f 45 4c 33 00 02 58 20 f6 fb
INFO: 62 99 a5 0c df db 02 0b 72 5b 1c 0b 63 6e 94 ee
INFO: 66 50 56 3a 29 9c cb 38 f0 ec 59 99 d4 2e a4 05
- INFO: 58 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00
- INFO: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
- INFO: 00 00 04 60 01 6a 48 57 5f 43 4f 4e 46 49 47 00
+ INFO: 58 20 b0 f3 82 09 12 97 d8 3a 37 7a 72 47 1b ec
+ INFO: 32 73 e9 92 32 e2 49 59 f6 5e 8b 4a 4a 46 d8 22
+ INFO: 9a da 04 60 01 6a 48 57 5f 43 4f 4e 46 49 47 00
INFO: 02 58 20 98 5d 87 21 84 06 33 9d c3 1f 91 f5 68
INFO: 8d a0 5a f0 d7 7e 20 51 ce 3b f2 a5 c3 05 2e 3c
INFO: 8b 52 31 19 01 09 78 1c 68 74 74 70 3a 2f 2f 61
@@ -559,31 +589,31 @@
"MEASUREMENT_VALUE": "b'B80165A7788BC659428D331085D1490ADC9EC3EEDF851BD2F073736A0C0711B8'"
},
{
- "SIGNER_ID": "b'0000000000000000000000000000000000000000000000000000000000000000'",
+ "SIGNER_ID": "b'b0f382091297d83a377a72471bec3273e99232e24959f65e8b4a4a46d8229ada'",
"SW_COMPONENT_VERSION": "",
"SW_COMPONENT_TYPE": "FW_CONFIG\u0000",
"MEASUREMENT_VALUE": "b'219EA01382E6D7975A1113A35F453968B1D9A3EA6AAB84233B8C06169820BAB9'"
},
{
- "SIGNER_ID": "b'0000000000000000000000000000000000000000000000000000000000000000'",
+ "SIGNER_ID": "b'b0f382091297d83a377a72471bec3273e99232e24959f65e8b4a4a46d8229ada'",
"SW_COMPONENT_VERSION": "",
"SW_COMPONENT_TYPE": "TB_FW_CONFIG\u0000",
"MEASUREMENT_VALUE": "b'4139F6C2108453C517AE9AE5BEC1207BCC2424F39D20A8FBC7B310E3EEAF1B05'"
},
{
- "SIGNER_ID": "b'0000000000000000000000000000000000000000000000000000000000000000'",
+ "SIGNER_ID": "b'b0f382091297d83a377a72471bec3273e99232e24959f65e8b4a4a46d8229ada'",
"SW_COMPONENT_VERSION": "",
"SW_COMPONENT_TYPE": "BL_2\u0000",
"MEASUREMENT_VALUE": "b'5C9620E1E33B0F2CEBC18E1A02A66586DD3497A74C9813BF7414452D302805C3'"
},
{
- "SIGNER_ID": "b'0000000000000000000000000000000000000000000000000000000000000000'",
+ "SIGNER_ID": "b'b0f382091297d83a377a72471bec3273e99232e24959f65e8b4a4a46d8229ada'",
"SW_COMPONENT_VERSION": "",
"SW_COMPONENT_TYPE": "SECURE_RT_EL3\u0000",
"MEASUREMENT_VALUE": "b'F6FB6299A50CDFDB020B725B1C0B636E94EE6650563A299CCB38F0EC5999D42E'"
},
{
- "SIGNER_ID": "b'0000000000000000000000000000000000000000000000000000000000000000'",
+ "SIGNER_ID": "b'b0f382091297d83a377a72471bec3273e99232e24959f65e8b4a4a46d8229ada'",
"SW_COMPONENT_VERSION": "",
"SW_COMPONENT_TYPE": "HW_CONFIG\u0000",
"MEASUREMENT_VALUE": "b'985D87218406339DC31F91F5688DA05AF0D77E2051CE3BF2A5C3052E3C8B5231'"
diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst
index c665715..2c018c3 100644
--- a/docs/getting_started/build-options.rst
+++ b/docs/getting_started/build-options.rst
@@ -519,6 +519,20 @@
Firmware as error. It can take the value 1 (flag the use of deprecated
APIs as error) or 0. The default is 0.
+- ``ETHOSN_NPU_DRIVER``: boolean option to enable a SiP service that can
+ configure an Arm® Ethos™-N NPU. To use this service the target platform's
+ ``HW_CONFIG`` must include the device tree nodes for the NPU. Currently, only
+ the Arm Juno platform has this included in its ``HW_CONFIG`` and the platform
+ only loads the ``HW_CONFIG`` in AArch64 builds. Default is 0.
+
+- ``ETHOSN_NPU_TZMP1``: boolean option to enable TZMP1 support for the
+ Arm® Ethos™-N NPU. Requires ``ETHOSN_NPU_DRIVER`` and
+ ``TRUSTED_BOARD_BOOT`` to be enabled.
+
+- ``ETHOSN_NPU_FW``: location of the NPU firmware binary
+ (```ethosn.bin```). This firmware image will be included in the FIP and
+ loaded at runtime.
+
- ``EL3_EXCEPTION_HANDLING``: When set to ``1``, enable handling of exceptions
targeted at EL3. When set ``0`` (default), no exceptions are expected or
handled at EL3, and a panic will result. The exception to this rule is when
diff --git a/docs/getting_started/docs-build.rst b/docs/getting_started/docs-build.rst
index aa8c2bb..50fff57 100644
--- a/docs/getting_started/docs-build.rst
+++ b/docs/getting_started/docs-build.rst
@@ -74,6 +74,26 @@
poetry run make -C docs help
+To build the documentation in PDF format, additionally ensure that the following
+packages are installed:
+
+- FreeSerif font
+- latexmk
+- librsvg2-bin
+- xelatex
+- xindy
+
+Below is an example set of instructions to install the required packages
+(tested on Ubuntu):
+
+.. code:: shell
+
+ sudo apt install fonts-freefont-otf latexmk librsvg2-bin texlive-xetex xindy
+
+Once all the dependencies are installed, run the command ``poetry run make -C
+docs latexpdf`` to build the documentation. Output from the build process
+(``trustedfirmware-a.pdf``) can be found in ``docs/build/latex``.
+
Building rendered documentation from Poetry's virtual environment
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
diff --git a/docs/plat/arm/arm-build-options.rst b/docs/plat/arm/arm-build-options.rst
index 3179267..e81052b 100644
--- a/docs/plat/arm/arm-build-options.rst
+++ b/docs/plat/arm/arm-build-options.rst
@@ -95,20 +95,6 @@
platforms. If this option is specified, then the path to the CryptoCell
SBROM library must be specified via ``CCSBROM_LIB_PATH`` flag.
-- ``ARM_ETHOSN_NPU_DRIVER``: boolean option to enable a SiP service that can
- configure an Arm® Ethos™-N NPU. To use this service the target platform's
- ``HW_CONFIG`` must include the device tree nodes for the NPU. Currently, only
- the Arm Juno platform has this included in its ``HW_CONFIG`` and the platform
- only loads the ``HW_CONFIG`` in AArch64 builds. Default is 0.
-
-- ``ARM_ETHOSN_NPU_TZMP1``: boolean option to enable TZMP1 support for the
- Arm® Ethos™-N NPU. Requires ``ARM_ETHOSN_NPU_DRIVER`` and
- ``TRUSTED_BOARD_BOOT`` to be enabled.
-
-- ``ARM_ETHOSN_NPU_FW``: location of the NPU firmware binary
- (```ethosn.bin```). This firmware image will be included in the FIP and
- loaded at runtime.
-
- ``ARM_GPT_SUPPORT``: Enable GPT parser to get the entry address and length of
the various partitions present in the GPT image. This support is available
only for the BL2 component, and it is disabled by default.
diff --git a/docs/porting-guide.rst b/docs/porting-guide.rst
index f074021..5a017ce 100644
--- a/docs/porting-guide.rst
+++ b/docs/porting-guide.rst
@@ -591,32 +591,32 @@
If the platform port uses the Arm® Ethos™-N NPU driver with TZMP1 support
enabled, the following constants and configuration must also be defined:
-- **ARM_ETHOSN_NPU_PROT_FW_NSAID**
+- **ETHOSN_NPU_PROT_FW_NSAID**
Defines the Non-secure Access IDentity (NSAID) that the NPU shall use to
access the protected memory that contains the NPU's firmware.
-- **ARM_ETHOSN_NPU_PROT_DATA_RW_NSAID**
+- **ETHOSN_NPU_PROT_DATA_RW_NSAID**
Defines the Non-secure Access IDentity (NSAID) that the NPU shall use for
read/write access to the protected memory that contains inference data.
-- **ARM_ETHOSN_NPU_PROT_DATA_RO_NSAID**
+- **ETHOSN_NPU_PROT_DATA_RO_NSAID**
Defines the Non-secure Access IDentity (NSAID) that the NPU shall use for
read-only access to the protected memory that contains inference data.
-- **ARM_ETHOSN_NPU_NS_RW_DATA_NSAID**
+- **ETHOSN_NPU_NS_RW_DATA_NSAID**
Defines the Non-secure Access IDentity (NSAID) that the NPU shall use for
read/write access to the non-protected memory.
-- **ARM_ETHOSN_NPU_NS_RO_DATA_NSAID**
+- **ETHOSN_NPU_NS_RO_DATA_NSAID**
Defines the Non-secure Access IDentity (NSAID) that the NPU shall use for
read-only access to the non-protected memory.
-- **ARM_ETHOSN_NPU_FW_IMAGE_BASE** and **ARM_ETHOSN_NPU_FW_IMAGE_LIMIT**
+- **ETHOSN_NPU_FW_IMAGE_BASE** and **ETHOSN_NPU_FW_IMAGE_LIMIT**
Defines the physical address range that the NPU's firmware will be loaded
into and executed from.
@@ -634,10 +634,10 @@
- Add MMU mappings such that:
- BL2 can write the NPU firmware into the region defined by
- ``ARM_ETHOSN_NPU_FW_IMAGE_BASE`` and ``ARM_ETHOSN_NPU_FW_IMAGE_LIMIT``
+ ``ETHOSN_NPU_FW_IMAGE_BASE`` and ``ETHOSN_NPU_FW_IMAGE_LIMIT``
- BL31 (SiP service) can read the NPU firmware from the same region
-- Add the firmware image ID ``ARM_ETHOSN_NPU_FW_IMAGE_ID`` to the list of images
+- Add the firmware image ID ``ETHOSN_NPU_FW_IMAGE_ID`` to the list of images
loaded by BL2.
Please see the reference implementation code for the Juno platform as an example.
diff --git a/drivers/arm/ethosn/ethosn_npu.mk b/drivers/arm/ethosn/ethosn_npu.mk
new file mode 100644
index 0000000..4a31b59
--- /dev/null
+++ b/drivers/arm/ethosn/ethosn_npu.mk
@@ -0,0 +1,49 @@
+#
+# Copyright (c) 2023, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# Arm(R) Ethos(TM)-N NPU SiP service
+ETHOSN_NPU_DRIVER := 0
+
+$(eval $(call assert_boolean,ETHOSN_NPU_DRIVER))
+$(eval $(call add_define,ETHOSN_NPU_DRIVER))
+
+#Ethos-N NPU TZMP1
+ETHOSN_NPU_TZMP1 := 0
+$(eval $(call assert_boolean,ETHOSN_NPU_TZMP1))
+$(eval $(call add_define,ETHOSN_NPU_TZMP1))
+ifeq (${ETHOSN_NPU_TZMP1},1)
+ ifeq (${ETHOSN_NPU_DRIVER},0)
+ $(error "ETHOSN_NPU_TZMP1 is only available if ETHOSN_NPU_DRIVER=1)
+ endif
+ ifeq (${PLAT},juno)
+ $(eval $(call add_define,JUNO_ETHOSN_TZMP1))
+ else
+ $(error "ETHOSN_NPU_TZMP1 only supported on Juno platform, not ", ${PLAT})
+ endif
+
+ ifeq (${TRUSTED_BOARD_BOOT},0)
+ # We rely on TRUSTED_BOARD_BOOT to prevent the firmware code from being
+ # tampered with, which is required to protect the confidentiality of protected
+ # inference data.
+ $(error "ETHOSN_NPU_TZMP1 is only available if TRUSTED_BOARD_BOOT is enabled)
+ endif
+
+ # We need the FW certificate and key certificate
+ $(eval $(call TOOL_ADD_PAYLOAD,${BUILD_PLAT}/npu_fw_key.crt,--npu-fw-key-cert))
+ $(eval $(call TOOL_ADD_PAYLOAD,${BUILD_PLAT}/npu_fw_content.crt,--npu-fw-cert))
+ # We need the firmware to be built into the FIP
+ $(eval $(call TOOL_ADD_IMG,ETHOSN_NPU_FW,--npu-fw))
+
+ # Needed for our OIDs to be available in tbbr_cot_bl2.c
+ $(eval $(call add_define, PLAT_DEF_OID))
+
+ # Needed so that UUIDs from the FIP are available in BL2
+ $(eval $(call add_define,PLAT_DEF_FIP_UUID))
+
+ PLAT_INCLUDES += -I${PLAT_DIR}certificate/include
+ PLAT_INCLUDES += -Iinclude/drivers/arm/
+ PLAT_INCLUDES += -I${PLAT_DIR}fip
+endif
diff --git a/drivers/arm/ethosn/ethosn_smc.c b/drivers/arm/ethosn/ethosn_smc.c
index 85a12c5..42158e4 100644
--- a/drivers/arm/ethosn/ethosn_smc.c
+++ b/drivers/arm/ethosn/ethosn_smc.c
@@ -17,9 +17,9 @@
#include <platform_def.h>
-#if ARM_ETHOSN_NPU_TZMP1
+#if ETHOSN_NPU_TZMP1
#include "ethosn_big_fw.h"
-#endif
+#endif /* ETHOSN_NPU_TZMP1 */
/*
* Number of Arm(R) Ethos(TM)-N NPU (NPU) devices available
@@ -51,11 +51,11 @@
#define SEC_AUXCTLR_STASHING_VAL U(0xA5000000)
#define SEC_DEL_REG U(0x0004)
-#if ARM_ETHOSN_NPU_TZMP1
+#if ETHOSN_NPU_TZMP1
#define SEC_DEL_VAL U(0x808)
#else
#define SEC_DEL_VAL U(0x80C)
-#endif
+#endif /* ETHOSN_NPU_TZMP1 */
#define SEC_DEL_EXCC_MASK U(0x20)
#define SEC_SECCTLR_REG U(0x0010)
@@ -69,7 +69,7 @@
#define SEC_SYSCTRL0_CPU_WAIT U(1)
#define SEC_SYSCTRL0_SLEEPING U(1U << 4)
#define SEC_SYSCTRL0_INITVTOR_MASK U(0x1FFFFF80)
-#define SEC_SYSCTRL0_SOFT_RESET U(3U << 29)
+#define SEC_SYSCTRL0_SOFT_RESET U(1U << 29)
#define SEC_SYSCTRL0_HARD_RESET U(1U << 31)
#define SEC_SYSCTRL1_REG U(0x001C)
@@ -104,8 +104,8 @@
#define TO_EXTEND_ADDR(addr) \
((addr >> SEC_ADDR_EXT_SHIFT) & SEC_ADDR_EXT_MASK)
-#if ARM_ETHOSN_NPU_TZMP1
-CASSERT(ARM_ETHOSN_NPU_FW_IMAGE_BASE > 0U, assert_ethosn_invalid_fw_image_base);
+#if ETHOSN_NPU_TZMP1
+CASSERT(ETHOSN_NPU_FW_IMAGE_BASE > 0U, assert_ethosn_invalid_fw_image_base);
static const struct ethosn_big_fw *big_fw;
#define FW_INITVTOR_ADDR(big_fw) \
@@ -115,7 +115,7 @@
#define SYSCTRL0_INITVTOR_ADDR(value) \
(value & SEC_SYSCTRL0_INITVTOR_MASK)
-#endif
+#endif /* ETHOSN_NPU_TZMP1 */
static bool ethosn_get_device_and_core(uintptr_t core_addr,
const struct ethosn_device_t **dev_match,
@@ -142,7 +142,7 @@
return false;
}
-#if ARM_ETHOSN_NPU_TZMP1
+#if ETHOSN_NPU_TZMP1
static uint32_t ethosn_core_read_arch_version(uintptr_t core_addr)
{
uint32_t npu_id = mmio_read_32(ETHOSN_CORE_SEC_REG(core_addr,
@@ -155,23 +155,23 @@
bool is_protected)
{
size_t i;
- uint32_t streams[9] = {[0 ... 8] = ARM_ETHOSN_NPU_NS_RO_DATA_NSAID};
+ uint32_t streams[9] = {[0 ... 8] = ETHOSN_NPU_NS_RO_DATA_NSAID};
- streams[FIRMWARE_STREAM_INDEX] = ARM_ETHOSN_NPU_PROT_FW_NSAID;
- streams[PLE_STREAM_INDEX] = ARM_ETHOSN_NPU_PROT_FW_NSAID;
+ streams[FIRMWARE_STREAM_INDEX] = ETHOSN_NPU_PROT_FW_NSAID;
+ streams[PLE_STREAM_INDEX] = ETHOSN_NPU_PROT_FW_NSAID;
- streams[WORKING_STREAM_INDEX] = ARM_ETHOSN_NPU_NS_RW_DATA_NSAID;
+ streams[WORKING_STREAM_INDEX] = ETHOSN_NPU_NS_RW_DATA_NSAID;
if (is_protected) {
- streams[INPUT_STREAM_INDEX] = ARM_ETHOSN_NPU_PROT_RO_DATA_NSAID;
+ streams[INPUT_STREAM_INDEX] = ETHOSN_NPU_PROT_RO_DATA_NSAID;
streams[INTERMEDIATE_STREAM_INDEX] =
- ARM_ETHOSN_NPU_PROT_RW_DATA_NSAID;
- streams[OUTPUT_STREAM_INDEX] = ARM_ETHOSN_NPU_PROT_RW_DATA_NSAID;
+ ETHOSN_NPU_PROT_RW_DATA_NSAID;
+ streams[OUTPUT_STREAM_INDEX] = ETHOSN_NPU_PROT_RW_DATA_NSAID;
} else {
- streams[INPUT_STREAM_INDEX] = ARM_ETHOSN_NPU_NS_RO_DATA_NSAID;
+ streams[INPUT_STREAM_INDEX] = ETHOSN_NPU_NS_RO_DATA_NSAID;
streams[INTERMEDIATE_STREAM_INDEX] =
- ARM_ETHOSN_NPU_NS_RW_DATA_NSAID;
- streams[OUTPUT_STREAM_INDEX] = ARM_ETHOSN_NPU_NS_RW_DATA_NSAID;
+ ETHOSN_NPU_NS_RW_DATA_NSAID;
+ streams[OUTPUT_STREAM_INDEX] = ETHOSN_NPU_NS_RW_DATA_NSAID;
}
for (i = 0U; i < ARRAY_SIZE(streams); ++i) {
@@ -188,7 +188,7 @@
FW_INITVTOR_ADDR(big_fw));
}
-#endif
+#endif /* ETHOSN_NPU_TZMP1 */
static void ethosn_configure_events(uintptr_t core_addr)
{
@@ -343,7 +343,7 @@
static int ethosn_core_boot_fw(uintptr_t core_addr)
{
-#if ARM_ETHOSN_NPU_TZMP1
+#if ETHOSN_NPU_TZMP1
const uintptr_t sysctrl0_reg = ETHOSN_CORE_SEC_REG(core_addr, SEC_SYSCTRL0_REG);
const uint32_t sysctrl0_val = mmio_read_32(sysctrl0_reg);
const bool waiting = (sysctrl0_val & SEC_SYSCTRL0_CPU_WAIT);
@@ -363,7 +363,7 @@
return ETHOSN_SUCCESS;
#else
return ETHOSN_NOT_SUPPORTED;
-#endif
+#endif /* ETHOSN_NPU_TZMP1 */
}
static int ethosn_core_full_reset(const struct ethosn_device_t *device,
@@ -392,17 +392,17 @@
if (!device->has_reserved_memory) {
ethosn_configure_smmu_streams(device, core, asset_alloc_idx);
-#if ARM_ETHOSN_NPU_TZMP1
+#if ETHOSN_NPU_TZMP1
ethosn_configure_stream_nsaid(core, is_protected);
-#endif
+#endif /* ETHOSN_NPU_TZMP1 */
}
ethosn_configure_stream_addr_extends(device, core->addr);
ethosn_configure_stream_attr_ctlr(core->addr);
-#if ARM_ETHOSN_NPU_TZMP1
+#if ETHOSN_NPU_TZMP1
ethosn_configure_vector_table(core->addr);
-#endif
+#endif /* ETHOSN_NPU_TZMP1 */
ethosn_delegate_to_ns(core->addr);
@@ -481,7 +481,7 @@
static uintptr_t ethosn_smc_fw_prop_handler(u_register_t fw_property,
void *handle)
{
-#if ARM_ETHOSN_NPU_TZMP1
+#if ETHOSN_NPU_TZMP1
switch (fw_property) {
case ETHOSN_FW_PROP_VERSION:
SMC_RET4(handle, ETHOSN_SUCCESS,
@@ -507,7 +507,7 @@
}
#else
SMC_RET1(handle, ETHOSN_NOT_SUPPORTED);
-#endif
+#endif /* ETHOSN_NPU_TZMP1 */
}
uintptr_t ethosn_smc_handler(uint32_t smc_fid,
@@ -554,17 +554,17 @@
int ethosn_smc_setup(void)
{
-#if ARM_ETHOSN_NPU_TZMP1
+#if ETHOSN_NPU_TZMP1
struct ethosn_device_t *dev;
uint32_t arch_ver;
-#endif
+#endif /* ETHOSN_NPU_TZMP1 */
if (ETHOSN_NUM_DEVICES == 0U) {
ERROR("ETHOSN: No NPU found\n");
return ETHOSN_FAILURE;
}
-#if ARM_ETHOSN_NPU_TZMP1
+#if ETHOSN_NPU_TZMP1
/* Only one NPU core is supported in the TZMP1 setup */
if ((ETHOSN_NUM_DEVICES != 1U) ||
@@ -580,7 +580,7 @@
}
arch_ver = ethosn_core_read_arch_version(dev->cores[0U].addr);
- big_fw = (struct ethosn_big_fw *)ARM_ETHOSN_NPU_FW_IMAGE_BASE;
+ big_fw = (struct ethosn_big_fw *)ETHOSN_NPU_FW_IMAGE_BASE;
if (!ethosn_big_fw_verify_header(big_fw, arch_ver)) {
return ETHOSN_FAILURE;
@@ -591,7 +591,7 @@
big_fw->fw_ver_patch);
#else
NOTICE("ETHOSN: Setup succeeded\n");
-#endif
+#endif /* ETHOSN_NPU_TZMP1 */
return 0;
}
diff --git a/drivers/arm/fvp/fvp_pwrc.c b/drivers/arm/fvp/fvp_pwrc.c
index 75a2b66..fb77f77 100644
--- a/drivers/arm/fvp/fvp_pwrc.c
+++ b/drivers/arm/fvp/fvp_pwrc.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -10,22 +10,39 @@
#include <plat/arm/common/plat_arm.h>
#include <platform_def.h>
+#define FVP_PWRC_ID_MASK U(0x00FFFFFF)
+
/*
* TODO: Someday there will be a generic power controller api. At the moment
* each platform has its own pwrc so just exporting functions is fine.
*/
ARM_INSTANTIATE_LOCK;
+/*
+ * Core ID field is 24 bits wide and extracted from MPIDR.
+ * Bits[23:16] represent Affinity Level 2
+ * Bits[15:8] represent Affinity Level 1
+ * Bits[7:0] represent Affinity Level 0
+ */
+static unsigned int fvp_pwrc_core_id(u_register_t mpidr)
+{
+ return (unsigned int)(mpidr & FVP_PWRC_ID_MASK);
+}
+
unsigned int fvp_pwrc_get_cpu_wkr(u_register_t mpidr)
{
- return PSYSR_WK(fvp_pwrc_read_psysr(mpidr));
+ unsigned int id = fvp_pwrc_core_id(mpidr);
+
+ return PSYSR_WK(fvp_pwrc_read_psysr(id));
}
unsigned int fvp_pwrc_read_psysr(u_register_t mpidr)
{
unsigned int rc;
+ unsigned int id = fvp_pwrc_core_id(mpidr);
+
arm_lock_get();
- mmio_write_32(PWRC_BASE + PSYSR_OFF, (unsigned int) mpidr);
+ mmio_write_32(PWRC_BASE + PSYSR_OFF, id);
rc = mmio_read_32(PWRC_BASE + PSYSR_OFF);
arm_lock_release();
return rc;
@@ -33,38 +50,47 @@
void fvp_pwrc_write_pponr(u_register_t mpidr)
{
+ unsigned int id = fvp_pwrc_core_id(mpidr);
+
arm_lock_get();
- mmio_write_32(PWRC_BASE + PPONR_OFF, (unsigned int) mpidr);
+ mmio_write_32(PWRC_BASE + PPONR_OFF, id);
arm_lock_release();
}
void fvp_pwrc_write_ppoffr(u_register_t mpidr)
{
+ unsigned int id = fvp_pwrc_core_id(mpidr);
+
arm_lock_get();
- mmio_write_32(PWRC_BASE + PPOFFR_OFF, (unsigned int) mpidr);
+ mmio_write_32(PWRC_BASE + PPOFFR_OFF, id);
arm_lock_release();
}
void fvp_pwrc_set_wen(u_register_t mpidr)
{
+ unsigned int id = fvp_pwrc_core_id(mpidr);
+
arm_lock_get();
mmio_write_32(PWRC_BASE + PWKUPR_OFF,
- (unsigned int) (PWKUPR_WEN | mpidr));
+ (unsigned int) (PWKUPR_WEN | id));
arm_lock_release();
}
void fvp_pwrc_clr_wen(u_register_t mpidr)
{
+ unsigned int id = fvp_pwrc_core_id(mpidr);
+
arm_lock_get();
- mmio_write_32(PWRC_BASE + PWKUPR_OFF,
- (unsigned int) mpidr);
+ mmio_write_32(PWRC_BASE + PWKUPR_OFF, id);
arm_lock_release();
}
void fvp_pwrc_write_pcoffr(u_register_t mpidr)
{
+ unsigned int id = fvp_pwrc_core_id(mpidr);
+
arm_lock_get();
- mmio_write_32(PWRC_BASE + PCOFFR_OFF, (unsigned int) mpidr);
+ mmio_write_32(PWRC_BASE + PCOFFR_OFF, id);
arm_lock_release();
}
diff --git a/drivers/auth/auth_mod.c b/drivers/auth/auth_mod.c
index 7a9cca8..105dc05 100644
--- a/drivers/auth/auth_mod.c
+++ b/drivers/auth/auth_mod.c
@@ -20,6 +20,8 @@
#include <lib/fconf/fconf_tbbr_getter.h>
#include <plat/common/platform.h>
+#include <tools_share/zero_oid.h>
+
/* ASN.1 tags */
#define ASN1_INTEGER 0x02
@@ -148,7 +150,7 @@
const auth_img_desc_t *img_desc,
void *img, unsigned int img_len)
{
- void *data_ptr, *pk_ptr, *pk_plat_ptr, *sig_ptr, *sig_alg_ptr;
+ void *data_ptr, *pk_ptr, *pk_plat_ptr, *sig_ptr, *sig_alg_ptr, *pk_oid;
unsigned int data_len, pk_len, pk_plat_len, sig_len, sig_alg_len;
unsigned int flags = 0;
int rc = 0;
@@ -226,6 +228,25 @@
return -1;
}
}
+
+ /*
+ * Set Zero-OID for ROTPK(subject key) as a the certificate
+ * does not hold Key-OID information for ROTPK.
+ */
+ if (param->pk->cookie != NULL) {
+ pk_oid = param->pk->cookie;
+ } else {
+ pk_oid = ZERO_OID;
+ }
+
+ /*
+ * Public key is verified at this stage, notify platform
+ * to measure and publish it.
+ */
+ rc = plat_mboot_measure_key(pk_oid, pk_ptr, pk_len);
+ if (rc != 0) {
+ WARN("Public Key measurement failure = %d\n", rc);
+ }
}
/* Ask the crypto module to verify the signature */
@@ -381,6 +402,7 @@
unsigned int img_len)
{
const auth_img_desc_t *img_desc = NULL;
+ const auth_param_type_desc_t *type_desc = NULL;
const auth_method_desc_t *auth_method = NULL;
void *param_ptr;
unsigned int param_len;
@@ -462,6 +484,21 @@
/* Copy the parameter for later use */
memcpy((void *)img_desc->authenticated_data[i].data.ptr,
(void *)param_ptr, param_len);
+
+ /*
+ * If this is a public key then measure and publicise
+ * it.
+ */
+ type_desc = img_desc->authenticated_data[i].type_desc;
+ if (type_desc->type == AUTH_PARAM_PUB_KEY) {
+ rc = plat_mboot_measure_key(type_desc->cookie,
+ param_ptr,
+ param_len);
+ if (rc != 0) {
+ WARN("Public Key measurement "
+ "failure = %d\n", rc);
+ }
+ }
}
}
diff --git a/drivers/measured_boot/rss/rss_measured_boot.c b/drivers/measured_boot/rss/rss_measured_boot.c
index 1b2f177..258aa8d 100644
--- a/drivers/measured_boot/rss/rss_measured_boot.c
+++ b/drivers/measured_boot/rss/rss_measured_boot.c
@@ -32,6 +32,19 @@
# error Invalid Measured Boot algorithm.
#endif /* MBOOT_ALG_ID */
+#if ENABLE_ASSERTIONS
+static bool null_arr(const uint8_t *signer_id, size_t signer_id_size)
+{
+ for (size_t i = 0U; i < signer_id_size; i++) {
+ if (signer_id[i] != 0U) {
+ return false;
+ }
+ }
+
+ return true;
+}
+#endif /* ENABLE_ASSERTIONS */
+
/* Functions' declarations */
void rss_measured_boot_init(struct rss_mboot_metadata *metadata_ptr)
{
@@ -39,6 +52,7 @@
/* Init the non-const members of the metadata structure */
while (metadata_ptr->id != RSS_MBOOT_INVALID_ID) {
+ assert(null_arr(metadata_ptr->signer_id, MBOOT_DIGEST_SIZE));
metadata_ptr->sw_type_size =
strlen((const char *)&metadata_ptr->sw_type) + 1;
metadata_ptr++;
@@ -93,36 +107,53 @@
}
int rss_mboot_set_signer_id(struct rss_mboot_metadata *metadata_ptr,
- unsigned int img_id,
+ const void *pk_oid,
const void *pk_ptr,
size_t pk_len)
{
unsigned char hash_data[CRYPTO_MD_MAX_SIZE];
int rc;
+ bool hash_calc_done = false;
assert(metadata_ptr != NULL);
- /* Get the metadata associated with this image. */
- while ((metadata_ptr->id != RSS_MBOOT_INVALID_ID) &&
- (metadata_ptr->id != img_id)) {
- metadata_ptr++;
- }
+ /*
+ * Do an exhaustive search over the platform metadata to find
+ * all images whose key OID matches the one passed in argument.
+ *
+ * Note that it is not an error if do not get any matches.
+ * The platform may decide not to measure all of the images
+ * in the system.
+ */
+ while (metadata_ptr->id != RSS_MBOOT_INVALID_ID) {
+ /* Get the metadata associated with this key-oid */
+ if (metadata_ptr->pk_oid == pk_oid) {
+ if (!hash_calc_done) {
+ /* Calculate public key hash */
+ rc = crypto_mod_calc_hash(CRYPTO_MD_ID,
+ (void *)pk_ptr,
+ pk_len, hash_data);
+ if (rc != 0) {
+ return rc;
+ }
- /* If image is not present in metadata array then skip */
- if (metadata_ptr->id == RSS_MBOOT_INVALID_ID) {
- return 0;
- }
+ hash_calc_done = true;
+ }
- /* Calculate public key hash */
- rc = crypto_mod_calc_hash(CRYPTO_MD_ID, (void *)pk_ptr,
- pk_len, hash_data);
- if (rc != 0) {
- return rc;
- }
+ /*
+ * Fill the signer-ID field with the newly/already
+ * computed hash of the public key and update its
+ * signer ID size field with compile-time decided
+ * digest size.
+ */
+ (void)memcpy(metadata_ptr->signer_id,
+ hash_data,
+ MBOOT_DIGEST_SIZE);
+ metadata_ptr->signer_id_size = MBOOT_DIGEST_SIZE;
+ }
- /* Update metadata struct with the received signer_id */
- (void)memcpy(metadata_ptr->signer_id, hash_data, MBOOT_DIGEST_SIZE);
- metadata_ptr->signer_id_size = MBOOT_DIGEST_SIZE;
+ metadata_ptr++;
+ }
return 0;
}
diff --git a/fdts/juno.dts b/fdts/juno.dts
index 56fe167..8e373e7 100644
--- a/fdts/juno.dts
+++ b/fdts/juno.dts
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -10,6 +10,6 @@
};
-#if ARM_ETHOSN_NPU_DRIVER
+#if ETHOSN_NPU_DRIVER
#include "juno-ethosn.dtsi"
#endif
diff --git a/include/drivers/measured_boot/rss/rss_measured_boot.h b/include/drivers/measured_boot/rss/rss_measured_boot.h
index 76affd8..7ab517c 100644
--- a/include/drivers/measured_boot/rss/rss_measured_boot.h
+++ b/include/drivers/measured_boot/rss/rss_measured_boot.h
@@ -40,6 +40,7 @@
size_t version_size;
uint8_t sw_type[SW_TYPE_MAX_SIZE];
size_t sw_type_size;
+ void *pk_oid;
bool lock_measurement;
};
@@ -49,9 +50,8 @@
uintptr_t data_base, uint32_t data_size,
uint32_t data_id);
-/* TODO: These metadata are currently not available during TF-A boot */
int rss_mboot_set_signer_id(struct rss_mboot_metadata *metadata_ptr,
- unsigned int img_id, const void *pk_ptr,
+ const void *pk_oid, const void *pk_ptr,
size_t pk_len);
#endif /* RSS_MEASURED_BOOT_H */
diff --git a/include/export/lib/bl_aux_params/bl_aux_params_exp.h b/include/export/lib/bl_aux_params/bl_aux_params_exp.h
index 7391dec..5ae1d64 100644
--- a/include/export/lib/bl_aux_params/bl_aux_params_exp.h
+++ b/include/export/lib/bl_aux_params/bl_aux_params_exp.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/export/lib/utils_def_exp.h b/include/export/lib/utils_def_exp.h
index 2ee5769..8c58cbb 100644
--- a/include/export/lib/utils_def_exp.h
+++ b/include/export/lib/utils_def_exp.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/bakery_lock.h b/include/lib/bakery_lock.h
index 2cf2b44..5d165c9 100644
--- a/include/lib/bakery_lock.h
+++ b/include/lib/bakery_lock.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2018, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/bl_aux_params/bl_aux_params.h b/include/lib/bl_aux_params/bl_aux_params.h
index 072a29d..c2da96c 100644
--- a/include/lib/bl_aux_params/bl_aux_params.h
+++ b/include/lib/bl_aux_params/bl_aux_params.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/cassert.h b/include/lib/cassert.h
index bbfdfdb..512a2ad 100644
--- a/include/lib/cassert.h
+++ b/include/lib/cassert.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2018, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/coreboot.h b/include/lib/coreboot.h
index 42d4149..c8e1b2d 100644
--- a/include/lib/coreboot.h
+++ b/include/lib/coreboot.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2020, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/cpus/aarch32/aem_generic.h b/include/lib/cpus/aarch32/aem_generic.h
index 1d40cec..f631f26 100644
--- a/include/lib/cpus/aarch32/aem_generic.h
+++ b/include/lib/cpus/aarch32/aem_generic.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/cpus/aarch32/cortex_a12.h b/include/lib/cpus/aarch32/cortex_a12.h
index abacdba..789b4cf 100644
--- a/include/lib/cpus/aarch32/cortex_a12.h
+++ b/include/lib/cpus/aarch32/cortex_a12.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/cpus/aarch32/cortex_a15.h b/include/lib/cpus/aarch32/cortex_a15.h
index 9526a9c..aca4d34 100644
--- a/include/lib/cpus/aarch32/cortex_a15.h
+++ b/include/lib/cpus/aarch32/cortex_a15.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/cpus/aarch32/cortex_a17.h b/include/lib/cpus/aarch32/cortex_a17.h
index 89a8eb6..b9e754a 100644
--- a/include/lib/cpus/aarch32/cortex_a17.h
+++ b/include/lib/cpus/aarch32/cortex_a17.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/cpus/aarch32/cortex_a32.h b/include/lib/cpus/aarch32/cortex_a32.h
index 6ddd533..841898a 100644
--- a/include/lib/cpus/aarch32/cortex_a32.h
+++ b/include/lib/cpus/aarch32/cortex_a32.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/cpus/aarch32/cortex_a5.h b/include/lib/cpus/aarch32/cortex_a5.h
index 76703b7..c0763f9 100644
--- a/include/lib/cpus/aarch32/cortex_a5.h
+++ b/include/lib/cpus/aarch32/cortex_a5.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/cpus/aarch32/cortex_a53.h b/include/lib/cpus/aarch32/cortex_a53.h
index 8dd0192..b9bb310 100644
--- a/include/lib/cpus/aarch32/cortex_a53.h
+++ b/include/lib/cpus/aarch32/cortex_a53.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/cpus/aarch32/cortex_a57.h b/include/lib/cpus/aarch32/cortex_a57.h
index ffabd61..bb977ff 100644
--- a/include/lib/cpus/aarch32/cortex_a57.h
+++ b/include/lib/cpus/aarch32/cortex_a57.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/cpus/aarch32/cortex_a7.h b/include/lib/cpus/aarch32/cortex_a7.h
index 730fdb5..16fbfaa 100644
--- a/include/lib/cpus/aarch32/cortex_a7.h
+++ b/include/lib/cpus/aarch32/cortex_a7.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/cpus/aarch32/cortex_a72.h b/include/lib/cpus/aarch32/cortex_a72.h
index 954f736..0a3a23a 100644
--- a/include/lib/cpus/aarch32/cortex_a72.h
+++ b/include/lib/cpus/aarch32/cortex_a72.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/cpus/aarch32/cortex_a9.h b/include/lib/cpus/aarch32/cortex_a9.h
index a8c978a..337bad9 100644
--- a/include/lib/cpus/aarch32/cortex_a9.h
+++ b/include/lib/cpus/aarch32/cortex_a9.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/cpus/aarch64/aem_generic.h b/include/lib/cpus/aarch64/aem_generic.h
index 6bb30a2..acb6adb 100644
--- a/include/lib/cpus/aarch64/aem_generic.h
+++ b/include/lib/cpus/aarch64/aem_generic.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/cpus/aarch64/cortex_a35.h b/include/lib/cpus/aarch64/cortex_a35.h
index 5421478..cef2960 100644
--- a/include/lib/cpus/aarch64/cortex_a35.h
+++ b/include/lib/cpus/aarch64/cortex_a35.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/cpus/aarch64/cortex_a53.h b/include/lib/cpus/aarch64/cortex_a53.h
index 54e646c..18796ee 100644
--- a/include/lib/cpus/aarch64/cortex_a53.h
+++ b/include/lib/cpus/aarch64/cortex_a53.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/cpus/aarch64/cortex_a55.h b/include/lib/cpus/aarch64/cortex_a55.h
index 60ed957..0a1593a 100644
--- a/include/lib/cpus/aarch64/cortex_a55.h
+++ b/include/lib/cpus/aarch64/cortex_a55.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/cpus/aarch64/cortex_a57.h b/include/lib/cpus/aarch64/cortex_a57.h
index dc40e31..19ac513 100644
--- a/include/lib/cpus/aarch64/cortex_a57.h
+++ b/include/lib/cpus/aarch64/cortex_a57.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2019, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
diff --git a/include/lib/cpus/aarch64/cortex_a72.h b/include/lib/cpus/aarch64/cortex_a72.h
index bef9337..a00f6d6 100644
--- a/include/lib/cpus/aarch64/cortex_a72.h
+++ b/include/lib/cpus/aarch64/cortex_a72.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/cpus/aarch64/cortex_a73.h b/include/lib/cpus/aarch64/cortex_a73.h
index 271a333..ede76d1 100644
--- a/include/lib/cpus/aarch64/cortex_a73.h
+++ b/include/lib/cpus/aarch64/cortex_a73.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/cpus/aarch64/cortex_a75.h b/include/lib/cpus/aarch64/cortex_a75.h
index e5ca1ba..ca79991 100644
--- a/include/lib/cpus/aarch64/cortex_a75.h
+++ b/include/lib/cpus/aarch64/cortex_a75.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/cpus/aarch64/cortex_a76.h b/include/lib/cpus/aarch64/cortex_a76.h
index 74fb6e9..b2ec8aa 100644
--- a/include/lib/cpus/aarch64/cortex_a76.h
+++ b/include/lib/cpus/aarch64/cortex_a76.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -36,6 +36,7 @@
#define CORTEX_A76_CPUACTLR2_EL1 S3_0_C15_C1_1
#define CORTEX_A76_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2)
+#define CORTEX_A76_CPUACTLR2_EL1_BIT_59 (ULL(1) << 59)
#define CORTEX_A76_CPUACTLR2_EL1_DISABLE_LOAD_PASS_STORE (ULL(1) << 16)
diff --git a/include/lib/cpus/aarch64/cortex_a77.h b/include/lib/cpus/aarch64/cortex_a77.h
index a9b4546..39717a3 100644
--- a/include/lib/cpus/aarch64/cortex_a77.h
+++ b/include/lib/cpus/aarch64/cortex_a77.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/cpus/aarch64/cortex_a78.h b/include/lib/cpus/aarch64/cortex_a78.h
index 66f565d..2984f82 100644
--- a/include/lib/cpus/aarch64/cortex_a78.h
+++ b/include/lib/cpus/aarch64/cortex_a78.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2023, ARM Limited. All rights reserved.
+ * Copyright (c) 2019-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/cpus/aarch64/cortex_a78_ae.h b/include/lib/cpus/aarch64/cortex_a78_ae.h
index b68ec1e..4ada845 100644
--- a/include/lib/cpus/aarch64/cortex_a78_ae.h
+++ b/include/lib/cpus/aarch64/cortex_a78_ae.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2022, ARM Limited. All rights reserved.
+ * Copyright (c) 2019-2022, Arm Limited. All rights reserved.
* Copyright (c) 2021-2022, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
diff --git a/include/lib/cpus/aarch64/cpu_macros.S b/include/lib/cpus/aarch64/cpu_macros.S
index d945d7c..6faef5d 100644
--- a/include/lib/cpus/aarch64/cpu_macros.S
+++ b/include/lib/cpus/aarch64/cpu_macros.S
@@ -472,15 +472,25 @@
* _chosen:
* Compile time flag on whether the erratum is included
*
- * clobbers: x0-x9 (PCS compliant)
+ * _get_rev:
+ * Optional parameter that determines whether to insert a call to the CPU revision fetching
+ * procedure. Stores the result of this in the temporary register x10.
+ *
+ * clobbers: x0-x10 (PCS compliant)
*/
-.macro apply_erratum _cpu:req, _cve:req, _id:req, _chosen:req
- .if \_chosen
+.macro apply_erratum _cpu:req, _cve:req, _id:req, _chosen:req, _get_rev=GET_CPU_REV
+ .if (\_chosen & \_get_rev)
mov x9, x30
bl cpu_get_rev_var
+ mov x10, x0
+ .elseif (\_chosen)
+ mov x9, x30
+ mov x0, x10
+ .endif
+
+ .if \_chosen
bl erratum_\_cpu\()_\_id\()_wa
mov x30, x9
-
.endif
.endm
diff --git a/include/lib/cpus/aarch64/cpuamu.h b/include/lib/cpus/aarch64/cpuamu.h
index 463f890..cb004bf 100644
--- a/include/lib/cpus/aarch64/cpuamu.h
+++ b/include/lib/cpus/aarch64/cpuamu.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/cpus/aarch64/denver.h b/include/lib/cpus/aarch64/denver.h
index 24b6a87..84ab6bb 100644
--- a/include/lib/cpus/aarch64/denver.h
+++ b/include/lib/cpus/aarch64/denver.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2018, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/cpus/aarch64/neoverse_e1.h b/include/lib/cpus/aarch64/neoverse_e1.h
index 96b4661..6e784f6 100644
--- a/include/lib/cpus/aarch64/neoverse_e1.h
+++ b/include/lib/cpus/aarch64/neoverse_e1.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/cpus/aarch64/neoverse_n1.h b/include/lib/cpus/aarch64/neoverse_n1.h
index b6b8d8d..0ba5ad1 100644
--- a/include/lib/cpus/aarch64/neoverse_n1.h
+++ b/include/lib/cpus/aarch64/neoverse_n1.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2022, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/cpus/aarch64/neoverse_n2.h b/include/lib/cpus/aarch64/neoverse_n2.h
index cb1be5b..0d50854 100644
--- a/include/lib/cpus/aarch64/neoverse_n2.h
+++ b/include/lib/cpus/aarch64/neoverse_n2.h
@@ -43,9 +43,17 @@
#define NEOVERSE_N2_CPUACTLR2_EL1_BIT_40 (ULL(1) << 40)
/*******************************************************************************
+ * CPU Auxiliary Control register 3 specific definitions.
+ ******************************************************************************/
+#define NEOVERSE_N2_CPUACTLR3_EL1 S3_0_C15_C1_2
+#define NEOVERSE_N2_CPUACTLR3_EL1_BIT_47 (ULL(1) << 47)
+
+/*******************************************************************************
* CPU Auxiliary Control register 5 specific definitions.
******************************************************************************/
#define NEOVERSE_N2_CPUACTLR5_EL1 S3_0_C15_C8_0
+#define NEOVERSE_N2_CPUACTLR5_EL1_BIT_56 (ULL(1) << 56)
+#define NEOVERSE_N2_CPUACTLR5_EL1_BIT_55 (ULL(1) << 55)
#define NEOVERSE_N2_CPUACTLR5_EL1_BIT_44 (ULL(1) << 44)
#define NEOVERSE_N2_CPUACTLR5_EL1_BIT_13 (ULL(1) << 13)
#define NEOVERSE_N2_CPUACTLR5_EL1_BIT_17 (ULL(1) << 17)
diff --git a/include/lib/cpus/aarch64/neoverse_poseidon.h b/include/lib/cpus/aarch64/neoverse_poseidon.h
index 798ecd1..202ef5c 100644
--- a/include/lib/cpus/aarch64/neoverse_poseidon.h
+++ b/include/lib/cpus/aarch64/neoverse_poseidon.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022, ARM Limited. All rights reserved.
+ * Copyright (c) 2022, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/cpus/aarch64/neoverse_v1.h b/include/lib/cpus/aarch64/neoverse_v1.h
index 3d48623..d618994 100644
--- a/include/lib/cpus/aarch64/neoverse_v1.h
+++ b/include/lib/cpus/aarch64/neoverse_v1.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2023, ARM Limited. All rights reserved.
+ * Copyright (c) 2019-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -42,7 +42,10 @@
#define NEOVERSE_V1_ACTLR2_EL1_BIT_40 (ULL(1) << 40)
#define NEOVERSE_V1_ACTLR3_EL1 S3_0_C15_C1_2
+#define NEOVERSE_V1_ACTLR3_EL1_BIT_47 (ULL(1) << 47)
#define NEOVERSE_V1_ACTLR5_EL1 S3_0_C15_C9_0
+#define NEOVERSE_V1_ACTLR5_EL1_BIT_55 (ULL(1) << 55)
+#define NEOVERSE_V1_ACTLR5_EL1_BIT_56 (ULL(1) << 56)
#endif /* NEOVERSE_V1_H */
diff --git a/include/lib/cpus/aarch64/qemu_max.h b/include/lib/cpus/aarch64/qemu_max.h
index 14da170..58923d2 100644
--- a/include/lib/cpus/aarch64/qemu_max.h
+++ b/include/lib/cpus/aarch64/qemu_max.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2021, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/cpus/errata.h b/include/lib/cpus/errata.h
index b280435..2080898 100644
--- a/include/lib/cpus/errata.h
+++ b/include/lib/cpus/errata.h
@@ -66,6 +66,9 @@
#define NO_ASSERT 0
#define NO_APPLY_AT_RESET 0
#define APPLY_AT_RESET 1
+#define GET_CPU_REV 1
+#define NO_GET_CPU_REV 0
+
/* useful for errata that end up always being worked around */
#define ERRATUM_ALWAYS_CHOSEN 1
diff --git a/include/lib/cpus/wa_cve_2017_5715.h b/include/lib/cpus/wa_cve_2017_5715.h
index 940fc65..2ad56e1 100644
--- a/include/lib/cpus/wa_cve_2017_5715.h
+++ b/include/lib/cpus/wa_cve_2017_5715.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/cpus/wa_cve_2018_3639.h b/include/lib/cpus/wa_cve_2018_3639.h
index e37db37..5a7c9bf 100644
--- a/include/lib/cpus/wa_cve_2018_3639.h
+++ b/include/lib/cpus/wa_cve_2018_3639.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/cpus/wa_cve_2022_23960.h b/include/lib/cpus/wa_cve_2022_23960.h
index 35b3fd8..50c0f76 100644
--- a/include/lib/cpus/wa_cve_2022_23960.h
+++ b/include/lib/cpus/wa_cve_2022_23960.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2022, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/el3_runtime/aarch32/context.h b/include/lib/el3_runtime/aarch32/context.h
index df77c0f..3b698e3 100644
--- a/include/lib/el3_runtime/aarch32/context.h
+++ b/include/lib/el3_runtime/aarch32/context.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2020, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/el3_runtime/pubsub_events.h b/include/lib/el3_runtime/pubsub_events.h
index 5012082..d0c0502 100644
--- a/include/lib/el3_runtime/pubsub_events.h
+++ b/include/lib/el3_runtime/pubsub_events.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/extensions/amu.h b/include/lib/extensions/amu.h
index 80ad68c..09d8dee 100644
--- a/include/lib/extensions/amu.h
+++ b/include/lib/extensions/amu.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/extensions/pauth.h b/include/lib/extensions/pauth.h
index 2e780de..dbc2226 100644
--- a/include/lib/extensions/pauth.h
+++ b/include/lib/extensions/pauth.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/extensions/ras.h b/include/lib/extensions/ras.h
index 793ab9f..6997da0 100644
--- a/include/lib/extensions/ras.h
+++ b/include/lib/extensions/ras.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
diff --git a/include/lib/extensions/ras_arch.h b/include/lib/extensions/ras_arch.h
index 55760b0..e0aee50 100644
--- a/include/lib/extensions/ras_arch.h
+++ b/include/lib/extensions/ras_arch.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
diff --git a/include/lib/fconf/fconf.h b/include/lib/fconf/fconf.h
index 3762021..5b54c04 100644
--- a/include/lib/fconf/fconf.h
+++ b/include/lib/fconf/fconf.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2022, ARM Limited. All rights reserved.
+ * Copyright (c) 2019-2022, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/fconf/fconf_tbbr_getter.h b/include/lib/fconf/fconf_tbbr_getter.h
index db98b68..541a396 100644
--- a/include/lib/fconf/fconf_tbbr_getter.h
+++ b/include/lib/fconf/fconf_tbbr_getter.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2020, ARM Limited. All rights reserved.
+ * Copyright (c) 2019-2020, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/libc/aarch32/endian_.h b/include/lib/libc/aarch32/endian_.h
index 0cf2c75..edca496 100644
--- a/include/lib/libc/aarch32/endian_.h
+++ b/include/lib/libc/aarch32/endian_.h
@@ -32,7 +32,7 @@
* $FreeBSD$
*/
/*
- * Portions copyright (c) 2018, ARM Limited and Contributors.
+ * Portions copyright (c) 2018, Arm Limited and Contributors.
* All rights reserved.
*/
diff --git a/include/lib/libc/aarch32/inttypes_.h b/include/lib/libc/aarch32/inttypes_.h
index ef3fb8f..0888bf0 100644
--- a/include/lib/libc/aarch32/inttypes_.h
+++ b/include/lib/libc/aarch32/inttypes_.h
@@ -4,7 +4,7 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
- * Portions copyright (c) 2020, ARM Limited and Contributors.
+ * Portions copyright (c) 2020, Arm Limited and Contributors.
* All rights reserved.
*/
diff --git a/include/lib/libc/aarch32/limits_.h b/include/lib/libc/aarch32/limits_.h
index a67ec53..5b0516a 100644
--- a/include/lib/libc/aarch32/limits_.h
+++ b/include/lib/libc/aarch32/limits_.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/libc/aarch32/stddef_.h b/include/lib/libc/aarch32/stddef_.h
index 36dc20b..14ed094 100644
--- a/include/lib/libc/aarch32/stddef_.h
+++ b/include/lib/libc/aarch32/stddef_.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/libc/aarch32/stdint_.h b/include/lib/libc/aarch32/stdint_.h
index dafe142..6e2deed 100644
--- a/include/lib/libc/aarch32/stdint_.h
+++ b/include/lib/libc/aarch32/stdint_.h
@@ -4,7 +4,7 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
- * Portions copyright (c) 2020, ARM Limited and Contributors.
+ * Portions copyright (c) 2020, Arm Limited and Contributors.
* All rights reserved.
*/
diff --git a/include/lib/libc/aarch32/stdio_.h b/include/lib/libc/aarch32/stdio_.h
index 5e49425..7042664 100644
--- a/include/lib/libc/aarch32/stdio_.h
+++ b/include/lib/libc/aarch32/stdio_.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/libc/aarch64/endian_.h b/include/lib/libc/aarch64/endian_.h
index 7c79fd4..58273d7 100644
--- a/include/lib/libc/aarch64/endian_.h
+++ b/include/lib/libc/aarch64/endian_.h
@@ -32,7 +32,7 @@
* $FreeBSD$
*/
/*
- * Portions copyright (c) 2018, ARM Limited and Contributors.
+ * Portions copyright (c) 2018, Arm Limited and Contributors.
* All rights reserved.
*/
diff --git a/include/lib/libc/aarch64/inttypes_.h b/include/lib/libc/aarch64/inttypes_.h
index f25882f..6109084 100644
--- a/include/lib/libc/aarch64/inttypes_.h
+++ b/include/lib/libc/aarch64/inttypes_.h
@@ -4,7 +4,7 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
- * Portions copyright (c) 2020, ARM Limited and Contributors.
+ * Portions copyright (c) 2020, Arm Limited and Contributors.
* All rights reserved.
*/
diff --git a/include/lib/libc/aarch64/limits_.h b/include/lib/libc/aarch64/limits_.h
index 1bb0681..834439e 100644
--- a/include/lib/libc/aarch64/limits_.h
+++ b/include/lib/libc/aarch64/limits_.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/libc/aarch64/setjmp_.h b/include/lib/libc/aarch64/setjmp_.h
index f880a17..a7d0b5c 100644
--- a/include/lib/libc/aarch64/setjmp_.h
+++ b/include/lib/libc/aarch64/setjmp_.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/libc/aarch64/stddef_.h b/include/lib/libc/aarch64/stddef_.h
index 6ecc606..963048e 100644
--- a/include/lib/libc/aarch64/stddef_.h
+++ b/include/lib/libc/aarch64/stddef_.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/libc/aarch64/stdint_.h b/include/lib/libc/aarch64/stdint_.h
index 56e9f1b..34a75ec 100644
--- a/include/lib/libc/aarch64/stdint_.h
+++ b/include/lib/libc/aarch64/stdint_.h
@@ -4,7 +4,7 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
- * Portions copyright (c) 2020, ARM Limited and Contributors.
+ * Portions copyright (c) 2020, Arm Limited and Contributors.
* All rights reserved.
*/
diff --git a/include/lib/libc/aarch64/stdio_.h b/include/lib/libc/aarch64/stdio_.h
index afaeadc..331bcaa 100644
--- a/include/lib/libc/aarch64/stdio_.h
+++ b/include/lib/libc/aarch64/stdio_.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/libc/arm_acle.h b/include/lib/libc/arm_acle.h
index eb08552..d1bc0f9 100644
--- a/include/lib/libc/arm_acle.h
+++ b/include/lib/libc/arm_acle.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021 ARM Limited
+ * Copyright (c) 2021 Arm Limited
*
* SPDX-License-Identifier: BSD-3-Clause
*
diff --git a/include/lib/libc/assert.h b/include/lib/libc/assert.h
index 462bb43..acfd147 100644
--- a/include/lib/libc/assert.h
+++ b/include/lib/libc/assert.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/libc/cdefs.h b/include/lib/libc/cdefs.h
index 2423f38..b11d072 100644
--- a/include/lib/libc/cdefs.h
+++ b/include/lib/libc/cdefs.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/libc/endian.h b/include/lib/libc/endian.h
index 4100f57..9c9fd58 100644
--- a/include/lib/libc/endian.h
+++ b/include/lib/libc/endian.h
@@ -28,7 +28,7 @@
* $FreeBSD$
*/
/*
- * Portions copyright (c) 2018, ARM Limited and Contributors.
+ * Portions copyright (c) 2018, Arm Limited and Contributors.
* All rights reserved.
*/
diff --git a/include/lib/libc/errno.h b/include/lib/libc/errno.h
index 029912f..b536fe9 100644
--- a/include/lib/libc/errno.h
+++ b/include/lib/libc/errno.h
@@ -37,7 +37,7 @@
* $FreeBSD$
*/
/*
- * Portions copyright (c) 2018, ARM Limited and Contributors.
+ * Portions copyright (c) 2018, Arm Limited and Contributors.
* All rights reserved.
*/
diff --git a/include/lib/libc/inttypes.h b/include/lib/libc/inttypes.h
index 6ad1c9e..344b71c 100644
--- a/include/lib/libc/inttypes.h
+++ b/include/lib/libc/inttypes.h
@@ -4,7 +4,7 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
- * Portions copyright (c) 2020, ARM Limited and Contributors.
+ * Portions copyright (c) 2020, Arm Limited and Contributors.
* All rights reserved.
*/
diff --git a/include/lib/libc/limits.h b/include/lib/libc/limits.h
index 41bb658..c5c8764 100644
--- a/include/lib/libc/limits.h
+++ b/include/lib/libc/limits.h
@@ -4,7 +4,7 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
- * Portions copyright (c) 2018, ARM Limited and Contributors.
+ * Portions copyright (c) 2018, Arm Limited and Contributors.
* All rights reserved.
*/
diff --git a/include/lib/libc/setjmp.h b/include/lib/libc/setjmp.h
index be8e2c0..871c868 100644
--- a/include/lib/libc/setjmp.h
+++ b/include/lib/libc/setjmp.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/libc/stdarg.h b/include/lib/libc/stdarg.h
index e260b9b..2d1f785 100644
--- a/include/lib/libc/stdarg.h
+++ b/include/lib/libc/stdarg.h
@@ -4,7 +4,7 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
- * Portions copyright (c) 2018, ARM Limited and Contributors.
+ * Portions copyright (c) 2018, Arm Limited and Contributors.
* All rights reserved.
*/
diff --git a/include/lib/libc/stdbool.h b/include/lib/libc/stdbool.h
index b58334c..c2c9b22 100644
--- a/include/lib/libc/stdbool.h
+++ b/include/lib/libc/stdbool.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/libc/stddef.h b/include/lib/libc/stddef.h
index 58a519e..aaad673 100644
--- a/include/lib/libc/stddef.h
+++ b/include/lib/libc/stddef.h
@@ -4,7 +4,7 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
- * Portions copyright (c) 2018-2019, ARM Limited and Contributors.
+ * Portions copyright (c) 2018-2019, Arm Limited and Contributors.
* All rights reserved.
*/
diff --git a/include/lib/libc/stdint.h b/include/lib/libc/stdint.h
index e96a25c..88502e7 100644
--- a/include/lib/libc/stdint.h
+++ b/include/lib/libc/stdint.h
@@ -4,7 +4,7 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
- * Portions copyright (c) 2018-2019, ARM Limited and Contributors.
+ * Portions copyright (c) 2018-2019, Arm Limited and Contributors.
* All rights reserved.
*/
diff --git a/include/lib/libc/stdio.h b/include/lib/libc/stdio.h
index ba13683..5ceaf68 100644
--- a/include/lib/libc/stdio.h
+++ b/include/lib/libc/stdio.h
@@ -4,7 +4,7 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
- * Portions copyright (c) 2018-2019, ARM Limited and Contributors.
+ * Portions copyright (c) 2018-2019, Arm Limited and Contributors.
* All rights reserved.
*/
diff --git a/include/lib/libc/stdlib.h b/include/lib/libc/stdlib.h
index 4641e56..4e5a824 100644
--- a/include/lib/libc/stdlib.h
+++ b/include/lib/libc/stdlib.h
@@ -4,7 +4,7 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
- * Portions copyright (c) 2018-2019, ARM Limited and Contributors.
+ * Portions copyright (c) 2018-2019, Arm Limited and Contributors.
* All rights reserved.
*/
diff --git a/include/lib/libc/string.h b/include/lib/libc/string.h
index 7ddeed9..8129404 100644
--- a/include/lib/libc/string.h
+++ b/include/lib/libc/string.h
@@ -4,7 +4,7 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
- * Portions copyright (c) 2018-2020, ARM Limited and Contributors.
+ * Portions copyright (c) 2018-2020, Arm Limited and Contributors.
* Portions copyright (c) 2023, Intel Corporation. All rights reserved.
* All rights reserved.
*/
diff --git a/include/lib/libc/time.h b/include/lib/libc/time.h
index c1c95e5..e1eb2a5 100644
--- a/include/lib/libc/time.h
+++ b/include/lib/libc/time.h
@@ -4,7 +4,7 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
- * Portions copyright (c) 2018-2019, ARM Limited and Contributors.
+ * Portions copyright (c) 2018-2019, Arm Limited and Contributors.
* All rights reserved.
*/
diff --git a/include/lib/mmio.h b/include/lib/mmio.h
index 3242a7c..591d7b6 100644
--- a/include/lib/mmio.h
+++ b/include/lib/mmio.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2014, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/object_pool.h b/include/lib/object_pool.h
index 66e8c47..49584eb 100644
--- a/include/lib/object_pool.h
+++ b/include/lib/object_pool.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/optee_utils.h b/include/lib/optee_utils.h
index 8224d50..e1e9d80 100644
--- a/include/lib/optee_utils.h
+++ b/include/lib/optee_utils.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/pmf/aarch64/pmf_asm_macros.S b/include/lib/pmf/aarch64/pmf_asm_macros.S
index 5f3e6b7..792ede9 100644
--- a/include/lib/pmf/aarch64/pmf_asm_macros.S
+++ b/include/lib/pmf/aarch64/pmf_asm_macros.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2018, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/pmf/pmf.h b/include/lib/pmf/pmf.h
index fa990d2..9d901e2 100644
--- a/include/lib/pmf/pmf.h
+++ b/include/lib/pmf/pmf.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2020, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/pmf/pmf_helpers.h b/include/lib/pmf/pmf_helpers.h
index 01cc179..f5f040b 100644
--- a/include/lib/pmf/pmf_helpers.h
+++ b/include/lib/pmf/pmf_helpers.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2020, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/psci/psci.h b/include/lib/psci/psci.h
index 01dc3cb..c40f955 100644
--- a/include/lib/psci/psci.h
+++ b/include/lib/psci/psci.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2023, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
diff --git a/include/lib/runtime_instr.h b/include/lib/runtime_instr.h
index 303f27e..65fafa7 100644
--- a/include/lib/runtime_instr.h
+++ b/include/lib/runtime_instr.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2018, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/semihosting.h b/include/lib/semihosting.h
index 24b030c..5c72e8b 100644
--- a/include/lib/semihosting.h
+++ b/include/lib/semihosting.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2014, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/smccc.h b/include/lib/smccc.h
index fb2b3a2..8fd6093 100644
--- a/include/lib/smccc.h
+++ b/include/lib/smccc.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/spinlock.h b/include/lib/spinlock.h
index 0bf3ee0..9fd3fc6 100644
--- a/include/lib/spinlock.h
+++ b/include/lib/spinlock.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2018, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/utils.h b/include/lib/utils.h
index 17ee936..ce76de2 100644
--- a/include/lib/utils.h
+++ b/include/lib/utils.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/utils_def.h b/include/lib/utils_def.h
index 63eda63..ba52bc6 100644
--- a/include/lib/utils_def.h
+++ b/include/lib/utils_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2022, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
diff --git a/include/lib/xlat_mpu/xlat_mpu.h b/include/lib/xlat_mpu/xlat_mpu.h
index 252b92c..3a470ad 100644
--- a/include/lib/xlat_mpu/xlat_mpu.h
+++ b/include/lib/xlat_mpu/xlat_mpu.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/xlat_tables/aarch32/xlat_tables_aarch32.h b/include/lib/xlat_tables/aarch32/xlat_tables_aarch32.h
index 30eb5e9..42a48f4 100644
--- a/include/lib/xlat_tables/aarch32/xlat_tables_aarch32.h
+++ b/include/lib/xlat_tables/aarch32/xlat_tables_aarch32.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2018, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/xlat_tables/aarch64/xlat_tables_aarch64.h b/include/lib/xlat_tables/aarch64/xlat_tables_aarch64.h
index 3014c8f..6c0d73b 100644
--- a/include/lib/xlat_tables/aarch64/xlat_tables_aarch64.h
+++ b/include/lib/xlat_tables/aarch64/xlat_tables_aarch64.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2018, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/xlat_tables/xlat_mmu_helpers.h b/include/lib/xlat_tables/xlat_mmu_helpers.h
index 269afd2..fabc494 100644
--- a/include/lib/xlat_tables/xlat_mmu_helpers.h
+++ b/include/lib/xlat_tables/xlat_mmu_helpers.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2018, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/xlat_tables/xlat_tables.h b/include/lib/xlat_tables/xlat_tables.h
index a156969..24f833c 100644
--- a/include/lib/xlat_tables/xlat_tables.h
+++ b/include/lib/xlat_tables/xlat_tables.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2021, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/xlat_tables/xlat_tables_arch.h b/include/lib/xlat_tables/xlat_tables_arch.h
index 0ce0cac..46e058c 100644
--- a/include/lib/xlat_tables/xlat_tables_arch.h
+++ b/include/lib/xlat_tables/xlat_tables_arch.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2018, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/xlat_tables/xlat_tables_compat.h b/include/lib/xlat_tables/xlat_tables_compat.h
index 5f28195..3877c91 100644
--- a/include/lib/xlat_tables/xlat_tables_compat.h
+++ b/include/lib/xlat_tables/xlat_tables_compat.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/xlat_tables/xlat_tables_v2.h b/include/lib/xlat_tables/xlat_tables_v2.h
index 4d16ced..64fe5ef 100644
--- a/include/lib/xlat_tables/xlat_tables_v2.h
+++ b/include/lib/xlat_tables/xlat_tables_v2.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/xlat_tables/xlat_tables_v2_helpers.h b/include/lib/xlat_tables/xlat_tables_v2_helpers.h
index 62f853d..992c94e 100644
--- a/include/lib/xlat_tables/xlat_tables_v2_helpers.h
+++ b/include/lib/xlat_tables/xlat_tables_v2_helpers.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2020, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/zlib/tf_gunzip.h b/include/lib/zlib/tf_gunzip.h
index 741ba50..9435860 100644
--- a/include/lib/zlib/tf_gunzip.h
+++ b/include/lib/zlib/tf_gunzip.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/plat/arm/common/fconf_ethosn_getter.h b/include/plat/arm/common/fconf_ethosn_getter.h
index cafbc3e..d45c269 100644
--- a/include/plat/arm/common/fconf_ethosn_getter.h
+++ b/include/plat/arm/common/fconf_ethosn_getter.h
@@ -57,8 +57,6 @@
struct ethosn_device_t devices[ETHOSN_DEV_NUM_MAX];
};
-int fconf_populate_arm_ethosn(uintptr_t config);
-
extern struct ethosn_config_t ethosn_config;
#endif /* FCONF_ETHOSN_GETTER_H */
diff --git a/include/plat/common/platform.h b/include/plat/common/platform.h
index d146a29..e024d91 100644
--- a/include/plat/common/platform.h
+++ b/include/plat/common/platform.h
@@ -146,6 +146,8 @@
int plat_mboot_measure_critical_data(unsigned int critical_data_id,
const void *base,
size_t size);
+int plat_mboot_measure_key(const void *pk_oid, const void *pk_ptr,
+ size_t pk_len);
#else
static inline int plat_mboot_measure_image(unsigned int image_id __unused,
image_info_t *image_data __unused)
@@ -159,6 +161,12 @@
{
return 0;
}
+static inline int plat_mboot_measure_key(const void *pk_oid __unused,
+ const void *pk_ptr __unused,
+ size_t pk_len __unused)
+{
+ return 0;
+}
#endif /* MEASURED_BOOT */
/*******************************************************************************
diff --git a/include/tools_share/cca_oid.h b/include/tools_share/cca_oid.h
index 2ca12c9..8c53ef9 100644
--- a/include/tools_share/cca_oid.h
+++ b/include/tools_share/cca_oid.h
@@ -28,4 +28,17 @@
/* CCAFirmwareNVCounter - Non-volatile counter extension */
#define CCA_FW_NVCOUNTER_OID "1.3.6.1.4.1.4128.2100.3"
+/*
+ * First undef previous definitions from tbbr_oid.h.
+ * CCA ROTPK authenticates BL31 and its configuration image in
+ * CCA CoT.
+ **/
+#undef BL31_IMAGE_KEY_OID
+#undef SOC_FW_CONFIG_KEY_OID
+#undef HW_CONFIG_KEY_OID
+#define BL31_IMAGE_KEY_OID ZERO_OID
+#define SOC_FW_CONFIG_KEY_OID ZERO_OID
+#define HW_CONFIG_KEY_OID ZERO_OID
+#define RMM_IMAGE_KEY_OID ZERO_OID
+
#endif /* CCA_OID_H */
diff --git a/include/tools_share/dualroot_oid.h b/include/tools_share/dualroot_oid.h
index 3e88a6d..3762c79 100644
--- a/include/tools_share/dualroot_oid.h
+++ b/include/tools_share/dualroot_oid.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020, Arm Limited. All rights reserved.
+ * Copyright (c) 2020-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/tools_share/tbbr_oid.h b/include/tools_share/tbbr_oid.h
index 52b43ab..9881d1a 100644
--- a/include/tools_share/tbbr_oid.h
+++ b/include/tools_share/tbbr_oid.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,6 +7,8 @@
#ifndef TBBR_OID_H
#define TBBR_OID_H
+#include "zero_oid.h"
+
#define MAX_OID_NAME_LEN 30
/*
@@ -160,6 +162,14 @@
#define SP_PKG7_HASH_OID "1.3.6.1.4.1.4128.2100.1307"
#define SP_PKG8_HASH_OID "1.3.6.1.4.1.4128.2100.1308"
+/*
+ * Public Keys present in SOC FW content certificates authenticate BL31 and
+ * its configuration.
+ */
+#define BL31_IMAGE_KEY_OID SOC_FW_CONTENT_CERT_PK_OID
+#define SOC_FW_CONFIG_KEY_OID SOC_FW_CONTENT_CERT_PK_OID
+#define HW_CONFIG_KEY_OID ZERO_OID
+
#ifdef PLAT_DEF_OID
#include <platform_oid.h>
#endif
diff --git a/include/tools_share/zero_oid.h b/include/tools_share/zero_oid.h
new file mode 100644
index 0000000..9b83094
--- /dev/null
+++ b/include/tools_share/zero_oid.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2023, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef ZERO_OID_H
+#define ZERO_OID_H
+
+#define ZERO_OID "0.0.0.0.0.0.0.0.0"
+
+#endif /* ZERO_OID_H */
diff --git a/lib/aarch32/arm32_aeabi_divmod.c b/lib/aarch32/arm32_aeabi_divmod.c
index ea8e2bb..89a9033 100644
--- a/lib/aarch32/arm32_aeabi_divmod.c
+++ b/lib/aarch32/arm32_aeabi_divmod.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/aarch32/arm32_aeabi_divmod_a32.S b/lib/aarch32/arm32_aeabi_divmod_a32.S
index 6915dcd..9155100 100644
--- a/lib/aarch32/arm32_aeabi_divmod_a32.S
+++ b/lib/aarch32/arm32_aeabi_divmod_a32.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/aarch32/armclang_printf.S b/lib/aarch32/armclang_printf.S
index 2b87bf7..e736a11 100644
--- a/lib/aarch32/armclang_printf.S
+++ b/lib/aarch32/armclang_printf.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/aarch32/misc_helpers.S b/lib/aarch32/misc_helpers.S
index 59e15bd..c010cbc 100644
--- a/lib/aarch32/misc_helpers.S
+++ b/lib/aarch32/misc_helpers.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2021, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/aarch64/armclang_printf.S b/lib/aarch64/armclang_printf.S
index 52a6976..f9326fd 100644
--- a/lib/aarch64/armclang_printf.S
+++ b/lib/aarch64/armclang_printf.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/bl_aux_params/bl_aux_params.c b/lib/bl_aux_params/bl_aux_params.c
index 7f357b7..6e30ecf 100644
--- a/lib/bl_aux_params/bl_aux_params.c
+++ b/lib/bl_aux_params/bl_aux_params.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/compiler-rt/compiler-rt.mk b/lib/compiler-rt/compiler-rt.mk
index b41c4d0..2b16504 100644
--- a/lib/compiler-rt/compiler-rt.mk
+++ b/lib/compiler-rt/compiler-rt.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
diff --git a/lib/coreboot/coreboot.mk b/lib/coreboot/coreboot.mk
index 4201823..e07d28c 100644
--- a/lib/coreboot/coreboot.mk
+++ b/lib/coreboot/coreboot.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2017, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
diff --git a/lib/coreboot/coreboot_table.c b/lib/coreboot/coreboot_table.c
index 43e9835..c954e97 100644
--- a/lib/coreboot/coreboot_table.c
+++ b/lib/coreboot/coreboot_table.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2020, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/cpus/aarch32/aem_generic.S b/lib/cpus/aarch32/aem_generic.S
index 7bd586a..9f45e38 100644
--- a/lib/cpus/aarch32/aem_generic.S
+++ b/lib/cpus/aarch32/aem_generic.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2017, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/cpus/aarch32/cortex_a12.S b/lib/cpus/aarch32/cortex_a12.S
index 5300fe0..8eec27c 100644
--- a/lib/cpus/aarch32/cortex_a12.S
+++ b/lib/cpus/aarch32/cortex_a12.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -64,19 +64,16 @@
bl plat_disable_acp
+ /* Flush L2 caches */
+ mov r0, #DC_OP_CISW
+ bl dcsw_op_level2
+
/* Exit cluster coherency */
pop {r12, lr}
b cortex_a12_disable_smp
endfunc cortex_a12_cluster_pwr_dwn
-#if REPORT_ERRATA
-/*
- * Errata printing function for Cortex-A12. Must follow AAPCS.
- */
-func cortex_a12_errata_report
- bx lr
-endfunc cortex_a12_errata_report
-#endif
+errata_report_shim cortex_a12
declare_cpu_ops cortex_a12, CORTEX_A12_MIDR, \
cortex_a12_reset_func, \
diff --git a/lib/cpus/aarch32/cortex_a15.S b/lib/cpus/aarch32/cortex_a15.S
index 1143e9b..b41676d 100644
--- a/lib/cpus/aarch32/cortex_a15.S
+++ b/lib/cpus/aarch32/cortex_a15.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2022, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -62,6 +62,7 @@
bx lr
endfunc check_errata_816470
+add_erratum_entry cortex_a15, ERRATUM(816470), ERRATA_A15_816470
/* ----------------------------------------------------
* Errata Workaround for Cortex A15 Errata #827671.
* This applies only to revision >= r3p0 of Cortex A15.
@@ -91,6 +92,8 @@
b cpu_rev_var_hs
endfunc check_errata_827671
+add_erratum_entry cortex_a15, ERRATUM(827671), ERRATA_A15_827671
+
func check_errata_cve_2017_5715
#if WORKAROUND_CVE_2017_5715
mov r0, #ERRATA_APPLIES
@@ -100,6 +103,8 @@
bx lr
endfunc check_errata_cve_2017_5715
+add_erratum_entry cortex_a15, CVE(2017, 5715), WORKAROUND_CVE_2017_5715
+
func check_errata_cve_2022_23960
#if WORKAROUND_CVE_2022_23960
mov r0, #ERRATA_APPLIES
@@ -109,29 +114,7 @@
bx lr
endfunc check_errata_cve_2022_23960
-#if REPORT_ERRATA
-/*
- * Errata printing function for Cortex A15. Must follow AAPCS.
- */
-func cortex_a15_errata_report
- push {r12, lr}
-
- bl cpu_get_rev_var
- mov r4, r0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata ERRATA_A15_816470, cortex_a15, 816470
- report_errata ERRATA_A15_827671, cortex_a15, 827671
- report_errata WORKAROUND_CVE_2017_5715, cortex_a15, cve_2017_5715
- report_errata WORKAROUND_CVE_2022_23960, cortex_a15, cve_2022_23960
-
- pop {r12, lr}
- bx lr
-endfunc cortex_a15_errata_report
-#endif
+add_erratum_entry cortex_a15, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
func cortex_a15_reset_func
mov r5, lr
@@ -180,11 +163,17 @@
bl plat_disable_acp
+ /* Flush L2 caches */
+ mov r0, #DC_OP_CISW
+ bl dcsw_op_level2
+
/* Exit cluster coherency */
pop {r12, lr}
b cortex_a15_disable_smp
endfunc cortex_a15_cluster_pwr_dwn
+errata_report_shim cortex_a15
+
declare_cpu_ops cortex_a15, CORTEX_A15_MIDR, \
cortex_a15_reset_func, \
cortex_a15_core_pwr_dwn, \
diff --git a/lib/cpus/aarch32/cortex_a17.S b/lib/cpus/aarch32/cortex_a17.S
index 8d76ab2..1877570 100644
--- a/lib/cpus/aarch32/cortex_a17.S
+++ b/lib/cpus/aarch32/cortex_a17.S
@@ -159,6 +159,10 @@
bl plat_disable_acp
+ /* Flush L2 caches */
+ mov r0, #DC_OP_CISW
+ bl dcsw_op_level2
+
/* Exit cluster coherency */
pop {r12, lr}
b cortex_a17_disable_smp
diff --git a/lib/cpus/aarch32/cortex_a32.S b/lib/cpus/aarch32/cortex_a32.S
index dfa159f..d08b4ff 100644
--- a/lib/cpus/aarch32/cortex_a32.S
+++ b/lib/cpus/aarch32/cortex_a32.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/cpus/aarch32/cortex_a5.S b/lib/cpus/aarch32/cortex_a5.S
index 8abb66f..625ea7b 100644
--- a/lib/cpus/aarch32/cortex_a5.S
+++ b/lib/cpus/aarch32/cortex_a5.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -69,14 +69,7 @@
b cortex_a5_disable_smp
endfunc cortex_a5_cluster_pwr_dwn
-#if REPORT_ERRATA
-/*
- * Errata printing function for Cortex-A5. Must follow AAPCS.
- */
-func cortex_a5_errata_report
- bx lr
-endfunc cortex_a5_errata_report
-#endif
+errata_report_shim cortex_a5
declare_cpu_ops cortex_a5, CORTEX_A5_MIDR, \
cortex_a5_reset_func, \
diff --git a/lib/cpus/aarch32/cortex_a7.S b/lib/cpus/aarch32/cortex_a7.S
index 4d4bb77..4842ca6 100644
--- a/lib/cpus/aarch32/cortex_a7.S
+++ b/lib/cpus/aarch32/cortex_a7.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -64,19 +64,16 @@
bl plat_disable_acp
+ /* Flush L2 caches */
+ mov r0, #DC_OP_CISW
+ bl dcsw_op_level2
+
/* Exit cluster coherency */
pop {r12, lr}
b cortex_a7_disable_smp
endfunc cortex_a7_cluster_pwr_dwn
-#if REPORT_ERRATA
-/*
- * Errata printing function for Cortex-A7. Must follow AAPCS.
- */
-func cortex_a7_errata_report
- bx lr
-endfunc cortex_a7_errata_report
-#endif
+errata_report_shim cortex_a7
declare_cpu_ops cortex_a7, CORTEX_A7_MIDR, \
cortex_a7_reset_func, \
diff --git a/lib/cpus/aarch32/cortex_a9.S b/lib/cpus/aarch32/cortex_a9.S
index 9e75e4e..1e9757a 100644
--- a/lib/cpus/aarch32/cortex_a9.S
+++ b/lib/cpus/aarch32/cortex_a9.S
@@ -35,14 +35,16 @@
bx lr
endfunc cortex_a9_enable_smp
-func check_errata_a9_794073
+func check_errata_794073
#if ERRATA_A9_794073
mov r0, #ERRATA_APPLIES
#else
mov r0, #ERRATA_MISSING
#endif
bx lr
-endfunc check_errata_a9_794073
+endfunc check_errata_794073
+
+add_erratum_entry cortex_a9, ERRATUM(794073), ERRATA_A9_794073
func check_errata_cve_2017_5715
#if WORKAROUND_CVE_2017_5715
@@ -53,27 +55,9 @@
bx lr
endfunc check_errata_cve_2017_5715
-#if REPORT_ERRATA
-/*
- * Errata printing function for Cortex A9. Must follow AAPCS.
- */
-func cortex_a9_errata_report
- push {r12, lr}
-
- bl cpu_get_rev_var
- mov r4, r0
+add_erratum_entry cortex_a9, CVE(2017, 5715), WORKAROUND_CVE_2017_5715
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata WORKAROUND_CVE_2017_5715, cortex_a9, cve_2017_5715
- report_errata ERRATA_A9_794073, cortex_a9, a9_794073
-
- pop {r12, lr}
- bx lr
-endfunc cortex_a9_errata_report
-#endif
+errata_report_shim cortex_a9
func cortex_a9_reset_func
#if IMAGE_BL32 && WORKAROUND_CVE_2017_5715
diff --git a/lib/cpus/aarch32/cpu_helpers.S b/lib/cpus/aarch32/cpu_helpers.S
index 05bc5d9..83e3e49 100644
--- a/lib/cpus/aarch32/cpu_helpers.S
+++ b/lib/cpus/aarch32/cpu_helpers.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/cpus/aarch64/aem_generic.S b/lib/cpus/aarch64/aem_generic.S
index 6291e43..d47279a 100644
--- a/lib/cpus/aarch64/aem_generic.S
+++ b/lib/cpus/aarch64/aem_generic.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/cpus/aarch64/cortex_a35.S b/lib/cpus/aarch64/cortex_a35.S
index be3c652..6ffb944 100644
--- a/lib/cpus/aarch64/cortex_a35.S
+++ b/lib/cpus/aarch64/cortex_a35.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -16,9 +16,7 @@
* ---------------------------------------------
*/
func cortex_a35_disable_dcache
- mrs x1, sctlr_el3
- bic x1, x1, #SCTLR_C_BIT
- msr sctlr_el3, x1
+ sysreg_bit_clear sctlr_el3, SCTLR_C_BIT
isb
ret
endfunc cortex_a35_disable_dcache
@@ -28,65 +26,29 @@
* ---------------------------------------------
*/
func cortex_a35_disable_smp
- mrs x0, CORTEX_A35_CPUECTLR_EL1
- bic x0, x0, #CORTEX_A35_CPUECTLR_SMPEN_BIT
- msr CORTEX_A35_CPUECTLR_EL1, x0
+ sysreg_bit_clear CORTEX_A35_CPUECTLR_EL1, CORTEX_A35_CPUECTLR_SMPEN_BIT
isb
dsb sy
ret
endfunc cortex_a35_disable_smp
- /* ---------------------------------------------------
- * Errata Workaround for Cortex A35 Errata #855472.
- * This applies to revisions r0p0 of Cortex A35.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ---------------------------------------------------
- */
-func errata_a35_855472_wa
- /*
- * Compare x0 against revision r0p0
- */
- mov x17, x30
- bl check_errata_855472
- cbz x0, 1f
- mrs x1, CORTEX_A35_CPUACTLR_EL1
- orr x1, x1, #CORTEX_A35_CPUACTLR_EL1_ENDCCASCI
- msr CORTEX_A35_CPUACTLR_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_a35_855472_wa
+workaround_reset_start cortex_a35, ERRATUM(855472), ERRATA_A35_855472
+ sysreg_bit_set CORTEX_A35_CPUACTLR_EL1, CORTEX_A35_CPUACTLR_EL1_ENDCCASCI
+workaround_reset_end cortex_a35, ERRATUM(855472)
-func check_errata_855472
- mov x1, #0x00
- b cpu_rev_var_ls
-endfunc check_errata_855472
+check_erratum_ls cortex_a35, ERRATUM(855472), CPU_REV(0, 0)
/* -------------------------------------------------
* The CPU Ops reset function for Cortex-A35.
- * Clobbers: x0
* -------------------------------------------------
*/
-func cortex_a35_reset_func
- mov x19, x30
- bl cpu_get_rev_var
-
-#if ERRATA_A35_855472
- bl errata_a35_855472_wa
-#endif
-
+cpu_reset_func_start cortex_a35
/* ---------------------------------------------
* Enable the SMP bit.
* ---------------------------------------------
*/
- mrs x0, CORTEX_A35_CPUECTLR_EL1
- orr x0, x0, #CORTEX_A35_CPUECTLR_SMPEN_BIT
- msr CORTEX_A35_CPUECTLR_EL1, x0
- isb
- ret x19
-endfunc cortex_a35_reset_func
+ sysreg_bit_set CORTEX_A35_CPUECTLR_EL1, CORTEX_A35_CPUECTLR_SMPEN_BIT
+cpu_reset_func_end cortex_a35
func cortex_a35_core_pwr_dwn
mov x18, x30
@@ -149,27 +111,7 @@
b cortex_a35_disable_smp
endfunc cortex_a35_cluster_pwr_dwn
-#if REPORT_ERRATA
-/*
- * Errata printing function for Cortex A35. Must follow AAPCS.
- */
-func cortex_a35_errata_report
- stp x8, x30, [sp, #-16]!
-
- bl cpu_get_rev_var
- mov x8, x0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata ERRATA_A35_855472, cortex_a35, 855472
-
- ldp x8, x30, [sp], #16
- ret
-endfunc cortex_a35_errata_report
-#endif
-
+errata_report_shim cortex_a35
/* ---------------------------------------------
* This function provides cortex_a35 specific
diff --git a/lib/cpus/aarch64/cortex_a55.S b/lib/cpus/aarch64/cortex_a55.S
index 0e0388b..712b6e0 100644
--- a/lib/cpus/aarch64/cortex_a55.S
+++ b/lib/cpus/aarch64/cortex_a55.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -18,63 +18,37 @@
.globl cortex_a55_reset_func
.globl cortex_a55_core_pwr_dwn
- /* --------------------------------------------------
- * Errata Workaround for Cortex A55 Errata #768277.
- * This applies only to revision r0p0 of Cortex A55.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a55_768277_wa
- /*
- * Compare x0 against revision r0p0
- */
- mov x17, x30
- bl check_errata_768277
- cbz x0, 1f
- mrs x1, CORTEX_A55_CPUACTLR_EL1
- orr x1, x1, #CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE
- msr CORTEX_A55_CPUACTLR_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_a55_768277_wa
-func check_errata_768277
- mov x1, #0x00
- b cpu_rev_var_ls
-endfunc check_errata_768277
+/* ERRATA_DSU_798953:
+ * The errata is defined in dsu_helpers.S but applies to cortex_a55
+ * as well. Henceforth creating symbolic names to the already existing errata
+ * workaround functions to get them registered under the Errata Framework.
+ */
+.equ check_erratum_cortex_a55_798953, check_errata_dsu_798953
+.equ erratum_cortex_a55_798953_wa, errata_dsu_798953_wa
+add_erratum_entry cortex_a55, ERRATUM(798953), ERRATA_DSU_798953, APPLY_AT_RESET
- /* ------------------------------------------------------------------
- * Errata Workaround for Cortex A55 Errata #778703.
- * This applies only to revision r0p0 of Cortex A55 where L2 cache is
- * not configured.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ------------------------------------------------------------------
- */
-func errata_a55_778703_wa
- /*
- * Compare x0 against revision r0p0 and check that no private L2 cache
- * is configured
- */
- mov x17, x30
- bl check_errata_778703
- cbz x0, 1f
- mrs x1, CORTEX_A55_CPUECTLR_EL1
- orr x1, x1, #CORTEX_A55_CPUECTLR_EL1_L1WSCTL
- msr CORTEX_A55_CPUECTLR_EL1, x1
- mrs x1, CORTEX_A55_CPUACTLR_EL1
- orr x1, x1, #CORTEX_A55_CPUACTLR_EL1_DISABLE_WRITE_STREAMING
- msr CORTEX_A55_CPUACTLR_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_a55_778703_wa
+/* ERRATA_DSU_936184:
+ * The errata is defined in dsu_helpers.S but applies to cortex_a55
+ * as well. Henceforth creating symbolic names to the already existing errata
+ * workaround functions to get them registered under the Errata Framework.
+ */
+.equ check_erratum_cortex_a55_936184, check_errata_dsu_936184
+.equ erratum_cortex_a55_936184_wa, errata_dsu_936184_wa
+add_erratum_entry cortex_a55, ERRATUM(936184), ERRATA_DSU_936184, APPLY_AT_RESET
+
+workaround_reset_start cortex_a55, ERRATUM(768277), ERRATA_A55_768277
+ sysreg_bit_set CORTEX_A55_CPUACTLR_EL1, CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE
+workaround_reset_end cortex_a55, ERRATUM(768277)
-func check_errata_778703
+check_erratum_ls cortex_a55, ERRATUM(768277), CPU_REV(0, 0)
+
+workaround_reset_start cortex_a55, ERRATUM(778703), ERRATA_A55_778703
+ sysreg_bit_set CORTEX_A55_CPUECTLR_EL1, CORTEX_A55_CPUECTLR_EL1_L1WSCTL
+ sysreg_bit_set CORTEX_A55_CPUACTLR_EL1, CORTEX_A55_CPUACTLR_EL1_DISABLE_WRITE_STREAMING
+workaround_reset_end cortex_a55, ERRATUM(778703)
+
+check_erratum_custom_start cortex_a55, ERRATUM(778703)
mov x16, x30
mov x1, #0x00
bl cpu_rev_var_ls
@@ -87,111 +61,27 @@
mov x2, #ERRATA_NOT_APPLIES
csel x0, x0, x2, eq
ret x16
-endfunc check_errata_778703
+check_erratum_custom_end cortex_a55, ERRATUM(778703)
- /* --------------------------------------------------
- * Errata Workaround for Cortex A55 Errata #798797.
- * This applies only to revision r0p0 of Cortex A55.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a55_798797_wa
- /*
- * Compare x0 against revision r0p0
- */
- mov x17, x30
- bl check_errata_798797
- cbz x0, 1f
- mrs x1, CORTEX_A55_CPUACTLR_EL1
- orr x1, x1, #CORTEX_A55_CPUACTLR_EL1_DISABLE_L1_PAGEWALKS
- msr CORTEX_A55_CPUACTLR_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_a55_798797_wa
+workaround_reset_start cortex_a55, ERRATUM(798797), ERRATA_A55_798797
+ sysreg_bit_set CORTEX_A55_CPUACTLR_EL1, CORTEX_A55_CPUACTLR_EL1_DISABLE_L1_PAGEWALKS
+workaround_reset_end cortex_a55, ERRATUM(798797)
-func check_errata_798797
- mov x1, #0x00
- b cpu_rev_var_ls
-endfunc check_errata_798797
+check_erratum_ls cortex_a55, ERRATUM(798797), CPU_REV(0, 0)
- /* --------------------------------------------------------------------
- * Errata Workaround for Cortex A55 Errata #846532.
- * This applies only to revisions <= r0p1 of Cortex A55.
- * Disabling dual-issue has a small impact on performance. Disabling a
- * power optimization feature is an alternate workaround with no impact
- * on performance but with an increase in power consumption (see errata
- * notice).
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------------------------
- */
-func errata_a55_846532_wa
- /*
- * Compare x0 against revision r0p1
- */
- mov x17, x30
- bl check_errata_846532
- cbz x0, 1f
- mrs x1, CORTEX_A55_CPUACTLR_EL1
- orr x1, x1, #CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE
- msr CORTEX_A55_CPUACTLR_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_a55_846532_wa
+workaround_reset_start cortex_a55, ERRATUM(846532), ERRATA_A55_846532
+ sysreg_bit_set CORTEX_A55_CPUACTLR_EL1, CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE
+workaround_reset_end cortex_a55, ERRATUM(846532)
-func check_errata_846532
- mov x1, #0x01
- b cpu_rev_var_ls
-endfunc check_errata_846532
+check_erratum_ls cortex_a55, ERRATUM(846532), CPU_REV(0, 1)
- /* -----------------------------------------------------
- * Errata Workaround for Cortex A55 Errata #903758.
- * This applies only to revisions <= r0p1 of Cortex A55.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * -----------------------------------------------------
- */
-func errata_a55_903758_wa
- /*
- * Compare x0 against revision r0p1
- */
- mov x17, x30
- bl check_errata_903758
- cbz x0, 1f
- mrs x1, CORTEX_A55_CPUACTLR_EL1
- orr x1, x1, #CORTEX_A55_CPUACTLR_EL1_DISABLE_L1_PAGEWALKS
- msr CORTEX_A55_CPUACTLR_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_a55_903758_wa
+workaround_reset_start cortex_a55, ERRATUM(903758), ERRATA_A55_903758
+ sysreg_bit_set CORTEX_A55_CPUACTLR_EL1, CORTEX_A55_CPUACTLR_EL1_DISABLE_L1_PAGEWALKS
+workaround_reset_end cortex_a55, ERRATUM(903758)
-func check_errata_903758
- mov x1, #0x01
- b cpu_rev_var_ls
-endfunc check_errata_903758
+check_erratum_ls cortex_a55, ERRATUM(903758), CPU_REV(0, 1)
- /* -----------------------------------------------------
- * Errata Workaround for Cortex A55 Errata #1221012.
- * This applies only to revisions <= r1p0 of Cortex A55.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * -----------------------------------------------------
- */
-func errata_a55_1221012_wa
- /*
- * Compare x0 against revision r1p0
- */
- mov x17, x30
- bl check_errata_1221012
- cbz x0, 1f
+workaround_reset_start cortex_a55, ERRATUM(1221012), ERRATA_A55_1221012
mov x0, #0x0020
movk x0, #0x0850, lsl #16
msr CPUPOR_EL3, x0
@@ -214,121 +104,30 @@
mov x0, #0x03fd
movk x0, #0x0110, lsl #16
msr CPUPCR_EL3, x0
- isb
-1:
- ret x17
-endfunc errata_a55_1221012_wa
+workaround_reset_end cortex_a55, ERRATUM(1221012)
-func check_errata_1221012
- mov x1, #0x10
- b cpu_rev_var_ls
-endfunc check_errata_1221012
+check_erratum_ls cortex_a55, ERRATUM(1221012), CPU_REV(1, 0)
- /* --------------------------------------------------
- * Errata workaround for Cortex A55 Errata #1530923.
- * This applies to all revisions of Cortex A55.
- * --------------------------------------------------
- */
-func check_errata_1530923
-#if ERRATA_A55_1530923
- mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
-#endif
- ret
-endfunc check_errata_1530923
-
-func cortex_a55_reset_func
- mov x19, x30
-
-#if ERRATA_DSU_798953
- bl errata_dsu_798953_wa
-#endif
-
-#if ERRATA_DSU_936184
- bl errata_dsu_936184_wa
-#endif
-
- bl cpu_get_rev_var
- mov x18, x0
-
-#if ERRATA_A55_768277
- mov x0, x18
- bl errata_a55_768277_wa
-#endif
-
-#if ERRATA_A55_778703
- mov x0, x18
- bl errata_a55_778703_wa
-#endif
-
-#if ERRATA_A55_798797
- mov x0, x18
- bl errata_a55_798797_wa
-#endif
+check_erratum_chosen cortex_a55, ERRATUM(1530923), ERRATA_A55_1530923
-#if ERRATA_A55_846532
- mov x0, x18
- bl errata_a55_846532_wa
-#endif
-
-#if ERRATA_A55_903758
- mov x0, x18
- bl errata_a55_903758_wa
-#endif
+/* erratum has no workaround in the cpu. Generic code must take care */
+add_erratum_entry cortex_a55, ERRATUM(1530923), ERRATA_A55_1530923, NO_APPLY_AT_RESET
-#if ERRATA_A55_1221012
- mov x0, x18
- bl errata_a55_1221012_wa
-#endif
+cpu_reset_func_start cortex_a55
+cpu_reset_func_end cortex_a55
- ret x19
-endfunc cortex_a55_reset_func
+errata_report_shim cortex_a55
/* ---------------------------------------------
* HW will do the cache maintenance while powering down
* ---------------------------------------------
*/
func cortex_a55_core_pwr_dwn
- /* ---------------------------------------------
- * Enable CPU power down bit in power control register
- * ---------------------------------------------
- */
- mrs x0, CORTEX_A55_CPUPWRCTLR_EL1
- orr x0, x0, #CORTEX_A55_CORE_PWRDN_EN_MASK
- msr CORTEX_A55_CPUPWRCTLR_EL1, x0
+ sysreg_bit_set CORTEX_A55_CPUPWRCTLR_EL1, CORTEX_A55_CORE_PWRDN_EN_MASK
isb
ret
endfunc cortex_a55_core_pwr_dwn
-#if REPORT_ERRATA
-/*
- * Errata printing function for Cortex A55. Must follow AAPCS & can use stack.
- */
-func cortex_a55_errata_report
- stp x8, x30, [sp, #-16]!
- bl cpu_get_rev_var
- mov x8, x0
-
- /*
- * Report all errata. The revision variant information is at x8, where
- * "report_errata" is expecting it and it doesn't corrupt it.
- */
- report_errata ERRATA_DSU_798953, cortex_a55, dsu_798953
- report_errata ERRATA_DSU_936184, cortex_a55, dsu_936184
- report_errata ERRATA_A55_768277, cortex_a55, 768277
- report_errata ERRATA_A55_778703, cortex_a55, 778703
- report_errata ERRATA_A55_798797, cortex_a55, 798797
- report_errata ERRATA_A55_846532, cortex_a55, 846532
- report_errata ERRATA_A55_903758, cortex_a55, 903758
- report_errata ERRATA_A55_1221012, cortex_a55, 1221012
- report_errata ERRATA_A55_1530923, cortex_a55, 1530923
-
- ldp x8, x30, [sp], #16
- ret
-endfunc cortex_a55_errata_report
-#endif
-
/* ---------------------------------------------
* This function provides cortex_a55 specific
* register information for crash reporting.
diff --git a/lib/cpus/aarch64/cortex_a710.S b/lib/cpus/aarch64/cortex_a710.S
index cebd6f0..eab5ada 100644
--- a/lib/cpus/aarch64/cortex_a710.S
+++ b/lib/cpus/aarch64/cortex_a710.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -26,22 +26,7 @@
wa_cve_2022_23960_bhb_vector_table CORTEX_A710_BHB_LOOP_COUNT, cortex_a710
#endif /* WORKAROUND_CVE_2022_23960 */
-/* --------------------------------------------------
- * Errata Workaround for Cortex-A710 Erratum 1987031.
- * This applies to revision r0p0, r1p0 and r2p0 of Cortex-A710. It is still
- * open.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a710_1987031_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_1987031
- cbz x0, 1f
-
- /* Apply instruction patching sequence */
+workaround_reset_start cortex_a710, ERRATUM(1987031), ERRATA_A710_1987031
ldr x0,=0x6
msr S3_6_c15_c8_0,x0
ldr x0,=0xF3A08002
@@ -58,33 +43,53 @@
msr S3_6_c15_c8_3,x0
ldr x0,=0x40000001003f3
msr S3_6_c15_c8_1,x0
- isb
-1:
- ret x17
-endfunc errata_a710_1987031_wa
+workaround_reset_end cortex_a710, ERRATUM(1987031)
-func check_errata_1987031
- /* Applies to r0p0, r1p0 and r2p0 */
- mov x1, #0x20
- b cpu_rev_var_ls
-endfunc check_errata_1987031
+check_erratum_ls cortex_a710, ERRATUM(1987031), CPU_REV(2, 0)
-/* --------------------------------------------------
- * Errata Workaround for Cortex-A710 Erratum 2081180.
- * This applies to revision r0p0, r1p0 and r2p0 of Cortex-A710.
- * It is still open.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a710_2081180_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_2081180
- cbz x0, 1f
+workaround_runtime_start cortex_a710, ERRATUM(2008768), ERRATA_A710_2008768
+ /* Stash ERRSELR_EL1 in x2 */
+ mrs x2, ERRSELR_EL1
+
+ /* Select error record 0 and clear ED bit */
+ msr ERRSELR_EL1, xzr
+ mrs x1, ERXCTLR_EL1
+ bfi x1, xzr, #ERXCTLR_ED_SHIFT, #1
+ msr ERXCTLR_EL1, x1
- /* Apply instruction patching sequence */
+ /* Select error record 1 and clear ED bit */
+ mov x0, #1
+ msr ERRSELR_EL1, x0
+ mrs x1, ERXCTLR_EL1
+ bfi x1, xzr, #ERXCTLR_ED_SHIFT, #1
+ msr ERXCTLR_EL1, x1
+
+ /* Restore ERRSELR_EL1 from x2 */
+ msr ERRSELR_EL1, x2
+workaround_runtime_end cortex_a710, ERRATUM(2008768), NO_ISB
+
+check_erratum_ls cortex_a710, ERRATUM(2008768), CPU_REV(2, 0)
+
+workaround_reset_start cortex_a710, ERRATUM(2017096), ERRATA_A710_2017096
+ sysreg_bit_set CORTEX_A710_CPUECTLR_EL1, CORTEX_A710_CPUECTLR_EL1_PFSTIDIS_BIT
+workaround_reset_end cortex_a710, ERRATUM(2017096)
+
+check_erratum_ls cortex_a710, ERRATUM(2017096), CPU_REV(2, 0)
+
+workaround_reset_start cortex_a710, ERRATUM(2055002), ERRATA_A710_2055002
+ sysreg_bit_set CORTEX_A710_CPUACTLR_EL1, CORTEX_A710_CPUACTLR_EL1_BIT_46
+workaround_reset_end cortex_a710, ERRATUM(2055002)
+
+check_erratum_ls cortex_a710, ERRATUM(2055002), CPU_REV(2, 0)
+
+workaround_reset_start cortex_a710, ERRATUM(2058056), ERRATA_A710_2058056
+ sysreg_bitfield_insert CORTEX_A710_CPUECTLR2_EL1, CORTEX_A710_CPUECTLR2_EL1_PF_MODE_CNSRV, \
+ CPUECTLR2_EL1_PF_MODE_LSB, CPUECTLR2_EL1_PF_MODE_WIDTH
+workaround_reset_end cortex_a710, ERRATUM(2058056)
+
+check_erratum_ls cortex_a710, ERRATUM(2058056), CPU_REV(2, 0)
+
+workaround_reset_start cortex_a710, ERRATUM(2081180), ERRATA_A710_2081180
ldr x0,=0x3
msr S3_6_c15_c8_0,x0
ldr x0,=0xF3A08002
@@ -101,238 +106,30 @@
msr S3_6_c15_c8_3,x0
ldr x0,=0x10002001003F3
msr S3_6_c15_c8_1,x0
- isb
-1:
- ret x17
-endfunc errata_a710_2081180_wa
-
-func check_errata_2081180
- /* Applies to r0p0, r1p0 and r2p0 */
- mov x1, #0x20
- b cpu_rev_var_ls
-endfunc check_errata_2081180
-
-/* ---------------------------------------------------------------------
- * Errata Workaround for Cortex-A710 Erratum 2055002.
- * This applies to revision r1p0, r2p0 of Cortex-A710 and is still open.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ---------------------------------------------------------------------
- */
-func errata_a710_2055002_wa
- /* Compare x0 against revision r2p0 */
- mov x17, x30
- bl check_errata_2055002
- cbz x0, 1f
- mrs x1, CORTEX_A710_CPUACTLR_EL1
- orr x1, x1, CORTEX_A710_CPUACTLR_EL1_BIT_46
- msr CORTEX_A710_CPUACTLR_EL1, x1
-1:
- ret x17
-endfunc errata_a710_2055002_wa
-
-func check_errata_2055002
- /* Applies to r1p0, r2p0 */
- mov x1, #0x20
- b cpu_rev_var_ls
-endfunc check_errata_2055002
-
-/* -------------------------------------------------------------
- * Errata Workaround for Cortex-A710 Erratum 2017096.
- * This applies to revisions r0p0, r1p0 and r2p0 of Cortex-A710.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * -------------------------------------------------------------
- */
-func errata_a710_2017096_wa
- /* Compare x0 against revision r0p0 to r2p0 */
- mov x17, x30
- bl check_errata_2017096
- cbz x0, 1f
- mrs x1, CORTEX_A710_CPUECTLR_EL1
- orr x1, x1, CORTEX_A710_CPUECTLR_EL1_PFSTIDIS_BIT
- msr CORTEX_A710_CPUECTLR_EL1, x1
-
-1:
- ret x17
-endfunc errata_a710_2017096_wa
-
-func check_errata_2017096
- /* Applies to r0p0, r1p0, r2p0 */
- mov x1, #0x20
- b cpu_rev_var_ls
-endfunc check_errata_2017096
-
-
-/* ---------------------------------------------------------------------
- * Errata Workaround for Cortex-A710 Erratum 2083908.
- * This applies to revision r2p0 of Cortex-A710 and is still open.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ---------------------------------------------------------------------
- */
-func errata_a710_2083908_wa
- /* Compare x0 against revision r2p0 */
- mov x17, x30
- bl check_errata_2083908
- cbz x0, 1f
- mrs x1, CORTEX_A710_CPUACTLR5_EL1
- orr x1, x1, CORTEX_A710_CPUACTLR5_EL1_BIT_13
- msr CORTEX_A710_CPUACTLR5_EL1, x1
-1:
- ret x17
-endfunc errata_a710_2083908_wa
-
-func check_errata_2083908
- /* Applies to r2p0 */
- mov x1, #CPU_REV(2, 0)
- mov x2, #CPU_REV(2, 0)
- b cpu_rev_var_range
-endfunc check_errata_2083908
-
-/* ---------------------------------------------------------------------
- * Errata Workaround for Cortex-A710 Erratum 2058056.
- * This applies to revisions r0p0, r1p0 and r2p0 of Cortex-A710 and is still
- * open.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ---------------------------------------------------------------------
- */
-func errata_a710_2058056_wa
- /* Compare x0 against revision r2p0 */
- mov x17, x30
- bl check_errata_2058056
- cbz x0, 1f
- mrs x1, CORTEX_A710_CPUECTLR2_EL1
- mov x0, #CORTEX_A710_CPUECTLR2_EL1_PF_MODE_CNSRV
- bfi x1, x0, #CPUECTLR2_EL1_PF_MODE_LSB, #CPUECTLR2_EL1_PF_MODE_WIDTH
- msr CORTEX_A710_CPUECTLR2_EL1, x1
-1:
- ret x17
-endfunc errata_a710_2058056_wa
+workaround_reset_end cortex_a710, ERRATUM(2081180)
-func check_errata_2058056
- /* Applies to r0p0, r1p0 and r2p0 */
- mov x1, #0x20
- b cpu_rev_var_ls
-endfunc check_errata_2058056
+check_erratum_ls cortex_a710, ERRATUM(2081180), CPU_REV(2, 0)
-/* --------------------------------------------------
- * Errata Workaround for Cortex-A710 Erratum 2267065.
- * This applies to revisions r0p0, r1p0 and r2p0.
- * It is fixed in r2p1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x1, x17
- * --------------------------------------------------
- */
-func errata_a710_2267065_wa
- /* Compare x0 against revision r2p0 */
- mov x17, x30
- bl check_errata_2267065
- cbz x0, 1f
-
- /* Apply instruction patching sequence */
- mrs x1, CORTEX_A710_CPUACTLR_EL1
- orr x1, x1, CORTEX_A710_CPUACTLR_EL1_BIT_22
- msr CORTEX_A710_CPUACTLR_EL1, x1
-1:
- ret x17
-endfunc errata_a710_2267065_wa
+workaround_reset_start cortex_a710, ERRATUM(2083908), ERRATA_A710_2083908
+ sysreg_bit_set CORTEX_A710_CPUACTLR5_EL1, CORTEX_A710_CPUACTLR5_EL1_BIT_13
+workaround_reset_end cortex_a710, ERRATUM(2083908)
-func check_errata_2267065
- /* Applies to r0p0, r1p0 and r2p0 */
- mov x1, #0x20
- b cpu_rev_var_ls
-endfunc check_errata_2267065
+check_erratum_range cortex_a710, ERRATUM(2083908), CPU_REV(2, 0), CPU_REV(2, 0)
-/* ---------------------------------------------------------------
- * Errata Workaround for Cortex-A710 Erratum 2136059.
- * This applies to revision r0p0, r1p0 and r2p0.
- * It is fixed in r2p1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ---------------------------------------------------------------
- */
-func errata_a710_2136059_wa
- /* Compare x0 against revision r2p0 */
- mov x17, x30
- bl check_errata_2136059
- cbz x0, 1f
+workaround_reset_start cortex_a710, ERRATUM(2136059), ERRATA_A710_2136059
+ sysreg_bit_set CORTEX_A710_CPUACTLR5_EL1, CORTEX_A710_CPUACTLR5_EL1_BIT_44
+workaround_reset_end cortex_a710, ERRATUM(2136059)
- /* Apply the workaround */
- mrs x1, CORTEX_A710_CPUACTLR5_EL1
- orr x1, x1, CORTEX_A710_CPUACTLR5_EL1_BIT_44
- msr CORTEX_A710_CPUACTLR5_EL1, x1
+check_erratum_ls cortex_a710, ERRATUM(2136059), CPU_REV(2, 0)
-1:
- ret x17
-endfunc errata_a710_2136059_wa
+workaround_reset_start cortex_a710, ERRATUM(2147715), ERRATA_A710_2147715
+ sysreg_bit_set CORTEX_A710_CPUACTLR_EL1, CORTEX_A710_CPUACTLR_EL1_BIT_22
+workaround_reset_end cortex_a710, ERRATUM(2147715)
-func check_errata_2136059
- /* Applies to r0p0, r1p0 and r2p0 */
- mov x1, #0x20
- b cpu_rev_var_ls
-endfunc check_errata_2136059
+check_erratum_range cortex_a710, ERRATUM(2147715), CPU_REV(2, 0), CPU_REV(2, 0)
-/* ----------------------------------------------------------------
- * Errata workaround for Cortex-A710 Erratum 2147715.
- * This applies to revision r2p0, and is fixed in r2p1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x17
- * ----------------------------------------------------------------
- */
-func errata_a710_2147715_wa
- mov x17, x30
- bl check_errata_2147715
- cbz x0, 1f
-
- /* Apply workaround; set CPUACTLR_EL1[22]
- * to 1, which will cause the CFP instruction
- * to invalidate all branch predictor resources
- * regardless of context.
- */
- mrs x1, CORTEX_A710_CPUACTLR_EL1
- orr x1, x1, CORTEX_A710_CPUACTLR_EL1_BIT_22
- msr CORTEX_A710_CPUACTLR_EL1, x1
-1:
- ret x17
-endfunc errata_a710_2147715_wa
-
-func check_errata_2147715
- mov x1, #0x20
- mov x2, #0x20
- b cpu_rev_var_range
-endfunc check_errata_2147715
-
-/* ---------------------------------------------------------------
- * Errata Workaround for Cortex-A710 Erratum 2216384.
- * This applies to revision r0p0, r1p0 and r2p0.
- * It is fixed in r2p1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ---------------------------------------------------------------
- */
-func errata_a710_2216384_wa
- /* Compare x0 against revision r2p0 */
- mov x17, x30
- bl check_errata_2216384
- cbz x0, 1f
-
- /* Apply workaround: set CPUACTLR5_EL1[17]
- * to 1 and the following instruction
- * patching sequence.
- */
- mrs x1, CORTEX_A710_CPUACTLR5_EL1
- orr x1, x1, CORTEX_A710_CPUACTLR5_EL1_BIT_17
- msr CORTEX_A710_CPUACTLR5_EL1, x1
+workaround_reset_start cortex_a710, ERRATUM(2216384), ERRATA_A710_2216384
+ sysreg_bit_set CORTEX_A710_CPUACTLR5_EL1, CORTEX_A710_CPUACTLR5_EL1_BIT_17
ldr x0,=0x5
msr CORTEX_A710_CPUPSELR_EL3, x0
@@ -342,338 +139,88 @@
msr CORTEX_A710_CPUPMR_EL3, x0
ldr x0,=0x80000000003FF
msr CORTEX_A710_CPUPCR_EL3, x0
- isb
-1:
- ret x17
-endfunc errata_a710_2216384_wa
+workaround_reset_end cortex_a710, ERRATUM(2216384)
-func check_errata_2216384
- /* Applies to r0p0, r1p0 and r2p0 */
- mov x1, #0x20
- b cpu_rev_var_ls
-endfunc check_errata_2216384
+check_erratum_ls cortex_a710, ERRATUM(2216384), CPU_REV(2, 0)
-/* ---------------------------------------------------------------
- * Errata Workaround for Cortex-A710 Erratum 2282622.
- * This applies to revision r0p0, r1p0, r2p0 and r2p1.
- * It is still open.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x17
- * ---------------------------------------------------------------
- */
-func errata_a710_2282622_wa
- /* Compare x0 against revision r2p1 */
- mov x17, x30
- bl check_errata_2282622
- cbz x0, 1f
+workaround_reset_start cortex_a710, ERRATUM(2267065), ERRATA_A710_2267065
+ sysreg_bit_set CORTEX_A710_CPUACTLR_EL1, CORTEX_A710_CPUACTLR_EL1_BIT_22
+workaround_reset_end cortex_a710, ERRATUM(2267065)
- /* Apply the workaround */
- mrs x1, CORTEX_A710_CPUACTLR2_EL1
- orr x1, x1, #BIT(0)
- msr CORTEX_A710_CPUACTLR2_EL1, x1
+check_erratum_ls cortex_a710, ERRATUM(2267065), CPU_REV(2, 0)
-1:
- ret x17
-endfunc errata_a710_2282622_wa
+workaround_reset_start cortex_a710, ERRATUM(2282622), ERRATA_A710_2282622
+ sysreg_bit_set CORTEX_A710_CPUACTLR2_EL1, BIT(0)
+workaround_reset_end cortex_a710, ERRATUM(2282622)
-func check_errata_2282622
- /* Applies to r0p0, r1p0, r2p0 and r2p1 */
- mov x1, #0x21
- b cpu_rev_var_ls
-endfunc check_errata_2282622
+check_erratum_ls cortex_a710, ERRATUM(2282622), CPU_REV(2, 1)
-/* ------------------------------------------------------------------------
- * Errata Workaround for Cortex-A710 Erratum 2291219 on power down request.
- * This applies to revision <= r2p0 and is fixed in r2p1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x1, x17
- * ------------------------------------------------------------------------
- */
-func errata_a710_2291219_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_2291219
- cbz x0, 1f
-
+workaround_runtime_start cortex_a710, ERRATUM(2291219), ERRATA_A710_2291219
/* Set bit 36 in ACTLR2_EL1 */
- mrs x1, CORTEX_A710_CPUACTLR2_EL1
- orr x1, x1, #CORTEX_A710_CPUACTLR2_EL1_BIT_36
- msr CORTEX_A710_CPUACTLR2_EL1, x1
-1:
- ret x17
-endfunc errata_a710_2291219_wa
+ sysreg_bit_set CORTEX_A710_CPUACTLR2_EL1, CORTEX_A710_CPUACTLR2_EL1_BIT_36
+workaround_runtime_end cortex_a710, ERRATUM(2291219), NO_ISB
-func check_errata_2291219
- /* Applies to <= r2p0. */
- mov x1, #0x20
- b cpu_rev_var_ls
-endfunc check_errata_2291219
+check_erratum_ls cortex_a710, ERRATUM(2291219), CPU_REV(2, 0)
-/* ---------------------------------------------------------------
- * Errata Workaround for Cortex-A710 Erratum 2008768.
- * This applies to revision r0p0, r1p0 and r2p0.
- * It is fixed in r2p1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x2, x17
- * ---------------------------------------------------------------
+/*
+ * ERRATA_DSU_2313941 is defined in dsu_helpers.S but applies to Cortex-A710 as
+ * well. Create a symbollic link to existing errata workaround to get them
+ * registered under the Errata Framework.
*/
-func errata_a710_2008768_wa
- mov x17, x30
- bl check_errata_2008768
- cbz x0, 1f
-
- /* Stash ERRSELR_EL1 in x2 */
- mrs x2, ERRSELR_EL1
+.equ check_erratum_cortex_a710_2313941, check_errata_dsu_2313941
+.equ erratum_cortex_a710_2313941_wa, errata_dsu_2313941_wa
+add_erratum_entry cortex_a710, ERRATUM(2313941), ERRATA_DSU_2313941, APPLY_AT_RESET
- /* Select error record 0 and clear ED bit */
- msr ERRSELR_EL1, xzr
- mrs x1, ERXCTLR_EL1
- bfi x1, xzr, #ERXCTLR_ED_SHIFT, #1
- msr ERXCTLR_EL1, x1
-
- /* Select error record 1 and clear ED bit */
- mov x0, #1
- msr ERRSELR_EL1, x0
- mrs x1, ERXCTLR_EL1
- bfi x1, xzr, #ERXCTLR_ED_SHIFT, #1
- msr ERXCTLR_EL1, x1
-
- /* Restore ERRSELR_EL1 from x2 */
- msr ERRSELR_EL1, x2
-
-1:
- ret x17
-endfunc errata_a710_2008768_wa
-
-func check_errata_2008768
- /* Applies to r0p0, r1p0 and r2p0 */
- mov x1, #0x20
- b cpu_rev_var_ls
-endfunc check_errata_2008768
-
-/* -------------------------------------------------------
- * Errata Workaround for Cortex-A710 Erratum 2371105.
- * This applies to revisions <= r2p0 and is fixed in r2p1.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * -------------------------------------------------------
- */
-func errata_a710_2371105_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_2371105
- cbz x0, 1f
-
+workaround_reset_start cortex_a710, ERRATUM(2371105), ERRATA_A710_2371105
/* Set bit 40 in CPUACTLR2_EL1 */
- mrs x1, CORTEX_A710_CPUACTLR2_EL1
- orr x1, x1, #CORTEX_A710_CPUACTLR2_EL1_BIT_40
- msr CORTEX_A710_CPUACTLR2_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_a710_2371105_wa
+ sysreg_bit_set CORTEX_A710_CPUACTLR2_EL1, CORTEX_A710_CPUACTLR2_EL1_BIT_40
+workaround_reset_end cortex_a710, ERRATUM(2371105)
-func check_errata_2371105
- /* Applies to <= r2p0. */
- mov x1, #0x20
- b cpu_rev_var_ls
-endfunc check_errata_2371105
+check_erratum_ls cortex_a710, ERRATUM(2371105), CPU_REV(2, 0)
-/* ----------------------------------------------------
- * Errata Workaround for Cortex-A710 Errata #2768515
- * This applies to revisions <= r2p1 and is still open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ----------------------------------------------------
- */
-func errata_a710_2768515_wa
- mov x17, x30
- bl check_errata_2768515
- cbz x0, 1f
-
+workaround_runtime_start cortex_a710, ERRATUM(2768515), ERRATA_A710_2768515
/* dsb before isb of power down sequence */
dsb sy
-1:
- ret x17
-endfunc errata_a710_2768515_wa
+workaround_runtime_end cortex_a710, ERRATUM(2768515), NO_ISB
-func check_errata_2768515
- /* Applies to all revisions <= r2p1 */
- mov x1, #0x21
- b cpu_rev_var_ls
-endfunc check_errata_2768515
+check_erratum_ls cortex_a710, ERRATUM(2768515), CPU_REV(2, 1)
-func check_errata_cve_2022_23960
-#if WORKAROUND_CVE_2022_23960
- mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
-#endif
- ret
-endfunc check_errata_cve_2022_23960
+workaround_reset_start cortex_a710, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
+#if IMAGE_BL31
+ /*
+ * The Cortex-A710 generic vectors are overridden to apply errata
+ * mitigation on exception entry from lower ELs.
+ */
+ override_vector_table wa_cve_vbar_cortex_a710
+#endif /* IMAGE_BL31 */
+workaround_reset_end cortex_a710, CVE(2022, 23960)
+
+check_erratum_chosen cortex_a710, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
/* ----------------------------------------------------
* HW will do the cache maintenance while powering down
* ----------------------------------------------------
*/
func cortex_a710_core_pwr_dwn
-
-#if ERRATA_A710_2008768
- mov x4, x30
- bl cpu_get_rev_var
- bl errata_a710_2008768_wa
- mov x30, x4
-#endif
-
-#if ERRATA_A710_2291219
- mov x15, x30
- bl cpu_get_rev_var
- bl errata_a710_2291219_wa
- mov x30, x15
-#endif /* ERRATA_A710_2291219 */
+ apply_erratum cortex_a710, ERRATUM(2008768), ERRATA_A710_2008768
+ apply_erratum cortex_a710, ERRATUM(2291219), ERRATA_A710_2291219, NO_GET_CPU_REV
/* ---------------------------------------------------
* Enable CPU power down bit in power control register
* ---------------------------------------------------
*/
- mrs x0, CORTEX_A710_CPUPWRCTLR_EL1
- orr x0, x0, #CORTEX_A710_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
- msr CORTEX_A710_CPUPWRCTLR_EL1, x0
-#if ERRATA_A710_2768515
- mov x15, x30
- bl cpu_get_rev_var
- bl errata_a710_2768515_wa
- mov x30, x15
-#endif /* ERRATA_A710_2768515 */
+ sysreg_bit_set CORTEX_A710_CPUPWRCTLR_EL1, CORTEX_A710_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
+ apply_erratum cortex_a710, ERRATUM(2768515), ERRATA_A710_2768515, NO_GET_CPU_REV
isb
ret
endfunc cortex_a710_core_pwr_dwn
-#if REPORT_ERRATA
- /*
- * Errata printing function for Cortex-A710. Must follow AAPCS.
- */
-func cortex_a710_errata_report
- stp x8, x30, [sp, #-16]!
-
- bl cpu_get_rev_var
- mov x8, x0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata ERRATA_A710_1987031, cortex_a710, 1987031
- report_errata ERRATA_A710_2081180, cortex_a710, 2081180
- report_errata ERRATA_A710_2055002, cortex_a710, 2055002
- report_errata ERRATA_A710_2017096, cortex_a710, 2017096
- report_errata ERRATA_A710_2083908, cortex_a710, 2083908
- report_errata ERRATA_A710_2058056, cortex_a710, 2058056
- report_errata ERRATA_A710_2267065, cortex_a710, 2267065
- report_errata ERRATA_A710_2136059, cortex_a710, 2136059
- report_errata ERRATA_A710_2282622, cortex_a710, 2282622
- report_errata ERRATA_A710_2008768, cortex_a710, 2008768
- report_errata ERRATA_A710_2147715, cortex_a710, 2147715
- report_errata ERRATA_A710_2216384, cortex_a710, 2216384
- report_errata ERRATA_A710_2291219, cortex_a710, 2291219
- report_errata ERRATA_A710_2371105, cortex_a710, 2371105
- report_errata ERRATA_A710_2768515, cortex_a710, 2768515
- report_errata WORKAROUND_CVE_2022_23960, cortex_a710, cve_2022_23960
- report_errata ERRATA_DSU_2313941, cortex_a710, dsu_2313941
-
- ldp x8, x30, [sp], #16
- ret
-endfunc cortex_a710_errata_report
-#endif
+errata_report_shim cortex_a710
-func cortex_a710_reset_func
- mov x19, x30
-
+cpu_reset_func_start cortex_a710
/* Disable speculative loads */
msr SSBS, xzr
-
- bl cpu_get_rev_var
- mov x18, x0
-
-#if ERRATA_DSU_2313941
- bl errata_dsu_2313941_wa
-#endif
-
-#if ERRATA_A710_1987031
- mov x0, x18
- bl errata_a710_1987031_wa
-#endif
-
-#if ERRATA_A710_2081180
- mov x0, x18
- bl errata_a710_2081180_wa
-#endif
-
-#if ERRATA_A710_2055002
- mov x0, x18
- bl errata_a710_2055002_wa
-#endif
-
-#if ERRATA_A710_2017096
- mov x0, x18
- bl errata_a710_2017096_wa
-#endif
-
-#if ERRATA_A710_2083908
- mov x0, x18
- bl errata_a710_2083908_wa
-#endif
-
-#if ERRATA_A710_2058056
- mov x0, x18
- bl errata_a710_2058056_wa
-#endif
-
-#if ERRATA_A710_2267065
- mov x0, x18
- bl errata_a710_2267065_wa
-#endif
-
-#if ERRATA_A710_2136059
- mov x0, x18
- bl errata_a710_2136059_wa
-#endif
-
-#if ERRATA_A710_2147715
- mov x0, x18
- bl errata_a710_2147715_wa
-#endif
-
-#if ERRATA_A710_2216384
- mov x0, x18
- bl errata_a710_2216384_wa
-#endif /* ERRATA_A710_2216384 */
-
-#if ERRATA_A710_2282622
- mov x0, x18
- bl errata_a710_2282622_wa
-#endif
-
-#if ERRATA_A710_2371105
- mov x0, x18
- bl errata_a710_2371105_wa
-#endif
-
-#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
- /*
- * The Cortex-A710 generic vectors are overridden to apply errata
- * mitigation on exception entry from lower ELs.
- */
- adr x0, wa_cve_vbar_cortex_a710
- msr vbar_el3, x0
-#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
-
- isb
- ret x19
-endfunc cortex_a710_reset_func
+cpu_reset_func_end cortex_a710
/* ---------------------------------------------
* This function provides Cortex-A710 specific
diff --git a/lib/cpus/aarch64/cortex_a73.S b/lib/cpus/aarch64/cortex_a73.S
index edcd1f5..3a6b922 100644
--- a/lib/cpus/aarch64/cortex_a73.S
+++ b/lib/cpus/aarch64/cortex_a73.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -15,9 +15,7 @@
* ---------------------------------------------
*/
func cortex_a73_disable_dcache
- mrs x1, sctlr_el3
- bic x1, x1, #SCTLR_C_BIT
- msr sctlr_el3, x1
+ sysreg_bit_clear sctlr_el3, SCTLR_C_BIT
isb
ret
endfunc cortex_a73_disable_dcache
@@ -27,124 +25,97 @@
* ---------------------------------------------
*/
func cortex_a73_disable_smp
- mrs x0, CORTEX_A73_CPUECTLR_EL1
- bic x0, x0, #CORTEX_A73_CPUECTLR_SMP_BIT
- msr CORTEX_A73_CPUECTLR_EL1, x0
+ sysreg_bit_clear CORTEX_A73_CPUECTLR_EL1, CORTEX_A73_CPUECTLR_SMP_BIT
isb
dsb sy
ret
endfunc cortex_a73_disable_smp
- /* ---------------------------------------------------
- * Errata Workaround for Cortex A73 Errata #852427.
- * This applies only to revision r0p0 of Cortex A73.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ---------------------------------------------------
- */
-func errata_a73_852427_wa
- /*
- * Compare x0 against revision r0p0
- */
- mov x17, x30
- bl check_errata_852427
- cbz x0, 1f
- mrs x1, CORTEX_A73_DIAGNOSTIC_REGISTER
- orr x1, x1, #(1 << 12)
- msr CORTEX_A73_DIAGNOSTIC_REGISTER, x1
- isb
-1:
- ret x17
-endfunc errata_a73_852427_wa
+func check_smccc_arch_workaround_3
+ mov x0, #ERRATA_APPLIES
+ ret
+endfunc check_smccc_arch_workaround_3
-func check_errata_852427
- mov x1, #0x00
- b cpu_rev_var_ls
-endfunc check_errata_852427
+workaround_reset_start cortex_a73, ERRATUM(852427), ERRATA_A73_852427
+ sysreg_bit_set CORTEX_A73_DIAGNOSTIC_REGISTER, BIT(12)
+workaround_reset_end cortex_a73, ERRATUM(852427)
- /* ---------------------------------------------------
- * Errata Workaround for Cortex A73 Errata #855423.
- * This applies only to revision <= r0p1 of Cortex A73.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ---------------------------------------------------
- */
-func errata_a73_855423_wa
- /*
- * Compare x0 against revision r0p1
- */
- mov x17, x30
- bl check_errata_855423
- cbz x0, 1f
- mrs x1, CORTEX_A73_IMP_DEF_REG2
- orr x1, x1, #(1 << 7)
- msr CORTEX_A73_IMP_DEF_REG2, x1
- isb
-1:
- ret x17
-endfunc errata_a73_855423_wa
+check_erratum_ls cortex_a73, ERRATUM(852427), CPU_REV(0, 0)
-func check_errata_855423
- mov x1, #0x01
- b cpu_rev_var_ls
-endfunc check_errata_855423
+workaround_reset_start cortex_a73, ERRATUM(855423), ERRATA_A73_855423
+ sysreg_bit_set CORTEX_A73_IMP_DEF_REG2, BIT(7)
+workaround_reset_end cortex_a73, ERRATUM(855423)
- /* -------------------------------------------------
- * The CPU Ops reset function for Cortex-A73.
- * -------------------------------------------------
- */
+check_erratum_ls cortex_a73, ERRATUM(855423), CPU_REV(0, 1)
-func cortex_a73_reset_func
- mov x19, x30
- bl cpu_get_rev_var
- mov x18, x0
+workaround_reset_start cortex_a73, CVE(2017, 5715), WORKAROUND_CVE_2017_5715
+#if IMAGE_BL31
+ override_vector_table wa_cve_2017_5715_bpiall_vbar
+#endif /* IMAGE_BL31 */
+workaround_reset_end cortex_a73, CVE(2017, 5715)
-#if ERRATA_A73_852427
- mov x0, x18
- bl errata_a73_852427_wa
+check_erratum_custom_start cortex_a73, CVE(2017, 5715)
+ cpu_check_csv2 x0, 1f
+#if WORKAROUND_CVE_2017_5715
+ mov x0, #ERRATA_APPLIES
+#else
+ mov x0, #ERRATA_MISSING
#endif
+ ret
+1:
+ mov x0, #ERRATA_NOT_APPLIES
+ ret
+check_erratum_custom_end cortex_a73, CVE(2017, 5715)
-#if ERRATA_A73_855423
- mov x0, x18
- bl errata_a73_855423_wa
-#endif
+workaround_reset_start cortex_a73, CVE(2018, 3639), WORKAROUND_CVE_2018_3639
+ sysreg_bit_set CORTEX_A73_IMP_DEF_REG1, CORTEX_A73_IMP_DEF_REG1_DISABLE_LOAD_PASS_STORE
+workaround_reset_end cortex_a73, CVE(2018, 3639)
-#if IMAGE_BL31 && (WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960)
- cpu_check_csv2 x0, 1f
- adr x0, wa_cve_2017_5715_bpiall_vbar
- msr vbar_el3, x0
- isb
+check_erratum_chosen cortex_a73, CVE(2018, 3639), WORKAROUND_CVE_2018_3639
+
+workaround_reset_start cortex_a73, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
+#if IMAGE_BL31
/* Skip installing vector table again for CVE_2022_23960 */
- b 2f
+ adr x0, wa_cve_2017_5715_bpiall_vbar
+ mrs x1, vbar_el3
+
+ cmp x0, x1
+ b.eq 1f
+ msr vbar_el3, x0
1:
+#endif /* IMAGE_BL31 */
+workaround_reset_end cortex_a73, CVE(2022, 23960)
+
+check_erratum_custom_start cortex_a73, CVE(2022, 23960)
+#if WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960
+ cpu_check_csv2 x0, 1f
+ mov x0, #ERRATA_APPLIES
+ ret
+ 1:
#if WORKAROUND_CVE_2022_23960
- adr x0, wa_cve_2017_5715_bpiall_vbar
- msr vbar_el3, x0
- isb
-#endif
-2:
-#endif /* IMAGE_BL31 && (WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960) */
+ mov x0, #ERRATA_APPLIES
+#else
+ mov x0, #ERRATA_MISSING
+#endif /* WORKAROUND_CVE_2022_23960 */
+ ret
+#endif /* WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 */
+ mov x0, #ERRATA_MISSING
+ ret
+check_erratum_custom_end cortex_a73, CVE(2022, 23960)
-#if WORKAROUND_CVE_2018_3639
- mrs x0, CORTEX_A73_IMP_DEF_REG1
- orr x0, x0, #CORTEX_A73_IMP_DEF_REG1_DISABLE_LOAD_PASS_STORE
- msr CORTEX_A73_IMP_DEF_REG1, x0
- isb
-#endif
+ /* -------------------------------------------------
+ * The CPU Ops reset function for Cortex-A73.
+ * -------------------------------------------------
+ */
+cpu_reset_func_start cortex_a73
/* ---------------------------------------------
* Enable the SMP bit.
* Clobbers : x0
* ---------------------------------------------
*/
- mrs x0, CORTEX_A73_CPUECTLR_EL1
- orr x0, x0, #CORTEX_A73_CPUECTLR_SMP_BIT
- msr CORTEX_A73_CPUECTLR_EL1, x0
- isb
- ret x19
-endfunc cortex_a73_reset_func
+ sysreg_bit_set CORTEX_A73_CPUECTLR_EL1, CORTEX_A73_CPUECTLR_SMP_BIT
+cpu_reset_func_end cortex_a73
func cortex_a73_core_pwr_dwn
mov x18, x30
@@ -207,74 +178,8 @@
b cortex_a73_disable_smp
endfunc cortex_a73_cluster_pwr_dwn
-func check_errata_cve_2017_5715
- cpu_check_csv2 x0, 1f
-#if WORKAROUND_CVE_2017_5715
- mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
-#endif
- ret
-1:
- mov x0, #ERRATA_NOT_APPLIES
- ret
-endfunc check_errata_cve_2017_5715
-
-func check_errata_cve_2018_3639
-#if WORKAROUND_CVE_2018_3639
- mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
-#endif
- ret
-endfunc check_errata_cve_2018_3639
-func check_errata_cve_2022_23960
-#if WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960
- cpu_check_csv2 x0, 1f
- mov x0, #ERRATA_APPLIES
- ret
- 1:
-# if WORKAROUND_CVE_2022_23960
- mov x0, #ERRATA_APPLIES
-# else
- mov x0, #ERRATA_MISSING
-# endif /* WORKAROUND_CVE_2022_23960 */
- ret
-#endif /* WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 */
- mov x0, #ERRATA_MISSING
- ret
-endfunc check_errata_cve_2022_23960
-
-func check_smccc_arch_workaround_3
- mov x0, #ERRATA_APPLIES
- ret
-endfunc check_smccc_arch_workaround_3
-
-#if REPORT_ERRATA
-/*
- * Errata printing function for Cortex A75. Must follow AAPCS.
- */
-func cortex_a73_errata_report
- stp x8, x30, [sp, #-16]!
-
- bl cpu_get_rev_var
- mov x8, x0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata ERRATA_A73_852427, cortex_a73, 852427
- report_errata ERRATA_A73_855423, cortex_a73, 855423
- report_errata WORKAROUND_CVE_2017_5715, cortex_a73, cve_2017_5715
- report_errata WORKAROUND_CVE_2018_3639, cortex_a73, cve_2018_3639
- report_errata WORKAROUND_CVE_2022_23960, cortex_a73, cve_2022_23960
-
- ldp x8, x30, [sp], #16
- ret
-endfunc cortex_a73_errata_report
-#endif
+errata_report_shim cortex_a73
/* ---------------------------------------------
* This function provides cortex_a73 specific
@@ -298,7 +203,7 @@
declare_cpu_ops_wa cortex_a73, CORTEX_A73_MIDR, \
cortex_a73_reset_func, \
- check_errata_cve_2017_5715, \
+ check_erratum_cortex_a73_5715, \
CPU_NO_EXTRA2_FUNC, \
check_smccc_arch_workaround_3, \
cortex_a73_core_pwr_dwn, \
diff --git a/lib/cpus/aarch64/cortex_a75.S b/lib/cpus/aarch64/cortex_a75.S
index 0a7b9fb..c90be67 100644
--- a/lib/cpus/aarch64/cortex_a75.S
+++ b/lib/cpus/aarch64/cortex_a75.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/cpus/aarch64/cortex_a75_pubsub.c b/lib/cpus/aarch64/cortex_a75_pubsub.c
index bd2c697..11190c8 100644
--- a/lib/cpus/aarch64/cortex_a75_pubsub.c
+++ b/lib/cpus/aarch64/cortex_a75_pubsub.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2018, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/cpus/aarch64/cortex_a76.S b/lib/cpus/aarch64/cortex_a76.S
index 36507de..8b3d730 100644
--- a/lib/cpus/aarch64/cortex_a76.S
+++ b/lib/cpus/aarch64/cortex_a76.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -298,154 +298,50 @@
endfunc apply_cve_2018_3639_sync_wa
#endif /* DYNAMIC_WORKAROUND_CVE_2018_3639 */
- /* --------------------------------------------------
- * Errata Workaround for Cortex A76 Errata #1073348.
- * This applies only to revision <= r1p0 of Cortex A76.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a76_1073348_wa
- /*
- * Compare x0 against revision r1p0
- */
- mov x17, x30
- bl check_errata_1073348
- cbz x0, 1f
- mrs x1, CORTEX_A76_CPUACTLR_EL1
- orr x1, x1 ,#CORTEX_A76_CPUACTLR_EL1_DISABLE_STATIC_PREDICTION
- msr CORTEX_A76_CPUACTLR_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_a76_1073348_wa
+workaround_reset_start cortex_a76, ERRATUM(1073348), ERRATA_A76_1073348
+ sysreg_bit_set CORTEX_A76_CPUACTLR_EL1 ,CORTEX_A76_CPUACTLR_EL1_DISABLE_STATIC_PREDICTION
+workaround_reset_end cortex_a76, ERRATUM(1073348)
-func check_errata_1073348
- mov x1, #0x10
- b cpu_rev_var_ls
-endfunc check_errata_1073348
+check_erratum_ls cortex_a76, ERRATUM(1073348), CPU_REV(1, 0)
- /* --------------------------------------------------
- * Errata Workaround for Cortex A76 Errata #1130799.
- * This applies only to revision <= r2p0 of Cortex A76.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a76_1130799_wa
- /*
- * Compare x0 against revision r2p0
- */
- mov x17, x30
- bl check_errata_1130799
- cbz x0, 1f
- mrs x1, CORTEX_A76_CPUACTLR2_EL1
- orr x1, x1 ,#(1 << 59)
+workaround_reset_start cortex_a76, ERRATUM(1130799), ERRATA_A76_1130799
+ sysreg_bit_set CORTEX_A76_CPUACTLR2_EL1, CORTEX_A76_CPUACTLR2_EL1_BIT_59
msr CORTEX_A76_CPUACTLR2_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_a76_1130799_wa
+workaround_reset_end cortex_a76, ERRATUM(1130799)
-func check_errata_1130799
- mov x1, #0x20
- b cpu_rev_var_ls
-endfunc check_errata_1130799
+check_erratum_ls cortex_a76, ERRATUM(1130799), CPU_REV(2, 0)
- /* --------------------------------------------------
- * Errata Workaround for Cortex A76 Errata #1220197.
- * This applies only to revision <= r2p0 of Cortex A76.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a76_1220197_wa
-/*
- * Compare x0 against revision r2p0
- */
- mov x17, x30
- bl check_errata_1220197
- cbz x0, 1f
- mrs x1, CORTEX_A76_CPUECTLR_EL1
- orr x1, x1, #CORTEX_A76_CPUECTLR_EL1_WS_THR_L2
- msr CORTEX_A76_CPUECTLR_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_a76_1220197_wa
+workaround_reset_start cortex_a76, ERRATUM(1220197), ERRATA_A76_1220197
+ sysreg_bit_set CORTEX_A76_CPUECTLR_EL1, CORTEX_A76_CPUECTLR_EL1_WS_THR_L2
+workaround_reset_end cortex_a76, ERRATUM(1220197)
-func check_errata_1220197
- mov x1, #0x20
- b cpu_rev_var_ls
-endfunc check_errata_1220197
+check_erratum_ls cortex_a76, ERRATUM(1220197), CPU_REV(2, 0)
- /* --------------------------------------------------
- * Errata Workaround for Cortex A76 Errata #1257314.
- * This applies only to revision <= r3p0 of Cortex A76.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a76_1257314_wa
- /*
- * Compare x0 against revision r3p0
- */
- mov x17, x30
- bl check_errata_1257314
- cbz x0, 1f
- mrs x1, CORTEX_A76_CPUACTLR3_EL1
- orr x1, x1, CORTEX_A76_CPUACTLR3_EL1_BIT_10
- msr CORTEX_A76_CPUACTLR3_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_a76_1257314_wa
+workaround_reset_start cortex_a76, ERRATUM(1257314), ERRATA_A76_1257314
+ sysreg_bit_set CORTEX_A76_CPUACTLR3_EL1, CORTEX_A76_CPUACTLR3_EL1_BIT_10
+workaround_reset_end cortex_a76, ERRATUM(1257314)
-func check_errata_1257314
- mov x1, #0x30
- b cpu_rev_var_ls
-endfunc check_errata_1257314
+check_erratum_ls cortex_a76, ERRATUM(1257314), CPU_REV(3, 0)
- /* --------------------------------------------------
- * Errata Workaround for Cortex A76 Errata #1262888.
- * This applies only to revision <= r3p0 of Cortex A76.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a76_1262888_wa
- /*
- * Compare x0 against revision r3p0
- */
- mov x17, x30
- bl check_errata_1262888
- cbz x0, 1f
- mrs x1, CORTEX_A76_CPUECTLR_EL1
- orr x1, x1, CORTEX_A76_CPUECTLR_EL1_BIT_51
- msr CORTEX_A76_CPUECTLR_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_a76_1262888_wa
+workaround_reset_start cortex_a76, ERRATUM(1262606), ERRATA_A76_1262606
+ sysreg_bit_set CORTEX_A76_CPUACTLR_EL1, CORTEX_A76_CPUACTLR_EL1_BIT_13
+workaround_reset_end cortex_a76, ERRATUM(1262606)
-func check_errata_1262888
- mov x1, #0x30
- b cpu_rev_var_ls
-endfunc check_errata_1262888
+check_erratum_ls cortex_a76, ERRATUM(1262606), CPU_REV(3, 0)
- /* ---------------------------------------------------
- * Errata Workaround for Cortex A76 Errata #1286807.
- * This applies only to revision <= r3p0 of Cortex A76.
- * Due to the nature of the errata it is applied unconditionally
- * when built in, report it as applicable in this case
- * ---------------------------------------------------
- */
-func check_errata_1286807
+workaround_reset_start cortex_a76, ERRATUM(1262888), ERRATA_A76_1262888
+ sysreg_bit_set CORTEX_A76_CPUECTLR_EL1, CORTEX_A76_CPUECTLR_EL1_BIT_51
+workaround_reset_end cortex_a76, ERRATUM(1262888)
+
+check_erratum_ls cortex_a76, ERRATUM(1262888), CPU_REV(3, 0)
+
+workaround_reset_start cortex_a76, ERRATUM(1275112), ERRATA_A76_1275112
+ sysreg_bit_set CORTEX_A76_CPUACTLR_EL1, CORTEX_A76_CPUACTLR_EL1_BIT_13
+workaround_reset_end cortex_a76, ERRATUM(1275112)
+
+check_erratum_ls cortex_a76, ERRATUM(1275112), CPU_REV(3, 0)
+
+check_erratum_custom_start cortex_a76, ERRATUM(1286807)
#if ERRATA_A76_1286807
mov x0, #ERRATA_APPLIES
ret
@@ -453,100 +349,21 @@
mov x1, #0x30
b cpu_rev_var_ls
#endif
-endfunc check_errata_1286807
-
- /* --------------------------------------------------
- * Errata workaround for Cortex A76 Errata #1791580.
- * This applies to revisions <= r4p0 of Cortex A76.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a76_1791580_wa
- /* Compare x0 against revision r4p0 */
- mov x17, x30
- bl check_errata_1791580
- cbz x0, 1f
- mrs x1, CORTEX_A76_CPUACTLR2_EL1
- orr x1, x1, CORTEX_A76_CPUACTLR2_EL1_BIT_2
- msr CORTEX_A76_CPUACTLR2_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_a76_1791580_wa
-
-func check_errata_1791580
- /* Applies to everything <=r4p0. */
- mov x1, #0x40
- b cpu_rev_var_ls
-endfunc check_errata_1791580
-
- /* --------------------------------------------------
- * Errata Workaround for Cortex A76 Errata #1262606,
- * #1275112, and #1868343. #1262606 and #1275112
- * apply to revisions <= r3p0 and #1868343 applies to
- * revisions <= r4p0.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
+check_erratum_custom_end cortex_a76, ERRATUM(1286807)
-func errata_a76_1262606_1275112_1868343_wa
- mov x17, x30
+workaround_reset_start cortex_a76, ERRATUM(1791580), ERRATA_A76_1791580
+ sysreg_bit_set CORTEX_A76_CPUACTLR2_EL1, CORTEX_A76_CPUACTLR2_EL1_BIT_2
+workaround_reset_end cortex_a76, ERRATUM(1791580)
-/* Check for <= r3p0 cases and branch if check passes. */
-#if ERRATA_A76_1262606 || ERRATA_A76_1275112
- bl check_errata_1262606
- cbnz x0, 1f
-#endif
-
-/* Check for <= r4p0 cases and branch if check fails. */
-#if ERRATA_A76_1868343
- bl check_errata_1868343
- cbz x0, 2f
-#endif
-1:
- mrs x1, CORTEX_A76_CPUACTLR_EL1
- orr x1, x1, #CORTEX_A76_CPUACTLR_EL1_BIT_13
- msr CORTEX_A76_CPUACTLR_EL1, x1
- isb
-2:
- ret x17
-endfunc errata_a76_1262606_1275112_1868343_wa
+check_erratum_ls cortex_a76, ERRATUM(1791580), CPU_REV(4, 0)
-func check_errata_1262606
- mov x1, #0x30
- b cpu_rev_var_ls
-endfunc check_errata_1262606
+workaround_reset_start cortex_a76, ERRATUM(1868343), ERRATA_A76_1868343
+ sysreg_bit_set CORTEX_A76_CPUACTLR_EL1, CORTEX_A76_CPUACTLR_EL1_BIT_13
+workaround_reset_end cortex_a76, ERRATUM(1868343)
-func check_errata_1275112
- mov x1, #0x30
- b cpu_rev_var_ls
-endfunc check_errata_1275112
+check_erratum_ls cortex_a76, ERRATUM(1868343), CPU_REV(4, 0)
-func check_errata_1868343
- mov x1, #0x40
- b cpu_rev_var_ls
-endfunc check_errata_1868343
-
-/* --------------------------------------------------
- * Errata Workaround for A76 Erratum 1946160.
- * This applies to revisions r3p0 - r4p1 of A76.
- * It also exists in r0p0 - r2p0 but there is no fix
- * in those revisions.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a76_1946160_wa
- /* Compare x0 against revisions r3p0 - r4p1 */
- mov x17, x30
- bl check_errata_1946160
- cbz x0, 1f
-
+workaround_reset_start cortex_a76, ERRATUM(1946160), ERRATA_A76_1946160
mov x0, #3
msr S3_6_C15_C8_0, x0
ldr x0, =0x10E3900002
@@ -573,68 +390,33 @@
msr S3_6_C15_C8_3, x0
ldr x0, =0x2001003FF
msr S3_6_C15_C8_1, x0
-
- isb
-1:
- ret x17
-endfunc errata_a76_1946160_wa
+workaround_reset_end cortex_a76, ERRATUM(1946160)
-func check_errata_1946160
- /* Applies to revisions r3p0 - r4p1. */
- mov x1, #0x30
- mov x2, #0x41
- b cpu_rev_var_range
-endfunc check_errata_1946160
-
- /* ----------------------------------------------------
- * Errata Workaround for Cortex-A76 Errata #2743102
- * This applies to revisions <= r4p1 and is still open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ----------------------------------------------------
- */
-func errata_a76_2743102_wa
- mov x17, x30
- bl check_errata_2743102
- cbz x0, 1f
+check_erratum_range cortex_a76, ERRATUM(1946160), CPU_REV(3, 0), CPU_REV(4, 1)
+workaround_runtime_start cortex_a76, ERRATUM(2743102), ERRATA_A76_2743102
/* dsb before isb of power down sequence */
dsb sy
-1:
- ret x17
-endfunc errata_a76_2743102_wa
+workaround_runtime_end cortex_a76, ERRATUM(2743102)
-func check_errata_2743102
- /* Applies to all revisions <= r4p1 */
- mov x1, #0x41
- b cpu_rev_var_ls
-endfunc check_errata_2743102
+check_erratum_ls cortex_a76, ERRATUM(2743102), CPU_REV(4, 1)
-func check_errata_cve_2018_3639
-#if WORKAROUND_CVE_2018_3639
- mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
-#endif
- ret
-endfunc check_errata_cve_2018_3639
+check_erratum_chosen cortex_a76, CVE(2018, 3639), WORKAROUND_CVE_2018_3639
func cortex_a76_disable_wa_cve_2018_3639
- mrs x0, CORTEX_A76_CPUACTLR2_EL1
- bic x0, x0, #CORTEX_A76_CPUACTLR2_EL1_DISABLE_LOAD_PASS_STORE
- msr CORTEX_A76_CPUACTLR2_EL1, x0
+ sysreg_bit_clear CORTEX_A76_CPUACTLR2_EL1, CORTEX_A76_CPUACTLR2_EL1_DISABLE_LOAD_PASS_STORE
isb
ret
endfunc cortex_a76_disable_wa_cve_2018_3639
- /* --------------------------------------------------------------
- * Errata Workaround for Cortex A76 Errata #1165522.
- * This applies only to revisions <= r3p0 of Cortex A76.
- * Due to the nature of the errata it is applied unconditionally
- * when built in, report it as applicable in this case
- * --------------------------------------------------------------
- */
-func check_errata_1165522
+/* --------------------------------------------------------------
+ * Errata Workaround for Cortex A76 Errata #1165522.
+ * This applies only to revisions <= r3p0 of Cortex A76.
+ * Due to the nature of the errata it is applied unconditionally
+ * when built in, report it as applicable in this case
+ * --------------------------------------------------------------
+ */
+check_erratum_custom_start cortex_a76, ERRATUM(1165522)
#if ERRATA_A76_1165522
mov x0, #ERRATA_APPLIES
ret
@@ -642,66 +424,32 @@
mov x1, #0x30
b cpu_rev_var_ls
#endif
-endfunc check_errata_1165522
-
-func check_errata_cve_2022_23960
-#if WORKAROUND_CVE_2022_23960
- mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
-#endif /* WORKAROUND_CVE_2022_23960 */
- ret
-endfunc check_errata_cve_2022_23960
+check_erratum_custom_end cortex_a76, ERRATUM(1165522)
- /* -------------------------------------------------
- * The CPU Ops reset function for Cortex-A76.
- * Shall clobber: x0-x19
- * -------------------------------------------------
- */
-func cortex_a76_reset_func
- mov x19, x30
- bl cpu_get_rev_var
- mov x18, x0
+check_erratum_chosen cortex_a76, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
-#if ERRATA_A76_1073348
- mov x0, x18
- bl errata_a76_1073348_wa
-#endif
+/* erratum has no workaround in the cpu. Generic code must take care */
+add_erratum_entry cortex_a76, CVE(2022, 23960), WORKAROUND_CVE_2022_23960, NO_APPLY_AT_RESET
-#if ERRATA_A76_1130799
- mov x0, x18
- bl errata_a76_1130799_wa
-#endif
-
-#if ERRATA_A76_1220197
- mov x0, x18
- bl errata_a76_1220197_wa
-#endif
-
-#if ERRATA_A76_1257314
- mov x0, x18
- bl errata_a76_1257314_wa
-#endif
-
-#if ERRATA_A76_1262606 || ERRATA_A76_1275112 || ERRATA_A76_1868343
- mov x0, x18
- bl errata_a76_1262606_1275112_1868343_wa
-#endif
-
-#if ERRATA_A76_1262888
- mov x0, x18
- bl errata_a76_1262888_wa
-#endif
+/* ERRATA_DSU_798953 :
+ * The errata is defined in dsu_helpers.S but applies to cortex_a76
+ * as well. Henceforth creating symbolic names to the already existing errata
+ * workaround functions to get them registered under the Errata Framework.
+ */
+.equ check_erratum_cortex_a76_798953, check_errata_dsu_798953
+.equ erratum_cortex_a76_798953_wa, errata_dsu_798953_wa
+add_erratum_entry cortex_a76, ERRATUM(798953), ERRATA_DSU_798953, APPLY_AT_RESET
-#if ERRATA_A76_1791580
- mov x0, x18
- bl errata_a76_1791580_wa
-#endif
+/* ERRATA_DSU_936184 :
+ * The errata is defined in dsu_helpers.S but applies to cortex_a76
+ * as well. Henceforth creating symbolic names to the already existing errata
+ * workaround functions to get them registered under the Errata Framework.
+ */
+.equ check_erratum_cortex_a76_936184, check_errata_dsu_936184
+.equ erratum_cortex_a76_936184_wa, errata_dsu_936184_wa
+add_erratum_entry cortex_a76, ERRATUM(936184), ERRATA_DSU_936184, APPLY_AT_RESET
-#if ERRATA_A76_1946160
- mov x0, x18
- bl errata_a76_1946160_wa
-#endif
+cpu_reset_func_start cortex_a76
#if WORKAROUND_CVE_2018_3639
/* If the PE implements SSBS, we don't need the dynamic workaround */
@@ -714,9 +462,7 @@
#endif
#if DYNAMIC_WORKAROUND_CVE_2018_3639
cbnz x0, 1f
- mrs x0, CORTEX_A76_CPUACTLR2_EL1
- orr x0, x0, #CORTEX_A76_CPUACTLR2_EL1_DISABLE_LOAD_PASS_STORE
- msr CORTEX_A76_CPUACTLR2_EL1, x0
+ sysreg_bit_set CORTEX_A76_CPUACTLR2_EL1, CORTEX_A76_CPUACTLR2_EL1_DISABLE_LOAD_PASS_STORE
isb
#ifdef IMAGE_BL31
@@ -727,8 +473,7 @@
* If the below vector table is used, skip overriding it again for
* CVE_2022_23960 as both use the same vbar.
*/
- adr x0, cortex_a76_wa_cve_vbar
- msr vbar_el3, x0
+ override_vector_table cortex_a76_wa_cve_vbar
isb
b 2f
#endif /* IMAGE_BL31 */
@@ -743,22 +488,11 @@
* mitigation on exception entry from lower ELs. This will be bypassed
* if DYNAMIC_WORKAROUND_CVE_2018_3639 has overridden the vectors.
*/
- adr x0, cortex_a76_wa_cve_vbar
- msr vbar_el3, x0
+ override_vector_table cortex_a76_wa_cve_vbar
isb
#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
2:
-
-#if ERRATA_DSU_798953
- bl errata_dsu_798953_wa
-#endif
-
-#if ERRATA_DSU_936184
- bl errata_dsu_936184_wa
-#endif
-
- ret x19
-endfunc cortex_a76_reset_func
+cpu_reset_func_end cortex_a76
/* ---------------------------------------------
* HW will do the cache maintenance while powering down
@@ -769,55 +503,15 @@
* Enable CPU power down bit in power control register
* ---------------------------------------------
*/
- mrs x0, CORTEX_A76_CPUPWRCTLR_EL1
- orr x0, x0, #CORTEX_A76_CORE_PWRDN_EN_MASK
- msr CORTEX_A76_CPUPWRCTLR_EL1, x0
-#if ERRATA_A76_2743102
- mov x15, x30
- bl cpu_get_rev_var
- bl errata_a76_2743102_wa
- mov x30, x15
-#endif /* ERRATA_A76_2743102 */
+ sysreg_bit_set CORTEX_A76_CPUPWRCTLR_EL1, CORTEX_A76_CORE_PWRDN_EN_MASK
+
+ apply_erratum cortex_a76, ERRATUM(2743102), ERRATA_A76_2743102
+
isb
ret
endfunc cortex_a76_core_pwr_dwn
-#if REPORT_ERRATA
-/*
- * Errata printing function for Cortex A76. Must follow AAPCS.
- */
-func cortex_a76_errata_report
- stp x8, x30, [sp, #-16]!
-
- bl cpu_get_rev_var
- mov x8, x0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata ERRATA_A76_1073348, cortex_a76, 1073348
- report_errata ERRATA_A76_1130799, cortex_a76, 1130799
- report_errata ERRATA_A76_1165522, cortex_a76, 1165522
- report_errata ERRATA_A76_1220197, cortex_a76, 1220197
- report_errata ERRATA_A76_1257314, cortex_a76, 1257314
- report_errata ERRATA_A76_1262606, cortex_a76, 1262606
- report_errata ERRATA_A76_1262888, cortex_a76, 1262888
- report_errata ERRATA_A76_1275112, cortex_a76, 1275112
- report_errata ERRATA_A76_1286807, cortex_a76, 1286807
- report_errata ERRATA_A76_1791580, cortex_a76, 1791580
- report_errata ERRATA_A76_1868343, cortex_a76, 1868343
- report_errata ERRATA_A76_1946160, cortex_a76, 1946160
- report_errata ERRATA_A76_2743102, cortex_a76, 2743102
- report_errata WORKAROUND_CVE_2018_3639, cortex_a76, cve_2018_3639
- report_errata ERRATA_DSU_798953, cortex_a76, dsu_798953
- report_errata ERRATA_DSU_936184, cortex_a76, dsu_936184
- report_errata WORKAROUND_CVE_2022_23960, cortex_a76, cve_2022_23960
-
- ldp x8, x30, [sp], #16
- ret
-endfunc cortex_a76_errata_report
-#endif
+errata_report_shim cortex_a76
/* ---------------------------------------------
* This function provides cortex_a76 specific
diff --git a/lib/cpus/aarch64/cortex_a76ae.S b/lib/cpus/aarch64/cortex_a76ae.S
index 5c19548..08a6ef9 100644
--- a/lib/cpus/aarch64/cortex_a76ae.S
+++ b/lib/cpus/aarch64/cortex_a76ae.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -25,71 +25,34 @@
wa_cve_2022_23960_bhb_vector_table CORTEX_A76AE_BHB_LOOP_COUNT, cortex_a76ae
#endif /* WORKAROUND_CVE_2022_23960 */
-func check_errata_cve_2022_23960
-#if WORKAROUND_CVE_2022_23960
- mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
-#endif /* WORKAROUND_CVE_2022_23960 */
- ret
-endfunc check_errata_cve_2022_23960
+check_erratum_chosen cortex_a76ae, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
- /* --------------------------------------------
- * The CPU Ops reset function for Cortex-A76AE.
- * Shall clobber: x0-x19
- * --------------------------------------------
- */
-func cortex_a76ae_reset_func
-#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
+workaround_reset_start cortex_a76ae, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
+#if IMAGE_BL31
/*
* The Cortex-A76ae generic vectors are overridden to apply errata
* mitigation on exception entry from lower ELs.
*/
- adr x0, wa_cve_vbar_cortex_a76ae
- msr vbar_el3, x0
+ override_vector_table wa_cve_vbar_cortex_a76ae
isb
-#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
+#endif /* IMAGE_BL31 */
+workaround_reset_end cortex_a76ae, CVE(2022, 23960)
- ret
-endfunc cortex_a76ae_reset_func
+cpu_reset_func_start cortex_a76ae
+cpu_reset_func_end cortex_a76ae
+
+errata_report_shim cortex_a76ae
/* ----------------------------------------------------
* HW will do the cache maintenance while powering down
* ----------------------------------------------------
*/
func cortex_a76ae_core_pwr_dwn
- /* ---------------------------------------------------
- * Enable CPU power down bit in power control register
- * ---------------------------------------------------
- */
- mrs x0, CORTEX_A76AE_CPUPWRCTLR_EL1
- orr x0, x0, #CORTEX_A76AE_CORE_PWRDN_EN_MASK
- msr CORTEX_A76AE_CPUPWRCTLR_EL1, x0
+ sysreg_bit_set CORTEX_A76AE_CPUPWRCTLR_EL1, CORTEX_A76AE_CORE_PWRDN_EN_MASK
isb
ret
endfunc cortex_a76ae_core_pwr_dwn
-#if REPORT_ERRATA
-/*
- * Errata printing function for Cortex-A76AE. Must follow AAPCS.
- */
-func cortex_a76ae_errata_report
- stp x8, x30, [sp, #-16]!
-
- bl cpu_get_rev_var
- mov x8, x0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata WORKAROUND_CVE_2022_23960, cortex_a76ae, cve_2022_23960
-
- ldp x8, x30, [sp], #16
- ret
-endfunc cortex_a76ae_errata_report
-#endif /* REPORT_ERRATA */
-
/* ---------------------------------------------
* This function provides cortex_a76ae specific
* register information for crash reporting.
diff --git a/lib/cpus/aarch64/cortex_a77.S b/lib/cpus/aarch64/cortex_a77.S
index 2882df7..86c2561 100644
--- a/lib/cpus/aarch64/cortex_a77.S
+++ b/lib/cpus/aarch64/cortex_a77.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -26,26 +26,13 @@
wa_cve_2022_23960_bhb_vector_table CORTEX_A77_BHB_LOOP_COUNT, cortex_a77
#endif /* WORKAROUND_CVE_2022_23960 */
- /* --------------------------------------------------
- * Errata Workaround for Cortex A77 Errata #1508412.
- * This applies only to revision <= r1p0 of Cortex A77.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a77_1508412_wa
- /*
- * Compare x0 against revision r1p0
- */
- mov x17, x30
- bl check_errata_1508412
- cbz x0, 3f
- /*
- * Compare x0 against revision r0p0
- */
- bl check_errata_1508412_0
+workaround_reset_start cortex_a77, ERRATUM(1508412), ERRATA_A77_1508412
+ /* move cpu revision in again and compare against r0p0 */
+ mov x0, x7
+ mov x1, #CPU_REV(0, 0)
+ bl cpu_rev_var_ls
cbz x0, 1f
+
ldr x0, =0x0
msr CORTEX_A77_CPUPSELR_EL3, x0
ldr x0, =0x00E8400000
@@ -75,64 +62,30 @@
2:
ldr x0, =0x04004003FF
msr CORTEX_A77_CPUPCR_EL3, x0
- isb
-3:
- ret x17
-endfunc errata_a77_1508412_wa
+workaround_reset_end cortex_a77, ERRATUM(1508412)
-func check_errata_1508412
- mov x1, #0x10
- b cpu_rev_var_ls
-endfunc check_errata_1508412
+check_erratum_ls cortex_a77, ERRATUM(1508412), CPU_REV(1, 0)
-func check_errata_1508412_0
- mov x1, #0x0
- b cpu_rev_var_ls
-endfunc check_errata_1508412_0
+workaround_reset_start cortex_a77, ERRATUM(1791578), ERRATA_A77_1791578
+ sysreg_bit_set CORTEX_A77_ACTLR2_EL1, CORTEX_A77_ACTLR2_EL1_BIT_2
+workaround_reset_end cortex_a77, ERRATUM(1791578)
- /* --------------------------------------------------
- * Errata Workaround for Cortex A77 Errata #1925769.
- * This applies to revision <= r1p1 of Cortex A77.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a77_1925769_wa
- /* Compare x0 against revision <= r1p1 */
- mov x17, x30
- bl check_errata_1925769
- cbz x0, 1f
+check_erratum_ls cortex_a77, ERRATUM(1791578), CPU_REV(1, 1)
- /* Set bit 8 in ECTLR_EL1 */
- mrs x1, CORTEX_A77_CPUECTLR_EL1
- orr x1, x1, #CORTEX_A77_CPUECTLR_EL1_BIT_8
- msr CORTEX_A77_CPUECTLR_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_a77_1925769_wa
+workaround_reset_start cortex_a77, ERRATUM(1800714), ERRATA_A77_1800714
+ /* Disable allocation of splintered pages in the L2 TLB */
+ sysreg_bit_set CORTEX_A77_CPUECTLR_EL1, CORTEX_A77_CPUECTLR_EL1_BIT_53
+workaround_reset_end cortex_a77, ERRATUM(1800714)
-func check_errata_1925769
- /* Applies to everything <= r1p1 */
- mov x1, #0x11
- b cpu_rev_var_ls
-endfunc check_errata_1925769
+check_erratum_ls cortex_a77, ERRATUM(1800714), CPU_REV(1, 1)
- /* --------------------------------------------------
- * Errata Workaround for Cortex A77 Errata #1946167.
- * This applies to revision <= r1p1 of Cortex A77.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a77_1946167_wa
- /* Compare x0 against revision <= r1p1 */
- mov x17, x30
- bl check_errata_1946167
- cbz x0, 1f
+workaround_reset_start cortex_a77, ERRATUM(1925769), ERRATA_A77_1925769
+ sysreg_bit_set CORTEX_A77_CPUECTLR_EL1, CORTEX_A77_CPUECTLR_EL1_BIT_8
+workaround_reset_end cortex_a77, ERRATUM(1925769)
+
+check_erratum_ls cortex_a77, ERRATUM(1925769), CPU_REV(1, 1)
+workaround_reset_start cortex_a77, ERRATUM(1946167), ERRATA_A77_1946167
ldr x0,=0x4
msr CORTEX_A77_CPUPSELR_EL3,x0
ldr x0,=0x10E3900002
@@ -159,188 +112,42 @@
msr CORTEX_A77_CPUPMR_EL3,x0
ldr x0,=0x2001003FF
msr CORTEX_A77_CPUPCR_EL3,x0
+workaround_reset_end cortex_a77, ERRATUM(1946167)
- isb
-1:
- ret x17
-endfunc errata_a77_1946167_wa
+check_erratum_ls cortex_a77, ERRATUM(1946167), CPU_REV(1, 1)
-func check_errata_1946167
- /* Applies to everything <= r1p1 */
- mov x1, #0x11
- b cpu_rev_var_ls
-endfunc check_errata_1946167
+workaround_reset_start cortex_a77, ERRATUM(2356587), ERRATA_A77_2356587
+ sysreg_bit_set CORTEX_A77_ACTLR2_EL1, CORTEX_A77_ACTLR2_EL1_BIT_0
+workaround_reset_end cortex_a77, ERRATUM(2356587)
- /* --------------------------------------------------
- * Errata Workaround for Cortex A77 Errata #1791578.
- * This applies to revisions r0p0, r1p0, and r1p1 and is still open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a77_1791578_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_1791578
- cbz x0, 1f
+check_erratum_ls cortex_a77, ERRATUM(2356587), CPU_REV(1, 1)
- /* Set bit 2 in ACTLR2_EL1 */
- mrs x1, CORTEX_A77_ACTLR2_EL1
- orr x1, x1, #CORTEX_A77_ACTLR2_EL1_BIT_2
- msr CORTEX_A77_ACTLR2_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_a77_1791578_wa
-
-func check_errata_1791578
- /* Applies to r0p0, r1p0, and r1p1 right now */
- mov x1, #0x11
- b cpu_rev_var_ls
-endfunc check_errata_1791578
-
- /* --------------------------------------------------
- * Errata Workaround for Cortex A77 Errata #2356587.
- * This applies to revisions r0p0, r1p0, and r1p1 and is still open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a77_2356587_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_2356587
- cbz x0, 1f
-
- /* Set bit 0 in ACTLR2_EL1 */
- mrs x1, CORTEX_A77_ACTLR2_EL1
- orr x1, x1, #CORTEX_A77_ACTLR2_EL1_BIT_0
- msr CORTEX_A77_ACTLR2_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_a77_2356587_wa
-
-func check_errata_2356587
- /* Applies to r0p0, r1p0, and r1p1 right now */
- mov x1, #0x11
- b cpu_rev_var_ls
-endfunc check_errata_2356587
-
- /* -----------------------------------------------------------------
- * Errata Workaround for Cortex A77 Errata #2743100
- * This applies to revisions r0p0, r1p0, and r1p1 and is still open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * -----------------------------------------------------------------
- */
-func errata_a77_2743100_wa
- mov x17, x30
- bl check_errata_2743100
- cbz x0, 1f
-
+workaround_runtime_start cortex_a77, ERRATUM(2743100), ERRATA_A77_2743100
/* dsb before isb of power down sequence */
dsb sy
-1:
- ret x17
-endfunc errata_a77_2743100_wa
+workaround_runtime_end cortex_a77, ERRATUM(2743100), NO_ISB
-func check_errata_2743100
- /* Applies to r0p0, r1p0, and r1p1 right now */
- mov x1, #0x11
- b cpu_rev_var_ls
-endfunc check_errata_2743100
+check_erratum_ls cortex_a77, ERRATUM(2743100), CPU_REV(1, 1)
-func check_errata_cve_2022_23960
-#if WORKAROUND_CVE_2022_23960
- mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
-#endif
- ret
-endfunc check_errata_cve_2022_23960
-
- /* --------------------------------------------------
- * Errata Workaround for Cortex A77 Errata #1800714.
- * This applies to revision <= r1p1 of Cortex A77.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a77_1800714_wa
- /* Compare x0 against revision <= r1p1 */
- mov x17, x30
- bl check_errata_1800714
- cbz x0, 1f
-
- /* Disable allocation of splintered pages in the L2 TLB */
- mrs x1, CORTEX_A77_CPUECTLR_EL1
- orr x1, x1, CORTEX_A77_CPUECTLR_EL1_BIT_53
- msr CORTEX_A77_CPUECTLR_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_a77_1800714_wa
-
-func check_errata_1800714
- /* Applies to everything <= r1p1 */
- mov x1, #0x11
- b cpu_rev_var_ls
-endfunc check_errata_1800714
-
- /* -------------------------------------------------
- * The CPU Ops reset function for Cortex-A77.
- * Shall clobber: x0-x19
- * -------------------------------------------------
- */
-func cortex_a77_reset_func
- mov x19, x30
- bl cpu_get_rev_var
- mov x18, x0
-
-#if ERRATA_A77_1508412
- mov x0, x18
- bl errata_a77_1508412_wa
-#endif
-
-#if ERRATA_A77_1925769
- mov x0, x18
- bl errata_a77_1925769_wa
-#endif
-
-#if ERRATA_A77_1946167
- mov x0, x18
- bl errata_a77_1946167_wa
-#endif
-
-#if ERRATA_A77_1791578
- mov x0, x18
- bl errata_a77_1791578_wa
-#endif
-
-#if ERRATA_A77_2356587
- mov x0, x18
- bl errata_a77_2356587_wa
-#endif
-
-#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
+workaround_reset_start cortex_a77, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
+#if IMAGE_BL31
/*
* The Cortex-A77 generic vectors are overridden to apply errata
* mitigation on exception entry from lower ELs.
*/
adr x0, wa_cve_vbar_cortex_a77
msr vbar_el3, x0
-#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
+#endif /* IMAGE_BL31 */
+workaround_reset_end cortex_a77, CVE(2022, 23960)
-#if ERRATA_A77_1800714
- mov x0, x18
- bl errata_a77_1800714_wa
-#endif
+check_erratum_chosen cortex_a77, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
- isb
- ret x19
-endfunc cortex_a77_reset_func
+ /* -------------------------------------------------
+ * The CPU Ops reset function for Cortex-A77. Must follow AAPCS.
+ * -------------------------------------------------
+ */
+cpu_reset_func_start cortex_a77
+cpu_reset_func_end cortex_a77
/* ---------------------------------------------
* HW will do the cache maintenance while powering down
@@ -351,48 +158,16 @@
* Enable CPU power down bit in power control register
* ---------------------------------------------
*/
- mrs x0, CORTEX_A77_CPUPWRCTLR_EL1
- orr x0, x0, #CORTEX_A77_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
- msr CORTEX_A77_CPUPWRCTLR_EL1, x0
-#if ERRATA_A77_2743100
- mov x15, x30
- bl cpu_get_rev_var
- bl errata_a77_2743100_wa
- mov x30, x15
-#endif /* ERRATA_A77_2743100 */
- isb
- ret
-endfunc cortex_a77_core_pwr_dwn
+ sysreg_bit_set CORTEX_A77_CPUPWRCTLR_EL1, \
+ CORTEX_A77_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
-#if REPORT_ERRATA
-/*
- * Errata printing function for Cortex-A77. Must follow AAPCS.
- */
-func cortex_a77_errata_report
- stp x8, x30, [sp, #-16]!
-
- bl cpu_get_rev_var
- mov x8, x0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata ERRATA_A77_1508412, cortex_a77, 1508412
- report_errata ERRATA_A77_1791578, cortex_a77, 1791578
- report_errata ERRATA_A77_1800714, cortex_a77, 1800714
- report_errata ERRATA_A77_1925769, cortex_a77, 1925769
- report_errata ERRATA_A77_1946167, cortex_a77, 1946167
- report_errata ERRATA_A77_2356587, cortex_a77, 2356587
- report_errata ERRATA_A77_2743100, cortex_a77, 2743100
- report_errata WORKAROUND_CVE_2022_23960, cortex_a77, cve_2022_23960
+ apply_erratum cortex_a77, ERRATUM(2743100), ERRATA_A77_2743100
- ldp x8, x30, [sp], #16
+ isb
ret
-endfunc cortex_a77_errata_report
-#endif
-
+endfunc cortex_a77_core_pwr_dwn
+errata_report_shim cortex_a77
/* ---------------------------------------------
* This function provides Cortex-A77 specific
* register information for crash reporting.
diff --git a/lib/cpus/aarch64/cortex_a78.S b/lib/cpus/aarch64/cortex_a78.S
index 69d7ab0..b5c24e1 100644
--- a/lib/cpus/aarch64/cortex_a78.S
+++ b/lib/cpus/aarch64/cortex_a78.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2023, ARM Limited. All rights reserved.
+ * Copyright (c) 2019-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -24,77 +24,25 @@
wa_cve_2022_23960_bhb_vector_table CORTEX_A78_BHB_LOOP_COUNT, cortex_a78
#endif /* WORKAROUND_CVE_2022_23960 */
-/* --------------------------------------------------
- * Errata Workaround for A78 Erratum 1688305.
- * This applies to revision r0p0 and r1p0 of A78.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a78_1688305_wa
- /* Compare x0 against revision r1p0 */
- mov x17, x30
- bl check_errata_1688305
- cbz x0, 1f
- mrs x1, CORTEX_A78_ACTLR2_EL1
- orr x1, x1, #CORTEX_A78_ACTLR2_EL1_BIT_1
- msr CORTEX_A78_ACTLR2_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_a78_1688305_wa
+workaround_reset_start cortex_a78, ERRATUM(1688305), ERRATA_A78_1688305
+ sysreg_bit_set CORTEX_A78_ACTLR2_EL1, CORTEX_A78_ACTLR2_EL1_BIT_1
+workaround_reset_end cortex_a78, ERRATUM(1688305)
-func check_errata_1688305
- /* Applies to r0p0 and r1p0 */
- mov x1, #0x10
- b cpu_rev_var_ls
-endfunc check_errata_1688305
+check_erratum_ls cortex_a78, ERRATUM(1688305), CPU_REV(1, 0)
-/* --------------------------------------------------
- * Errata Workaround for Cortex A78 Errata #1941498.
- * This applies to revisions r0p0, r1p0, and r1p1.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a78_1941498_wa
- /* Compare x0 against revision <= r1p1 */
- mov x17, x30
- bl check_errata_1941498
- cbz x0, 1f
+workaround_reset_start cortex_a78, ERRATUM(1821534), ERRATA_A78_1821534
+ sysreg_bit_set CORTEX_A78_ACTLR2_EL1, CORTEX_A78_ACTLR2_EL1_BIT_2
+workaround_reset_end cortex_a78, ERRATUM(1821534)
- /* Set bit 8 in ECTLR_EL1 */
- mrs x1, CORTEX_A78_CPUECTLR_EL1
- orr x1, x1, #CORTEX_A78_CPUECTLR_EL1_BIT_8
- msr CORTEX_A78_CPUECTLR_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_a78_1941498_wa
+check_erratum_ls cortex_a78, ERRATUM(1821534), CPU_REV(1, 0)
-func check_errata_1941498
- /* Check for revision <= r1p1, might need to be updated later. */
- mov x1, #0x11
- b cpu_rev_var_ls
-endfunc check_errata_1941498
+workaround_reset_start cortex_a78, ERRATUM(1941498), ERRATA_A78_1941498
+ sysreg_bit_set CORTEX_A78_CPUECTLR_EL1, CORTEX_A78_CPUECTLR_EL1_BIT_8
+workaround_reset_end cortex_a78, ERRATUM(1941498)
-/* --------------------------------------------------
- * Errata Workaround for A78 Erratum 1951500.
- * This applies to revisions r1p0 and r1p1 of A78.
- * The issue also exists in r0p0 but there is no fix
- * in that revision.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a78_1951500_wa
- /* Compare x0 against revisions r1p0 - r1p1 */
- mov x17, x30
- bl check_errata_1951500
- cbz x0, 1f
+check_erratum_ls cortex_a78, ERRATUM(1941498), CPU_REV(1, 1)
+workaround_reset_start cortex_a78, ERRATUM(1951500), ERRATA_A78_1951500
msr S3_6_c15_c8_0, xzr
ldr x0, =0x10E3900002
msr S3_6_c15_c8_2, x0
@@ -120,60 +68,11 @@
msr S3_6_c15_c8_3, x0
ldr x0, =0x2001003FF
msr S3_6_c15_c8_1, x0
-
- isb
-1:
- ret x17
-endfunc errata_a78_1951500_wa
-
-func check_errata_1951500
- /* Applies to revisions r1p0 and r1p1. */
- mov x1, #CPU_REV(1, 0)
- mov x2, #CPU_REV(1, 1)
- b cpu_rev_var_range
-endfunc check_errata_1951500
-
-/* --------------------------------------------------
- * Errata Workaround for Cortex A78 Errata #1821534.
- * This applies to revisions r0p0 and r1p0.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a78_1821534_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_1821534
- cbz x0, 1f
-
- /* Set bit 2 in ACTLR2_EL1 */
- mrs x1, CORTEX_A78_ACTLR2_EL1
- orr x1, x1, #CORTEX_A78_ACTLR2_EL1_BIT_2
- msr CORTEX_A78_ACTLR2_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_a78_1821534_wa
+workaround_reset_end cortex_a78, ERRATUM(1951500)
-func check_errata_1821534
- /* Applies to r0p0 and r1p0 */
- mov x1, #0x10
- b cpu_rev_var_ls
-endfunc check_errata_1821534
+check_erratum_range cortex_a78, ERRATUM(1951500), CPU_REV(1, 0), CPU_REV(1, 1)
-/* --------------------------------------------------
- * Errata Workaround for Cortex A78 Errata 1952683.
- * This applies to revision r0p0.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a78_1952683_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_1952683
- cbz x0, 1f
-
+workaround_reset_start cortex_a78, ERRATUM(1952683), ERRATA_A78_1952683
ldr x0,=0x5
msr S3_6_c15_c8_0,x0
ldr x0,=0xEEE10A10
@@ -194,61 +93,21 @@
msr S3_6_c15_c8_3,x0
ldr x0,=0x40000080023ff
msr S3_6_c15_c8_1,x0
- isb
-1:
- ret x17
-endfunc errata_a78_1952683_wa
+workaround_reset_end cortex_a78, ERRATUM(1952683)
-func check_errata_1952683
- /* Applies to r0p0 only */
- mov x1, #0x00
- b cpu_rev_var_ls
-endfunc check_errata_1952683
+check_erratum_ls cortex_a78, ERRATUM(1952683), CPU_REV(0, 0)
-/* --------------------------------------------------
- * Errata Workaround for Cortex A78 Errata 2132060.
- * This applies to revisions r0p0, r1p0, r1p1, and r1p2.
- * It is still open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x1, x17
- * --------------------------------------------------
- */
-func errata_a78_2132060_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_2132060
- cbz x0, 1f
-
+workaround_reset_start cortex_a78, ERRATUM(2132060), ERRATA_A78_2132060
/* Apply the workaround. */
mrs x1, CORTEX_A78_CPUECTLR_EL1
mov x0, #CORTEX_A78_CPUECTLR_EL1_PF_MODE_CNSRV
bfi x1, x0, #CPUECTLR_EL1_PF_MODE_LSB, #CPUECTLR_EL1_PF_MODE_WIDTH
msr CORTEX_A78_CPUECTLR_EL1, x1
-1:
- ret x17
-endfunc errata_a78_2132060_wa
+workaround_reset_end cortex_a78, ERRATUM(2132060)
-func check_errata_2132060
- /* Applies to r0p0, r0p1, r1p1, and r1p2 */
- mov x1, #0x12
- b cpu_rev_var_ls
-endfunc check_errata_2132060
+check_erratum_ls cortex_a78, ERRATUM(2132060), CPU_REV(1, 2)
-/* --------------------------------------------------------------------
- * Errata Workaround for A78 Erratum 2242635.
- * This applies to revisions r1p0, r1p1, and r1p2 of the Cortex A78
- * processor and is still open.
- * The issue also exists in r0p0 but there is no fix in that revision.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------------------------
- */
-func errata_a78_2242635_wa
- /* Compare x0 against revisions r1p0 - r1p2 */
- mov x17, x30
- bl check_errata_2242635
- cbz x0, 1f
-
+workaround_reset_start cortex_a78, ERRATUM(2242635), ERRATA_A78_2242635
ldr x0, =0x5
msr S3_6_c15_c8_0, x0 /* CPUPSELR_EL3 */
ldr x0, =0x10F600E000
@@ -257,242 +116,64 @@
msr S3_6_c15_c8_3, x0 /* CPUPMR_EL3 */
ldr x0, =0x80000000003FF
msr S3_6_c15_c8_1, x0 /* CPUPCR_EL3 */
+workaround_reset_end cortex_a78, ERRATUM(2242635)
- isb
-1:
- ret x17
-endfunc errata_a78_2242635_wa
+check_erratum_range cortex_a78, ERRATUM(2242635), CPU_REV(1, 0), CPU_REV(1, 2)
-func check_errata_2242635
- /* Applies to revisions r1p0 through r1p2. */
- mov x1, #CPU_REV(1, 0)
- mov x2, #CPU_REV(1, 2)
- b cpu_rev_var_range
-endfunc check_errata_2242635
+workaround_reset_start cortex_a78, ERRATUM(2376745), ERRATA_A78_2376745
+ sysreg_bit_set CORTEX_A78_ACTLR2_EL1, BIT(0)
+workaround_reset_end cortex_a78, ERRATUM(2376745)
-/* --------------------------------------------------
- * Errata Workaround for Cortex A78 Errata 2376745.
- * This applies to revisions r0p0, r1p0, r1p1, and r1p2.
- * It is still open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x1, x17
- * --------------------------------------------------
- */
-func errata_a78_2376745_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_2376745
- cbz x0, 1f
-
- /* Apply the workaround. */
- mrs x1, CORTEX_A78_ACTLR2_EL1
- orr x1, x1, #BIT(0)
- msr CORTEX_A78_ACTLR2_EL1, x1
-1:
- ret x17
-endfunc errata_a78_2376745_wa
+check_erratum_ls cortex_a78, ERRATUM(2376745), CPU_REV(1, 2)
-func check_errata_2376745
- /* Applies to r0p0, r0p1, r1p1, and r1p2 */
- mov x1, #CPU_REV(1, 2)
- b cpu_rev_var_ls
-endfunc check_errata_2376745
+workaround_reset_start cortex_a78, ERRATUM(2395406), ERRATA_A78_2395406
+ sysreg_bit_set CORTEX_A78_ACTLR2_EL1, BIT(40)
+workaround_reset_end cortex_a78, ERRATUM(2395406)
-/* --------------------------------------------------
- * Errata Workaround for Cortex A78 Errata 2395406.
- * This applies to revisions r0p0, r1p0, r1p1, and r1p2.
- * It is still open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x1, x17
- * --------------------------------------------------
- */
-func errata_a78_2395406_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_2395406
- cbz x0, 1f
-
- /* Apply the workaround. */
- mrs x1, CORTEX_A78_ACTLR2_EL1
- orr x1, x1, #BIT(40)
- msr CORTEX_A78_ACTLR2_EL1, x1
-1:
- ret x17
-endfunc errata_a78_2395406_wa
+check_erratum_ls cortex_a78, ERRATUM(2395406), CPU_REV(1, 2)
-func check_errata_2395406
- /* Applies to r0p0, r0p1, r1p1, and r1p2 */
- mov x1, #CPU_REV(1, 2)
- b cpu_rev_var_ls
-endfunc check_errata_2395406
-
-/* ----------------------------------------------------
- * Errata Workaround for Cortex A78 Errata 2742426.
- * This applies to revisions r0p0, r1p0, r1p1 and r1p2.
- * It is still open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x1, x17
- * ----------------------------------------------------
- */
-func errata_a78_2742426_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_2742426
- cbz x0, 1f
-
+workaround_reset_start cortex_a78, ERRATUM(2742426), ERRATA_A78_2742426
/* Apply the workaround */
mrs x1, CORTEX_A78_ACTLR5_EL1
bic x1, x1, #BIT(56)
orr x1, x1, #BIT(55)
msr CORTEX_A78_ACTLR5_EL1, x1
+workaround_reset_end cortex_a78, ERRATUM(2742426)
-1:
- ret x17
-endfunc errata_a78_2742426_wa
+check_erratum_ls cortex_a78, ERRATUM(2742426), CPU_REV(1, 2)
-func check_errata_2742426
- /* Applies to r0p0, r1p0, r1p1, r1p2 */
- mov x1, #CPU_REV(1, 2)
- b cpu_rev_var_ls
-endfunc check_errata_2742426
-
-/* ----------------------------------------------------
- * Errata Workaround for Cortex-A78 Errata 2772019
- * This applies to revisions <= r1p2 and is still open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ----------------------------------------------------
- */
-func errata_a78_2772019_wa
- mov x17, x30
- bl check_errata_2772019
- cbz x0, 1f
-
-
+workaround_runtime_start cortex_a78, ERRATUM(2772019), ERRATA_A78_2772019
/* dsb before isb of power down sequence */
dsb sy
-1:
- ret x17
-endfunc errata_a78_2772019_wa
-
-func check_errata_2772019
- /* Applies to all revisions <= r1p2 */
- mov x1, #0x12
- b cpu_rev_var_ls
-endfunc check_errata_2772019
-
-/* ----------------------------------------------------
- * Errata Workaround for Cortex A78 Errata 2779479.
- * This applies to revisions r0p0, r1p0, r1p1, and r1p2.
- * It is still open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x1, x17
- * ----------------------------------------------------
- */
-func errata_a78_2779479_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_2779479
- cbz x0, 1f
+workaround_runtime_end cortex_a78, ERRATUM(2772019)
- /* Apply the workaround */
- mrs x1, CORTEX_A78_ACTLR3_EL1
- orr x1, x1, #BIT(47)
- msr CORTEX_A78_ACTLR3_EL1, x1
-
-1:
- ret x17
-endfunc errata_a78_2779479_wa
+check_erratum_ls cortex_a78, ERRATUM(2772019), CPU_REV(1, 2)
-func check_errata_2779479
- /* Applies to r0p0, r1p0, r1p1, r1p2 */
- mov x1, #CPU_REV(1, 2)
- b cpu_rev_var_ls
-endfunc check_errata_2779479
+workaround_reset_start cortex_a78, ERRATUM(2779479), ERRATA_A78_2779479
+ sysreg_bit_set CORTEX_A78_ACTLR3_EL1, BIT(47)
+workaround_reset_end cortex_a78, ERRATUM(2779479)
-func check_errata_cve_2022_23960
-#if WORKAROUND_CVE_2022_23960
- mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
-#endif
- ret
-endfunc check_errata_cve_2022_23960
+check_erratum_ls cortex_a78, ERRATUM(2779479), CPU_REV(1, 2)
- /* -------------------------------------------------
- * The CPU Ops reset function for Cortex-A78
- * -------------------------------------------------
+workaround_reset_start cortex_a78, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
+#if IMAGE_BL31
+ /*
+ * The Cortex-X1 generic vectors are overridden to apply errata
+ * mitigation on exception entry from lower ELs.
*/
-func cortex_a78_reset_func
- mov x19, x30
- bl cpu_get_rev_var
- mov x18, x0
-
-#if ERRATA_A78_1688305
- mov x0, x18
- bl errata_a78_1688305_wa
-#endif
-
-#if ERRATA_A78_1941498
- mov x0, x18
- bl errata_a78_1941498_wa
-#endif
-
-#if ERRATA_A78_1951500
- mov x0, x18
- bl errata_a78_1951500_wa
-#endif
-
-#if ERRATA_A78_1821534
- mov x0, x18
- bl errata_a78_1821534_wa
-#endif
-
-#if ERRATA_A78_1952683
- mov x0, x18
- bl errata_a78_1952683_wa
-#endif
-
-#if ERRATA_A78_2132060
- mov x0, x18
- bl errata_a78_2132060_wa
-#endif
+ override_vector_table wa_cve_vbar_cortex_a78
+#endif /* IMAGE_BL31 */
+workaround_reset_end cortex_a78, CVE(2022, 23960)
-#if ERRATA_A78_2242635
- mov x0, x18
- bl errata_a78_2242635_wa
-#endif
-
-#if ERRATA_A78_2376745
- mov x0, x18
- bl errata_a78_2376745_wa
-#endif
+check_erratum_chosen cortex_a78, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
-#if ERRATA_A78_2395406
- mov x0, x18
- bl errata_a78_2395406_wa
-#endif
-
-#if ERRATA_A78_2742426
- mov x0, x18
- bl errata_a78_2742426_wa
-#endif
-
-#if ERRATA_A78_2779479
- mov x0, x18
- bl errata_a78_2779479_wa
-#endif
-
+cpu_reset_func_start cortex_a78
#if ENABLE_FEAT_AMU
/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
- mrs x0, actlr_el3
- bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT
- msr actlr_el3, x0
+ sysreg_bit_clear actlr_el3, CORTEX_A78_ACTLR_TAM_BIT
/* Make sure accesses from non-secure EL0/EL1 are not trapped to EL2 */
- mrs x0, actlr_el2
- bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT
- msr actlr_el2, x0
+ sysreg_bit_clear actlr_el2, CORTEX_A78_ACTLR_TAM_BIT
/* Enable group0 counters */
mov x0, #CORTEX_A78_AMU_GROUP0_MASK
@@ -502,74 +183,22 @@
mov x0, #CORTEX_A78_AMU_GROUP1_MASK
msr CPUAMCNTENSET1_EL0, x0
#endif
-
-#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
- /*
- * The Cortex-A78 generic vectors are overridden to apply errata
- * mitigation on exception entry from lower ELs.
- */
- adr x0, wa_cve_vbar_cortex_a78
- msr vbar_el3, x0
-#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
-
- isb
- ret x19
-endfunc cortex_a78_reset_func
+cpu_reset_func_end cortex_a78
/* ---------------------------------------------
* HW will do the cache maintenance while powering down
* ---------------------------------------------
*/
func cortex_a78_core_pwr_dwn
- /* ---------------------------------------------
- * Enable CPU power down bit in power control register
- * ---------------------------------------------
- */
- mrs x0, CORTEX_A78_CPUPWRCTLR_EL1
- orr x0, x0, #CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
- msr CORTEX_A78_CPUPWRCTLR_EL1, x0
-#if ERRATA_A78_2772019
- mov x15, x30
- bl cpu_get_rev_var
- bl errata_a78_2772019_wa
- mov x30, x15
-#endif /* ERRATA_A78_2772019 */
+ sysreg_bit_set CORTEX_A78_CPUPWRCTLR_EL1, CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
+
+ apply_erratum cortex_a78, ERRATUM(2772019), ERRATA_A78_2772019
+
isb
ret
endfunc cortex_a78_core_pwr_dwn
- /*
- * Errata printing function for cortex_a78. Must follow AAPCS.
- */
-#if REPORT_ERRATA
-func cortex_a78_errata_report
- stp x8, x30, [sp, #-16]!
-
- bl cpu_get_rev_var
- mov x8, x0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata ERRATA_A78_1688305, cortex_a78, 1688305
- report_errata ERRATA_A78_1941498, cortex_a78, 1941498
- report_errata ERRATA_A78_1951500, cortex_a78, 1951500
- report_errata ERRATA_A78_1821534, cortex_a78, 1821534
- report_errata ERRATA_A78_1952683, cortex_a78, 1952683
- report_errata ERRATA_A78_2132060, cortex_a78, 2132060
- report_errata ERRATA_A78_2242635, cortex_a78, 2242635
- report_errata ERRATA_A78_2376745, cortex_a78, 2376745
- report_errata ERRATA_A78_2395406, cortex_a78, 2395406
- report_errata ERRATA_A78_2742426, cortex_a78, 2742426
- report_errata ERRATA_A78_2772019, cortex_a78, 2772019
- report_errata ERRATA_A78_2779479, cortex_a78, 2779479
- report_errata WORKAROUND_CVE_2022_23960, cortex_a78, cve_2022_23960
-
- ldp x8, x30, [sp], #16
- ret
-endfunc cortex_a78_errata_report
-#endif
+errata_report_shim cortex_a78
/* ---------------------------------------------
* This function provides cortex_a78 specific
diff --git a/lib/cpus/aarch64/cortex_a78_ae.S b/lib/cpus/aarch64/cortex_a78_ae.S
index d56f835..9f729c1 100644
--- a/lib/cpus/aarch64/cortex_a78_ae.S
+++ b/lib/cpus/aarch64/cortex_a78_ae.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2022, ARM Limited. All rights reserved.
+ * Copyright (c) 2019-2023, Arm Limited. All rights reserved.
* Copyright (c) 2021-2022, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -22,50 +22,13 @@
wa_cve_2022_23960_bhb_vector_table CORTEX_A78_AE_BHB_LOOP_COUNT, cortex_a78_ae
#endif /* WORKAROUND_CVE_2022_23960 */
-/* --------------------------------------------------
- * Errata Workaround for A78 AE Erratum 1941500.
- * This applies to revisions r0p0 and r0p1 of A78 AE.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a78_ae_1941500_wa
- /* Compare x0 against revisions r0p0 - r0p1 */
- mov x17, x30
- bl check_errata_1941500
- cbz x0, 1f
-
- /* Set bit 8 in ECTLR_EL1 */
- mrs x0, CORTEX_A78_AE_CPUECTLR_EL1
- bic x0, x0, #CORTEX_A78_AE_CPUECTLR_EL1_BIT_8
- msr CORTEX_A78_AE_CPUECTLR_EL1, x0
- isb
-1:
- ret x17
-endfunc errata_a78_ae_1941500_wa
+workaround_reset_start cortex_a78_ae, ERRATUM(1941500), ERRATA_A78_AE_1941500
+ sysreg_bit_clear CORTEX_A78_AE_CPUECTLR_EL1, CORTEX_A78_AE_CPUECTLR_EL1_BIT_8
+workaround_reset_end cortex_a78_ae, ERRATUM(1941500)
-func check_errata_1941500
- /* Applies to revisions r0p0 and r0p1. */
- mov x1, #CPU_REV(0, 0)
- mov x2, #CPU_REV(0, 1)
- b cpu_rev_var_range
-endfunc check_errata_1941500
+check_erratum_ls cortex_a78_ae, ERRATUM(1941500), CPU_REV(0, 1)
-/* --------------------------------------------------
- * Errata Workaround for A78 AE Erratum 1951502.
- * This applies to revisions r0p0 and r0p1 of A78 AE.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a78_ae_1951502_wa
- /* Compare x0 against revisions r0p0 - r0p1 */
- mov x17, x30
- bl check_errata_1951502
- cbz x0, 1f
-
+workaround_reset_start cortex_a78_ae, ERRATUM(1951502), ERRATA_A78_AE_1951502
msr S3_6_c15_c8_0, xzr
ldr x0, =0x10E3900002
msr S3_6_c15_c8_2, x0
@@ -91,33 +54,11 @@
msr S3_6_c15_c8_3, x0
ldr x0, =0x2001003FF
msr S3_6_c15_c8_1, x0
+workaround_reset_end cortex_a78_ae, ERRATUM(1951502)
- isb
-1:
- ret x17
-endfunc errata_a78_ae_1951502_wa
+check_erratum_ls cortex_a78_ae, ERRATUM(1951502), CPU_REV(0, 1)
-func check_errata_1951502
- /* Applies to revisions r0p0 and r0p1. */
- mov x1, #CPU_REV(0, 0)
- mov x2, #CPU_REV(0, 1)
- b cpu_rev_var_range
-endfunc check_errata_1951502
-
-/* --------------------------------------------------
- * Errata Workaround for A78 AE Erratum 2376748.
- * This applies to revisions r0p0 and r0p1 of A78 AE.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a78_ae_2376748_wa
- /* Compare x0 against revisions r0p0 - r0p1 */
- mov x17, x30
- bl check_errata_2376748
- cbz x0, 1f
-
+workaround_reset_start cortex_a78_ae, ERRATUM(2376748), ERRATA_A78_AE_2376748
/* -------------------------------------------------------
* Set CPUACTLR2_EL1[0] to 1 to force PLDW/PFRM ST to
* behave like PLD/PRFM LD and not cause invalidations to
@@ -126,104 +67,42 @@
* that share data.
* -------------------------------------------------------
*/
- mrs x0, CORTEX_A78_AE_ACTLR2_EL1
- orr x0, x0, #CORTEX_A78_AE_ACTLR2_EL1_BIT_0
- msr CORTEX_A78_AE_ACTLR2_EL1, x0
- isb
-1:
- ret x17
-endfunc errata_a78_ae_2376748_wa
-
-func check_errata_2376748
- /* Applies to revisions r0p0 and r0p1. */
- mov x1, #CPU_REV(0, 0)
- mov x2, #CPU_REV(0, 1)
- b cpu_rev_var_range
-endfunc check_errata_2376748
+ sysreg_bit_set CORTEX_A78_AE_ACTLR2_EL1, CORTEX_A78_AE_ACTLR2_EL1_BIT_0
+workaround_reset_end cortex_a78_ae, ERRATUM(2376748)
-/* --------------------------------------------------
- * Errata Workaround for A78 AE Erratum 2395408.
- * This applies to revisions r0p0 and r0p1 of A78 AE.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a78_ae_2395408_wa
- /* Compare x0 against revisions r0p0 - r0p1 */
- mov x17, x30
- bl check_errata_2395408
- cbz x0, 1f
+check_erratum_ls cortex_a78_ae, ERRATUM(2376748), CPU_REV(0, 1)
+workaround_reset_start cortex_a78_ae, ERRATUM(2395408), ERRATA_A78_AE_2395408
/* --------------------------------------------------------
* Disable folding of demand requests into older prefetches
* with L2 miss requests outstanding by setting the
* CPUACTLR2_EL1[40] to 1.
* --------------------------------------------------------
*/
- mrs x0, CORTEX_A78_AE_ACTLR2_EL1
- orr x0, x0, #CORTEX_A78_AE_ACTLR2_EL1_BIT_40
- msr CORTEX_A78_AE_ACTLR2_EL1, x0
- isb
-1:
- ret x17
-endfunc errata_a78_ae_2395408_wa
-
-func check_errata_2395408
- /* Applies to revisions r0p0 and r0p1. */
- mov x1, #CPU_REV(0, 0)
- mov x2, #CPU_REV(0, 1)
- b cpu_rev_var_range
-endfunc check_errata_2395408
+ sysreg_bit_set CORTEX_A78_AE_ACTLR2_EL1, CORTEX_A78_AE_ACTLR2_EL1_BIT_40
+workaround_reset_end cortex_a78_ae, ERRATUM(2395408)
-func check_errata_cve_2022_23960
-#if WORKAROUND_CVE_2022_23960
- mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
-#endif
- ret
-endfunc check_errata_cve_2022_23960
+check_erratum_ls cortex_a78_ae, ERRATUM(2395408), CPU_REV(0, 1)
- /* -------------------------------------------------
- * The CPU Ops reset function for Cortex-A78-AE
- * -------------------------------------------------
+workaround_reset_start cortex_a78_ae, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
+#if IMAGE_BL31
+ /*
+ * The Cortex-A78AE generic vectors are overridden to apply errata
+ * mitigation on exception entry from lower ELs.
*/
-func cortex_a78_ae_reset_func
- mov x19, x30
- bl cpu_get_rev_var
- mov x18, x0
+ override_vector_table wa_cve_vbar_cortex_a78_ae
+#endif /* IMAGE_BL31 */
+workaround_reset_end cortex_a78_ae, CVE(2022, 23960)
-#if ERRATA_A78_AE_1941500
- mov x0, x18
- bl errata_a78_ae_1941500_wa
-#endif
+check_erratum_chosen cortex_a78_ae, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
-#if ERRATA_A78_AE_1951502
- mov x0, x18
- bl errata_a78_ae_1951502_wa
-#endif
-
-#if ERRATA_A78_AE_2376748
- mov x0, x18
- bl errata_a78_ae_2376748_wa
-#endif
-
-#if ERRATA_A78_AE_2395408
- mov x0, x18
- bl errata_a78_ae_2395408_wa
-#endif
-
+cpu_reset_func_start cortex_a78_ae
#if ENABLE_FEAT_AMU
/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
- mrs x0, actlr_el3
- bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT
- msr actlr_el3, x0
+ sysreg_bit_clear actlr_el3, CORTEX_A78_ACTLR_TAM_BIT
/* Make sure accesses from non-secure EL0/EL1 are not trapped to EL2 */
- mrs x0, actlr_el2
- bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT
- msr actlr_el2, x0
+ sysreg_bit_clear actlr_el2, CORTEX_A78_ACTLR_TAM_BIT
/* Enable group0 counters */
mov x0, #CORTEX_A78_AMU_GROUP0_MASK
@@ -233,19 +112,7 @@
mov x0, #CORTEX_A78_AMU_GROUP1_MASK
msr CPUAMCNTENSET1_EL0, x0
#endif
-
-#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
- /*
- * The Cortex-A78AE generic vectors are overridden to apply errata
- * mitigation on exception entry from lower ELs.
- */
- adr x0, wa_cve_vbar_cortex_a78_ae
- msr vbar_el3, x0
-#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
-
- isb
- ret x19
-endfunc cortex_a78_ae_reset_func
+cpu_reset_func_end cortex_a78_ae
/* -------------------------------------------------------
* HW will do the cache maintenance while powering down
@@ -256,37 +123,12 @@
* Enable CPU power down bit in power control register
* -------------------------------------------------------
*/
- mrs x0, CORTEX_A78_CPUPWRCTLR_EL1
- orr x0, x0, #CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
- msr CORTEX_A78_CPUPWRCTLR_EL1, x0
+ sysreg_bit_set CORTEX_A78_CPUPWRCTLR_EL1, CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
isb
ret
endfunc cortex_a78_ae_core_pwr_dwn
- /*
- * Errata printing function for cortex_a78_ae. Must follow AAPCS.
- */
-#if REPORT_ERRATA
-func cortex_a78_ae_errata_report
- stp x8, x30, [sp, #-16]!
-
- bl cpu_get_rev_var
- mov x8, x0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata ERRATA_A78_AE_1941500, cortex_a78_ae, 1941500
- report_errata ERRATA_A78_AE_1951502, cortex_a78_ae, 1951502
- report_errata ERRATA_A78_AE_2376748, cortex_a78_ae, 2376748
- report_errata ERRATA_A78_AE_2395408, cortex_a78_ae, 2395408
- report_errata WORKAROUND_CVE_2022_23960, cortex_a78_ae, cve_2022_23960
-
- ldp x8, x30, [sp], #16
- ret
-endfunc cortex_a78_ae_errata_report
-#endif
+errata_report_shim cortex_a78_ae
/* -------------------------------------------------------
* This function provides cortex_a78_ae specific
diff --git a/lib/cpus/aarch64/cortex_a78c.S b/lib/cpus/aarch64/cortex_a78c.S
index fddd24f..d19c693 100644
--- a/lib/cpus/aarch64/cortex_a78c.S
+++ b/lib/cpus/aarch64/cortex_a78c.S
@@ -17,174 +17,37 @@
#error "cortex_a78c must be compiled with HW_ASSISTED_COHERENCY enabled"
#endif
-/* --------------------------------------------------
- * Errata Workaround for A78C Erratum 1827430.
- * This applies to revision r0p0 of the Cortex A78C
- * processor and is fixed in r0p1.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a78c_1827430_wa
- mov x17, x30
- bl check_errata_1827430
- cbz x0, 1f
+#if WORKAROUND_CVE_2022_23960
+ wa_cve_2022_23960_bhb_vector_table CORTEX_A78C_BHB_LOOP_COUNT, cortex_a78c
+#endif /* WORKAROUND_CVE_2022_23960 */
+workaround_reset_start cortex_a78c, ERRATUM(1827430), ERRATA_A78C_1827430
/* Disable allocation of splintered pages in the L2 TLB */
- mrs x1, CORTEX_A78C_CPUECTLR_EL1
- orr x1, x1, CORTEX_A78C_CPUECTLR_EL1_MM_ASP_EN
- msr CORTEX_A78C_CPUECTLR_EL1, x1
-1:
- ret x17
-endfunc errata_a78c_1827430_wa
+ sysreg_bit_set CORTEX_A78C_CPUECTLR_EL1, CORTEX_A78C_CPUECTLR_EL1_MM_ASP_EN
+workaround_reset_end cortex_a78c, ERRATUM(1827430)
-func check_errata_1827430
- /* Applies to revision r0p0 only */
- mov x1, #0x00
- b cpu_rev_var_ls
-endfunc check_errata_1827430
+check_erratum_ls cortex_a78c, ERRATUM(1827430), CPU_REV(0, 0)
-/* --------------------------------------------------
- * Errata Workaround for A78C Erratum 1827440.
- * This applies to revision r0p0 of the Cortex A78C
- * processor and is fixed in r0p1.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a78c_1827440_wa
- mov x17, x30
- bl check_errata_1827440
- cbz x0, 1f
-
+workaround_reset_start cortex_a78c, ERRATUM(1827440), ERRATA_A78C_1827440
/* Force Atomic Store to WB memory be done in L1 data cache */
- mrs x1, CORTEX_A78C_CPUACTLR2_EL1
- orr x1, x1, #BIT(2)
- msr CORTEX_A78C_CPUACTLR2_EL1, x1
-1:
- ret x17
-endfunc errata_a78c_1827440_wa
-
-func check_errata_1827440
- /* Applies to revision r0p0 only */
- mov x1, #0x00
- b cpu_rev_var_ls
-endfunc check_errata_1827440
+ sysreg_bit_set CORTEX_A78C_CPUACTLR2_EL1, BIT(2)
+workaround_reset_end cortex_a78c, ERRATUM(1827440)
-/* --------------------------------------------------
- * Errata Workaround for Cortex A78C Erratum 2376749.
- * This applies to revision r0p1 and r0p2 of the A78C
- * and is currently open. It is a Cat B erratum.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x4, x17
- * --------------------------------------------------
- */
-func errata_a78c_2376749_wa
- /* Check revision */
- mov x17, x30
- bl check_errata_2376749
- cbz x0, 1f
- /* Set CPUACTLR2_EL1[0] to 1. */
- mrs x1, CORTEX_A78C_CPUACTLR2_EL1
- orr x1, x1, #CORTEX_A78C_CPUACTLR2_EL1_BIT_0
- msr CORTEX_A78C_CPUACTLR2_EL1, x1
-1:
- ret x17
-endfunc errata_a78c_2376749_wa
+check_erratum_ls cortex_a78c, ERRATUM(1827440), CPU_REV(0, 0)
-func check_errata_2376749
- /* Applies to r0p1 and r0p2*/
- mov x1, #0x01
- mov x2, #0x02
- b cpu_rev_var_range
-endfunc check_errata_2376749
-
-/* --------------------------------------------------
- * Errata Workaround for Cortex A78C Erratum 2395411.
- * This applies to revision r0p1 and r0p2 of the A78C
- * and is currently open. It is a Cat B erratum.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x4, x17
- * --------------------------------------------------
- */
-func errata_a78c_2395411_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_2395411
- cbz x0, 1f
-
- /* Set CPUACTRL2_EL1[40] to 1. */
- mrs x1, CORTEX_A78C_CPUACTLR2_EL1
- orr x1, x1, #CORTEX_A78C_CPUACTLR2_EL1_BIT_40
- msr CORTEX_A78C_CPUACTLR2_EL1, x1
-1:
- ret x17
-endfunc errata_a78c_2395411_wa
-
-func check_errata_2395411
- /* Applies to r0p1 and r0p2 */
- mov x1, #0x01
- mov x2, #0x02
- b cpu_rev_var_range
-endfunc check_errata_2395411
-
-#if WORKAROUND_CVE_2022_23960
- wa_cve_2022_23960_bhb_vector_table CORTEX_A78C_BHB_LOOP_COUNT, cortex_a78c
-#endif /* WORKAROUND_CVE_2022_23960 */
-
-/* --------------------------------------------------
- * Errata Workaround for A78C Erratum 2132064.
- * This applies to revisions r0p1 and r0p2 of A78C
- * and is still open.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a78c_2132064_wa
- /* Compare x0 against revisions r0p0 - r0p1 */
- mov x17, x30
- bl check_errata_2132064
- cbz x0, 1f
-
+workaround_reset_start cortex_a78c, ERRATUM(2132064), ERRATA_A78C_2132064
/* --------------------------------------------------------
* Place the data prefetcher in the most conservative mode
* to reduce prefetches by writing the following bits to
* the value indicated: ecltr[7:6], PF_MODE = 2'b11
* --------------------------------------------------------
*/
- mrs x0, CORTEX_A78C_CPUECTLR_EL1
- orr x0, x0, #CORTEX_A78C_CPUECTLR_EL1_BIT_6
- orr x0, x0, #CORTEX_A78C_CPUECTLR_EL1_BIT_7
- msr CORTEX_A78C_CPUECTLR_EL1, x0
- isb
-1:
- ret x17
-endfunc errata_a78c_2132064_wa
-
-func check_errata_2132064
- /* Applies to revisions r0p1 and r0p2. */
- mov x1, #CPU_REV(0, 1)
- mov x2, #CPU_REV(0, 2)
- b cpu_rev_var_range
-endfunc check_errata_2132064
+ sysreg_bit_set CORTEX_A78C_CPUECTLR_EL1, (CORTEX_A78C_CPUECTLR_EL1_BIT_6 | CORTEX_A78C_CPUECTLR_EL1_BIT_7)
+workaround_reset_end cortex_a78c, ERRATUM(2132064)
-/* ----------------------------------------------------------
- * Errata Workaround for A78C Erratum 2242638.
- * This applies to revisions r0p1 and r0p2 of the Cortex A78C
- * processor and is still open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ----------------------------------------------------------
- */
-func errata_a78c_2242638_wa
- /* Compare x0 against revisions r0p1 - r0p2 */
- mov x17, x30
- bl check_errata_2242638
- cbz x0, 1f
+check_erratum_range cortex_a78c, ERRATUM(2132064), CPU_REV(0, 1), CPU_REV(0, 2)
+workaround_reset_start cortex_a78c, ERRATUM(2242638), ERRATA_A78C_2242638
ldr x0, =0x5
msr CORTEX_A78C_IMP_CPUPSELR_EL3, x0
ldr x0, =0x10F600E000
@@ -193,139 +56,51 @@
msr CORTEX_A78C_IMP_CPUPMR_EL3, x0
ldr x0, =0x80000000003FF
msr CORTEX_A78C_IMP_CPUPCR_EL3, x0
-
- isb
-1:
- ret x17
-endfunc errata_a78c_2242638_wa
-
-func check_errata_2242638
- /* Applies to revisions r0p1-r0p2. */
- mov x1, #CPU_REV(0, 1)
- mov x2, #CPU_REV(0, 2)
- b cpu_rev_var_range
-endfunc check_errata_2242638
-
-/* ----------------------------------------------------------------
- * Errata Workaround for A78C Erratum 2772121.
- * This applies to revisions r0p0, r0p1 and r0p2 of the Cortex A78C
- * processor and is still open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ----------------------------------------------------------------
- */
-func errata_a78c_2772121_wa
- mov x17, x30
- bl check_errata_2772121
- cbz x0, 1f
-
- /* dsb before isb of power down sequence */
- dsb sy
-1:
- ret x17
-endfunc errata_a78c_2772121_wa
-
-func check_errata_2772121
- /* Applies to all revisions <= r0p2 */
- mov x1, #0x02
- b cpu_rev_var_ls
-endfunc check_errata_2772121
+workaround_reset_end cortex_a78c, ERRATUM(2242638)
-/* --------------------------------------------------
- * Errata Workaround for Cortex A78C Errata 2779484.
- * This applies to revisions r0p1 and r0p2.
- * It is still open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x1, x17
- * --------------------------------------------------
- */
-func errata_a78c_2779484_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_2779484
- cbz x0, 1f
+check_erratum_range cortex_a78c, ERRATUM(2242638), CPU_REV(0, 1), CPU_REV(0, 2)
- /* Apply the workaround */
- mrs x1, CORTEX_A78C_ACTLR3_EL1
- orr x1, x1, #BIT(47)
- msr CORTEX_A78C_ACTLR3_EL1, x1
+workaround_reset_start cortex_a78c, ERRATUM(2376749), ERRATA_A78C_2376749
+ sysreg_bit_set CORTEX_A78C_CPUACTLR2_EL1, CORTEX_A78C_CPUACTLR2_EL1_BIT_0
+workaround_reset_end cortex_a78c, ERRATUM(2376749)
-1:
- ret x17
-endfunc errata_a78c_2779484_wa
+check_erratum_range cortex_a78c, ERRATUM(2376749), CPU_REV(0, 1), CPU_REV(0, 2)
-func check_errata_2779484
- /* Applies to r0p1 and r0p2*/
- mov x1, #0x01
- mov x2, #0x02
- b cpu_rev_var_range
-endfunc check_errata_2779484
+workaround_reset_start cortex_a78c, ERRATUM(2395411), ERRATA_A78C_2395411
+ sysreg_bit_set CORTEX_A78C_CPUACTLR2_EL1, CORTEX_A78C_CPUACTLR2_EL1_BIT_40
+workaround_reset_end cortex_a78c, ERRATUM(2395411)
-func check_errata_cve_2022_23960
-#if WORKAROUND_CVE_2022_23960
- mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
-#endif
- ret
-endfunc check_errata_cve_2022_23960
+check_erratum_range cortex_a78c, ERRATUM(2395411), CPU_REV(0, 1), CPU_REV(0, 2)
- /* -------------------------------------------------
- * The CPU Ops reset function for Cortex-A78C
- * -------------------------------------------------
- */
-func cortex_a78c_reset_func
- mov x19, x30
- bl cpu_get_rev_var
- mov x18, x0
-
-#if ERRATA_A78C_1827430
- mov x0, x18
- bl errata_a78c_1827430_wa
-#endif
-
-#if ERRATA_A78C_1827440
- mov x0, x18
- bl errata_a78c_1827440_wa
-#endif
-
-#if ERRATA_A78C_2132064
- mov x0, x18
- bl errata_a78c_2132064_wa
-#endif
+workaround_runtime_start cortex_a78c, ERRATUM(2772121), ERRATA_A78C_2772121
+ /* dsb before isb of power down sequence */
+ dsb sy
+workaround_runtime_end cortex_a78c, ERRATUM(2772121)
-#if ERRATA_A78C_2242638
- mov x0, x18
- bl errata_a78c_2242638_wa
-#endif
+check_erratum_ls cortex_a78c, ERRATUM(2772121), CPU_REV(0, 2)
-#if ERRATA_A78C_2376749
- mov x0, x18
- bl errata_a78c_2376749_wa
-#endif
+workaround_reset_start cortex_a78c, ERRATUM(2779484), ERRATA_A78C_2779484
+ sysreg_bit_set CORTEX_A78C_ACTLR3_EL1, BIT(47)
+workaround_reset_end cortex_a78c, ERRATUM(2779484)
-#if ERRATA_A78C_2395411
- mov x0, x18
- bl errata_a78c_2395411_wa
-#endif
+check_erratum_range cortex_a78c, ERRATUM(2779484), CPU_REV(0, 1), CPU_REV(0, 2)
-#if ERRATA_A78C_2779484
- mov x0, x18
- bl errata_a78c_2779484_wa
-#endif
+check_erratum_chosen cortex_a78c, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
-#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
+workaround_reset_start cortex_a78c, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
+#if IMAGE_BL31
/*
* The Cortex-A78c generic vectors are overridden to apply errata
* mitigation on exception entry from lower ELs.
*/
- adr x0, wa_cve_vbar_cortex_a78c
- msr vbar_el3, x0
-#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
+ override_vector_table wa_cve_vbar_cortex_a78c
+#endif /* IMAGE_BL31 */
+workaround_reset_end cortex_a78c, CVE(2022, 23960)
- isb
- ret x19
-endfunc cortex_a78c_reset_func
+cpu_reset_func_start cortex_a78c
+cpu_reset_func_end cortex_a78c
+
+errata_report_shim cortex_a78c
/* ----------------------------------------------------
* HW will do the cache maintenance while powering down
@@ -336,48 +111,14 @@
* Enable CPU power down bit in power control register
* ---------------------------------------------------
*/
- mrs x0, CORTEX_A78C_CPUPWRCTLR_EL1
- orr x0, x0, #CORTEX_A78C_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
- msr CORTEX_A78C_CPUPWRCTLR_EL1, x0
-#if ERRATA_A78C_2772121
- mov x15, x30
- bl cpu_get_rev_var
- bl errata_a78c_2772121_wa
- mov x30, x15
-#endif /* ERRATA_A78C_2772121 */
+ sysreg_bit_set CORTEX_A78C_CPUPWRCTLR_EL1, CORTEX_A78C_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
+
+ apply_erratum cortex_a78c, ERRATUM(2772121), ERRATA_A78C_2772121
+
isb
ret
endfunc cortex_a78c_core_pwr_dwn
-#if REPORT_ERRATA
-/*
- * Errata printing function for Cortex A78C. Must follow AAPCS.
- */
-func cortex_a78c_errata_report
- stp x8, x30, [sp, #-16]!
-
- bl cpu_get_rev_var
- mov x8, x0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata ERRATA_A78C_1827430, cortex_a78c, 1827430
- report_errata ERRATA_A78C_1827440, cortex_a78c, 1827440
- report_errata ERRATA_A78C_2132064, cortex_a78c, 2132064
- report_errata ERRATA_A78C_2242638, cortex_a78c, 2242638
- report_errata ERRATA_A78C_2376749, cortex_a78c, 2376749
- report_errata ERRATA_A78C_2395411, cortex_a78c, 2395411
- report_errata ERRATA_A78C_2772121, cortex_a78c, 2772121
- report_errata ERRATA_A78C_2779484, cortex_a78c, 2779484
- report_errata WORKAROUND_CVE_2022_23960, cortex_a78c, cve_2022_23960
-
- ldp x8, x30, [sp], #16
- ret
-endfunc cortex_a78c_errata_report
-#endif
-
/* ---------------------------------------------
* This function provides cortex_a78c specific
* register information for crash reporting.
diff --git a/lib/cpus/aarch64/cortex_x1.S b/lib/cpus/aarch64/cortex_x1.S
index de65365..42634f1 100644
--- a/lib/cpus/aarch64/cortex_x1.S
+++ b/lib/cpus/aarch64/cortex_x1.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022, Google LLC. All rights reserved.
+ * Copyright (c) 2022-2023, Google LLC. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -23,175 +23,50 @@
wa_cve_2022_23960_bhb_vector_table CORTEX_X1_BHB_LOOP_COUNT, cortex_x1
#endif /* WORKAROUND_CVE_2022_23960 */
-/* --------------------------------------------------
- * Errata Workaround for X1 Erratum 1821534.
- * This applies to revision r0p0 and r1p0 of X1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_x1_1821534_wa
- /* Compare x0 against revision r1p0 */
- mov x17, x30
- bl check_errata_1821534
- cbz x0, 1f
- mrs x1, CORTEX_X1_ACTLR2_EL1
- orr x1, x1, #BIT(2)
- msr CORTEX_X1_ACTLR2_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_x1_1821534_wa
-
-func check_errata_1821534
- /* Applies to r0p0 and r1p0 */
- mov x1, #0x10
- b cpu_rev_var_ls
-endfunc check_errata_1821534
-
-/* --------------------------------------------------
- * Errata Workaround for X1 Erratum 1688305.
- * This applies to revision r0p0 and r1p0 of X1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_x1_1688305_wa
- /* Compare x0 against revision r1p0 */
- mov x17, x30
- bl check_errata_1688305
- cbz x0, 1f
- mrs x0, CORTEX_X1_ACTLR2_EL1
- orr x0, x0, #BIT(1)
- msr CORTEX_X1_ACTLR2_EL1, x0
- isb
-
-1:
- ret x17
-endfunc errata_x1_1688305_wa
-
-func check_errata_1688305
- /* Applies to r0p0 and r1p0 */
- mov x1, #0x10
- b cpu_rev_var_ls
-endfunc check_errata_1688305
+workaround_reset_start cortex_x1, ERRATUM(1688305), ERRATA_X1_1688305
+ sysreg_bit_set CORTEX_X1_ACTLR2_EL1, BIT(1)
+workaround_reset_end cortex_x1, ERRATUM(1688305)
-/* --------------------------------------------------
- * Errata Workaround for X1 Erratum 1827429.
- * This applies to revision r0p0 and r1p0 of X1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_x1_1827429_wa
- /* Compare x0 against revision r1p0 */
- mov x17, x30
- bl check_errata_1827429
- cbz x0, 1f
- mrs x0, CORTEX_X1_CPUECTLR_EL1
- orr x0, x0, #BIT(53)
- msr CORTEX_X1_CPUECTLR_EL1, x0
- isb
+check_erratum_ls cortex_x1, ERRATUM(1688305), CPU_REV(1, 0)
-1:
- ret x17
-endfunc errata_x1_1827429_wa
+workaround_reset_start cortex_x1, ERRATUM(1821534), ERRATA_X1_1821534
+ sysreg_bit_set CORTEX_X1_ACTLR2_EL1, BIT(2)
+workaround_reset_end cortex_x1, ERRATUM(1821534)
-func check_errata_1827429
- /* Applies to r0p0 and r1p0 */
- mov x1, #0x10
- b cpu_rev_var_ls
-endfunc check_errata_1827429
+check_erratum_ls cortex_x1, ERRATUM(1821534), CPU_REV(1, 0)
-func check_errata_cve_2022_23960
-#if WORKAROUND_CVE_2022_23960
- mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
-#endif
- ret
-endfunc check_errata_cve_2022_23960
+workaround_reset_start cortex_x1, ERRATUM(1827429), ERRATA_X1_1827429
+ sysreg_bit_set CORTEX_X1_CPUECTLR_EL1, BIT(53)
+workaround_reset_end cortex_x1, ERRATUM(1827429)
- /* -------------------------------------------------
- * The CPU Ops reset function for Cortex-X1.
- * Shall clobber: x0-x19
- * -------------------------------------------------
- */
-func cortex_x1_reset_func
- mov x19, x30
- bl cpu_get_rev_var
- mov x18, x0
+check_erratum_ls cortex_x1, ERRATUM(1827429), CPU_REV(1, 0)
-#if ERRATA_X1_1821534
- mov x0, x18
- bl errata_x1_1821534_wa
-#endif
+check_erratum_chosen cortex_x1, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
-#if ERRATA_X1_1688305
- mov x0, x18
- bl errata_x1_1688305_wa
-#endif
-
-#if ERRATA_X1_1827429
- mov x0, x18
- bl errata_x1_1827429_wa
-#endif
-
-#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
+workaround_reset_start cortex_x1, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
+#if IMAGE_BL31
/*
* The Cortex-X1 generic vectors are overridden to apply errata
* mitigation on exception entry from lower ELs.
*/
- adr x0, wa_cve_vbar_cortex_x1
- msr vbar_el3, x0
-#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
+ override_vector_table wa_cve_vbar_cortex_x1
+#endif /* IMAGE_BL31 */
+workaround_reset_end cortex_x1, CVE(2022, 23960)
- isb
- ret x19
-endfunc cortex_x1_reset_func
+cpu_reset_func_start cortex_x1
+cpu_reset_func_end cortex_x1
/* ---------------------------------------------
* HW will do the cache maintenance while powering down
* ---------------------------------------------
*/
func cortex_x1_core_pwr_dwn
- /* ---------------------------------------------
- * Enable CPU power down bit in power control register
- * ---------------------------------------------
- */
- mrs x0, CORTEX_X1_CPUPWRCTLR_EL1
- orr x0, x0, #CORTEX_X1_CORE_PWRDN_EN_MASK
- msr CORTEX_X1_CPUPWRCTLR_EL1, x0
+ sysreg_bit_set CORTEX_X1_CPUPWRCTLR_EL1, CORTEX_X1_CORE_PWRDN_EN_MASK
isb
ret
endfunc cortex_x1_core_pwr_dwn
-#if REPORT_ERRATA
-/*
- * Errata printing function for Cortex X1. Must follow AAPCS.
- */
-func cortex_x1_errata_report
- stp x8, x30, [sp, #-16]!
-
- bl cpu_get_rev_var
- mov x8, x0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata ERRATA_X1_1821534, cortex_x1, 1821534
- report_errata ERRATA_X1_1688305, cortex_x1, 1688305
- report_errata ERRATA_X1_1827429, cortex_x1, 1827429
- report_errata WORKAROUND_CVE_2022_23960, cortex_x1, cve_2022_23960
-
- ldp x8, x30, [sp], #16
- ret
-endfunc cortex_x1_errata_report
-#endif
+errata_report_shim cortex_x1
/* ---------------------------------------------
* This function provides Cortex X1 specific
diff --git a/lib/cpus/aarch64/cortex_x3.S b/lib/cpus/aarch64/cortex_x3.S
index f104b48..c781d38 100644
--- a/lib/cpus/aarch64/cortex_x3.S
+++ b/lib/cpus/aarch64/cortex_x3.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -26,141 +26,51 @@
wa_cve_2022_23960_bhb_vector_table CORTEX_X3_BHB_LOOP_COUNT, cortex_x3
#endif /* WORKAROUND_CVE_2022_23960 */
- /* ----------------------------------------------------
- * HW will do the cache maintenance while powering down
- * ----------------------------------------------------
- */
-func cortex_x3_core_pwr_dwn
-#if ERRATA_X3_2313909
- mov x15, x30
- bl cpu_get_rev_var
- bl errata_cortex_x3_2313909_wa
- mov x30, x15
-#endif /* ERRATA_X3_2313909 */
+workaround_runtime_start cortex_x3, ERRATUM(2313909), ERRATA_X3_2313909
+ sysreg_bit_set CORTEX_X3_CPUACTLR2_EL1, CORTEX_X3_CPUACTLR2_EL1_BIT_36
+workaround_runtime_end cortex_x3, ERRATUM(2313909), NO_ISB
- /* ---------------------------------------------------
- * Enable CPU power down bit in power control register
- * ---------------------------------------------------
- */
- mrs x0, CORTEX_X3_CPUPWRCTLR_EL1
- orr x0, x0, #CORTEX_X3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
- msr CORTEX_X3_CPUPWRCTLR_EL1, x0
- isb
- ret
-endfunc cortex_x3_core_pwr_dwn
-
-func check_errata_cve_2022_23960
-#if WORKAROUND_CVE_2022_23960
- mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
-#endif
- ret
-endfunc check_errata_cve_2022_23960
-
-func cortex_x3_reset_func
- mov x19, x30
- /* Disable speculative loads */
- msr SSBS, xzr
-
-#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
- /*
- * The Cortex-X3 generic vectors are overridden to apply
- * errata mitigation on exception entry from lower ELs.
- */
- adr x0, wa_cve_vbar_cortex_x3
- msr vbar_el3, x0
-#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
+check_erratum_ls cortex_x3, ERRATUM(2313909), CPU_REV(1, 0)
- bl cpu_get_rev_var
-
-#if ERRATA_X3_2615812
- bl errata_cortex_x3_2615812_wa
-#endif /* ERRATA_X3_2615812 */
-
- isb
- ret x19
-endfunc cortex_x3_reset_func
-
-/* ----------------------------------------------------------------------
- * Errata Workaround for Cortex-X3 Erratum 2313909 on power down request.
- * This applies to revision r0p0 and r1p0 of Cortex-X3. Fixed in r1p1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x1, x17
- * ----------------------------------------------------------------------
- */
-func errata_cortex_x3_2313909_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_2313909
- cbz x0, 1f
-
- /* Set bit 36 in ACTLR2_EL1 */
- mrs x1, CORTEX_X3_CPUACTLR2_EL1
- orr x1, x1, #CORTEX_X3_CPUACTLR2_EL1_BIT_36
- msr CORTEX_X3_CPUACTLR2_EL1, x1
-1:
- ret x17
-endfunc errata_cortex_x3_2313909_wa
-
-func check_errata_2313909
- /* Applies to r0p0 and r1p0 */
- mov x1, #0x10
- b cpu_rev_var_ls
-endfunc check_errata_2313909
-
-/* ----------------------------------------------------------------------
- * Errata Workaround for Cortex-X3 Erratum 2615812 on power-on.
- * This applies to revision r0p0, r1p0, r1p1 of Cortex-X3. Open.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x1, x17
- * ----------------------------------------------------------------------
- */
-func errata_cortex_x3_2615812_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_2615812
- cbz x0, 1f
-
+workaround_reset_start cortex_x3, ERRATUM(2615812), ERRATA_X3_2615812
/* Disable retention control for WFI and WFE. */
mrs x0, CORTEX_X3_CPUPWRCTLR_EL1
bfi x0, xzr, #CORTEX_X3_CPUPWRCTLR_EL1_WFI_RET_CTRL_BITS_SHIFT, #3
bfi x0, xzr, #CORTEX_X3_CPUPWRCTLR_EL1_WFE_RET_CTRL_BITS_SHIFT, #3
msr CORTEX_X3_CPUPWRCTLR_EL1, x0
-1:
- ret x17
-endfunc errata_cortex_x3_2615812_wa
+workaround_reset_end cortex_x3, ERRATUM(2615812)
-func check_errata_2615812
- /* Applies to r1p1 and below. */
- mov x1, #0x11
- b cpu_rev_var_ls
-endfunc check_errata_2615812
+check_erratum_ls cortex_x3, ERRATUM(2615812), CPU_REV(1, 1)
-#if REPORT_ERRATA
- /*
- * Errata printing function for Cortex-X3. Must follow AAPCS.
- */
-func cortex_x3_errata_report
- stp x8, x30, [sp, #-16]!
+workaround_reset_start cortex_x3, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
+#if IMAGE_BL31
+ override_vector_table wa_cve_vbar_cortex_x3
+#endif /* IMAGE_BL31 */
+workaround_reset_end cortex_x3, CVE(2022, 23960)
- bl cpu_get_rev_var
- mov x8, x0
+check_erratum_chosen cortex_x3, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata ERRATA_X3_2313909, cortex_x3, 2313909
- report_errata ERRATA_X3_2615812, cortex_x3, 2615812
- report_errata WORKAROUND_CVE_2022_23960, cortex_x3, cve_2022_23960
+cpu_reset_func_start cortex_x3
+ /* Disable speculative loads */
+ msr SSBS, xzr
+cpu_reset_func_end cortex_x3
- ldp x8, x30, [sp], #16
+ /* ----------------------------------------------------
+ * HW will do the cache maintenance while powering down
+ * ----------------------------------------------------
+ */
+func cortex_x3_core_pwr_dwn
+apply_erratum cortex_x3, ERRATUM(2313909), ERRATA_X3_2313909
+ /* ---------------------------------------------------
+ * Enable CPU power down bit in power control register
+ * ---------------------------------------------------
+ */
+ sysreg_bit_set CORTEX_X3_CPUPWRCTLR_EL1, CORTEX_X3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
+ isb
ret
-endfunc cortex_x3_errata_report
-#endif
+endfunc cortex_x3_core_pwr_dwn
+
+errata_report_shim cortex_x3
/* ---------------------------------------------
* This function provides Cortex-X3-
diff --git a/lib/cpus/aarch64/cpu_helpers.S b/lib/cpus/aarch64/cpu_helpers.S
index a4285ed..1ae3180 100644
--- a/lib/cpus/aarch64/cpu_helpers.S
+++ b/lib/cpus/aarch64/cpu_helpers.S
@@ -33,6 +33,15 @@
/* Get the matching cpu_ops pointer */
bl get_cpu_ops_ptr
+#if ENABLE_ASSERTIONS
+ /*
+ * Assert if invalid cpu_ops obtained. If this is not valid, it may
+ * suggest that the proper CPU file hasn't been included.
+ */
+ cmp x0, #0
+ ASM_ASSERT(ne)
+#endif
+
/* Get the cpu_ops reset handler */
ldr x2, [x0, #CPU_RESET_FUNC]
mov x30, x19
diff --git a/lib/cpus/aarch64/cpuamu_helpers.S b/lib/cpus/aarch64/cpuamu_helpers.S
index 5a77fc7..e71e345 100644
--- a/lib/cpus/aarch64/cpuamu_helpers.S
+++ b/lib/cpus/aarch64/cpuamu_helpers.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/cpus/aarch64/denver.S b/lib/cpus/aarch64/denver.S
index 3c54a6f..884281d 100644
--- a/lib/cpus/aarch64/denver.S
+++ b/lib/cpus/aarch64/denver.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2020-2022, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -207,7 +207,14 @@
2: ret
endfunc denver_disable_dco
-func check_errata_cve_2017_5715
+workaround_reset_start denver, CVE(2017, 5715), WORKAROUND_CVE_2017_5715
+#if IMAGE_BL31
+ adr x1, workaround_bpflush_runtime_exceptions
+ msr vbar_el3, x1
+#endif
+workaround_reset_end denver, CVE(2017, 5715)
+
+check_erratum_custom_start denver, CVE(2017, 5715)
mov x0, #ERRATA_MISSING
#if WORKAROUND_CVE_2017_5715
/*
@@ -224,43 +231,9 @@
1:
#endif
ret
-endfunc check_errata_cve_2017_5715
-
-func check_errata_cve_2018_3639
-#if WORKAROUND_CVE_2018_3639
- mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
-#endif
- ret
-endfunc check_errata_cve_2018_3639
-
- /* -------------------------------------------------
- * The CPU Ops reset function for Denver.
- * -------------------------------------------------
- */
-func denver_reset_func
-
- mov x19, x30
-
-#if IMAGE_BL31 && WORKAROUND_CVE_2017_5715
- /*
- * Check if the CPU supports the special instruction
- * required to flush the indirect branch predictor and
- * RSB. Support for this operation can be determined by
- * comparing bits 19:16 of ID_AFR0_EL1 with 0b0001.
- */
- mrs x0, id_afr0_el1
- mov x1, #0x10000
- and x0, x0, x1
- cmp x0, #0
- adr x1, workaround_bpflush_runtime_exceptions
- mrs x2, vbar_el3
- csel x0, x1, x2, ne
- msr vbar_el3, x0
-#endif
+check_erratum_custom_end denver, CVE(2017, 5715)
-#if WORKAROUND_CVE_2018_3639
+workaround_reset_start denver, CVE(2018, 3639), WORKAROUND_CVE_2018_3639
/*
* Denver CPUs with DENVER_MIDR_PN3 or earlier, use different
* bits in the ACTLR_EL3 register to disable speculative
@@ -277,8 +250,11 @@
msr actlr_el3, x0
isb
dsb sy
-#endif
+workaround_reset_end denver, CVE(2018, 3639)
+
+check_erratum_chosen denver, CVE(2018, 3639), WORKAROUND_CVE_2018_3639
+cpu_reset_func_start denver
/* ----------------------------------------------------
* Reset ACTLR.PMSTATE to C1 state
* ----------------------------------------------------
@@ -293,9 +269,7 @@
* ----------------------------------------------------
*/
bl denver_enable_dco
-
- ret x19
-endfunc denver_reset_func
+cpu_reset_func_end denver
/* ----------------------------------------------------
* The CPU Ops core power down function for Denver.
@@ -322,27 +296,7 @@
ret
endfunc denver_cluster_pwr_dwn
-#if REPORT_ERRATA
- /*
- * Errata printing function for Denver. Must follow AAPCS.
- */
-func denver_errata_report
- stp x8, x30, [sp, #-16]!
-
- bl cpu_get_rev_var
- mov x8, x0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata WORKAROUND_CVE_2017_5715, denver, cve_2017_5715
- report_errata WORKAROUND_CVE_2018_3639, denver, cve_2018_3639
-
- ldp x8, x30, [sp], #16
- ret
-endfunc denver_errata_report
-#endif
+errata_report_shim denver
/* ---------------------------------------------
* This function provides Denver specific
@@ -367,7 +321,7 @@
.macro denver_cpu_ops_wa midr
declare_cpu_ops_wa denver, \midr, \
denver_reset_func, \
- check_errata_cve_2017_5715, \
+ check_erratum_denver_5715, \
CPU_NO_EXTRA2_FUNC, \
CPU_NO_EXTRA3_FUNC, \
denver_core_pwr_dwn, \
diff --git a/lib/cpus/aarch64/neoverse_n1_pubsub.c b/lib/cpus/aarch64/neoverse_n1_pubsub.c
index b1b7bb8..ecfb501 100644
--- a/lib/cpus/aarch64/neoverse_n1_pubsub.c
+++ b/lib/cpus/aarch64/neoverse_n1_pubsub.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/cpus/aarch64/neoverse_n2.S b/lib/cpus/aarch64/neoverse_n2.S
index 60d322f..acf8dee 100644
--- a/lib/cpus/aarch64/neoverse_n2.S
+++ b/lib/cpus/aarch64/neoverse_n2.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020-2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2020-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -24,20 +24,17 @@
wa_cve_2022_23960_bhb_vector_table NEOVERSE_N2_BHB_LOOP_COUNT, neoverse_n2
#endif /* WORKAROUND_CVE_2022_23960 */
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N2 Erratum 2002655.
- * This applies to revision r0p0 of Neoverse N2. it is still open.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
+/*
+ * ERRATA_DSU_2313941:
+ * The errata is defined in dsu_helpers.S and applies to Neoverse N2.
+ * Henceforth creating symbolic names to the already existing errata
+ * workaround functions to get them registered under the Errata Framework.
*/
-func errata_n2_2002655_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_2002655
- cbz x0, 1f
+.equ check_erratum_neoverse_n2_2313941, check_errata_dsu_2313941
+.equ erratum_neoverse_n2_2313941_wa, errata_dsu_2313941_wa
+add_erratum_entry neoverse_n2, ERRATUM(2313941), ERRATA_DSU_2313941, APPLY_AT_RESET
+workaround_reset_start neoverse_n2, ERRATUM(2002655), ERRATA_N2_2002655
/* Apply instruction patching sequence */
ldr x0,=0x6
msr S3_6_c15_c8_0,x0
@@ -55,111 +52,33 @@
msr S3_6_c15_c8_3,x0
ldr x0,=0x40000001003f3
msr S3_6_c15_c8_1,x0
- isb
-1:
- ret x17
-endfunc errata_n2_2002655_wa
-
-func check_errata_2002655
- /* Applies to r0p0 */
- mov x1, #0x00
- b cpu_rev_var_ls
-endfunc check_errata_2002655
+workaround_reset_end neoverse_n2, ERRATUM(2002655)
-/* ---------------------------------------------------------------
- * Errata Workaround for Neoverse N2 Erratum 2067956.
- * This applies to revision r0p0 of Neoverse N2 and is still open.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ---------------------------------------------------------------
- */
-func errata_n2_2067956_wa
- /* Compare x0 against revision r0p0 */
- mov x17, x30
- bl check_errata_2067956
- cbz x0, 1f
- mrs x1, NEOVERSE_N2_CPUACTLR_EL1
- orr x1, x1, NEOVERSE_N2_CPUACTLR_EL1_BIT_46
- msr NEOVERSE_N2_CPUACTLR_EL1, x1
-1:
- ret x17
-endfunc errata_n2_2067956_wa
+check_erratum_ls neoverse_n2, ERRATUM(2002655), CPU_REV(0, 0)
-func check_errata_2067956
- /* Applies to r0p0 */
- mov x1, #0x00
- b cpu_rev_var_ls
-endfunc check_errata_2067956
+workaround_reset_start neoverse_n2, ERRATUM(2025414), ERRATA_N2_2025414
+ sysreg_bit_set NEOVERSE_N2_CPUECTLR_EL1, NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT
+workaround_reset_end neoverse_n2, ERRATUM(2025414)
-/* ---------------------------------------------------------------
- * Errata Workaround for Neoverse N2 Erratum 2025414.
- * This applies to revision r0p0 of Neoverse N2 and is still open.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ---------------------------------------------------------------
- */
-func errata_n2_2025414_wa
- /* Compare x0 against revision r0p0 */
- mov x17, x30
- bl check_errata_2025414
- cbz x0, 1f
- mrs x1, NEOVERSE_N2_CPUECTLR_EL1
- orr x1, x1, NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT
- msr NEOVERSE_N2_CPUECTLR_EL1, x1
+check_erratum_ls neoverse_n2, ERRATUM(2025414), CPU_REV(0, 0)
-1:
- ret x17
-endfunc errata_n2_2025414_wa
+workaround_reset_start neoverse_n2, ERRATUM(2067956), ERRATA_N2_2067956
+ sysreg_bit_set NEOVERSE_N2_CPUACTLR_EL1, NEOVERSE_N2_CPUACTLR_EL1_BIT_46
+workaround_reset_end neoverse_n2, ERRATUM(2067956)
-func check_errata_2025414
- /* Applies to r0p0 */
- mov x1, #0x00
- b cpu_rev_var_ls
-endfunc check_errata_2025414
+check_erratum_ls neoverse_n2, ERRATUM(2067956), CPU_REV(0, 0)
-/* ---------------------------------------------------------------
- * Errata Workaround for Neoverse N2 Erratum 2189731.
- * This applies to revision r0p0 of Neoverse N2 and is still open.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ---------------------------------------------------------------
- */
-func errata_n2_2189731_wa
- /* Compare x0 against revision r0p0 */
- mov x17, x30
- bl check_errata_2189731
- cbz x0, 1f
- mrs x1, NEOVERSE_N2_CPUACTLR5_EL1
- orr x1, x1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_44
- msr NEOVERSE_N2_CPUACTLR5_EL1, x1
-
-1:
- ret x17
-endfunc errata_n2_2189731_wa
-
-func check_errata_2189731
- /* Applies to r0p0 */
- mov x1, #0x00
- b cpu_rev_var_ls
-endfunc check_errata_2189731
+workaround_reset_start neoverse_n2, ERRATUM(2138953), ERRATA_N2_2138953
+ /* Apply instruction patching sequence */
+ mrs x1, NEOVERSE_N2_CPUECTLR2_EL1
+ mov x0, #NEOVERSE_N2_CPUECTLR2_EL1_PF_MODE_CNSRV
+ bfi x1, x0, #CPUECTLR2_EL1_PF_MODE_LSB, #CPUECTLR2_EL1_PF_MODE_WIDTH
+ msr NEOVERSE_N2_CPUECTLR2_EL1, x1
+workaround_reset_end neoverse_n2, ERRATUM(2138953)
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N2 Erratum 2138956.
- * This applies to revision r0p0 of Neoverse N2. it is still open.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_n2_2138956_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_2138956
- cbz x0, 1f
+check_erratum_ls neoverse_n2, ERRATUM(2138953), CPU_REV(0, 3)
+workaround_reset_start neoverse_n2, ERRATUM(2138956), ERRATA_N2_2138956
/* Apply instruction patching sequence */
ldr x0,=0x3
msr S3_6_c15_c8_0,x0
@@ -177,120 +96,27 @@
msr S3_6_c15_c8_3,x0
ldr x0,=0x10002001003F3
msr S3_6_c15_c8_1,x0
- isb
-1:
- ret x17
-endfunc errata_n2_2138956_wa
+workaround_reset_end neoverse_n2, ERRATUM(2138956)
-func check_errata_2138956
- /* Applies to r0p0 */
- mov x1, #0x00
- b cpu_rev_var_ls
-endfunc check_errata_2138956
+check_erratum_ls neoverse_n2, ERRATUM(2138956), CPU_REV(0, 0)
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N2 Erratum 2242415.
- * This applies to revision r0p0 of Neoverse N2. it is still open.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x1, x17
- * --------------------------------------------------
- */
-func errata_n2_2242415_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_2242415
- cbz x0, 1f
+workaround_reset_start neoverse_n2, ERRATUM(2138958), ERRATA_N2_2138958
/* Apply instruction patching sequence */
- mrs x1, NEOVERSE_N2_CPUACTLR_EL1
- orr x1, x1, NEOVERSE_N2_CPUACTLR_EL1_BIT_22
- msr NEOVERSE_N2_CPUACTLR_EL1, x1
-1:
- ret x17
-endfunc errata_n2_2242415_wa
+ sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_13
+workaround_reset_end neoverse_n2, ERRATUM(2138958)
-func check_errata_2242415
- /* Applies to r0p0 */
- mov x1, #0x00
- b cpu_rev_var_ls
-endfunc check_errata_2242415
+check_erratum_ls neoverse_n2, ERRATUM(2138958), CPU_REV(0, 0)
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N2 Erratum 2138953.
- * This applies to revision r0p0 of Neoverse N2. it is still open.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x1, x17
- * --------------------------------------------------
- */
-func errata_n2_2138953_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_2138953
- cbz x0, 1f
+workaround_reset_start neoverse_n2, ERRATUM(2189731), ERRATA_N2_2189731
+ sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_44
+workaround_reset_end neoverse_n2, ERRATUM(2189731)
- /* Apply instruction patching sequence */
- mrs x1, NEOVERSE_N2_CPUECTLR2_EL1
- mov x0, #NEOVERSE_N2_CPUECTLR2_EL1_PF_MODE_CNSRV
- bfi x1, x0, #CPUECTLR2_EL1_PF_MODE_LSB, #CPUECTLR2_EL1_PF_MODE_WIDTH
- msr NEOVERSE_N2_CPUECTLR2_EL1, x1
-1:
- ret x17
-endfunc errata_n2_2138953_wa
+check_erratum_ls neoverse_n2, ERRATUM(2189731), CPU_REV(0, 0)
-func check_errata_2138953
- /* Applies to r0p0 */
- mov x1, #0x00
- b cpu_rev_var_ls
-endfunc check_errata_2138953
-
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N2 Erratum 2138958.
- * This applies to revision r0p0 of Neoverse N2. it is still open.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x1, x17
- * --------------------------------------------------
- */
-func errata_n2_2138958_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_2138958
- cbz x0, 1f
-
- /* Apply instruction patching sequence */
- mrs x1, NEOVERSE_N2_CPUACTLR5_EL1
- orr x1, x1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_13
- msr NEOVERSE_N2_CPUACTLR5_EL1, x1
-1:
- ret x17
-endfunc errata_n2_2138958_wa
-
-func check_errata_2138958
- /* Applies to r0p0 */
- mov x1, #0x00
- b cpu_rev_var_ls
-endfunc check_errata_2138958
-
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N2 Erratum 2242400.
- * This applies to revision r0p0 of Neoverse N2. it is still open.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x1, x17
- * --------------------------------------------------
- */
-func errata_n2_2242400_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_2242400
- cbz x0, 1f
-
+workaround_reset_start neoverse_n2, ERRATUM(2242400), ERRATA_N2_2242400
/* Apply instruction patching sequence */
- mrs x1, NEOVERSE_N2_CPUACTLR5_EL1
- orr x1, x1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_17
- msr NEOVERSE_N2_CPUACTLR5_EL1, x1
+ sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_17
ldr x0, =0x2
msr S3_6_c15_c8_0, x0
ldr x0, =0x10F600E000
@@ -299,174 +125,86 @@
msr S3_6_c15_c8_3, x0
ldr x0, =0x80000000003FF
msr S3_6_c15_c8_1, x0
- isb
-1:
- ret x17
-endfunc errata_n2_2242400_wa
+workaround_reset_end neoverse_n2, ERRATUM(2242400)
-func check_errata_2242400
- /* Applies to r0p0 */
- mov x1, #0x00
- b cpu_rev_var_ls
-endfunc check_errata_2242400
+check_erratum_ls neoverse_n2, ERRATUM(2242400), CPU_REV(0, 0)
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N2 Erratum 2280757.
- * This applies to revision r0p0 of Neoverse N2. it is still open.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x1, x17
- * --------------------------------------------------
- */
-func errata_n2_2280757_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_2280757
- cbz x0, 1f
+workaround_reset_start neoverse_n2, ERRATUM(2242415), ERRATA_N2_2242415
+ sysreg_bit_set NEOVERSE_N2_CPUACTLR_EL1, NEOVERSE_N2_CPUACTLR_EL1_BIT_22
+workaround_reset_end neoverse_n2, ERRATUM(2242415)
- /* Apply instruction patching sequence */
- mrs x1, NEOVERSE_N2_CPUACTLR_EL1
- orr x1, x1, NEOVERSE_N2_CPUACTLR_EL1_BIT_22
- msr NEOVERSE_N2_CPUACTLR_EL1, x1
-1:
- ret x17
-endfunc errata_n2_2280757_wa
+check_erratum_ls neoverse_n2, ERRATUM(2242415), CPU_REV(0, 0)
-func check_errata_2280757
- /* Applies to r0p0 */
- mov x1, #0x00
- b cpu_rev_var_ls
-endfunc check_errata_2280757
+workaround_reset_start neoverse_n2, ERRATUM(2280757), ERRATA_N2_2280757
+ /* Apply instruction patching sequence */
+ sysreg_bit_set NEOVERSE_N2_CPUACTLR_EL1, NEOVERSE_N2_CPUACTLR_EL1_BIT_22
+workaround_reset_end neoverse_n2, ERRATUM(2280757)
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N2 Erratum 2326639.
- * This applies to revision r0p0 of Neoverse N2,
- * fixed in r0p1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x1, x17
- * --------------------------------------------------
- */
-func errata_n2_2326639_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_2326639
- cbz x0, 1f
+check_erratum_ls neoverse_n2, ERRATUM(2280757), CPU_REV(0, 0)
+workaround_runtime_start neoverse_n2, ERRATUM(2326639), ERRATA_N2_2326639
/* Set bit 36 in ACTLR2_EL1 */
- mrs x1, NEOVERSE_N2_CPUACTLR2_EL1
- orr x1, x1, #NEOVERSE_N2_CPUACTLR2_EL1_BIT_36
- msr NEOVERSE_N2_CPUACTLR2_EL1, x1
-1:
- ret x17
-endfunc errata_n2_2326639_wa
+ sysreg_bit_set NEOVERSE_N2_CPUACTLR2_EL1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_36
+workaround_runtime_end neoverse_n2, ERRATUM(2326639)
-func check_errata_2326639
- /* Applies to r0p0, fixed in r0p1 */
- mov x1, #0x00
- b cpu_rev_var_ls
-endfunc check_errata_2326639
+check_erratum_ls neoverse_n2, ERRATUM(2326639), CPU_REV(0, 0)
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N2 Erratum 2376738.
- * This applies to revision r0p0 of Neoverse N2,
- * fixed in r0p1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current CPU.
- * Shall clobber: x0-x1, x17
- * --------------------------------------------------
- */
-func errata_n2_2376738_wa
- mov x17, x30
- bl check_errata_2376738
- cbz x0, 1f
-
+workaround_reset_start neoverse_n2, ERRATUM(2376738), ERRATA_N2_2376738
/* Set CPUACTLR2_EL1[0] to 1 to force PLDW/PFRM
* ST to behave like PLD/PFRM LD and not cause
* invalidations to other PE caches.
*/
- mrs x1, NEOVERSE_N2_CPUACTLR2_EL1
- orr x1, x1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_0
- msr NEOVERSE_N2_CPUACTLR2_EL1, x1
-1:
- ret x17
-endfunc errata_n2_2376738_wa
-
-func check_errata_2376738
- /* Applies to r0p0, fixed in r0p1 */
- mov x1, 0x00
- b cpu_rev_var_ls
-endfunc check_errata_2376738
+ sysreg_bit_set NEOVERSE_N2_CPUACTLR2_EL1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_0
+workaround_reset_end neoverse_n2, ERRATUM(2376738)
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N2 Erratum 2388450.
- * This applies to revision r0p0 of Neoverse N2,
- * fixed in r0p1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x1, x17
- * --------------------------------------------------
- */
-func errata_n2_2388450_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_2388450
- cbz x0, 1f
+check_erratum_ls neoverse_n2, ERRATUM(2376738), CPU_REV(0, 3)
+workaround_reset_start neoverse_n2, ERRATUM(2388450), ERRATA_N2_2388450
/*Set bit 40 in ACTLR2_EL1 */
- mrs x1, NEOVERSE_N2_CPUACTLR2_EL1
- orr x1, x1, #NEOVERSE_N2_CPUACTLR2_EL1_BIT_40
- msr NEOVERSE_N2_CPUACTLR2_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_n2_2388450_wa
+ sysreg_bit_set NEOVERSE_N2_CPUACTLR2_EL1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_40
+workaround_reset_end neoverse_n2, ERRATUM(2388450)
-func check_errata_2388450
- /* Applies to r0p0, fixed in r0p1 */
- mov x1, #0x00
- b cpu_rev_var_ls
-endfunc check_errata_2388450
+check_erratum_ls neoverse_n2, ERRATUM(2388450), CPU_REV(0, 0)
-/* -------------------------------------------------------
- * Errata Workaround for Neoverse N2 Erratum 2743089.
- * This applies to revisions <= r0p2 and is fixed in r0p3.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * -------------------------------------------------------
- */
-func errata_n2_2743089_wa
- mov x17, x30
- bl check_errata_2743089
- cbz x0, 1f
+workaround_reset_start neoverse_n2, ERRATUM(2743014), ERRATA_N2_2743014
+ /* Set CPUACTLR5_EL1[56:55] to 2'b01 */
+ sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_55
+ sysreg_bit_clear NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_56
+workaround_reset_end neoverse_n2, ERRATUM(2743014)
+check_erratum_ls neoverse_n2, ERRATUM(2743014), CPU_REV(0, 2)
+
+workaround_runtime_start neoverse_n2, ERRATUM(2743089), ERRATA_N2_2743089
/* dsb before isb of power down sequence */
dsb sy
-1:
- ret x17
-endfunc errata_n2_2743089_wa
+workaround_runtime_end neoverse_n2, ERRATUM(2743089)
-func check_errata_2743089
- /* Applies to all revisions <= r0p2 */
- mov x1, #0x02
- b cpu_rev_var_ls
-endfunc check_errata_2743089
+check_erratum_ls neoverse_n2, ERRATUM(2743089), CPU_REV(0, 2)
-func check_errata_cve_2022_23960
-#if WORKAROUND_CVE_2022_23960
- mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
-#endif
- ret
-endfunc check_errata_cve_2022_23960
+workaround_reset_start neoverse_n2, ERRATUM(2779511), ERRATA_N2_2779511
+ /* Set bit 47 in ACTLR3_EL1 */
+ sysreg_bit_set NEOVERSE_N2_CPUACTLR3_EL1, NEOVERSE_N2_CPUACTLR3_EL1_BIT_47
+workaround_reset_end neoverse_n2, ERRATUM(2779511)
+
+check_erratum_ls neoverse_n2, ERRATUM(2779511), CPU_REV(0, 2)
+
+workaround_reset_start neoverse_n2, CVE(2022,23960), WORKAROUND_CVE_2022_23960
+#if IMAGE_BL31
+ /*
+ * The Neoverse-N2 generic vectors are overridden to apply errata
+ * mitigation on exception entry from lower ELs.
+ */
+ override_vector_table wa_cve_vbar_neoverse_n2
+#endif /* IMAGE_BL31 */
+workaround_reset_end neoverse_n2, CVE(2022,23960)
+
+check_erratum_chosen neoverse_n2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
/* -------------------------------------------
* The CPU Ops reset function for Neoverse N2.
* -------------------------------------------
*/
-func neoverse_n2_reset_func
- mov x19, x30
+cpu_reset_func_start neoverse_n2
/* Check if the PE implements SSBS */
mrs x0, id_aa64pfr1_el1
@@ -477,174 +215,39 @@
msr SSBS, xzr
1:
/* Force all cacheable atomic instructions to be near */
- mrs x0, NEOVERSE_N2_CPUACTLR2_EL1
- orr x0, x0, #NEOVERSE_N2_CPUACTLR2_EL1_BIT_2
- msr NEOVERSE_N2_CPUACTLR2_EL1, x0
-
- /* Get the CPU revision and stash it in x18. */
- bl cpu_get_rev_var
- mov x18, x0
-
-#if ERRATA_DSU_2313941
- bl errata_dsu_2313941_wa
-#endif
-
-#if ERRATA_N2_2067956
- mov x0, x18
- bl errata_n2_2067956_wa
-#endif
-
-#if ERRATA_N2_2025414
- mov x0, x18
- bl errata_n2_2025414_wa
-#endif
-
-#if ERRATA_N2_2189731
- mov x0, x18
- bl errata_n2_2189731_wa
-#endif
-
-
-#if ERRATA_N2_2138956
- mov x0, x18
- bl errata_n2_2138956_wa
-#endif
-
-#if ERRATA_N2_2138953
- mov x0, x18
- bl errata_n2_2138953_wa
-#endif
-
-#if ERRATA_N2_2242415
- mov x0, x18
- bl errata_n2_2242415_wa
-#endif
-
-#if ERRATA_N2_2138958
- mov x0, x18
- bl errata_n2_2138958_wa
-#endif
-
-#if ERRATA_N2_2242400
- mov x0, x18
- bl errata_n2_2242400_wa
-#endif
-
-#if ERRATA_N2_2280757
- mov x0, x18
- bl errata_n2_2280757_wa
-#endif
-
-#if ERRATA_N2_2376738
- mov x0, x18
- bl errata_n2_2376738_wa
-#endif
-
-#if ERRATA_N2_2388450
- mov x0, x18
- bl errata_n2_2388450_wa
-#endif
+ sysreg_bit_set NEOVERSE_N2_CPUACTLR2_EL1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_2
#if ENABLE_FEAT_AMU
/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
- mrs x0, cptr_el3
- orr x0, x0, #TAM_BIT
- msr cptr_el3, x0
-
+ sysreg_bit_set cptr_el3, TAM_BIT
/* Make sure accesses from EL0/EL1 are not trapped to EL2 */
- mrs x0, cptr_el2
- orr x0, x0, #TAM_BIT
- msr cptr_el2, x0
-
+ sysreg_bit_set cptr_el2, TAM_BIT
/* No need to enable the counters as this would be done at el3 exit */
#endif
#if NEOVERSE_Nx_EXTERNAL_LLC
/* Some systems may have External LLC, core needs to be made aware */
- mrs x0, NEOVERSE_N2_CPUECTLR_EL1
- orr x0, x0, NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT
- msr NEOVERSE_N2_CPUECTLR_EL1, x0
-#endif
-
-#if ERRATA_N2_2002655
- mov x0, x18
- bl errata_n2_2002655_wa
+ sysreg_bit_set NEOVERSE_N2_CPUECTLR_EL1, NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT
#endif
-
-#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
- /*
- * The Neoverse-N2 generic vectors are overridden to apply errata
- * mitigation on exception entry from lower ELs.
- */
- adr x0, wa_cve_vbar_neoverse_n2
- msr vbar_el3, x0
-#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
-
- isb
- ret x19
-endfunc neoverse_n2_reset_func
+cpu_reset_func_end neoverse_n2
func neoverse_n2_core_pwr_dwn
-#if ERRATA_N2_2326639
- mov x15, x30
- bl cpu_get_rev_var
- bl errata_n2_2326639_wa
- mov x30, x15
-#endif /* ERRATA_N2_2326639 */
+ apply_erratum neoverse_n2, ERRATUM(2326639), ERRATA_N2_2326639
/* ---------------------------------------------------
* Enable CPU power down bit in power control register
* No need to do cache maintenance here.
* ---------------------------------------------------
*/
- mrs x0, NEOVERSE_N2_CPUPWRCTLR_EL1
- orr x0, x0, #NEOVERSE_N2_CORE_PWRDN_EN_BIT
- msr NEOVERSE_N2_CPUPWRCTLR_EL1, x0
-#if ERRATA_N2_2743089
- mov x15, x30
- bl cpu_get_rev_var
- bl errata_n2_2743089_wa
- mov x30, x15
-#endif /* ERRATA_N2_2743089 */
+ sysreg_bit_set NEOVERSE_N2_CPUPWRCTLR_EL1, NEOVERSE_N2_CORE_PWRDN_EN_BIT
+
+ apply_erratum neoverse_n2, ERRATUM(2743089), ERRATA_N2_2743089
+
isb
ret
endfunc neoverse_n2_core_pwr_dwn
-#if REPORT_ERRATA
-/*
- * Errata printing function for Neoverse N2 cores. Must follow AAPCS.
- */
-func neoverse_n2_errata_report
- stp x8, x30, [sp, #-16]!
-
- bl cpu_get_rev_var
- mov x8, x0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata ERRATA_N2_2002655, neoverse_n2, 2002655
- report_errata ERRATA_N2_2067956, neoverse_n2, 2067956
- report_errata ERRATA_N2_2025414, neoverse_n2, 2025414
- report_errata ERRATA_N2_2189731, neoverse_n2, 2189731
- report_errata ERRATA_N2_2138956, neoverse_n2, 2138956
- report_errata ERRATA_N2_2138953, neoverse_n2, 2138953
- report_errata ERRATA_N2_2242415, neoverse_n2, 2242415
- report_errata ERRATA_N2_2138958, neoverse_n2, 2138958
- report_errata ERRATA_N2_2242400, neoverse_n2, 2242400
- report_errata ERRATA_N2_2280757, neoverse_n2, 2280757
- report_errata ERRATA_N2_2326639, neoverse_n2, 2326639
- report_errata ERRATA_N2_2376738, neoverse_n2, 2376738
- report_errata ERRATA_N2_2388450, neoverse_n2, 2388450
- report_errata ERRATA_N2_2743089, neoverse_n2, 2743089
- report_errata WORKAROUND_CVE_2022_23960, neoverse_n2, cve_2022_23960
- report_errata ERRATA_DSU_2313941, neoverse_n2, dsu_2313941
-
- ldp x8, x30, [sp], #16
- ret
-endfunc neoverse_n2_errata_report
-#endif
+errata_report_shim neoverse_n2
/* ---------------------------------------------
* This function provides Neoverse N2 specific
diff --git a/lib/cpus/aarch64/neoverse_poseidon.S b/lib/cpus/aarch64/neoverse_poseidon.S
index 030293d..3b3245d 100644
--- a/lib/cpus/aarch64/neoverse_poseidon.S
+++ b/lib/cpus/aarch64/neoverse_poseidon.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2022-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -26,6 +26,19 @@
wa_cve_2022_23960_bhb_vector_table NEOVERSE_POSEIDON_BHB_LOOP_COUNT, neoverse_poseidon
#endif /* WORKAROUND_CVE_2022_23960 */
+workaround_reset_start neoverse_poseidon, CVE(2022,23960), WORKAROUND_CVE_2022_23960
+#if IMAGE_BL31
+ /*
+ * The Neoverse-poseidon generic vectors are overridden to apply errata
+ * mitigation on exception entry from lower ELs.
+ */
+ override_vector_table wa_cve_vbar_neoverse_poseidon
+
+#endif /* IMAGE_BL31 */
+workaround_reset_end neoverse_poseidon, CVE(2022,23960)
+
+check_erratum_chosen neoverse_poseidon, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
+
/* ---------------------------------------------
* HW will do the cache maintenance while powering down
* ---------------------------------------------
@@ -35,59 +48,19 @@
* Enable CPU power down bit in power control register
* ---------------------------------------------
*/
- mrs x0, NEOVERSE_POSEIDON_CPUPWRCTLR_EL1
- orr x0, x0, #NEOVERSE_POSEIDON_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
- msr NEOVERSE_POSEIDON_CPUPWRCTLR_EL1, x0
+ sysreg_bit_set NEOVERSE_POSEIDON_CPUPWRCTLR_EL1, \
+ NEOVERSE_POSEIDON_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
+
isb
ret
endfunc neoverse_poseidon_core_pwr_dwn
-func check_errata_cve_2022_23960
-#if WORKAROUND_CVE_2022_23960
- mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
-#endif
- ret
-endfunc check_errata_cve_2022_23960
-
-func neoverse_poseidon_reset_func
+cpu_reset_func_start neoverse_poseidon
/* Disable speculative loads */
msr SSBS, xzr
+cpu_reset_func_end neoverse_poseidon
-#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
- /*
- * The Neoverse Poseidon generic vectors are overridden to apply
- * errata mitigation on exception entry from lower ELs.
- */
- adr x0, wa_cve_vbar_neoverse_poseidon
- msr vbar_el3, x0
-#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
-
- isb
- ret
-endfunc neoverse_poseidon_reset_func
-
-#if REPORT_ERRATA
- /*
- * Errata printing function for Neoverse Poseidon. Must follow AAPCS.
- */
-func neoverse_poseidon_errata_report
- stp x8, x30, [sp, #-16]!
-
- bl cpu_get_rev_var
- mov x8, x0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata WORKAROUND_CVE_2022_23960, neoverse_poseidon, cve_2022_23960
-
- ldp x8, x30, [sp], #16
- ret
-endfunc neoverse_poseidon_errata_report
-#endif
+errata_report_shim neoverse_poseidon
/* ---------------------------------------------
* This function provides Neoverse-Poseidon specific
diff --git a/lib/cpus/aarch64/neoverse_v1.S b/lib/cpus/aarch64/neoverse_v1.S
index 363c2e6..35d2c48 100644
--- a/lib/cpus/aarch64/neoverse_v1.S
+++ b/lib/cpus/aarch64/neoverse_v1.S
@@ -26,20 +26,7 @@
wa_cve_2022_23960_bhb_vector_table NEOVERSE_V1_BHB_LOOP_COUNT, neoverse_v1
#endif /* WORKAROUND_CVE_2022_23960 */
- /* --------------------------------------------------
- * Errata Workaround for Neoverse V1 Errata #1618635.
- * This applies to revision r0p0 and is fixed in
- * r1p0.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x17
- * --------------------------------------------------
- */
-func errata_neoverse_v1_1618635_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_1618635
- cbz x0, 1f
-
+workaround_reset_start neoverse_v1, ERRATUM(1618635), ERRATA_V1_1618635
/* Inserts a DMB SY before and after MRS PAR_EL1 */
ldr x0, =0x0
msr NEOVERSE_V1_CPUPSELR_EL3, x0
@@ -90,146 +77,39 @@
ldr x0, = 0x4004027FF
msr NEOVERSE_V1_CPUPCR_EL3, x0
- /* Synchronize to enable patches */
- isb
-1:
- ret x17
-endfunc errata_neoverse_v1_1618635_wa
-
-func check_errata_1618635
- /* Applies to revision r0p0. */
- mov x1, #0x00
- b cpu_rev_var_ls
-endfunc check_errata_1618635
+workaround_reset_end neoverse_v1, ERRATUM(1618635)
- /* --------------------------------------------------
- * Errata Workaround for Neoverse V1 Errata #1774420.
- * This applies to revisions r0p0 and r1p0, fixed in r1p1.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_neoverse_v1_1774420_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_1774420
- cbz x0, 1f
+check_erratum_ls neoverse_v1, ERRATUM(1618635), CPU_REV(0, 0)
+workaround_reset_start neoverse_v1, ERRATUM(1774420), ERRATA_V1_1774420
/* Set bit 53 in CPUECTLR_EL1 */
- mrs x1, NEOVERSE_V1_CPUECTLR_EL1
- orr x1, x1, #NEOVERSE_V1_CPUECTLR_EL1_BIT_53
- msr NEOVERSE_V1_CPUECTLR_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_neoverse_v1_1774420_wa
+ sysreg_bit_set NEOVERSE_V1_CPUECTLR_EL1, NEOVERSE_V1_CPUECTLR_EL1_BIT_53
+workaround_reset_end neoverse_v1, ERRATUM(1774420)
-func check_errata_1774420
- /* Applies to r0p0 and r1p0. */
- mov x1, #0x10
- b cpu_rev_var_ls
-endfunc check_errata_1774420
+check_erratum_ls neoverse_v1, ERRATUM(1774420), CPU_REV(1, 0)
- /* --------------------------------------------------
- * Errata Workaround for Neoverse V1 Errata #1791573.
- * This applies to revisions r0p0 and r1p0, fixed in r1p1.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_neoverse_v1_1791573_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_1791573
- cbz x0, 1f
-
+workaround_reset_start neoverse_v1, ERRATUM(1791573), ERRATA_V1_1791573
/* Set bit 2 in ACTLR2_EL1 */
- mrs x1, NEOVERSE_V1_ACTLR2_EL1
- orr x1, x1, #NEOVERSE_V1_ACTLR2_EL1_BIT_2
- msr NEOVERSE_V1_ACTLR2_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_neoverse_v1_1791573_wa
+ sysreg_bit_set NEOVERSE_V1_ACTLR2_EL1, NEOVERSE_V1_ACTLR2_EL1_BIT_2
+workaround_reset_end neoverse_v1, ERRATUM(1791573)
-func check_errata_1791573
- /* Applies to r0p0 and r1p0. */
- mov x1, #0x10
- b cpu_rev_var_ls
-endfunc check_errata_1791573
+check_erratum_ls neoverse_v1, ERRATUM(1791573), CPU_REV(1, 0)
- /* --------------------------------------------------
- * Errata Workaround for Neoverse V1 Errata #1852267.
- * This applies to revisions r0p0 and r1p0, fixed in r1p1.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_neoverse_v1_1852267_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_1852267
- cbz x0, 1f
-
+workaround_reset_start neoverse_v1, ERRATUM(1852267), ERRATA_V1_1852267
/* Set bit 28 in ACTLR2_EL1 */
- mrs x1, NEOVERSE_V1_ACTLR2_EL1
- orr x1, x1, #NEOVERSE_V1_ACTLR2_EL1_BIT_28
- msr NEOVERSE_V1_ACTLR2_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_neoverse_v1_1852267_wa
+ sysreg_bit_set NEOVERSE_V1_ACTLR2_EL1, NEOVERSE_V1_ACTLR2_EL1_BIT_28
+workaround_reset_end neoverse_v1, ERRATUM(1852267)
-func check_errata_1852267
- /* Applies to r0p0 and r1p0. */
- mov x1, #0x10
- b cpu_rev_var_ls
-endfunc check_errata_1852267
+check_erratum_ls neoverse_v1, ERRATUM(1852267), CPU_REV(1, 0)
- /* --------------------------------------------------
- * Errata Workaround for Neoverse V1 Errata #1925756.
- * This applies to revisions <= r1p1.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_neoverse_v1_1925756_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_1925756
- cbz x0, 1f
-
+workaround_reset_start neoverse_v1, ERRATUM(1925756), ERRATA_V1_1925756
/* Set bit 8 in CPUECTLR_EL1 */
- mrs x1, NEOVERSE_V1_CPUECTLR_EL1
- orr x1, x1, #NEOVERSE_V1_CPUECTLR_EL1_BIT_8
- msr NEOVERSE_V1_CPUECTLR_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_neoverse_v1_1925756_wa
+ sysreg_bit_set NEOVERSE_V1_CPUECTLR_EL1, NEOVERSE_V1_CPUECTLR_EL1_BIT_8
+workaround_reset_end neoverse_v1, ERRATUM(1925756)
-func check_errata_1925756
- /* Applies to <= r1p1. */
- mov x1, #0x11
- b cpu_rev_var_ls
-endfunc check_errata_1925756
+check_erratum_ls neoverse_v1, ERRATUM(1925756), CPU_REV(1, 1)
- /* --------------------------------------------------
- * Errata Workaround for Neoverse V1 Erratum #1940577
- * This applies to revisions r1p0 - r1p1 and is open.
- * It also exists in r0p0 but there is no fix in that
- * revision.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_neoverse_v1_1940577_wa
- /* Compare x0 against revisions r1p0 - r1p1 */
- mov x17, x30
- bl check_errata_1940577
- cbz x0, 1f
-
+workaround_reset_start neoverse_v1, ERRATUM(1940577), ERRATA_V1_1940577
mov x0, #0
msr S3_6_C15_C8_0, x0
ldr x0, =0x10E3900002
@@ -257,34 +137,11 @@
ldr x0, =0x2001003FF
msr S3_6_C15_C8_1, x0
- isb
-1:
- ret x17
-endfunc errata_neoverse_v1_1940577_wa
+workaround_reset_end neoverse_v1, ERRATUM(1940577)
-func check_errata_1940577
- /* Applies to revisions r1p0 - r1p1. */
- mov x1, #0x10
- mov x2, #0x11
- b cpu_rev_var_range
-endfunc check_errata_1940577
+check_erratum_range neoverse_v1, ERRATUM(1940577), CPU_REV(1, 0), CPU_REV(1, 1)
- /* --------------------------------------------------
- * Errata Workaround for Neoverse V1 Errata #1966096
- * This applies to revisions r1p0 - r1p1 and is open.
- * It also exists in r0p0 but there is no workaround
- * for that revision.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_neoverse_v1_1966096_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_1966096
- cbz x0, 1f
-
- /* Apply the workaround. */
+workaround_reset_start neoverse_v1, ERRATUM(1966096), ERRATA_V1_1966096
mov x0, #0x3
msr S3_6_C15_C8_0, x0
ldr x0, =0xEE010F12
@@ -293,33 +150,20 @@
msr S3_6_C15_C8_3, x0
ldr x0, =0x80000000003FF
msr S3_6_C15_C8_1, x0
- isb
+workaround_reset_end neoverse_v1, ERRATUM(1966096)
-1:
- ret x17
-endfunc errata_neoverse_v1_1966096_wa
+check_erratum_range neoverse_v1, ERRATUM(1966096), CPU_REV(1, 0), CPU_REV(1, 1)
-func check_errata_1966096
- mov x1, #0x10
- mov x2, #0x11
- b cpu_rev_var_range
-endfunc check_errata_1966096
+workaround_reset_start neoverse_v1, ERRATUM(2108267), ERRATA_V1_2108267
+ mrs x1, NEOVERSE_V1_CPUECTLR_EL1
+ mov x0, #NEOVERSE_V1_CPUECTLR_EL1_PF_MODE_CNSRV
+ bfi x1, x0, #CPUECTLR_EL1_PF_MODE_LSB, #CPUECTLR_EL1_PF_MODE_WIDTH
+ msr NEOVERSE_V1_CPUECTLR_EL1, x1
+workaround_reset_end neoverse_v1, ERRATUM(2108267)
- /* --------------------------------------------------
- * Errata Workaround for Neoverse V1 Errata #2139242.
- * This applies to revisions r0p0, r1p0, and r1p1, it
- * is still open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_neoverse_v1_2139242_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_2139242
- cbz x0, 1f
+check_erratum_ls neoverse_v1, ERRATUM(2108267), CPU_REV(1, 1)
- /* Apply the workaround. */
+workaround_reset_start neoverse_v1, ERRATUM(2139242), ERRATA_V1_2139242
mov x0, #0x3
msr S3_6_C15_C8_0, x0
ldr x0, =0xEE720F14
@@ -328,63 +172,11 @@
msr S3_6_C15_C8_3, x0
ldr x0, =0x40000005003FF
msr S3_6_C15_C8_1, x0
- isb
+workaround_reset_end neoverse_v1, ERRATUM(2139242)
-1:
- ret x17
-endfunc errata_neoverse_v1_2139242_wa
+check_erratum_ls neoverse_v1, ERRATUM(2139242), CPU_REV(1, 1)
-func check_errata_2139242
- /* Applies to r0p0, r1p0, r1p1 */
- mov x1, #0x11
- b cpu_rev_var_ls
-endfunc check_errata_2139242
-
- /* --------------------------------------------------
- * Errata Workaround for Neoverse V1 Errata #2108267.
- * This applies to revisions r0p0, r1p0, and r1p1, it
- * is still open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x1, x17
- * --------------------------------------------------
- */
-func errata_neoverse_v1_2108267_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_2108267
- cbz x0, 1f
-
- /* Apply the workaround. */
- mrs x1, NEOVERSE_V1_CPUECTLR_EL1
- mov x0, #NEOVERSE_V1_CPUECTLR_EL1_PF_MODE_CNSRV
- bfi x1, x0, #CPUECTLR_EL1_PF_MODE_LSB, #CPUECTLR_EL1_PF_MODE_WIDTH
- msr NEOVERSE_V1_CPUECTLR_EL1, x1
-1:
- ret x17
-endfunc errata_neoverse_v1_2108267_wa
-
-func check_errata_2108267
- /* Applies to r0p0, r1p0, r1p1 */
- mov x1, #0x11
- b cpu_rev_var_ls
-endfunc check_errata_2108267
-
- /* --------------------------------------------------
- * Errata Workaround for Neoverse V1 Errata #2216392.
- * This applies to revisions r1p0 and r1p1 and is
- * still open.
- * This issue is also present in r0p0 but there is no
- * workaround in that revision.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_neoverse_v1_2216392_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_2216392
- cbz x0, 1f
-
+workaround_reset_start neoverse_v1, ERRATUM(2216392), ERRATA_V1_2216392
ldr x0, =0x5
msr S3_6_c15_c8_0, x0 /* CPUPSELR_EL3 */
ldr x0, =0x10F600E000
@@ -393,167 +185,56 @@
msr S3_6_c15_c8_3, x0 /* CPUPMR_EL3 */
ldr x0, =0x80000000003FF
msr S3_6_c15_c8_1, x0 /* CPUPCR_EL3 */
+workaround_reset_end neoverse_v1, ERRATUM(2216392)
- isb
-1:
- ret x17
-endfunc errata_neoverse_v1_2216392_wa
+check_erratum_range neoverse_v1, ERRATUM(2216392), CPU_REV(1, 0), CPU_REV(1, 1)
-func check_errata_2216392
- /* Applies to revisions r1p0 and r1p1. */
- mov x1, #CPU_REV(1, 0)
- mov x2, #CPU_REV(1, 1)
- b cpu_rev_var_range
-endfunc check_errata_2216392
-
- /* -----------------------------------------------------------------
- * Errata Workaround for Neoverse V1 Errata #2294912.
- * This applies to revisions r0p0, r1p0, and r1p1 and is still open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * -----------------------------------------------------------------
- */
-func errata_neoverse_v1_2294912_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_2294912
- cbz x0, 1f
-
+workaround_reset_start neoverse_v1, ERRATUM(2294912), ERRATA_V1_2294912
/* Set bit 0 in ACTLR2_EL1 */
- mrs x1, NEOVERSE_V1_ACTLR2_EL1
- orr x1, x1, #NEOVERSE_V1_ACTLR2_EL1_BIT_0
- msr NEOVERSE_V1_ACTLR2_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_neoverse_v1_2294912_wa
+ sysreg_bit_set NEOVERSE_V1_ACTLR2_EL1, NEOVERSE_V1_ACTLR2_EL1_BIT_0
+workaround_reset_end neoverse_v1, ERRATUM(2294912)
-func check_errata_2294912
- /* Applies to r0p0, r1p0, and r1p1 right now */
- mov x1, #0x11
- b cpu_rev_var_ls
-endfunc check_errata_2294912
+check_erratum_ls neoverse_v1, ERRATUM(2294912), CPU_REV(1, 1)
- /* ---------------------------------------------------
- * Errata Workaround for Neoverse V1 Errata #2372203.
- * This applies to revisions <= r1p1 and is still open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ----------------------------------------------------
- */
-func errata_neoverse_v1_2372203_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_2372203
- cbz x0, 1f
-
+workaround_reset_start neoverse_v1, ERRATUM(2372203), ERRATA_V1_2372203
/* Set bit 40 in ACTLR2_EL1 */
- mrs x1, NEOVERSE_V1_ACTLR2_EL1
- orr x1, x1, #NEOVERSE_V1_ACTLR2_EL1_BIT_40
- msr NEOVERSE_V1_ACTLR2_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_neoverse_v1_2372203_wa
-
-func check_errata_2372203
- /* Applies to <= r1p1. */
- mov x1, #0x11
- b cpu_rev_var_ls
-endfunc check_errata_2372203
+ sysreg_bit_set NEOVERSE_V1_ACTLR2_EL1, NEOVERSE_V1_ACTLR2_EL1_BIT_40
+workaround_reset_end neoverse_v1, ERRATUM(2372203)
- /* ----------------------------------------------------
- * Errata Workaround for Neoverse V1 Errata #2743093.
- * This applies to revisions <= r1p2 and is still open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ----------------------------------------------------
- */
-func errata_neoverse_v1_2743093_wa
- mov x17, x30
- bl check_errata_2743093
- cbz x0, 1f
+check_erratum_ls neoverse_v1, ERRATUM(2372203), CPU_REV(1, 1)
+workaround_runtime_start neoverse_v1, ERRATUM(2743093), ERRATA_V1_2743093
/* dsb before isb of power down sequence */
dsb sy
-1:
- ret x17
-endfunc errata_neoverse_v1_2743093_wa
+workaround_runtime_end neoverse_v1, ERRATUM(2743093)
-func check_errata_2743093
- /* Applies to all revisions <= r1p2 */
- mov x1, #0x12
- b cpu_rev_var_ls
-endfunc check_errata_2743093
+check_erratum_ls neoverse_v1, ERRATUM(2743093), CPU_REV(1, 2)
- /* ---------------------------------------------------
- * Errata Workaround for Neoverse V1 Errata #2743233.
- * This applies to revisions r0p0, r1p0, r1p1 and r1p2.
- * It is still open.
- * x0: variant[4:7] and revisions[0:3] of current cpu.
- * Shall clobber: x0-x1, x17
- * ---------------------------------------------------
- */
-func errata_neoverse_v1_2743233_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_2743233
- cbz x0, 1f
+workaround_reset_start neoverse_v1, ERRATUM(2743233), ERRATA_V1_2743233
+ sysreg_bit_clear NEOVERSE_V1_ACTLR5_EL1, NEOVERSE_V1_ACTLR5_EL1_BIT_56
+ sysreg_bit_set NEOVERSE_V1_ACTLR5_EL1, NEOVERSE_V1_ACTLR5_EL1_BIT_55
+workaround_reset_end neoverse_v1, ERRATUM(2743233)
- /* Apply the workaround */
- mrs x1, NEOVERSE_V1_ACTLR5_EL1
- bic x1, x1, #BIT(56)
- orr x1, x1, #BIT(55)
- msr NEOVERSE_V1_ACTLR5_EL1, x1
+check_erratum_ls neoverse_v1, ERRATUM(2743233), CPU_REV(1, 2)
-1:
- ret x17
-endfunc errata_neoverse_v1_2743233_wa
+workaround_reset_start neoverse_v1, ERRATUM(2779461), ERRATA_V1_2779461
+ sysreg_bit_set NEOVERSE_V1_ACTLR3_EL1, NEOVERSE_V1_ACTLR3_EL1_BIT_47
+workaround_reset_end neoverse_v1, ERRATUM(2779461)
-func check_errata_2743233
- /* Applies to r0p0, r1p0, r1p1 and r1p2 */
- mov x1, #CPU_REV(1,2)
- b cpu_rev_var_ls
-endfunc check_errata_2743233
+check_erratum_ls neoverse_v1, ERRATUM(2779461), CPU_REV(1, 2)
- /* ----------------------------------------------------
- * Errata Workaround for Neoverse V1 Errata #2779461.
- * This applies to revisions r0p0, r1p0, r1p1, and r1p2.
- * It is still open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x1, x17
- * ----------------------------------------------------
+workaround_reset_start neoverse_v1, CVE(2022,23960), WORKAROUND_CVE_2022_23960
+#if IMAGE_BL31
+ /*
+ * The Neoverse-V1 generic vectors are overridden to apply errata
+ * mitigation on exception entry from lower ELs.
*/
-func errata_neoverse_v1_2779461_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_2779461
- cbz x0, 1f
-
- /* Apply the workaround */
- mrs x1, NEOVERSE_V1_ACTLR3_EL1
- orr x1, x1, #BIT(47)
- msr NEOVERSE_V1_ACTLR3_EL1, x1
+ override_vector_table wa_cve_vbar_neoverse_v1
+#endif /* IMAGE_BL31 */
+workaround_reset_end neoverse_v1, CVE(2022,23960)
-1:
- ret x17
-endfunc errata_neoverse_v1_2779461_wa
-
-func check_errata_2779461
- /* Applies to r0p0, r1p0, r1p1, r1p2 */
- mov x1, #CPU_REV(1, 2)
- b cpu_rev_var_ls
-endfunc check_errata_2779461
-
-func check_errata_cve_2022_23960
-#if WORKAROUND_CVE_2022_23960
- mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
-#endif
- ret
-endfunc check_errata_cve_2022_23960
+check_erratum_chosen neoverse_v1, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
/* ---------------------------------------------
* HW will do the cache maintenance while powering down
@@ -564,148 +245,19 @@
* Enable CPU power down bit in power control register
* ---------------------------------------------
*/
- mrs x0, NEOVERSE_V1_CPUPWRCTLR_EL1
- orr x0, x0, #NEOVERSE_V1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
- msr NEOVERSE_V1_CPUPWRCTLR_EL1, x0
-#if ERRATA_V1_2743093
- mov x15, x30
- bl cpu_get_rev_var
- bl errata_neoverse_v1_2743093_wa
- mov x30, x15
-#endif /* ERRATA_V1_2743093 */
+ sysreg_bit_set NEOVERSE_V1_CPUPWRCTLR_EL1, NEOVERSE_V1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
+ apply_erratum neoverse_v1, ERRATUM(2743093), ERRATA_V1_2743093
+
isb
ret
endfunc neoverse_v1_core_pwr_dwn
- /*
- * Errata printing function for Neoverse V1. Must follow AAPCS.
- */
-#if REPORT_ERRATA
-func neoverse_v1_errata_report
- stp x8, x30, [sp, #-16]!
-
- bl cpu_get_rev_var
- mov x8, x0
+errata_report_shim neoverse_v1
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata ERRATA_V1_1618635, neoverse_v1, 1618635
- report_errata ERRATA_V1_1774420, neoverse_v1, 1774420
- report_errata ERRATA_V1_1791573, neoverse_v1, 1791573
- report_errata ERRATA_V1_1852267, neoverse_v1, 1852267
- report_errata ERRATA_V1_1925756, neoverse_v1, 1925756
- report_errata ERRATA_V1_1940577, neoverse_v1, 1940577
- report_errata ERRATA_V1_1966096, neoverse_v1, 1966096
- report_errata ERRATA_V1_2108267, neoverse_v1, 2108267
- report_errata ERRATA_V1_2139242, neoverse_v1, 2139242
- report_errata ERRATA_V1_2216392, neoverse_v1, 2216392
- report_errata ERRATA_V1_2294912, neoverse_v1, 2294912
- report_errata ERRATA_V1_2372203, neoverse_v1, 2372203
- report_errata ERRATA_V1_2743093, neoverse_v1, 2743093
- report_errata ERRATA_V1_2743233, neoverse_v1, 2743233
- report_errata ERRATA_V1_2779461, neoverse_v1, 2779461
- report_errata WORKAROUND_CVE_2022_23960, neoverse_v1, cve_2022_23960
-
- ldp x8, x30, [sp], #16
- ret
-endfunc neoverse_v1_errata_report
-#endif
-
-func neoverse_v1_reset_func
- mov x19, x30
-
+cpu_reset_func_start neoverse_v1
/* Disable speculative loads */
msr SSBS, xzr
- isb
-
- /* Get the CPU revision and stash it in x18. */
- bl cpu_get_rev_var
- mov x18, x0
-
-#if ERRATA_V1_1618635
- mov x0, x18
- bl errata_neoverse_v1_1618635_wa
-#endif
-
-#if ERRATA_V1_1774420
- mov x0, x18
- bl errata_neoverse_v1_1774420_wa
-#endif
-
-#if ERRATA_V1_1791573
- mov x0, x18
- bl errata_neoverse_v1_1791573_wa
-#endif
-
-#if ERRATA_V1_1852267
- mov x0, x18
- bl errata_neoverse_v1_1852267_wa
-#endif
-
-#if ERRATA_V1_1925756
- mov x0, x18
- bl errata_neoverse_v1_1925756_wa
-#endif
-
-#if ERRATA_V1_1940577
- mov x0, x18
- bl errata_neoverse_v1_1940577_wa
-#endif
-
-#if ERRATA_V1_1966096
- mov x0, x18
- bl errata_neoverse_v1_1966096_wa
-#endif
-
-#if ERRATA_V1_2139242
- mov x0, x18
- bl errata_neoverse_v1_2139242_wa
-#endif
-
-#if ERRATA_V1_2108267
- mov x0, x18
- bl errata_neoverse_v1_2108267_wa
-#endif
-
-#if ERRATA_V1_2216392
- mov x0, x18
- bl errata_neoverse_v1_2216392_wa
-#endif
-
-#if ERRATA_V1_2294912
- mov x0, x18
- bl errata_neoverse_v1_2294912_wa
-#endif
-
-#if ERRATA_V1_2372203
- mov x0, x18
- bl errata_neoverse_v1_2372203_wa
-#endif
-
-#if ERRATA_V1_2743233
- mov x0, x18
- bl errata_neoverse_v1_2743233_wa
-#endif
-
-#if ERRATA_V1_2779461
- mov x0, x18
- bl errata_neoverse_v1_2779461_wa
-#endif
-
-#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
- /*
- * The Neoverse-V1 generic vectors are overridden to apply errata
- * mitigation on exception entry from lower ELs.
- */
- adr x0, wa_cve_vbar_neoverse_v1
- msr vbar_el3, x0
-#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
-
- isb
- ret x19
-endfunc neoverse_v1_reset_func
+cpu_reset_func_end neoverse_v1
/* ---------------------------------------------
* This function provides Neoverse-V1 specific
diff --git a/lib/cpus/aarch64/neoverse_v2.S b/lib/cpus/aarch64/neoverse_v2.S
index 6e00e5e..36ae4de 100644
--- a/lib/cpus/aarch64/neoverse_v2.S
+++ b/lib/cpus/aarch64/neoverse_v2.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -22,6 +22,25 @@
#error "Neoverse V2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#endif
+workaround_runtime_start neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372
+ /* dsb before isb of power down sequence */
+ dsb sy
+workaround_runtime_end neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372
+
+check_erratum_ls neoverse_v2, ERRATUM(2801372), CPU_REV(0, 1)
+
+workaround_reset_start neoverse_v2, CVE(2022,23960), WORKAROUND_CVE_2022_23960
+#if IMAGE_BL31
+ /*
+ * The Neoverse-V2 generic vectors are overridden to apply errata
+ * mitigation on exception entry from lower ELs.
+ */
+ override_vector_table wa_cve_vbar_neoverse_v2
+#endif /* IMAGE_BL31 */
+workaround_reset_end neoverse_v2, CVE(2022,23960)
+
+check_erratum_chosen neoverse_v2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
+
#if WORKAROUND_CVE_2022_23960
wa_cve_2022_23960_bhb_vector_table NEOVERSE_V2_BHB_LOOP_COUNT, neoverse_v2
#endif /* WORKAROUND_CVE_2022_23960 */
@@ -35,90 +54,19 @@
* Enable CPU power down bit in power control register
* ---------------------------------------------------
*/
- mrs x0, NEOVERSE_V2_CPUPWRCTLR_EL1
- orr x0, x0, #NEOVERSE_V2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
- msr NEOVERSE_V2_CPUPWRCTLR_EL1, x0
-#if ERRATA_V2_2801372
- mov x15, x30
- bl cpu_get_rev_var
- bl errata_neoverse_v2_2801372_wa
- mov x30, x15
-#endif /* ERRATA_V2_2801372 */
+ sysreg_bit_set NEOVERSE_V2_CPUPWRCTLR_EL1, NEOVERSE_V2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
+ apply_erratum neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372
+
isb
ret
endfunc neoverse_v2_core_pwr_dwn
-func check_errata_cve_2022_23960
-#if WORKAROUND_CVE_2022_23960
- mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
-#endif
- ret
-endfunc check_errata_cve_2022_23960
-
- /* ----------------------------------------------------
- * Errata Workaround for Neoverse V2 Errata #2801372
- * This applies to revisions <= r0p1 and is fixed in r0p2.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ----------------------------------------------------
- */
-func errata_neoverse_v2_2801372_wa
- mov x17, x30
- bl check_errata_2801372
- cbz x0, 1f
-
- /* dsb before isb of power down sequence */
- dsb sy
-1:
- ret x17
-endfunc errata_neoverse_v2_2801372_wa
-
-func check_errata_2801372
- /* Applies to all revisions <= r0p1 */
- mov x1, #0x01
- b cpu_rev_var_ls
-endfunc check_errata_2801372
-
-func neoverse_v2_reset_func
+cpu_reset_func_start neoverse_v2
/* Disable speculative loads */
msr SSBS, xzr
-
-#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
- /*
- * The Neoverse V2 vectors are overridden to apply
- * errata mitigation on exception entry from lower ELs.
- */
- adr x0, wa_cve_vbar_neoverse_v2
- msr vbar_el3, x0
-#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
- isb
- ret
-endfunc neoverse_v2_reset_func
-
-#if REPORT_ERRATA
-/*
- * Errata printing function for Neoverse V2. Must follow AAPCS.
- */
-func neoverse_v2_errata_report
- stp x8, x30, [sp, #-16]!
-
- bl cpu_get_rev_var
- mov x8, x0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata WORKAROUND_CVE_2022_23960, neoverse_v2, cve_2022_23960
- report_errata ERRATA_V2_2801372, neoverse_v2, 2801372
-
- ldp x8, x30, [sp], #16
- ret
-endfunc neoverse_v2_errata_report
-#endif
+cpu_reset_func_end neoverse_v2
+errata_report_shim neoverse_v2
/* ---------------------------------------------
* This function provides Neoverse V2-
* specific register information for crash
diff --git a/lib/cpus/aarch64/wa_cve_2017_5715_bpiall.S b/lib/cpus/aarch64/wa_cve_2017_5715_bpiall.S
index 0222818..8d9aa5e 100644
--- a/lib/cpus/aarch64/wa_cve_2017_5715_bpiall.S
+++ b/lib/cpus/aarch64/wa_cve_2017_5715_bpiall.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2022, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/cpus/aarch64/wa_cve_2017_5715_mmu.S b/lib/cpus/aarch64/wa_cve_2017_5715_mmu.S
index ed0a549..823f849 100644
--- a/lib/cpus/aarch64/wa_cve_2017_5715_mmu.S
+++ b/lib/cpus/aarch64/wa_cve_2017_5715_mmu.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2022, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/cpus/aarch64/wa_cve_2022_23960_bhb.S b/lib/cpus/aarch64/wa_cve_2022_23960_bhb.S
index ceb93f1..bf26658 100644
--- a/lib/cpus/aarch64/wa_cve_2022_23960_bhb.S
+++ b/lib/cpus/aarch64/wa_cve_2022_23960_bhb.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2022, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index 4a80bce..8df0a29 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -612,43 +612,43 @@
CPU_FLAG_LIST += ERRATA_A710_2768515
# Flag to apply erratum 2002655 workaround during reset. This erratum applies
-# to revisions r0p0 of the Neoverse-N2 cpu, it is still open.
+# to revisions r0p0 of the Neoverse-N2 cpu and is fixed in r0p1.
CPU_FLAG_LIST += ERRATA_N2_2002655
# Flag to apply erratum 2067956 workaround during reset. This erratum applies
-# to revision r0p0 of the Neoverse N2 cpu and is still open.
+# to revision r0p0 of the Neoverse N2 cpu and is fixed in r0p1.
CPU_FLAG_LIST += ERRATA_N2_2067956
# Flag to apply erratum 2025414 workaround during reset. This erratum applies
-# to revision r0p0 of the Neoverse N2 cpu and is still open.
+# to revision r0p0 of the Neoverse N2 cpu and is fixed in r0p1.
CPU_FLAG_LIST += ERRATA_N2_2025414
# Flag to apply erratum 2189731 workaround during reset. This erratum applies
-# to revision r0p0 of the Neoverse N2 cpu and is still open.
+# to revision r0p0 of the Neoverse N2 cpu and is fixed in r0p1.
CPU_FLAG_LIST += ERRATA_N2_2189731
# Flag to apply erratum 2138956 workaround during reset. This erratum applies
-# to revision r0p0 of the Neoverse N2 cpu and is still open.
+# to revision r0p0 of the Neoverse N2 cpu and is fixed in r0p1.
CPU_FLAG_LIST += ERRATA_N2_2138956
# Flag to apply erratum 2138953 workaround during reset. This erratum applies
-# to revision r0p0 of the Neoverse N2 cpu and is still open.
+# to revision r0p0, r0p1, r0p2, r0p3 of the Neoverse N2 cpu and is still open.
CPU_FLAG_LIST += ERRATA_N2_2138953
# Flag to apply erratum 2242415 workaround during reset. This erratum applies
-# to revision r0p0 of the Neoverse N2 cpu and is still open.
+# to revision r0p0 of the Neoverse N2 cpu and is fixed in r0p1.
CPU_FLAG_LIST += ERRATA_N2_2242415
# Flag to apply erratum 2138958 workaround during reset. This erratum applies
-# to revision r0p0 of the Neoverse N2 cpu and is still open.
+# to revision r0p0 of the Neoverse N2 cpu and is fixed in r0p1.
CPU_FLAG_LIST += ERRATA_N2_2138958
# Flag to apply erratum 2242400 workaround during reset. This erratum applies
-# to revision r0p0 of the Neoverse N2 cpu and is still open.
+# to revision r0p0 of the Neoverse N2 cpu and is fixed in r0p1.
CPU_FLAG_LIST += ERRATA_N2_2242400
# Flag to apply erratum 2280757 workaround during reset. This erratum applies
-# to revision r0p0 of the Neoverse N2 cpu and is still open.
+# to revision r0p0 of the Neoverse N2 cpu and is fixed in r0p1.
CPU_FLAG_LIST += ERRATA_N2_2280757
# Flag to apply erraturm 2326639 workaroud during powerdown. This erratum
@@ -656,7 +656,7 @@
CPU_FLAG_LIST += ERRATA_N2_2326639
# Flag to apply erratum 2376738 workaround during reset. This erratum applies
-# to revision r0p0 of the Neoverse N2 cpu, it is fixed in r0p1.
+# to revision r0p0, r0p1, r0p2, r0p3 of the Neoverse N2 cpu and is still open.
CPU_FLAG_LIST += ERRATA_N2_2376738
# Flag to apply erratum 2388450 workaround during reset. This erratum applies
@@ -668,10 +668,18 @@
# r0p3.
CPU_FLAG_LIST += ERRATA_N2_2728475
+# Flag to apply erratum 2743014 workaround during reset. This erratum applies
+# to r0p0, r0p1, r0p2 of the Neoverse N2 cpu, it is fixed in r0p3.
+CPU_FLAG_LIST += ERRATA_N2_2743014
+
# Flag to apply erratum 2743089 workaround during during powerdown. This erratum
# applies to all revisions <= r0p2 of the Neoverse N2 cpu, it is fixed in r0p3.
CPU_FLAG_LIST += ERRATA_N2_2743089
+# Flag to apply erratum 2779511 workaround during reset. This erratum applies
+# to r0p0, r0p1, r0p2 of the Neoverse N2 cpu, it is fixed in r0p3.
+CPU_FLAG_LIST += ERRATA_N2_2779511
+
# Flag to apply erratum 2002765 workaround during reset. This erratum applies
# to revisions r0p0, r1p0, and r2p0 of the Cortex-X2 cpu and is still open.
CPU_FLAG_LIST += ERRATA_X2_2002765
diff --git a/lib/debugfs/debugfs.mk b/lib/debugfs/debugfs.mk
index 138fc72..caa9fcf 100644
--- a/lib/debugfs/debugfs.mk
+++ b/lib/debugfs/debugfs.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2019, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
diff --git a/lib/debugfs/debugfs_smc.c b/lib/debugfs/debugfs_smc.c
index 13ced3d..64c64f8 100644
--- a/lib/debugfs/debugfs_smc.c
+++ b/lib/debugfs/debugfs_smc.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/el3_runtime/aarch32/cpu_data.S b/lib/el3_runtime/aarch32/cpu_data.S
index bdad2c1..e59b7fd 100644
--- a/lib/el3_runtime/aarch32/cpu_data.S
+++ b/lib/el3_runtime/aarch32/cpu_data.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/el3_runtime/aarch64/cpu_data.S b/lib/el3_runtime/aarch64/cpu_data.S
index 2392d6b..313f882 100644
--- a/lib/el3_runtime/aarch64/cpu_data.S
+++ b/lib/el3_runtime/aarch64/cpu_data.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2020, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/el3_runtime/cpu_data_array.c b/lib/el3_runtime/cpu_data_array.c
index 13d464c..2056182 100644
--- a/lib/el3_runtime/cpu_data_array.c
+++ b/lib/el3_runtime/cpu_data_array.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2016, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/extensions/amu/aarch32/amu.c b/lib/extensions/amu/aarch32/amu.c
index 03186d6..351a552 100644
--- a/lib/extensions/amu/aarch32/amu.c
+++ b/lib/extensions/amu/aarch32/amu.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/extensions/amu/aarch32/amu_helpers.S b/lib/extensions/amu/aarch32/amu_helpers.S
index 8ac7678..7090b2d 100644
--- a/lib/extensions/amu/aarch32/amu_helpers.S
+++ b/lib/extensions/amu/aarch32/amu_helpers.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/extensions/amu/aarch64/amu.c b/lib/extensions/amu/aarch64/amu.c
index e0d3399..8c5ef0b 100644
--- a/lib/extensions/amu/aarch64/amu.c
+++ b/lib/extensions/amu/aarch64/amu.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/extensions/amu/aarch64/amu_helpers.S b/lib/extensions/amu/aarch64/amu_helpers.S
index 0f6d799..95d4ad6 100644
--- a/lib/extensions/amu/aarch64/amu_helpers.S
+++ b/lib/extensions/amu/aarch64/amu_helpers.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/extensions/amu/amu_private.h b/lib/extensions/amu/amu_private.h
index eb7ff0e..a3b6845 100644
--- a/lib/extensions/amu/amu_private.h
+++ b/lib/extensions/amu/amu_private.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/extensions/ras/ras_common.c b/lib/extensions/ras/ras_common.c
index 622879e..50f3727 100644
--- a/lib/extensions/ras/ras_common.c
+++ b/lib/extensions/ras/ras_common.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
diff --git a/lib/extensions/ras/std_err_record.c b/lib/extensions/ras/std_err_record.c
index c03fbbe..6c1dc9f 100644
--- a/lib/extensions/ras/std_err_record.c
+++ b/lib/extensions/ras/std_err_record.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/fconf/fconf.c b/lib/fconf/fconf.c
index b1d6eaa..136e056 100644
--- a/lib/fconf/fconf.c
+++ b/lib/fconf/fconf.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2022, ARM Limited. All rights reserved.
+ * Copyright (c) 2019-2022, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/fconf/fconf.mk b/lib/fconf/fconf.mk
index fb88910..ff781aa 100644
--- a/lib/fconf/fconf.mk
+++ b/lib/fconf/fconf.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2019-2021, ARM Limited. All rights reserved.
+# Copyright (c) 2019-2021, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
diff --git a/lib/libc/aarch64/setjmp.S b/lib/libc/aarch64/setjmp.S
index 9d9eb49..9cb31ea 100644
--- a/lib/libc/aarch64/setjmp.S
+++ b/lib/libc/aarch64/setjmp.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/libc/abort.c b/lib/libc/abort.c
index 432b1d0..ac27f62 100644
--- a/lib/libc/abort.c
+++ b/lib/libc/abort.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2018, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/libc/assert.c b/lib/libc/assert.c
index 8973ed5..301d142 100644
--- a/lib/libc/assert.c
+++ b/lib/libc/assert.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/libc/exit.c b/lib/libc/exit.c
index f4ffe27..6de2e93 100644
--- a/lib/libc/exit.c
+++ b/lib/libc/exit.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2018, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/libc/libc.mk b/lib/libc/libc.mk
index 5eb8b52..95da68c 100644
--- a/lib/libc/libc.mk
+++ b/lib/libc/libc.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2016-2021, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
diff --git a/lib/libc/memchr.c b/lib/libc/memchr.c
index 8cbb715..66d7ba1 100644
--- a/lib/libc/memchr.c
+++ b/lib/libc/memchr.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/libc/memcmp.c b/lib/libc/memcmp.c
index cd5f0df..db2701b 100644
--- a/lib/libc/memcmp.c
+++ b/lib/libc/memcmp.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/libc/memcpy.c b/lib/libc/memcpy.c
index 158df9b..af9ed45 100644
--- a/lib/libc/memcpy.c
+++ b/lib/libc/memcpy.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/libc/memcpy_s.c b/lib/libc/memcpy_s.c
index 01e88b0..26953bf 100644
--- a/lib/libc/memcpy_s.c
+++ b/lib/libc/memcpy_s.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2023, Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
diff --git a/lib/libc/memmove.c b/lib/libc/memmove.c
index 63acf26..5c2b661 100644
--- a/lib/libc/memmove.c
+++ b/lib/libc/memmove.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2018, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/libc/memset.c b/lib/libc/memset.c
index 17f798c..c5bac8d 100644
--- a/lib/libc/memset.c
+++ b/lib/libc/memset.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2020, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/libc/putchar.c b/lib/libc/putchar.c
index 340bdd8..1f919d1 100644
--- a/lib/libc/putchar.c
+++ b/lib/libc/putchar.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/libc/puts.c b/lib/libc/puts.c
index 2a0ca11..f57fc98 100644
--- a/lib/libc/puts.c
+++ b/lib/libc/puts.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2018, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/libc/strchr.c b/lib/libc/strchr.c
index d94bb9e..1cd03ca 100644
--- a/lib/libc/strchr.c
+++ b/lib/libc/strchr.c
@@ -30,7 +30,7 @@
*/
/*
- * Portions copyright (c) 2018, ARM Limited and Contributors.
+ * Portions copyright (c) 2018, Arm Limited and Contributors.
* All rights reserved.
*/
diff --git a/lib/libc/strcmp.c b/lib/libc/strcmp.c
index b742f9b..290db4c 100644
--- a/lib/libc/strcmp.c
+++ b/lib/libc/strcmp.c
@@ -33,7 +33,7 @@
*/
/*
- * Portions copyright (c) 2018, ARM Limited and Contributors.
+ * Portions copyright (c) 2018, Arm Limited and Contributors.
* All rights reserved.
*/
diff --git a/lib/libc/strlen.c b/lib/libc/strlen.c
index 3c27630..e4b79d9 100644
--- a/lib/libc/strlen.c
+++ b/lib/libc/strlen.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/libc/strncmp.c b/lib/libc/strncmp.c
index ce9e5ed..f0bbadc 100644
--- a/lib/libc/strncmp.c
+++ b/lib/libc/strncmp.c
@@ -30,7 +30,7 @@
*/
/*
- * Portions copyright (c) 2018, ARM Limited and Contributors.
+ * Portions copyright (c) 2018, Arm Limited and Contributors.
* All rights reserved.
*/
diff --git a/lib/libc/strnlen.c b/lib/libc/strnlen.c
index b944e95..49e9f7a 100644
--- a/lib/libc/strnlen.c
+++ b/lib/libc/strnlen.c
@@ -27,7 +27,7 @@
*/
/*
- * Portions copyright (c) 2018, ARM Limited and Contributors.
+ * Portions copyright (c) 2018, Arm Limited and Contributors.
* All rights reserved.
*/
diff --git a/lib/libfdt/libfdt.mk b/lib/libfdt/libfdt.mk
index 1cbbd78..812057d 100644
--- a/lib/libfdt/libfdt.mk
+++ b/lib/libfdt/libfdt.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2016, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
diff --git a/lib/locks/bakery/bakery_lock_coherent.c b/lib/locks/bakery/bakery_lock_coherent.c
index 748eedd..bcd89ef 100644
--- a/lib/locks/bakery/bakery_lock_coherent.c
+++ b/lib/locks/bakery/bakery_lock_coherent.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2018, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/locks/bakery/bakery_lock_normal.c b/lib/locks/bakery/bakery_lock_normal.c
index 3c03ae6..9f27322 100644
--- a/lib/locks/bakery/bakery_lock_normal.c
+++ b/lib/locks/bakery/bakery_lock_normal.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2020, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
diff --git a/lib/locks/exclusive/aarch32/spinlock.S b/lib/locks/exclusive/aarch32/spinlock.S
index 9492cc0..853d096 100644
--- a/lib/locks/exclusive/aarch32/spinlock.S
+++ b/lib/locks/exclusive/aarch32/spinlock.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/locks/exclusive/aarch64/spinlock.S b/lib/locks/exclusive/aarch64/spinlock.S
index e941b8a..5144bf7 100644
--- a/lib/locks/exclusive/aarch64/spinlock.S
+++ b/lib/locks/exclusive/aarch64/spinlock.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/optee/optee_utils.c b/lib/optee/optee_utils.c
index 6641db9..14f5533 100644
--- a/lib/optee/optee_utils.c
+++ b/lib/optee/optee_utils.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/pmf/pmf_main.c b/lib/pmf/pmf_main.c
index ce2f0d9..bf0ad83 100644
--- a/lib/pmf/pmf_main.c
+++ b/lib/pmf/pmf_main.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2018, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/pmf/pmf_smc.c b/lib/pmf/pmf_smc.c
index 6d79502..71486df 100644
--- a/lib/pmf/pmf_smc.c
+++ b/lib/pmf/pmf_smc.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2018, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/psci/aarch32/psci_helpers.S b/lib/psci/aarch32/psci_helpers.S
index d28d469..4e1013c 100644
--- a/lib/psci/aarch32/psci_helpers.S
+++ b/lib/psci/aarch32/psci_helpers.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/psci/aarch64/psci_helpers.S b/lib/psci/aarch64/psci_helpers.S
index 61f31e5..3b77ab2 100644
--- a/lib/psci/aarch64/psci_helpers.S
+++ b/lib/psci/aarch64/psci_helpers.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/psci/psci_mem_protect.c b/lib/psci/psci_mem_protect.c
index 481051f..385dcd2 100644
--- a/lib/psci/psci_mem_protect.c
+++ b/lib/psci/psci_mem_protect.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2018, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/psci/psci_on.c b/lib/psci/psci_on.c
index 1f619ae..31875ff 100644
--- a/lib/psci/psci_on.c
+++ b/lib/psci/psci_on.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/psci/psci_setup.c b/lib/psci/psci_setup.c
index 1f93cc9..6bf1ff4 100644
--- a/lib/psci/psci_setup.c
+++ b/lib/psci/psci_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2020, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/psci/psci_stat.c b/lib/psci/psci_stat.c
index ecef95a..ad88d07 100644
--- a/lib/psci/psci_stat.c
+++ b/lib/psci/psci_stat.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/romlib/Makefile b/lib/romlib/Makefile
index 2ff480b..c3ddc5a 100644
--- a/lib/romlib/Makefile
+++ b/lib/romlib/Makefile
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
diff --git a/lib/romlib/gen_combined_bl1_romlib.sh b/lib/romlib/gen_combined_bl1_romlib.sh
index 1e3f73a..3941467 100755
--- a/lib/romlib/gen_combined_bl1_romlib.sh
+++ b/lib/romlib/gen_combined_bl1_romlib.sh
@@ -1,5 +1,5 @@
#!/bin/sh
-# Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
diff --git a/lib/romlib/init.s b/lib/romlib/init.s
index 7d97e4d..2bea15b 100644
--- a/lib/romlib/init.s
+++ b/lib/romlib/init.s
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/romlib/jmptbl.i b/lib/romlib/jmptbl.i
index 33710f5..44751a2 100644
--- a/lib/romlib/jmptbl.i
+++ b/lib/romlib/jmptbl.i
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
diff --git a/lib/romlib/romlib.ld.S b/lib/romlib/romlib.ld.S
index d54a684..0d076b4 100644
--- a/lib/romlib/romlib.ld.S
+++ b/lib/romlib/romlib.ld.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/semihosting/aarch32/semihosting_call.S b/lib/semihosting/aarch32/semihosting_call.S
index aced3d1..42d4718 100644
--- a/lib/semihosting/aarch32/semihosting_call.S
+++ b/lib/semihosting/aarch32/semihosting_call.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/semihosting/aarch64/semihosting_call.S b/lib/semihosting/aarch64/semihosting_call.S
index 97d2bca..6f60f3e 100644
--- a/lib/semihosting/aarch64/semihosting_call.S
+++ b/lib/semihosting/aarch64/semihosting_call.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2014, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/semihosting/semihosting.c b/lib/semihosting/semihosting.c
index 163a82d..adc6b78 100644
--- a/lib/semihosting/semihosting.c
+++ b/lib/semihosting/semihosting.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/stack_protector/aarch32/asm_stack_protector.S b/lib/stack_protector/aarch32/asm_stack_protector.S
index 19b7525..0ffcf8a 100644
--- a/lib/stack_protector/aarch32/asm_stack_protector.S
+++ b/lib/stack_protector/aarch32/asm_stack_protector.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/stack_protector/aarch64/asm_stack_protector.S b/lib/stack_protector/aarch64/asm_stack_protector.S
index c2245d3..a002617 100644
--- a/lib/stack_protector/aarch64/asm_stack_protector.S
+++ b/lib/stack_protector/aarch64/asm_stack_protector.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/stack_protector/stack_protector.c b/lib/stack_protector/stack_protector.c
index 3ff74fc..d0f2400 100644
--- a/lib/stack_protector/stack_protector.c
+++ b/lib/stack_protector/stack_protector.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/stack_protector/stack_protector.mk b/lib/stack_protector/stack_protector.mk
index b5aba15..4f13bc3 100644
--- a/lib/stack_protector/stack_protector.mk
+++ b/lib/stack_protector/stack_protector.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
diff --git a/lib/utils/mem_region.c b/lib/utils/mem_region.c
index fec086b..e9f0a12 100644
--- a/lib/utils/mem_region.c
+++ b/lib/utils/mem_region.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2020, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/xlat_mpu/aarch64/enable_mpu.S b/lib/xlat_mpu/aarch64/enable_mpu.S
index 3791f2d..0dda979 100644
--- a/lib/xlat_mpu/aarch64/enable_mpu.S
+++ b/lib/xlat_mpu/aarch64/enable_mpu.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/xlat_mpu/aarch64/xlat_mpu_arch.c b/lib/xlat_mpu/aarch64/xlat_mpu_arch.c
index 5068eb8..5a2120b 100644
--- a/lib/xlat_mpu/aarch64/xlat_mpu_arch.c
+++ b/lib/xlat_mpu/aarch64/xlat_mpu_arch.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/xlat_mpu/ro_xlat_mpu.mk b/lib/xlat_mpu/ro_xlat_mpu.mk
index 23f1d46..d3af3bd 100644
--- a/lib/xlat_mpu/ro_xlat_mpu.mk
+++ b/lib/xlat_mpu/ro_xlat_mpu.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2021, ARM Limited. All rights reserved.
+# Copyright (c) 2021, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
diff --git a/lib/xlat_mpu/xlat_mpu.mk b/lib/xlat_mpu/xlat_mpu.mk
index 041b91c..31bef04 100644
--- a/lib/xlat_mpu/xlat_mpu.mk
+++ b/lib/xlat_mpu/xlat_mpu.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
diff --git a/lib/xlat_mpu/xlat_mpu_context.c b/lib/xlat_mpu/xlat_mpu_context.c
index 28c463b..783f21d 100644
--- a/lib/xlat_mpu/xlat_mpu_context.c
+++ b/lib/xlat_mpu/xlat_mpu_context.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/xlat_mpu/xlat_mpu_core.c b/lib/xlat_mpu/xlat_mpu_core.c
index 6b4b0c2..33f381d 100644
--- a/lib/xlat_mpu/xlat_mpu_core.c
+++ b/lib/xlat_mpu/xlat_mpu_core.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/xlat_mpu/xlat_mpu_private.h b/lib/xlat_mpu/xlat_mpu_private.h
index e0e479d..14800e9 100644
--- a/lib/xlat_mpu/xlat_mpu_private.h
+++ b/lib/xlat_mpu/xlat_mpu_private.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/xlat_mpu/xlat_mpu_utils.c b/lib/xlat_mpu/xlat_mpu_utils.c
index 5400875..dc5f956 100644
--- a/lib/xlat_mpu/xlat_mpu_utils.c
+++ b/lib/xlat_mpu/xlat_mpu_utils.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/xlat_tables/aarch32/xlat_tables.c b/lib/xlat_tables/aarch32/xlat_tables.c
index 4b01b9b..6d098be 100644
--- a/lib/xlat_tables/aarch32/xlat_tables.c
+++ b/lib/xlat_tables/aarch32/xlat_tables.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2018, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/xlat_tables/aarch64/xlat_tables.c b/lib/xlat_tables/aarch64/xlat_tables.c
index dc167e3..4dbfc11 100644
--- a/lib/xlat_tables/aarch64/xlat_tables.c
+++ b/lib/xlat_tables/aarch64/xlat_tables.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2021, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/xlat_tables/xlat_tables_common.c b/lib/xlat_tables/xlat_tables_common.c
index e2c8370..8b44df2 100644
--- a/lib/xlat_tables/xlat_tables_common.c
+++ b/lib/xlat_tables/xlat_tables_common.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2018, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/xlat_tables/xlat_tables_private.h b/lib/xlat_tables/xlat_tables_private.h
index 82bc70c..cfecc39 100644
--- a/lib/xlat_tables/xlat_tables_private.h
+++ b/lib/xlat_tables/xlat_tables_private.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2018, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/xlat_tables_v2/aarch32/enable_mmu.S b/lib/xlat_tables_v2/aarch32/enable_mmu.S
index f2fff36..22c2876 100644
--- a/lib/xlat_tables_v2/aarch32/enable_mmu.S
+++ b/lib/xlat_tables_v2/aarch32/enable_mmu.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c b/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c
index a1a44af..920754b 100644
--- a/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c
+++ b/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/xlat_tables_v2/aarch64/enable_mmu.S b/lib/xlat_tables_v2/aarch64/enable_mmu.S
index 9f075e4..247a796 100644
--- a/lib/xlat_tables_v2/aarch64/enable_mmu.S
+++ b/lib/xlat_tables_v2/aarch64/enable_mmu.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/xlat_tables_v2/ro_xlat_tables.mk b/lib/xlat_tables_v2/ro_xlat_tables.mk
index fb8a426..20bb015 100644
--- a/lib/xlat_tables_v2/ro_xlat_tables.mk
+++ b/lib/xlat_tables_v2/ro_xlat_tables.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2020-2022, ARM Limited. All rights reserved.
+# Copyright (c) 2020-2022, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
diff --git a/lib/xlat_tables_v2/xlat_tables.mk b/lib/xlat_tables_v2/xlat_tables.mk
index bcc3e68..b4ad34b 100644
--- a/lib/xlat_tables_v2/xlat_tables.mk
+++ b/lib/xlat_tables_v2/xlat_tables.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2017-2020, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
diff --git a/lib/xlat_tables_v2/xlat_tables_context.c b/lib/xlat_tables_v2/xlat_tables_context.c
index 95dae88..2fbbc78 100644
--- a/lib/xlat_tables_v2/xlat_tables_context.c
+++ b/lib/xlat_tables_v2/xlat_tables_context.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2020, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/zlib/tf_gunzip.c b/lib/zlib/tf_gunzip.c
index 3ac80bc..8b8d14d 100644
--- a/lib/zlib/tf_gunzip.c
+++ b/lib/zlib/tf_gunzip.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/zlib/zlib.mk b/lib/zlib/zlib.mk
index 98d4efa..a8937a7 100644
--- a/lib/zlib/zlib.mk
+++ b/lib/zlib/zlib.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
diff --git a/plat/arm/board/fvp/fvp_bl1_measured_boot.c b/plat/arm/board/fvp/fvp_bl1_measured_boot.c
index b8431c5..dc95ba1 100644
--- a/plat/arm/board/fvp/fvp_bl1_measured_boot.c
+++ b/plat/arm/board/fvp/fvp_bl1_measured_boot.c
@@ -9,6 +9,7 @@
#include <drivers/measured_boot/event_log/event_log.h>
#include <drivers/measured_boot/rss/rss_measured_boot.h>
#include <plat/arm/common/plat_arm.h>
+#include <tools_share/zero_oid.h>
/* Event Log data */
static uint8_t event_log[PLAT_ARM_EVENT_LOG_MAX_SIZE];
@@ -31,18 +32,21 @@
.slot = U(6),
.signer_id_size = SIGNER_ID_MIN_SIZE,
.sw_type = RSS_MBOOT_FW_CONFIG_STRING,
+ .pk_oid = ZERO_OID,
.lock_measurement = true },
{
.id = TB_FW_CONFIG_ID,
.slot = U(7),
.signer_id_size = SIGNER_ID_MIN_SIZE,
.sw_type = RSS_MBOOT_TB_FW_CONFIG_STRING,
+ .pk_oid = ZERO_OID,
.lock_measurement = true },
{
.id = BL2_IMAGE_ID,
.slot = U(8),
.signer_id_size = SIGNER_ID_MIN_SIZE,
.sw_type = RSS_MBOOT_BL2_STRING,
+ .pk_oid = ZERO_OID,
.lock_measurement = true },
{
diff --git a/plat/arm/board/fvp/fvp_bl2_measured_boot.c b/plat/arm/board/fvp/fvp_bl2_measured_boot.c
index 564118e..349e064 100644
--- a/plat/arm/board/fvp/fvp_bl2_measured_boot.c
+++ b/plat/arm/board/fvp/fvp_bl2_measured_boot.c
@@ -9,7 +9,11 @@
#include <common/tbbr/tbbr_img_def.h>
#include <drivers/measured_boot/event_log/event_log.h>
#include <drivers/measured_boot/rss/rss_measured_boot.h>
+#if defined(ARM_COT_cca)
+#include <tools_share/cca_oid.h>
+#else
#include <tools_share/tbbr_oid.h>
+#endif /* ARM_COT_cca */
#include <fvp_critical_data.h>
#include <plat/arm/common/plat_arm.h>
@@ -62,25 +66,31 @@
.slot = U(9),
.signer_id_size = SIGNER_ID_MIN_SIZE,
.sw_type = RSS_MBOOT_BL31_STRING,
+ .pk_oid = BL31_IMAGE_KEY_OID,
.lock_measurement = true },
{
.id = HW_CONFIG_ID,
.slot = U(10),
.signer_id_size = SIGNER_ID_MIN_SIZE,
.sw_type = RSS_MBOOT_HW_CONFIG_STRING,
+ .pk_oid = HW_CONFIG_KEY_OID,
.lock_measurement = true },
{
.id = SOC_FW_CONFIG_ID,
.slot = U(11),
.signer_id_size = SIGNER_ID_MIN_SIZE,
.sw_type = RSS_MBOOT_SOC_FW_CONFIG_STRING,
+ .pk_oid = SOC_FW_CONFIG_KEY_OID,
.lock_measurement = true },
+#if ENABLE_RME
{
.id = RMM_IMAGE_ID,
.slot = U(12),
.signer_id_size = SIGNER_ID_MIN_SIZE,
.sw_type = RSS_MBOOT_RMM_STRING,
+ .pk_oid = RMM_IMAGE_KEY_OID,
.lock_measurement = true },
+#endif /* ENABLE_RME */
{
.id = RSS_MBOOT_INVALID_ID }
};
diff --git a/plat/arm/board/fvp/fvp_common_measured_boot.c b/plat/arm/board/fvp/fvp_common_measured_boot.c
index 7419e5e..0c1d5e7 100644
--- a/plat/arm/board/fvp/fvp_common_measured_boot.c
+++ b/plat/arm/board/fvp/fvp_common_measured_boot.c
@@ -45,3 +45,10 @@
return rc;
}
+
+int plat_mboot_measure_key(const void *pk_oid, const void *pk_ptr,
+ size_t pk_len)
+{
+ return rss_mboot_set_signer_id(fvp_rss_mboot_metadata, pk_oid, pk_ptr,
+ pk_len);
+}
diff --git a/plat/arm/board/fvp/fvp_cpu_errata.mk b/plat/arm/board/fvp/fvp_cpu_errata.mk
index 944571d..b8fa4ea 100644
--- a/plat/arm/board/fvp/fvp_cpu_errata.mk
+++ b/plat/arm/board/fvp/fvp_cpu_errata.mk
@@ -30,6 +30,7 @@
CORTEX_A77_H_INC := 1
CORTEX_A78_H_INC := 1
NEOVERSE_N1_H_INC := 1
+NEOVERSE_N2_H_INC := 1
NEOVERSE_V1_H_INC := 1
CORTEX_A78_AE_H_INC := 1
CORTEX_A510_H_INC := 1
@@ -41,6 +42,7 @@
$(eval $(call add_define, CORTEX_A77_H_INC))
$(eval $(call add_define, CORTEX_A78_H_INC))
$(eval $(call add_define, NEOVERSE_N1_H_INC))
+$(eval $(call add_define, NEOVERSE_N2_H_INC))
$(eval $(call add_define, NEOVERSE_V1_H_INC))
$(eval $(call add_define, CORTEX_A78_AE_H_INC))
$(eval $(call add_define, CORTEX_A510_H_INC))
diff --git a/plat/arm/board/juno/cert_create_tbbr.mk b/plat/arm/board/juno/cert_create_tbbr.mk
index c092fe0..4d133b2 100644
--- a/plat/arm/board/juno/cert_create_tbbr.mk
+++ b/plat/arm/board/juno/cert_create_tbbr.mk
@@ -7,7 +7,7 @@
PLAT_DEF_OID := 1
ifeq (${PLAT_DEF_OID},1)
- ifeq (${ARM_ETHOSN_NPU_DRIVER},1)
+ ifeq (${ETHOSN_NPU_DRIVER},1)
$(eval $(call add_define, PLAT_DEF_OID))
$(eval $(call add_define, PDEF_CERTS))
$(eval $(call add_define, PDEF_EXTS))
diff --git a/plat/arm/board/juno/fdts/juno_tb_fw_config.dts b/plat/arm/board/juno/fdts/juno_tb_fw_config.dts
index 986299e..ec72160 100644
--- a/plat/arm/board/juno/fdts/juno_tb_fw_config.dts
+++ b/plat/arm/board/juno/fdts/juno_tb_fw_config.dts
@@ -51,10 +51,10 @@
tos_fw_content_cert_uuid = "a49f4411-5e63-e411-8728-3f05722af33d";
nt_fw_content_cert_uuid = "8ec4c1f3-5d63-e411-a7a9-87ee40b23fa7";
plat_sp_content_cert_uuid = "776dfd44-8697-4c3b-91eb-c13e025a2a6f";
-#if ARM_ETHOSN_NPU_TZMP1
- arm_ethosn_npu_fw_uuid = "cfd499b5-a3bc-4a7e-98cb-48a41cb8dae1";
- arm_ethosn_npu_fw_key_cert_uuid = "5666d004-ab98-40aa-8988-b72a03a256e2";
- arm_ethosn_npu_fw_content_cert_uuid = "a5c418da-430f-48b1-88cd-93f67889d9ed";
+#if ETHOSN_NPU_TZMP1
+ ethosn_npu_fw_uuid = "cfd499b5-a3bc-4a7e-98cb-48a41cb8dae1";
+ ethosn_npu_fw_key_cert_uuid = "5666d004-ab98-40aa-8988-b72a03a256e2";
+ ethosn_npu_fw_content_cert_uuid = "a5c418da-430f-48b1-88cd-93f67889d9ed";
#endif
};
};
diff --git a/plat/arm/board/juno/fip/plat_def_fip_uuid.h b/plat/arm/board/juno/fip/plat_def_fip_uuid.h
index 0f0d11d..46adf24 100644
--- a/plat/arm/board/juno/fip/plat_def_fip_uuid.h
+++ b/plat/arm/board/juno/fip/plat_def_fip_uuid.h
@@ -7,8 +7,8 @@
#ifndef PLAT_DEF_FIP_UUID_H
#define PLAT_DEF_FIP_UUID_H
-#ifdef ARM_ETHOSN_NPU_TZMP1
+#ifdef ETHOSN_NPU_TZMP1
#include <drivers/arm/ethosn_fip.h>
-#endif
+#endif /* ETHOSN_NPU_TZMP1 */
#endif /* PLAT_DEF_FIP_UUID_H */
diff --git a/plat/arm/board/juno/fip/plat_def_uuid_config.c b/plat/arm/board/juno/fip/plat_def_uuid_config.c
index 8133927..705a8ca 100644
--- a/plat/arm/board/juno/fip/plat_def_uuid_config.c
+++ b/plat/arm/board/juno/fip/plat_def_uuid_config.c
@@ -12,11 +12,11 @@
#include "plat_def_fip_uuid.h"
toc_entry_t plat_def_toc_entries[] = {
-#ifdef ARM_ETHOSN_NPU_TZMP1
+#ifdef ETHOSN_NPU_TZMP1
ETHOSN_FW_KEY_CERTIFICATE_DEF,
ETHOSN_FW_CONTENT_CERTIFICATE_DEF,
ETHOSN_FW_DEF,
-#endif
+#endif /* ETHOSN_NPU_TZMP1 */
{
.name = NULL,
.uuid = { { 0 } },
diff --git a/plat/arm/board/juno/include/plat_tbbr_img_def.h b/plat/arm/board/juno/include/plat_tbbr_img_def.h
index 3e17ed3..5fbeb4e 100644
--- a/plat/arm/board/juno/include/plat_tbbr_img_def.h
+++ b/plat/arm/board/juno/include/plat_tbbr_img_def.h
@@ -7,12 +7,12 @@
#ifndef JUNO_IMG_DEF_H
#define JUNO_IMG_DEF_H
-#if ARM_ETHOSN_NPU_TZMP1
+#if ETHOSN_NPU_TZMP1
/* Arm(R) Ethos(TM)-N NPU images */
-#define ARM_ETHOSN_NPU_FW_KEY_CERT_ID U(MAX_IMG_IDS_WITH_SPMDS + 1)
-#define ARM_ETHOSN_NPU_FW_CONTENT_CERT_ID U(MAX_IMG_IDS_WITH_SPMDS + 2)
-#define ARM_ETHOSN_NPU_FW_IMAGE_ID U(MAX_IMG_IDS_WITH_SPMDS + 3)
+#define ETHOSN_NPU_FW_KEY_CERT_ID U(MAX_IMG_IDS_WITH_SPMDS + 1)
+#define ETHOSN_NPU_FW_CONTENT_CERT_ID U(MAX_IMG_IDS_WITH_SPMDS + 2)
+#define ETHOSN_NPU_FW_IMAGE_ID U(MAX_IMG_IDS_WITH_SPMDS + 3)
#define MAX_NUMBER_IDS U(MAX_IMG_IDS_WITH_SPMDS + 4)
-#endif
+#endif /* ETHOSN_NPU_TZMP1 */
#endif /* JUNO_IMG_DEF_H */
diff --git a/plat/arm/board/juno/include/platform_def.h b/plat/arm/board/juno/include/platform_def.h
index 47258cb..aa96038 100644
--- a/plat/arm/board/juno/include/platform_def.h
+++ b/plat/arm/board/juno/include/platform_def.h
@@ -327,15 +327,15 @@
/* Protected NSAIDs and memory regions for the Arm(R) Ethos(TM)-N NPU driver */
#ifdef JUNO_ETHOSN_TZMP1
-#define ARM_ETHOSN_NPU_PROT_FW_NSAID JUNO_ETHOSN_TZC400_NSAID_FW_PROT
-#define ARM_ETHOSN_NPU_PROT_RW_DATA_NSAID JUNO_ETHOSN_TZC400_NSAID_DATA_RW_PROT
-#define ARM_ETHOSN_NPU_PROT_RO_DATA_NSAID JUNO_ETHOSN_TZC400_NSAID_DATA_RO_PROT
+#define ETHOSN_NPU_PROT_FW_NSAID JUNO_ETHOSN_TZC400_NSAID_FW_PROT
+#define ETHOSN_NPU_PROT_RW_DATA_NSAID JUNO_ETHOSN_TZC400_NSAID_DATA_RW_PROT
+#define ETHOSN_NPU_PROT_RO_DATA_NSAID JUNO_ETHOSN_TZC400_NSAID_DATA_RO_PROT
-#define ARM_ETHOSN_NPU_NS_RW_DATA_NSAID JUNO_ETHOSN_TZC400_NSAID_DATA_RW_NS
-#define ARM_ETHOSN_NPU_NS_RO_DATA_NSAID JUNO_ETHOSN_TZC400_NSAID_DATA_RO_NS
+#define ETHOSN_NPU_NS_RW_DATA_NSAID JUNO_ETHOSN_TZC400_NSAID_DATA_RW_NS
+#define ETHOSN_NPU_NS_RO_DATA_NSAID JUNO_ETHOSN_TZC400_NSAID_DATA_RO_NS
-#define ARM_ETHOSN_NPU_FW_IMAGE_BASE JUNO_ETHOSN_FW_TZC_PROT_DRAM2_BASE
-#define ARM_ETHOSN_NPU_FW_IMAGE_LIMIT \
+#define ETHOSN_NPU_FW_IMAGE_BASE JUNO_ETHOSN_FW_TZC_PROT_DRAM2_BASE
+#define ETHOSN_NPU_FW_IMAGE_LIMIT \
(JUNO_ETHOSN_FW_TZC_PROT_DRAM2_BASE + JUNO_ETHOSN_FW_TZC_PROT_DRAM2_SIZE)
#endif
diff --git a/plat/arm/board/juno/juno_tbbr_cot_bl2.c b/plat/arm/board/juno/juno_tbbr_cot_bl2.c
index d48d2e6..8930dbb 100644
--- a/plat/arm/board/juno/juno_tbbr_cot_bl2.c
+++ b/plat/arm/board/juno/juno_tbbr_cot_bl2.c
@@ -32,9 +32,9 @@
#if defined(SPD_spmd)
static unsigned char sp_pkg_hash_buf[MAX_SP_IDS][HASH_DER_LEN];
#endif /* SPD_spmd */
-#if ARM_ETHOSN_NPU_TZMP1
+#if ETHOSN_NPU_TZMP1
static unsigned char npu_fw_image_hash_buf[HASH_DER_LEN];
-#endif /* ARM_ETHOSN_NPU_TZMP1 */
+#endif /* ETHOSN_NPU_TZMP1 */
static auth_param_type_desc_t non_trusted_nv_ctr = AUTH_PARAM_TYPE_DESC(
@@ -87,12 +87,12 @@
static auth_param_type_desc_t sp_pkg8_hash = AUTH_PARAM_TYPE_DESC(
AUTH_PARAM_HASH, SP_PKG8_HASH_OID);
#endif /* SPD_spmd */
-#if ARM_ETHOSN_NPU_TZMP1
+#if ETHOSN_NPU_TZMP1
static auth_param_type_desc_t npu_fw_cert_pk = AUTH_PARAM_TYPE_DESC(
AUTH_PARAM_PUB_KEY, ETHOSN_NPU_FW_CONTENT_CERT_PK_OID);
static auth_param_type_desc_t npu_fw_image_hash = AUTH_PARAM_TYPE_DESC(
AUTH_PARAM_HASH, ETHOSN_NPU_FW_BINARY_OID);
-#endif /* ARM_ETHOSN_NPU_TZMP1 */
+#endif /* ETHOSN_NPU_TZMP1 */
/*
* Trusted key certificate
@@ -662,9 +662,9 @@
DEFINE_SIP_SP_PKG(8);
#endif /* SPD_spmd */
-#if ARM_ETHOSN_NPU_TZMP1
+#if ETHOSN_NPU_TZMP1
static const auth_img_desc_t npu_fw_key_cert = {
- .img_id = ARM_ETHOSN_NPU_FW_KEY_CERT_ID,
+ .img_id = ETHOSN_NPU_FW_KEY_CERT_ID,
.img_type = IMG_CERT,
.parent = &trusted_key_cert,
.img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) {
@@ -697,7 +697,7 @@
};
static const auth_img_desc_t npu_fw_content_cert = {
- .img_id = ARM_ETHOSN_NPU_FW_CONTENT_CERT_ID,
+ .img_id = ETHOSN_NPU_FW_CONTENT_CERT_ID,
.img_type = IMG_CERT,
.parent = &npu_fw_key_cert,
.img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) {
@@ -730,7 +730,7 @@
};
static const auth_img_desc_t npu_fw_image = {
- .img_id = ARM_ETHOSN_NPU_FW_IMAGE_ID,
+ .img_id = ETHOSN_NPU_FW_IMAGE_ID,
.img_type = IMG_RAW,
.parent = &npu_fw_content_cert,
.img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) {
@@ -743,7 +743,7 @@
}
}
};
-#endif /* ARM_ETHOSN_NPU_TZMP1 */
+#endif /* ETHOSN_NPU_TZMP1 */
static const auth_img_desc_t * const cot_desc[] = {
@@ -778,11 +778,11 @@
[SP_PKG7_ID] = &sp_pkg7,
[SP_PKG8_ID] = &sp_pkg8,
#endif
-#if ARM_ETHOSN_NPU_TZMP1
- [ARM_ETHOSN_NPU_FW_KEY_CERT_ID] = &npu_fw_key_cert,
- [ARM_ETHOSN_NPU_FW_CONTENT_CERT_ID] = &npu_fw_content_cert,
- [ARM_ETHOSN_NPU_FW_IMAGE_ID] = &npu_fw_image,
-#endif /* ARM_ETHOSN_NPU_TZMP1 */
+#if ETHOSN_NPU_TZMP1
+ [ETHOSN_NPU_FW_KEY_CERT_ID] = &npu_fw_key_cert,
+ [ETHOSN_NPU_FW_CONTENT_CERT_ID] = &npu_fw_content_cert,
+ [ETHOSN_NPU_FW_IMAGE_ID] = &npu_fw_image,
+#endif /* ETHOSN_NPU_TZMP1 */
};
/* Register the CoT in the authentication module */
diff --git a/plat/arm/board/juno/platform.mk b/plat/arm/board/juno/platform.mk
index a4e6407..19091f3 100644
--- a/plat/arm/board/juno/platform.mk
+++ b/plat/arm/board/juno/platform.mk
@@ -43,8 +43,8 @@
JUNO_TZMP1 := 0
$(eval $(call assert_boolean,JUNO_TZMP1))
ifeq (${JUNO_TZMP1}, 1)
- ifeq (${ARM_ETHOSN_NPU_TZMP1},1)
- $(error JUNO_TZMP1 cannot be used together with ARM_ETHOSN_NPU_TZMP1)
+ ifeq (${ETHOSN_NPU_TZMP1},1)
+ $(error JUNO_TZMP1 cannot be used together with ETHOSN_NPU_TZMP1)
else
$(eval $(call add_define,JUNO_TZMP1))
endif
@@ -207,6 +207,7 @@
# Add the HW_CONFIG to FIP and specify the same to certtool
$(eval $(call TOOL_ADD_PAYLOAD,${HW_CONFIG},--hw-config,${HW_CONFIG}))
+include drivers/arm/ethosn/ethosn_npu.mk
include plat/arm/board/common/board_common.mk
include plat/arm/common/arm_common.mk
include plat/arm/soc/common/soc_css.mk
diff --git a/plat/arm/board/tc/tc_bl1_measured_boot.c b/plat/arm/board/tc/tc_bl1_measured_boot.c
index 6d4bb07..6821a6a 100644
--- a/plat/arm/board/tc/tc_bl1_measured_boot.c
+++ b/plat/arm/board/tc/tc_bl1_measured_boot.c
@@ -9,6 +9,7 @@
#include <drivers/arm/rss_comms.h>
#include <drivers/measured_boot/rss/rss_measured_boot.h>
#include <lib/psa/measured_boot.h>
+#include <tools_share/zero_oid.h>
#include <plat/arm/common/plat_arm.h>
#include <platform_def.h>
@@ -22,18 +23,21 @@
.slot = U(6),
.signer_id_size = SIGNER_ID_MIN_SIZE,
.sw_type = RSS_MBOOT_FW_CONFIG_STRING,
+ .pk_oid = ZERO_OID,
.lock_measurement = true },
{
.id = TB_FW_CONFIG_ID,
.slot = U(7),
.signer_id_size = SIGNER_ID_MIN_SIZE,
.sw_type = RSS_MBOOT_TB_FW_CONFIG_STRING,
+ .pk_oid = ZERO_OID,
.lock_measurement = true },
{
.id = BL2_IMAGE_ID,
.slot = U(8),
.signer_id_size = SIGNER_ID_MIN_SIZE,
.sw_type = RSS_MBOOT_BL2_STRING,
+ .pk_oid = ZERO_OID,
.lock_measurement = true },
{
diff --git a/plat/arm/board/tc/tc_bl2_measured_boot.c b/plat/arm/board/tc/tc_bl2_measured_boot.c
index 9039853..4b79170 100644
--- a/plat/arm/board/tc/tc_bl2_measured_boot.c
+++ b/plat/arm/board/tc/tc_bl2_measured_boot.c
@@ -9,6 +9,7 @@
#include <drivers/arm/rss_comms.h>
#include <drivers/measured_boot/rss/rss_measured_boot.h>
#include <lib/psa/measured_boot.h>
+#include <tools_share/tbbr_oid.h>
#include <plat/common/common_def.h>
#include <platform_def.h>
@@ -22,18 +23,21 @@
.slot = U(9),
.signer_id_size = SIGNER_ID_MIN_SIZE,
.sw_type = RSS_MBOOT_BL31_STRING,
+ .pk_oid = BL31_IMAGE_KEY_OID,
.lock_measurement = true },
{
.id = HW_CONFIG_ID,
.slot = U(10),
.signer_id_size = SIGNER_ID_MIN_SIZE,
.sw_type = RSS_MBOOT_HW_CONFIG_STRING,
+ .pk_oid = HW_CONFIG_KEY_OID,
.lock_measurement = true },
{
.id = SOC_FW_CONFIG_ID,
.slot = U(11),
.signer_id_size = SIGNER_ID_MIN_SIZE,
.sw_type = RSS_MBOOT_SOC_FW_CONFIG_STRING,
+ .pk_oid = SOC_FW_CONFIG_KEY_OID,
.lock_measurement = true },
{
.id = RSS_MBOOT_INVALID_ID }
diff --git a/plat/arm/board/tc/tc_common_measured_boot.c b/plat/arm/board/tc/tc_common_measured_boot.c
index eddcc81..925a411 100644
--- a/plat/arm/board/tc/tc_common_measured_boot.c
+++ b/plat/arm/board/tc/tc_common_measured_boot.c
@@ -28,3 +28,9 @@
return err;
}
+
+int plat_mboot_measure_key(void *pk_oid, void *pk_ptr, unsigned int pk_len)
+{
+ return rss_mboot_set_signer_id(tc_rss_mboot_metadata, pk_oid, pk_ptr,
+ pk_len);
+}
diff --git a/plat/arm/common/aarch64/arm_bl2_mem_params_desc.c b/plat/arm/common/aarch64/arm_bl2_mem_params_desc.c
index e512192..9a65e7c 100644
--- a/plat/arm/common/aarch64/arm_bl2_mem_params_desc.c
+++ b/plat/arm/common/aarch64/arm_bl2_mem_params_desc.c
@@ -223,17 +223,17 @@
},
#endif /* EL3_PAYLOAD_BASE */
-# if ARM_ETHOSN_NPU_TZMP1
+# if ETHOSN_NPU_TZMP1
{
- .image_id = ARM_ETHOSN_NPU_FW_IMAGE_ID,
+ .image_id = ETHOSN_NPU_FW_IMAGE_ID,
SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
VERSION_2, image_info_t, 0),
- .image_info.image_base = ARM_ETHOSN_NPU_FW_IMAGE_BASE,
- .image_info.image_max_size = ARM_ETHOSN_NPU_FW_IMAGE_LIMIT -
- ARM_ETHOSN_NPU_FW_IMAGE_BASE,
+ .image_info.image_base = ETHOSN_NPU_FW_IMAGE_BASE,
+ .image_info.image_max_size = ETHOSN_NPU_FW_IMAGE_LIMIT -
+ ETHOSN_NPU_FW_IMAGE_BASE,
.next_handoff_image_id = INVALID_IMAGE_ID,
},
-# endif
+#endif /* ETHOSN_NPU_TZMP1 */
};
REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs)
diff --git a/plat/arm/common/arm_common.mk b/plat/arm/common/arm_common.mk
index 647a9d9..4914553 100644
--- a/plat/arm/common/arm_common.mk
+++ b/plat/arm/common/arm_common.mk
@@ -114,48 +114,6 @@
endif
endif
-# Arm(R) Ethos(TM)-N NPU SiP service
-ARM_ETHOSN_NPU_DRIVER := 0
-$(eval $(call assert_boolean,ARM_ETHOSN_NPU_DRIVER))
-$(eval $(call add_define,ARM_ETHOSN_NPU_DRIVER))
-
-# Arm(R) Ethos(TM)-N NPU TZMP1
-ARM_ETHOSN_NPU_TZMP1 := 0
-$(eval $(call assert_boolean,ARM_ETHOSN_NPU_TZMP1))
-$(eval $(call add_define,ARM_ETHOSN_NPU_TZMP1))
-ifeq (${ARM_ETHOSN_NPU_TZMP1},1)
- ifeq (${ARM_ETHOSN_NPU_DRIVER},0)
- $(error ARM_ETHOSN_NPU_TZMP1 is only available if ARM_ETHOSN_NPU_DRIVER=1)
- endif
- ifeq (${PLAT},juno)
- $(eval $(call add_define,JUNO_ETHOSN_TZMP1))
- else
- $(error ARM_ETHOSN_NPU_TZMP1 only supported on Juno platform, not ${PLAT})
- endif
-
- ifeq (${TRUSTED_BOARD_BOOT},0)
- # We rely on TRUSTED_BOARD_BOOT to prevent the firmware code from being
- # tampered with, which is required to protect the confidentiality of protected
- # inference data.
- $(error ARM_ETHOSN_NPU_TZMP1 is only available if TRUSTED_BOARD_BOOT is enabled)
- endif
-
- # We need the FW certificate and key certificate
- $(eval $(call TOOL_ADD_PAYLOAD,${BUILD_PLAT}/npu_fw_key.crt,--npu-fw-key-cert))
- $(eval $(call TOOL_ADD_PAYLOAD,${BUILD_PLAT}/npu_fw_content.crt,--npu-fw-cert))
- # Needed for our OIDs to be available in tbbr_cot_bl2.c
- $(eval $(call add_define, PLAT_DEF_OID))
- PLAT_INCLUDES += -I${PLAT_DIR}certificate/include
- PLAT_INCLUDES += -Iinclude/drivers/arm/
-
- # We need the firmware to be built into the FIP
- $(eval $(call TOOL_ADD_IMG,ARM_ETHOSN_NPU_FW,--npu-fw))
-
- # Needed so that UUIDs from the FIP are available in BL2
- $(eval $(call add_define,PLAT_DEF_FIP_UUID))
- PLAT_INCLUDES += -I${PLAT_DIR}fip
-endif # ARM_ETHOSN_NPU_TZMP1
-
# Use an implementation of SHA-256 with a smaller memory footprint but reduced
# speed.
$(eval $(call add_define,MBEDTLS_SHA256_SMALLER))
@@ -348,18 +306,18 @@
plat/arm/common/arm_topology.c \
plat/common/plat_psci_common.c
-ifneq ($(filter 1,${ENABLE_PMF} ${ARM_ETHOSN_NPU_DRIVER}),)
+ifneq ($(filter 1,${ENABLE_PMF} ${ETHOSN_NPU_DRIVER}),)
ARM_SVC_HANDLER_SRCS :=
ifeq (${ENABLE_PMF},1)
ARM_SVC_HANDLER_SRCS += lib/pmf/pmf_smc.c
endif
-ifeq (${ARM_ETHOSN_NPU_DRIVER},1)
+ifeq (${ETHOSN_NPU_DRIVER},1)
ARM_SVC_HANDLER_SRCS += plat/arm/common/fconf/fconf_ethosn_getter.c \
drivers/delay_timer/delay_timer.c \
drivers/arm/ethosn/ethosn_smc.c
-ifeq (${ARM_ETHOSN_NPU_TZMP1},1)
+ifeq (${ETHOSN_NPU_TZMP1},1)
ARM_SVC_HANDLER_SRCS += drivers/arm/ethosn/ethosn_big_fw.c
endif
endif
diff --git a/plat/arm/common/arm_sip_svc.c b/plat/arm/common/arm_sip_svc.c
index 7c3e13d..352d477 100644
--- a/plat/arm/common/arm_sip_svc.c
+++ b/plat/arm/common/arm_sip_svc.c
@@ -37,13 +37,13 @@
#endif /* USE_DEBUGFS */
-#if ARM_ETHOSN_NPU_DRIVER
+#if ETHOSN_NPU_DRIVER
if (ethosn_smc_setup() != 0) {
return 1;
}
-#endif /* ARM_ETHOSN_NPU_DRIVER */
+#endif /* ETHOSN_NPU_DRIVER */
return 0;
}
@@ -84,14 +84,14 @@
#endif /* USE_DEBUGFS */
-#if ARM_ETHOSN_NPU_DRIVER
+#if ETHOSN_NPU_DRIVER
if (is_ethosn_fid(smc_fid)) {
return ethosn_smc_handler(smc_fid, x1, x2, x3, x4, cookie,
handle, flags);
}
-#endif /* ARM_ETHOSN_NPU_DRIVER */
+#endif /* ETHOSN_NPU_DRIVER */
switch (smc_fid) {
case ARM_SIP_SVC_EXE_STATE_SWITCH: {
@@ -117,10 +117,10 @@
/* PMF calls */
call_count += PMF_NUM_SMC_CALLS;
-#if ARM_ETHOSN_NPU_DRIVER
+#if ETHOSN_NPU_DRIVER
/* ETHOSN calls */
call_count += ETHOSN_NUM_SMC_CALLS;
-#endif /* ARM_ETHOSN_NPU_DRIVER */
+#endif /* ETHOSN_NPU_DRIVER */
/* State switch call */
call_count += 1;
diff --git a/plat/arm/common/fconf/arm_fconf_io.c b/plat/arm/common/fconf/arm_fconf_io.c
index 743cc90..27acc3a 100644
--- a/plat/arm/common/fconf/arm_fconf_io.c
+++ b/plat/arm/common/fconf/arm_fconf_io.c
@@ -68,9 +68,9 @@
[TOS_FW_CONFIG_ID] = {UUID_TOS_FW_CONFIG},
[NT_FW_CONFIG_ID] = {UUID_NT_FW_CONFIG},
[RMM_IMAGE_ID] = {UUID_REALM_MONITOR_MGMT_FIRMWARE},
-#if ARM_ETHOSN_NPU_TZMP1
- [ARM_ETHOSN_NPU_FW_IMAGE_ID] = {UUID_ETHOSN_FW},
-#endif /* ARM_ETHOSN_NPU_TZMP1 */
+#if ETHOSN_NPU_TZMP1
+ [ETHOSN_NPU_FW_IMAGE_ID] = {UUID_ETHOSN_FW},
+#endif /* ETHOSN_NPU_TZMP1 */
#endif /* ARM_IO_IN_DTB */
#if TRUSTED_BOARD_BOOT
[TRUSTED_BOOT_FW_CERT_ID] = {UUID_TRUSTED_BOOT_FW_CERT},
@@ -91,10 +91,10 @@
[SIP_SP_CONTENT_CERT_ID] = {UUID_SIP_SECURE_PARTITION_CONTENT_CERT},
[PLAT_SP_CONTENT_CERT_ID] = {UUID_PLAT_SECURE_PARTITION_CONTENT_CERT},
#endif
-#if ARM_ETHOSN_NPU_TZMP1
- [ARM_ETHOSN_NPU_FW_KEY_CERT_ID] = {UUID_ETHOSN_FW_KEY_CERTIFICATE},
- [ARM_ETHOSN_NPU_FW_CONTENT_CERT_ID] = {UUID_ETHOSN_FW_CONTENT_CERTIFICATE},
-#endif /* ARM_ETHOSN_NPU_TZMP1 */
+#if ETHOSN_NPU_TZMP1
+ [ETHOSN_NPU_FW_KEY_CERT_ID] = {UUID_ETHOSN_FW_KEY_CERTIFICATE},
+ [ETHOSN_NPU_FW_CONTENT_CERT_ID] = {UUID_ETHOSN_FW_CONTENT_CERTIFICATE},
+#endif /* ETHOSN_NPU_TZMP1 */
#endif /* ARM_IO_IN_DTB */
#endif /* TRUSTED_BOARD_BOOT */
};
@@ -198,13 +198,13 @@
(uintptr_t)&arm_uuid_spec[NT_FW_CONFIG_ID],
open_fip
},
-#if ARM_ETHOSN_NPU_TZMP1
- [ARM_ETHOSN_NPU_FW_IMAGE_ID] = {
+#if ETHOSN_NPU_TZMP1
+ [ETHOSN_NPU_FW_IMAGE_ID] = {
&fip_dev_handle,
- (uintptr_t)&arm_uuid_spec[ARM_ETHOSN_NPU_FW_IMAGE_ID],
+ (uintptr_t)&arm_uuid_spec[ETHOSN_NPU_FW_IMAGE_ID],
open_fip
},
-#endif /* ARM_ETHOSN_NPU_TZMP1 */
+#endif /* ETHOSN_NPU_TZMP1 */
#endif /* ARM_IO_IN_DTB */
#if TRUSTED_BOARD_BOOT
[TRUSTED_BOOT_FW_CERT_ID] = {
@@ -285,18 +285,18 @@
open_fip
},
#endif
-#if ARM_ETHOSN_NPU_TZMP1
- [ARM_ETHOSN_NPU_FW_KEY_CERT_ID] = {
+#if ETHOSN_NPU_TZMP1
+ [ETHOSN_NPU_FW_KEY_CERT_ID] = {
&fip_dev_handle,
- (uintptr_t)&arm_uuid_spec[ARM_ETHOSN_NPU_FW_KEY_CERT_ID],
+ (uintptr_t)&arm_uuid_spec[ETHOSN_NPU_FW_KEY_CERT_ID],
open_fip
},
- [ARM_ETHOSN_NPU_FW_CONTENT_CERT_ID] = {
+ [ETHOSN_NPU_FW_CONTENT_CERT_ID] = {
&fip_dev_handle,
- (uintptr_t)&arm_uuid_spec[ARM_ETHOSN_NPU_FW_CONTENT_CERT_ID],
+ (uintptr_t)&arm_uuid_spec[ETHOSN_NPU_FW_CONTENT_CERT_ID],
open_fip
},
-#endif /* ARM_ETHOSN_NPU_TZMP1 */
+#endif /* ETHOSN_NPU_TZMP1 */
#endif /* ARM_IO_IN_DTB */
#endif /* TRUSTED_BOARD_BOOT */
};
@@ -305,11 +305,11 @@
#define FCONF_ARM_IO_UUID_NUM_BASE U(10)
-#if ARM_ETHOSN_NPU_TZMP1
+#if ETHOSN_NPU_TZMP1
#define FCONF_ARM_IO_UUID_NUM_NPU U(1)
#else
#define FCONF_ARM_IO_UUID_NUM_NPU U(0)
-#endif
+#endif /* ETHOSN_NPU_TZMP1 */
#if TRUSTED_BOARD_BOOT
#define FCONF_ARM_IO_UUID_NUM_TBB U(12)
@@ -323,11 +323,11 @@
#define FCONF_ARM_IO_UUID_NUM_SPD U(0)
#endif /* TRUSTED_BOARD_BOOT && defined(SPD_spmd) */
-#if TRUSTED_BOARD_BOOT && ARM_ETHOSN_NPU_TZMP1
+#if TRUSTED_BOARD_BOOT && ETHOSN_NPU_TZMP1
#define FCONF_ARM_IO_UUID_NUM_NPU_TBB U(2)
#else
#define FCONF_ARM_IO_UUID_NUM_NPU_TBB U(0)
-#endif /* TRUSTED_BOARD_BOOT && ARM_ETHOSN_NPU_TZMP1 */
+#endif /* TRUSTED_BOARD_BOOT && ETHOSN_NPU_TZMP1 */
#define FCONF_ARM_IO_UUID_NUMBER FCONF_ARM_IO_UUID_NUM_BASE + \
FCONF_ARM_IO_UUID_NUM_NPU + \
@@ -355,9 +355,9 @@
{SOC_FW_CONFIG_ID, "soc_fw_cfg_uuid"},
{TOS_FW_CONFIG_ID, "tos_fw_cfg_uuid"},
{NT_FW_CONFIG_ID, "nt_fw_cfg_uuid"},
-#if ARM_ETHOSN_NPU_TZMP1
- {ARM_ETHOSN_NPU_FW_IMAGE_ID, "arm_ethosn_npu_fw_uuid"},
-#endif /* ARM_ETHOSN_NPU_TZMP1 */
+#if ETHOSN_NPU_TZMP1
+ {ETHOSN_NPU_FW_IMAGE_ID, "ethosn_npu_fw_uuid"},
+#endif /* ETHOSN_NPU_TZMP1 */
#if TRUSTED_BOARD_BOOT
{CCA_CONTENT_CERT_ID, "cca_cert_uuid"},
{CORE_SWD_KEY_CERT_ID, "core_swd_cert_uuid"},
@@ -375,10 +375,10 @@
{SIP_SP_CONTENT_CERT_ID, "sip_sp_content_cert_uuid"},
{PLAT_SP_CONTENT_CERT_ID, "plat_sp_content_cert_uuid"},
#endif
-#if ARM_ETHOSN_NPU_TZMP1
- {ARM_ETHOSN_NPU_FW_KEY_CERT_ID, "arm_ethosn_npu_fw_key_cert_uuid"},
- {ARM_ETHOSN_NPU_FW_CONTENT_CERT_ID, "arm_ethosn_npu_fw_content_cert_uuid"},
-#endif /* ARM_ETHOSN_NPU_TZMP1 */
+#if ETHOSN_NPU_TZMP1
+ {ETHOSN_NPU_FW_KEY_CERT_ID, "ethosn_npu_fw_key_cert_uuid"},
+ {ETHOSN_NPU_FW_CONTENT_CERT_ID, "ethosn_npu_fw_content_cert_uuid"},
+#endif /* ETHOSN_NPU_TZMP1 */
#endif /* TRUSTED_BOARD_BOOT */
};
diff --git a/plat/imx/imx8m/imx8m_measured_boot.c b/plat/imx/imx8m/imx8m_measured_boot.c
index e9ea2d8..bfcd6ce 100644
--- a/plat/imx/imx8m/imx8m_measured_boot.c
+++ b/plat/imx/imx8m/imx8m_measured_boot.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2022-2023, Arm Limited. All rights reserved.
* Copyright (c) 2022, Linaro.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -79,3 +79,9 @@
dump_event_log((uint8_t *)event_log, event_log_cur_size);
}
+
+int plat_mboot_measure_key(const void *pk_oid, const void *pk_ptr,
+ size_t pk_len)
+{
+ return 0;
+}
diff --git a/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c b/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c
index 8e66361..c8a3adf 100644
--- a/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c
+++ b/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c
@@ -131,7 +131,7 @@
void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
- unsigned int console_base = 0U;
+ unsigned int console_base = IMX_BOOT_UART_BASE;
static console_t console;
int i;
@@ -146,9 +146,6 @@
imx_csu_init(csu_cfg);
-#if IMX_BOOT_UART_BASE
- console_base = IMX_BOOT_UART_BASE;
-#endif
if (console_base == 0U) {
console_base = imx8m_uart_get_base();
}
diff --git a/plat/imx/imx8m/imx8mm/platform.mk b/plat/imx/imx8m/imx8mm/platform.mk
index 2462517..6f6daf8 100644
--- a/plat/imx/imx8m/imx8mm/platform.mk
+++ b/plat/imx/imx8m/imx8mm/platform.mk
@@ -159,6 +159,9 @@
$(eval $(call add_define,BL32_SIZE))
IMX_BOOT_UART_BASE ?= 0x30890000
+ifeq (${IMX_BOOT_UART_BASE},auto)
+ override IMX_BOOT_UART_BASE := 0
+endif
$(eval $(call add_define,IMX_BOOT_UART_BASE))
EL3_EXCEPTION_HANDLING := $(SDEI_SUPPORT)
diff --git a/plat/imx/imx8m/imx8mn/imx8mn_bl31_setup.c b/plat/imx/imx8m/imx8mn/imx8mn_bl31_setup.c
index aeb1cbf..147249e 100644
--- a/plat/imx/imx8m/imx8mn/imx8mn_bl31_setup.c
+++ b/plat/imx/imx8m/imx8mn/imx8mn_bl31_setup.c
@@ -122,7 +122,7 @@
void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
- unsigned int console_base = 0U;
+ unsigned int console_base = IMX_BOOT_UART_BASE;
static console_t console;
unsigned int val;
int i;
@@ -143,9 +143,6 @@
val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x2c);
mmio_write_32(IMX_IOMUX_GPR_BASE + 0x2c, val | 0x3DFF0000);
-#if IMX_BOOT_UART_BASE
- console_base = IMX_BOOT_UART_BASE;
-#endif
if (console_base == 0U) {
console_base = imx8m_uart_get_base();
}
diff --git a/plat/imx/imx8m/imx8mn/platform.mk b/plat/imx/imx8m/imx8mn/platform.mk
index 4651610..a6b43f2 100644
--- a/plat/imx/imx8m/imx8mn/platform.mk
+++ b/plat/imx/imx8m/imx8mn/platform.mk
@@ -65,6 +65,9 @@
$(eval $(call add_define,BL32_SIZE))
IMX_BOOT_UART_BASE ?= 0x30890000
+ifeq (${IMX_BOOT_UART_BASE},auto)
+ override IMX_BOOT_UART_BASE := 0
+endif
$(eval $(call add_define,IMX_BOOT_UART_BASE))
EL3_EXCEPTION_HANDLING := $(SDEI_SUPPORT)
diff --git a/plat/imx/imx8m/imx8mp/imx8mp_bl31_setup.c b/plat/imx/imx8m/imx8mp/imx8mp_bl31_setup.c
index e25668b..b0a41c7 100644
--- a/plat/imx/imx8m/imx8mp/imx8mp_bl31_setup.c
+++ b/plat/imx/imx8m/imx8mp/imx8mp_bl31_setup.c
@@ -118,7 +118,7 @@
void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
- unsigned int console_base = 0U;
+ unsigned int console_base = IMX_BOOT_UART_BASE;
static console_t console;
unsigned int val;
unsigned int i;
@@ -139,9 +139,6 @@
val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x2c);
mmio_write_32(IMX_IOMUX_GPR_BASE + 0x2c, val | 0x3DFF0000);
-#if IMX_BOOT_UART_BASE
- console_base = IMX_BOOT_UART_BASE;
-#endif
if (console_base == 0U) {
console_base = imx8m_uart_get_base();
}
diff --git a/plat/imx/imx8m/imx8mp/platform.mk b/plat/imx/imx8m/imx8mp/platform.mk
index 21836d9..a8400a4 100644
--- a/plat/imx/imx8m/imx8mp/platform.mk
+++ b/plat/imx/imx8m/imx8mp/platform.mk
@@ -156,6 +156,9 @@
$(eval $(call add_define,BL32_SIZE))
IMX_BOOT_UART_BASE ?= 0x30890000
+ifeq (${IMX_BOOT_UART_BASE},auto)
+ override IMX_BOOT_UART_BASE := 0
+endif
$(eval $(call add_define,IMX_BOOT_UART_BASE))
EL3_EXCEPTION_HANDLING := $(SDEI_SUPPORT)
diff --git a/plat/nvidia/tegra/include/lib/profiler.h b/plat/nvidia/tegra/include/lib/profiler.h
index 684c872..a7d5e7b 100644
--- a/plat/nvidia/tegra/include/lib/profiler.h
+++ b/plat/nvidia/tegra/include/lib/profiler.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
diff --git a/plat/nvidia/tegra/lib/debug/profiler.c b/plat/nvidia/tegra/lib/debug/profiler.c
index dd76a4e..b5baf42 100644
--- a/plat/nvidia/tegra/lib/debug/profiler.c
+++ b/plat/nvidia/tegra/lib/debug/profiler.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/plat/qemu/qemu/qemu_measured_boot.c b/plat/qemu/qemu/qemu_measured_boot.c
index 122bb23..077f7a4 100644
--- a/plat/qemu/qemu/qemu_measured_boot.c
+++ b/plat/qemu/qemu/qemu_measured_boot.c
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2022, Arm Limited. All rights reserved.
- * Copyright (c) 2022, Linaro.
+ * Copyright (c) 2022-2023, Linaro.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -118,3 +118,9 @@
return 0;
}
+
+int plat_mboot_measure_key(const void *pk_oid, const void *pk_ptr,
+ size_t pk_len)
+{
+ return 0;
+}
diff --git a/plat/st/common/bl2_io_storage.c b/plat/st/common/bl2_io_storage.c
index c935b7d..5b0a171 100644
--- a/plat/st/common/bl2_io_storage.c
+++ b/plat/st/common/bl2_io_storage.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -222,7 +222,7 @@
static void boot_mmc(enum mmc_device_type mmc_dev_type,
uint16_t boot_interface_instance)
{
- int io_result __unused;
+ int io_result __maybe_unused;
struct stm32_sdmmc2_params params;
zeromem(¶ms, sizeof(struct stm32_sdmmc2_params));
@@ -294,7 +294,7 @@
#if STM32MP_SPI_NOR
static void boot_spi_nor(boot_api_context_t *boot_context)
{
- int io_result __unused;
+ int io_result __maybe_unused;
io_result = stm32_qspi_init();
assert(io_result == 0);
@@ -313,7 +313,7 @@
#if STM32MP_RAW_NAND
static void boot_fmc2_nand(boot_api_context_t *boot_context)
{
- int io_result __unused;
+ int io_result __maybe_unused;
io_result = stm32_fmc2_init();
assert(io_result == 0);
@@ -332,7 +332,7 @@
#if STM32MP_SPI_NAND
static void boot_spi_nand(boot_api_context_t *boot_context)
{
- int io_result __unused;
+ int io_result __maybe_unused;
io_result = stm32_qspi_init();
assert(io_result == 0);
@@ -351,7 +351,7 @@
#if STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER
static void mmap_io_setup(void)
{
- int io_result __unused;
+ int io_result __maybe_unused;
io_result = register_io_dev_memmap(&memmap_dev_con);
assert(io_result == 0);
@@ -364,7 +364,7 @@
#if STM32MP_UART_PROGRAMMER
static void stm32cubeprogrammer_uart(void)
{
- int ret __unused;
+ int ret __maybe_unused;
boot_api_context_t *boot_context =
(boot_api_context_t *)stm32mp_get_boot_ctx_address();
uintptr_t uart_base;
@@ -378,7 +378,7 @@
#if STM32MP_USB_PROGRAMMER
static void stm32cubeprogrammer_usb(void)
{
- int ret __unused;
+ int ret __maybe_unused;
struct usb_handle *pdev;
/* Init USB on platform */
@@ -390,10 +390,9 @@
#endif
#endif /* STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER */
-
void stm32mp_io_setup(void)
{
- int io_result __unused;
+ int io_result __maybe_unused;
boot_api_context_t *boot_context =
(boot_api_context_t *)stm32mp_get_boot_ctx_address();
@@ -473,7 +472,7 @@
int bl2_plat_handle_pre_image_load(unsigned int image_id)
{
- static bool gpt_init_done __unused;
+ static bool gpt_init_done __maybe_unused;
uint16_t boot_itf = stm32mp_get_boot_itf_selected();
switch (boot_itf) {
@@ -516,6 +515,7 @@
gpt_init_done = true;
} else {
bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
+
assert(bl_mem_params != NULL);
mmc_block_dev_spec.buffer.offset = bl_mem_params->image_info.image_base;
@@ -538,7 +538,14 @@
#if STM32MP_SPI_NOR
case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_QSPI:
+/*
+ * With FWU Multi Bank feature enabled, the selection of
+ * the image to boot will be done by fwu_init calling the
+ * platform hook, plat_fwu_set_images_source.
+ */
+#if !PSA_FWU_SUPPORT
image_block_spec.offset = STM32MP_NOR_FIP_OFFSET;
+#endif
break;
#endif
@@ -591,7 +598,7 @@
return rc;
}
-#if (STM32MP_SDMMC || STM32MP_EMMC) && PSA_FWU_SUPPORT
+#if (STM32MP_SDMMC || STM32MP_EMMC || STM32MP_SPI_NOR) && PSA_FWU_SUPPORT
/*
* In each boot in non-trial mode, we set the BKP register to
* FWU_MAX_TRIAL_REBOOT, and return the active_index from metadata.
@@ -652,54 +659,108 @@
{
unsigned int i;
uint32_t boot_idx;
- const partition_entry_t *entry;
- const uuid_t *img_type_uuid, *img_uuid;
+ const partition_entry_t *entry __maybe_unused;
+ const uuid_t *img_type_uuid;
+ const uuid_t *img_uuid __maybe_unused;
io_block_spec_t *image_spec;
+ const uint16_t boot_itf = stm32mp_get_boot_itf_selected();
boot_idx = plat_fwu_get_boot_idx();
assert(boot_idx < NR_OF_FW_BANKS);
for (i = 0U; i < NR_OF_IMAGES_IN_FW_BANK; i++) {
img_type_uuid = &metadata->img_entry[i].img_type_uuid;
+
+ img_uuid = &metadata->img_entry[i].img_props[boot_idx].img_uuid;
+
image_spec = stm32_get_image_spec(img_type_uuid);
if (image_spec == NULL) {
ERROR("Unable to get image spec for the image in the metadata\n");
panic();
}
- img_uuid =
- &metadata->img_entry[i].img_props[boot_idx].img_uuid;
+ switch (boot_itf) {
+#if (STM32MP_SDMMC || STM32MP_EMMC)
+ case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD:
+ case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC:
+ entry = get_partition_entry_by_uuid(img_uuid);
+ if (entry == NULL) {
+ ERROR("No partition with the uuid mentioned in metadata\n");
+ panic();
+ }
- entry = get_partition_entry_by_uuid(img_uuid);
- if (entry == NULL) {
- ERROR("Unable to find the partition with the uuid mentioned in metadata\n");
+ image_spec->offset = entry->start;
+ image_spec->length = entry->length;
+ break;
+#endif
+#if STM32MP_SPI_NOR
+ case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_QSPI:
+ if (guidcmp(img_uuid, &STM32MP_NOR_FIP_A_GUID) == 0) {
+ image_spec->offset = STM32MP_NOR_FIP_A_OFFSET;
+ } else if (guidcmp(img_uuid, &STM32MP_NOR_FIP_B_GUID) == 0) {
+ image_spec->offset = STM32MP_NOR_FIP_B_OFFSET;
+ } else {
+ ERROR("Invalid uuid mentioned in metadata\n");
+ panic();
+ }
+ break;
+#endif
+ default:
panic();
+ break;
}
-
- image_spec->offset = entry->start;
- image_spec->length = entry->length;
}
}
static int plat_set_image_source(unsigned int image_id,
uintptr_t *handle,
- uintptr_t *image_spec,
- const char *part_name)
+ uintptr_t *image_spec)
{
struct plat_io_policy *policy;
- io_block_spec_t *spec;
- const partition_entry_t *entry = get_partition_entry(part_name);
-
- if (entry == NULL) {
- ERROR("Unable to find the %s partition\n", part_name);
- return -ENOENT;
- }
+ io_block_spec_t *spec __maybe_unused;
+ const partition_entry_t *entry __maybe_unused;
+ const uint16_t boot_itf = stm32mp_get_boot_itf_selected();
policy = &policies[image_id];
-
spec = (io_block_spec_t *)policy->image_spec;
- spec->offset = entry->start;
- spec->length = entry->length;
+
+ switch (boot_itf) {
+#if (STM32MP_SDMMC || STM32MP_EMMC)
+ case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD:
+ case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC:
+ partition_init(GPT_IMAGE_ID);
+
+ if (image_id == FWU_METADATA_IMAGE_ID) {
+ entry = get_partition_entry(METADATA_PART_1);
+ } else {
+ entry = get_partition_entry(METADATA_PART_2);
+ }
+
+ if (entry == NULL) {
+ ERROR("Unable to find a metadata partition\n");
+ return -ENOENT;
+ }
+
+ spec->offset = entry->start;
+ spec->length = entry->length;
+ break;
+#endif
+
+#if STM32MP_SPI_NOR
+ case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_QSPI:
+ if (image_id == FWU_METADATA_IMAGE_ID) {
+ spec->offset = STM32MP_NOR_METADATA1_OFFSET;
+ } else {
+ spec->offset = STM32MP_NOR_METADATA2_OFFSET;
+ }
+
+ spec->length = sizeof(struct fwu_metadata);
+ break;
+#endif
+ default:
+ panic();
+ break;
+ }
*image_spec = policy->image_spec;
*handle = *policy->dev_handle;
@@ -711,20 +772,9 @@
uintptr_t *handle,
uintptr_t *image_spec)
{
- char *part_name;
-
assert((image_id == FWU_METADATA_IMAGE_ID) ||
(image_id == BKUP_FWU_METADATA_IMAGE_ID));
- partition_init(GPT_IMAGE_ID);
-
- if (image_id == FWU_METADATA_IMAGE_ID) {
- part_name = METADATA_PART_1;
- } else {
- part_name = METADATA_PART_2;
- }
-
- return plat_set_image_source(image_id, handle, image_spec,
- part_name);
+ return plat_set_image_source(image_id, handle, image_spec);
}
-#endif /* (STM32MP_SDMMC || STM32MP_EMMC) && PSA_FWU_SUPPORT */
+#endif /* (STM32MP_SDMMC || STM32MP_EMMC || STM32MP_SPI_NOR) && PSA_FWU_SUPPORT */
diff --git a/plat/st/common/stm32mp_fconf_io.c b/plat/st/common/stm32mp_fconf_io.c
index 1a59f0b..5514c09 100644
--- a/plat/st/common/stm32mp_fconf_io.c
+++ b/plat/st/common/stm32mp_fconf_io.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2022, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2021-2023, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -27,12 +27,12 @@
};
#endif
-#if (STM32MP_SDMMC || STM32MP_EMMC) && PSA_FWU_SUPPORT
+#if (STM32MP_SDMMC || STM32MP_EMMC || STM32MP_SPI_NOR) && PSA_FWU_SUPPORT
static io_block_spec_t metadata_block_spec = {
.offset = 0, /* To be filled at runtime */
.length = 0, /* To be filled at runtime */
};
-#endif /* (STM32MP_SDMMC || STM32MP_EMMC) && PSA_FWU_SUPPORT */
+#endif /* (STM32MP_SDMMC || STM32MP_EMMC || STM32MP_SPI_NOR) && PSA_FWU_SUPPORT */
/* By default, STM32 platforms load images from the FIP */
struct plat_io_policy policies[MAX_NUMBER_IDS] = {
@@ -58,7 +58,7 @@
.check = open_storage
},
#endif
-#if (STM32MP_SDMMC || STM32MP_EMMC) && PSA_FWU_SUPPORT
+#if (STM32MP_SDMMC || STM32MP_EMMC || STM32MP_SPI_NOR) && PSA_FWU_SUPPORT
[FWU_METADATA_IMAGE_ID] = {
.dev_handle = &storage_dev_handle,
.image_spec = (uintptr_t)&metadata_block_spec,
@@ -71,7 +71,7 @@
.img_type_guid = NULL_GUID,
.check = open_storage
},
-#endif /* (STM32MP_SDMMC || STM32MP_EMMC) && PSA_FWU_SUPPORT */
+#endif /* (STM32MP_SDMMC || STM32MP_EMMC || STM32MP_SPI_NOR) && PSA_FWU_SUPPORT */
};
#define DEFAULT_UUID_NUMBER U(7)
diff --git a/plat/st/stm32mp1/sp_min/sp_min-stm32mp1.mk b/plat/st/stm32mp1/sp_min/sp_min-stm32mp1.mk
index f5184e7..9695c9b 100644
--- a/plat/st/stm32mp1/sp_min/sp_min-stm32mp1.mk
+++ b/plat/st/stm32mp1/sp_min/sp_min-stm32mp1.mk
@@ -48,6 +48,3 @@
BL32_SOURCES += plat/st/stm32mp1/services/bsec_svc.c \
plat/st/stm32mp1/services/stm32mp1_svc_setup.c \
plat/st/stm32mp1/stm32mp1_scmi.c
-
-# Arm Archtecture services
-BL32_SOURCES += services/arm_arch_svc/arm_arch_svc_setup.c
diff --git a/plat/st/stm32mp1/stm32mp1_fip_def.h b/plat/st/stm32mp1/stm32mp1_fip_def.h
index 4098386..fa2d20e 100644
--- a/plat/st/stm32mp1/stm32mp1_fip_def.h
+++ b/plat/st/stm32mp1/stm32mp1_fip_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2021-2022, STMicroelectronics - All Rights Reserved
+ * Copyright (C) 2021-2023, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -128,11 +128,26 @@
* STM32MP1 RAW partition offset for devices without GPT
******************************************************************************/
#define STM32MP_EMMC_BOOT_FIP_OFFSET U(0x00040000)
+#if PSA_FWU_SUPPORT
+#define STM32MP_NOR_METADATA1_OFFSET U(0x00080000)
+#define STM32MP_NOR_METADATA2_OFFSET U(0x000C0000)
+#define STM32MP_NOR_FIP_A_OFFSET U(0x00100000)
+#define STM32MP_NOR_FIP_A_GUID (const struct efi_guid)EFI_GUID(0x4fd84c93, \
+ 0x54ef, 0x463f, 0xa7, 0xef, 0xae, 0x25, 0xff,\
+ 0x88, 0x70, 0x87)
+
+#define STM32MP_NOR_FIP_B_OFFSET U(0x00500000)
+#define STM32MP_NOR_FIP_B_GUID (const struct efi_guid)EFI_GUID(0x09c54952, \
+ 0xd5bf, 0x45af, 0xac, 0xee, 0x33, 0x53, 0x03,\
+ 0x76, 0x6f, 0xb3)
+
+#else /* PSA_FWU_SUPPORT */
#ifndef STM32MP_NOR_FIP_OFFSET
#define STM32MP_NOR_FIP_OFFSET U(0x00080000)
#endif
#ifndef STM32MP_NAND_FIP_OFFSET
#define STM32MP_NAND_FIP_OFFSET U(0x00200000)
#endif
+#endif /* PSA_FWU_SUPPORT */
#endif /* STM32MP1_FIP_DEF_H */
diff --git a/plat/xilinx/common/include/pm_svc_main.h b/plat/xilinx/common/include/pm_svc_main.h
index 1a27bdf..4cf7727 100644
--- a/plat/xilinx/common/include/pm_svc_main.h
+++ b/plat/xilinx/common/include/pm_svc_main.h
@@ -10,6 +10,26 @@
#include <pm_common.h>
+/******************************************************************************/
+/**
+ * SECURE_REDUNDANT_CALL() - Adds redundancy to the function call. This is to
+ * avoid glitches which can skip a function call
+ * and cause altering of the code flow in security
+ * critical functions.
+ * @status: Variable which holds the return value of function executed
+ * @status_tmp: Variable which holds the return value of redundant function
+ * call executed
+ * @function: Function to be executed
+ *
+ * Return: None
+ *
+ ******************************************************************************/
+#define SECURE_REDUNDANT_CALL(status, status_tmp, function, ...) \
+ { \
+ status = function(__VA_ARGS__); \
+ status_tmp = function(__VA_ARGS__); \
+ }
+
int32_t pm_setup(void);
uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3,
uint64_t x4, const void *cookie, void *handle,
diff --git a/plat/xilinx/common/plat_fdt.c b/plat/xilinx/common/plat_fdt.c
index 3d12d51..dc3e893 100644
--- a/plat/xilinx/common/plat_fdt.c
+++ b/plat/xilinx/common/plat_fdt.c
@@ -4,8 +4,10 @@
* SPDX-License-Identifier: BSD-3-Clause
*
*/
+#include <common/debug.h>
#include <common/fdt_fixup.h>
#include <common/fdt_wrappers.h>
+#include <libfdt.h>
#include <plat_fdt.h>
#include <platform_def.h>
diff --git a/plat/xilinx/common/plat_startup.c b/plat/xilinx/common/plat_startup.c
index f45c9f0..5beb765 100644
--- a/plat/xilinx/common/plat_startup.c
+++ b/plat/xilinx/common/plat_startup.c
@@ -157,10 +157,10 @@
#endif /* PLAT_versal_net */
/**
- * xbl_tfa_handover() - Populates the bl32 and bl33 image info structures.
+ * xbl_handover() - Populates the bl32 and bl33 image info structures.
* @bl32: BL32 image info structure.
* @bl33: BL33 image info structure.
- * @tfa_handoff_addr: TF-A handoff address.
+ * @handoff_addr: TF-A handoff address.
*
* Process the handoff parameters from the XBL and populate the BL32 and BL33
* image info structures accordingly.
diff --git a/plat/xilinx/common/pm_service/pm_svc_main.c b/plat/xilinx/common/pm_service/pm_svc_main.c
index fb32f2a..1e5808c 100644
--- a/plat/xilinx/common/pm_service/pm_svc_main.c
+++ b/plat/xilinx/common/pm_service/pm_svc_main.c
@@ -23,6 +23,7 @@
#include "pm_api_sys.h"
#include "pm_client.h"
#include "pm_ipi.h"
+#include "pm_svc_main.h"
#define MODE 0x80000000U
@@ -399,8 +400,9 @@
{
uintptr_t ret;
uint32_t pm_arg[PAYLOAD_ARG_CNT] = {0};
- uint32_t security_flag = SECURE_FLAG;
+ uint32_t security_flag = NON_SECURE_FLAG;
uint32_t api_id;
+ bool status = false, status_tmp = false;
/* Handle case where PM wasn't initialized properly */
if (pm_up == false) {
@@ -408,11 +410,14 @@
}
/*
- * Mark BIT24 payload (i.e 1st bit of pm_arg[3] ) as non-secure (1)
- * if smc called is non secure
+ * Mark BIT24 payload (i.e 1st bit of pm_arg[3] ) as secure (0)
+ * if smc called is secure
+ *
+ * Add redundant macro call to immune the code from glitches
*/
- if (is_caller_non_secure(flags) != 0) {
- security_flag = NON_SECURE_FLAG;
+ SECURE_REDUNDANT_CALL(status, status_tmp, is_caller_secure, flags);
+ if ((status != false) && (status_tmp != false)) {
+ security_flag = SECURE_FLAG;
}
pm_arg[0] = (uint32_t)x1;
diff --git a/plat/xilinx/versal/aarch64/versal_helpers.S b/plat/xilinx/versal/aarch64/versal_helpers.S
index f868b18..350ddc4 100644
--- a/plat/xilinx/versal/aarch64/versal_helpers.S
+++ b/plat/xilinx/versal/aarch64/versal_helpers.S
@@ -4,9 +4,9 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
-#include <asm_macros.S>
#include <arch.h>
+#include <asm_macros.S>
#include <drivers/arm/gicv3.h>
#include <platform_def.h>
diff --git a/plat/xilinx/versal/versal_ipi.c b/plat/xilinx/versal/versal_ipi.c
index cdee6b5..74b082d 100644
--- a/plat/xilinx/versal/versal_ipi.c
+++ b/plat/xilinx/versal/versal_ipi.c
@@ -20,7 +20,7 @@
[IPI_ID_PMC] = {
.ipi_bit_mask = PMC_IPI_TRIG_BIT,
.ipi_reg_base = PMC_REG_BASE,
- .secure_only = 0U,
+ .secure_only = IPI_SECURE_MASK,
},
/* A72 IPI */
diff --git a/plat/xilinx/versal_net/aarch64/versal_net_helpers.S b/plat/xilinx/versal_net/aarch64/versal_net_helpers.S
index bc62efc..ccebff2 100644
--- a/plat/xilinx/versal_net/aarch64/versal_net_helpers.S
+++ b/plat/xilinx/versal_net/aarch64/versal_net_helpers.S
@@ -6,9 +6,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
-#include <asm_macros.S>
-
#include <arch.h>
+#include <asm_macros.S>
#include <drivers/arm/gicv3.h>
#include <platform_def.h>
diff --git a/plat/xilinx/versal_net/versal_net_ipi.c b/plat/xilinx/versal_net/versal_net_ipi.c
index 0943c62..e8d8fb7 100644
--- a/plat/xilinx/versal_net/versal_net_ipi.c
+++ b/plat/xilinx/versal_net/versal_net_ipi.c
@@ -26,7 +26,7 @@
[IPI_ID_PMC] = {
.ipi_bit_mask = PMC_IPI_TRIG_BIT,
.ipi_reg_base = IPI0_REG_BASE,
- .secure_only = 0,
+ .secure_only = IPI_SECURE_MASK,
},
/* RPU0 IPI */
diff --git a/plat/xilinx/zynqmp/aarch64/zynqmp_common.c b/plat/xilinx/zynqmp/aarch64/zynqmp_common.c
index a96c378..b584031 100644
--- a/plat/xilinx/zynqmp/aarch64/zynqmp_common.c
+++ b/plat/xilinx/zynqmp/aarch64/zynqmp_common.c
@@ -229,20 +229,9 @@
size_t i, j, len;
const char *name = "EG/EV";
-#ifdef IMAGE_BL32
- /*
- * For BL32, get the chip id info directly by reading corresponding
- * registers instead of making pm call. This has limitation
- * that these registers should be configured to have access
- * from APU which is default case.
- */
- chipid[0] = mmio_read_32(ZYNQMP_CSU_BASEADDR + ZYNQMP_CSU_IDCODE_OFFSET);
- chipid[1] = mmio_read_32(EFUSE_BASEADDR + EFUSE_IPDISABLE_OFFSET);
-#else
if (pm_get_chipid(chipid) != PM_RET_SUCCESS) {
return "XCZUUNKN";
}
-#endif
id = chipid[0] & (ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
ZYNQMP_CSU_IDCODE_SVD_MASK);
diff --git a/plat/xilinx/zynqmp/platform.mk b/plat/xilinx/zynqmp/platform.mk
index 36fa0f8..9c79855 100644
--- a/plat/xilinx/zynqmp/platform.mk
+++ b/plat/xilinx/zynqmp/platform.mk
@@ -20,7 +20,7 @@
EL3_EXCEPTION_HANDLING := $(SDEI_SUPPORT)
# pncd SPD requires secure SGI to be handled at EL1
-ifeq (${SPD},pncd)
+ifeq (${SPD}, $(filter ${SPD},pncd tspd))
ifeq (${ZYNQMP_WDT_RESTART},1)
$(error "Error: ZYNQMP_WDT_RESTART and SPD=pncd are incompatible")
endif
diff --git a/plat/xilinx/zynqmp/tsp/tsp_plat_setup.c b/plat/xilinx/zynqmp/tsp/tsp_plat_setup.c
index ed3300b..02d0b23 100644
--- a/plat/xilinx/zynqmp/tsp/tsp_plat_setup.c
+++ b/plat/xilinx/zynqmp/tsp/tsp_plat_setup.c
@@ -28,9 +28,6 @@
&tsp_boot_console);
console_set_scope(&tsp_boot_console,
CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_BOOT);
-
- /* Initialize the platform config for future decision making */
- zynqmp_config_setup();
}
/*******************************************************************************
diff --git a/services/arm_arch_svc/arm_arch_svc_setup.c b/services/arm_arch_svc/arm_arch_svc_setup.c
index bb042c7..57d211e 100644
--- a/services/arm_arch_svc/arm_arch_svc_setup.c
+++ b/services/arm_arch_svc/arm_arch_svc_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -28,6 +28,8 @@
return SMC_ARCH_CALL_SUCCESS;
case SMCCC_ARCH_SOC_ID:
return plat_is_smccc_feature_available(arg1);
+#ifdef __aarch64__
+ /* Workaround checks are currently only implemented for aarch64 */
#if WORKAROUND_CVE_2017_5715
case SMCCC_ARCH_WORKAROUND_1:
if (check_wa_cve_2017_5715() == ERRATA_NOT_APPLIES)
@@ -88,6 +90,7 @@
}
return 0; /* ERRATA_APPLIES || ERRATA_MISSING */
#endif
+#endif /* __aarch64__ */
/* Fallthrough */
@@ -128,6 +131,7 @@
SMC_RET1(handle, smccc_arch_features(x1));
case SMCCC_ARCH_SOC_ID:
SMC_RET1(handle, smccc_arch_id(x1));
+#ifdef __aarch64__
#if WORKAROUND_CVE_2017_5715
case SMCCC_ARCH_WORKAROUND_1:
/*
@@ -156,6 +160,7 @@
*/
SMC_RET0(handle);
#endif
+#endif /* __aarch64__ */
default:
WARN("Unimplemented Arm Architecture Service Call: 0x%x \n",
smc_fid);
diff --git a/services/std_svc/errata_abi/cpu_errata_info.h b/services/std_svc/errata_abi/cpu_errata_info.h
index 00a3b73..9906fac 100644
--- a/services/std_svc/errata_abi/cpu_errata_info.h
+++ b/services/std_svc/errata_abi/cpu_errata_info.h
@@ -39,7 +39,7 @@
#include <cortex_a9.h>
#endif
-#define MAX_ERRATA_ENTRIES 16
+#define MAX_ERRATA_ENTRIES 32
#define ERRATA_LIST_END (MAX_ERRATA_ENTRIES - 1)
diff --git a/services/std_svc/errata_abi/errata_abi_main.c b/services/std_svc/errata_abi/errata_abi_main.c
index d7f501b..71a907b 100644
--- a/services/std_svc/errata_abi/errata_abi_main.c
+++ b/services/std_svc/errata_abi/errata_abi_main.c
@@ -346,8 +346,10 @@
[12] = {2388450, 0x00, 0x00, ERRATA_N2_2388450},
[13] = {2728475, 0x00, 0x02, ERRATA_N2_2728475, \
ERRATA_NON_ARM_INTERCONNECT},
- [14] = {2743089, 0x00, 0x02, ERRATA_N2_2743089},
- [15 ... ERRATA_LIST_END] = UNDEF_ERRATA,
+ [14] = {2743014, 0x00, 0x02, ERRATA_N2_2743014},
+ [15] = {2743089, 0x00, 0x02, ERRATA_N2_2743089},
+ [16] = {2779511, 0x00, 0x02, ERRATA_N2_2779511},
+ [17 ... ERRATA_LIST_END] = UNDEF_ERRATA,
}
},
#endif /* NEOVERSE_N2_H_INC */
diff --git a/tools/fiptool/plat_fiptool/arm/board/juno/plat_fiptool.mk b/tools/fiptool/plat_fiptool/arm/board/juno/plat_fiptool.mk
index 46b5179..fef2116 100644
--- a/tools/fiptool/plat_fiptool/arm/board/juno/plat_fiptool.mk
+++ b/tools/fiptool/plat_fiptool/arm/board/juno/plat_fiptool.mk
@@ -8,8 +8,8 @@
ifeq (${PLAT_DEF_UUID}, yes)
HOSTCCFLAGS += -DPLAT_DEF_FIP_UUID
-ifeq (${ARM_ETHOSN_NPU_TZMP1},1)
-HOSTCCFLAGS += -DARM_ETHOSN_NPU_TZMP1
+ifeq (${ETHOSN_NPU_TZMP1},1)
+HOSTCCFLAGS += -DETHOSN_NPU_TZMP1
endif
INCLUDE_PATHS += -I./ -I${PLAT_DIR}fip -I../../include/
OBJECTS += ${PLAT_DIR}fip/plat_def_uuid_config.o
diff --git a/tools/sptool/sp_mk_generator.py b/tools/sptool/sp_mk_generator.py
index 4067331..c69e0a7 100644
--- a/tools/sptool/sp_mk_generator.py
+++ b/tools/sptool/sp_mk_generator.py
@@ -1,5 +1,5 @@
#!/usr/bin/python3
-# Copyright (c) 2020-2022, Arm Limited. All rights reserved.
+# Copyright (c) 2020-2023, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
@@ -21,6 +21,7 @@
param2: "SP_LAYOUT_FILE", json file containing platform provided information
param3: plat out directory
param4: CoT parameter
+param5: Generated dts file "sp_list_fragment.dts"
Generated "sp_gen.mk" file contains triplet of following information for each
Secure Partition entry
@@ -112,6 +113,34 @@
''' Helper to fetch pm offset from sp_layout.json '''
return get_offset_from_layout(node["pm"])
+def get_uuid(sp_layout, sp, args :dict):
+ ''' Helper to fetch uuid from pm file listed in sp_layout.json'''
+ if "uuid" in sp_layout[sp]:
+ # Extract the UUID from the JSON file if the SP entry has a 'uuid' field
+ uuid_std = uuid.UUID(sp_layout[sp]['uuid'])
+ else:
+ with open(get_sp_manifest_full_path(sp_layout[sp], args), "r") as pm_f:
+ uuid_lines = [l for l in pm_f if 'uuid' in l]
+ assert(len(uuid_lines) == 1)
+ # The uuid field in SP manifest is the little endian representation
+ # mapped to arguments as described in SMCCC section 5.3.
+ # Convert each unsigned integer value to a big endian representation
+ # required by fiptool.
+ uuid_parsed = re.findall("0x([0-9a-f]+)", uuid_lines[0])
+ y = list(map(bytearray.fromhex, uuid_parsed))
+ z = [int.from_bytes(i, byteorder='little', signed=False) for i in y]
+ uuid_std = uuid.UUID(f'{z[0]:08x}{z[1]:08x}{z[2]:08x}{z[3]:08x}')
+ return uuid_std
+
+def get_load_address(sp_layout, sp, args :dict):
+ ''' Helper to fetch load-address from pm file listed in sp_layout.json'''
+ with open(get_sp_manifest_full_path(sp_layout[sp], args), "r") as pm_f:
+ load_address_lines = [l for l in pm_f if 'load-address' in l]
+ assert(len(load_address_lines) == 1)
+ load_address_parsed = re.search("(0x[0-9a-f]+)", load_address_lines[0])
+ return load_address_parsed.group(0)
+
+
@SpSetupActions.sp_action(global_action=True)
def check_max_sps(sp_layout, _, args :dict):
''' Check validate the maximum number of SPs is respected. '''
@@ -195,37 +224,53 @@
@SpSetupActions.sp_action
def gen_fiptool_args(sp_layout, sp, args :dict):
''' Generate arguments for the FIP Tool. '''
- if "uuid" in sp_layout[sp]:
- # Extract the UUID from the JSON file if the SP entry has a 'uuid' field
- uuid_std = uuid.UUID(sp_layout[sp]['uuid'])
- else:
- with open(get_sp_manifest_full_path(sp_layout[sp], args), "r") as pm_f:
- uuid_lines = [l for l in pm_f if 'uuid' in l]
- assert(len(uuid_lines) == 1)
- # The uuid field in SP manifest is the little endian representation
- # mapped to arguments as described in SMCCC section 5.3.
- # Convert each unsigned integer value to a big endian representation
- # required by fiptool.
- uuid_parsed = re.findall("0x([0-9a-f]+)", uuid_lines[0])
- y = list(map(bytearray.fromhex, uuid_parsed))
- z = [int.from_bytes(i, byteorder='little', signed=False) for i in y]
- uuid_std = uuid.UUID(f'{z[0]:08x}{z[1]:08x}{z[2]:08x}{z[3]:08x}')
+ uuid_std = get_uuid(sp_layout, sp, args)
write_to_sp_mk_gen(f"FIP_ARGS += --blob uuid={str(uuid_std)},file={get_sp_pkg(sp, args)}\n", args)
return args
+@SpSetupActions.sp_action
+def gen_fconf_fragment(sp_layout, sp, args: dict):
+ ''' Generate the fconf fragment file'''
+ with open(args["fconf_fragment"], "a") as f:
+ uuid = get_uuid(sp_layout, sp, args)
+ owner = "Plat" if sp_layout[sp].get("owner") == "Plat" else "SiP"
+
+ if "physical-load-address" in sp_layout[sp].keys():
+ load_address = sp_layout[sp]["physical-load-address"]
+ else:
+ load_address = get_load_address(sp_layout, sp, args)
+
+ f.write(
+f'''\
+{sp} {{
+ uuid = "{uuid}";
+ load-address = <{load_address}>;
+ owner = "{owner}";
+}};
+
+''')
+ return args
+
def init_sp_actions(sys):
- sp_layout_file = os.path.abspath(sys.argv[2])
- with open(sp_layout_file) as json_file:
- sp_layout = json.load(json_file)
# Initialize arguments for the SP actions framework
args = {}
args["sp_gen_mk"] = os.path.abspath(sys.argv[1])
+ sp_layout_file = os.path.abspath(sys.argv[2])
args["sp_layout_dir"] = os.path.dirname(sp_layout_file)
args["out_dir"] = os.path.abspath(sys.argv[3])
args["dualroot"] = sys.argv[4] == "dualroot"
+ args["fconf_fragment"] = os.path.abspath(sys.argv[5])
+
+
+ with open(sp_layout_file) as json_file:
+ sp_layout = json.load(json_file)
#Clear content of file "sp_gen.mk".
with open(args["sp_gen_mk"], "w"):
None
+ #Clear content of file "fconf_fragment".
+ with open(args["fconf_fragment"], "w"):
+ None
+
return args, sp_layout
if __name__ == "__main__":