Tegra194: add RAS exception handling
This patch adds all Tegra194 RAS nodes definitions and support to
handle all uncorrectable RAS errors.
Change-Id: I109b5a8dbca91d92752dc282c4ca30f273c475f9
Signed-off-by: David Pu <dpu@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
diff --git a/include/lib/extensions/ras.h b/include/lib/extensions/ras.h
index 4fc8f04..793ab9f 100644
--- a/include/lib/extensions/ras.h
+++ b/include/lib/extensions/ras.h
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -192,6 +193,7 @@
probe_data);
}
+const char *ras_serr_to_str(unsigned int serr);
int ras_ea_handler(unsigned int ea_reason, uint64_t syndrome, void *cookie,
void *handle, uint64_t flags);
void ras_init(void);
diff --git a/include/lib/extensions/ras_arch.h b/include/lib/extensions/ras_arch.h
index 0c98c4a..55760b0 100644
--- a/include/lib/extensions/ras_arch.h
+++ b/include/lib/extensions/ras_arch.h
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -151,6 +152,9 @@
#define ERROR_STATUS_SET_UC 0x2 /* Uncontainable */
#define ERROR_STATUS_SET_CE 0x3 /* Corrected */
+/* Number of architecturally-defined primary error codes */
+#define ERROR_STATUS_NUM_SERR U(22)
+
/* Implementation Defined Syndrome bit in ESR */
#define SERROR_IDS_BIT U(24)