feat(sctlr2): add support for FEAT_SCTLR2
Arm v8.9 introduces FEAT_SCTLR2, adding SCTLR2_ELx registers.
Support this, context switching the registers and disabling
traps so lower ELs can access the new registers.
Change the FVP platform to default to handling this as a dynamic option
so the right decision can be made by the code at runtime.
Change-Id: I0c4cba86917b6b065a7e8dd6af7daf64ee18dcda
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
diff --git a/include/lib/el3_runtime/context_el1.h b/include/lib/el3_runtime/context_el1.h
index ab3be63..94af210 100644
--- a/include/lib/el3_runtime/context_el1.h
+++ b/include/lib/el3_runtime/context_el1.h
@@ -112,6 +112,10 @@
uint64_t rcwsmask_el1;
} el1_the_regs_t;
+typedef struct el1_sctlr2_regs {
+ uint64_t sctlr2_el1;
+} el1_sctlr2_regs_t;
+
typedef struct el1_sysregs {
el1_common_regs_t common;
@@ -164,6 +168,10 @@
el1_the_regs_t the;
#endif
+#if ENABLE_FEAT_SCTLR2
+ el1_sctlr2_regs_t sctlr2;
+#endif
+
} el1_sysregs_t;
@@ -285,6 +293,15 @@
#define write_el1_ctx_the(ctx, reg, val)
#endif /* ENABLE_FEAT_THE */
+#if ENABLE_FEAT_SCTLR2
+#define read_el1_ctx_sctlr2(ctx, reg) (((ctx)->sctlr2).reg)
+#define write_el1_ctx_sctlr2(ctx, reg, val) ((((ctx)->sctlr2).reg) \
+ = (uint64_t) (val))
+#else
+#define read_el1_ctx_sctlr2(ctx, reg) ULL(0)
+#define write_el1_ctx_sctlr2(ctx, reg, val)
+#endif /* ENABLE_FEAT_SCTLR2 */
+
/******************************************************************************/
#endif /* __ASSEMBLER__ */
diff --git a/include/lib/el3_runtime/context_el2.h b/include/lib/el3_runtime/context_el2.h
index 14c1fb6..ad0b68f 100644
--- a/include/lib/el3_runtime/context_el2.h
+++ b/include/lib/el3_runtime/context_el2.h
@@ -135,6 +135,10 @@
uint64_t mpamvpmv_el2;
} el2_mpam_regs_t;
+typedef struct el2_sctlr2_regs {
+ uint64_t sctlr2_el2;
+} el2_sctlr2_regs_t;
+
typedef struct el2_sysregs {
el2_common_regs_t common;
@@ -203,6 +207,10 @@
el2_mpam_regs_t mpam;
#endif
+#if ENABLE_FEAT_SCTLR2
+ el2_sctlr2_regs_t sctlr2;
+#endif
+
} el2_sysregs_t;
/*
@@ -358,6 +366,15 @@
#define write_el2_ctx_mpam(ctx, reg, val)
#endif /* CTX_INCLUDE_MPAM_REGS */
+#if ENABLE_FEAT_SCTLR2
+#define read_el2_ctx_sctlr2(ctx, reg) (((ctx)->sctlr2).reg)
+#define write_el2_ctx_sctlr2(ctx, reg, val) ((((ctx)->sctlr2).reg) \
+ = (uint64_t) (val))
+#else
+#define read_el2_ctx_sctlr2(ctx, reg) ULL(0)
+#define write_el2_ctx_sctlr2(ctx, reg, val)
+#endif /* ENABLE_FEAT_SCTLR2 */
+
/******************************************************************************/
#endif /* __ASSEMBLER__ */