sc7180 platform support
Adding support for QTI CHIP SC7180 on ATF
Change-Id: I0d82d3a378036003fbd0bc4784f61464bb76ea82
Signed-off-by: Saurabh Gorecha <sgorecha@codeaurora.org>
Co-authored-by: Maulik Shah <mkshah@codeaurora.org>
diff --git a/plat/qti/common/src/aarch64/qti_helpers.S b/plat/qti/common/src/aarch64/qti_helpers.S
new file mode 100644
index 0000000..c1ea7b3
--- /dev/null
+++ b/plat/qti/common/src/aarch64/qti_helpers.S
@@ -0,0 +1,88 @@
+/*
+ * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018,2020, The Linux Foundation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <drivers/arm/gicv2.h>
+#include <drivers/arm/gicv3.h>
+#include <drivers/console.h>
+
+#include <platform_def.h>
+
+ .globl plat_my_core_pos
+ .globl plat_qti_core_pos_by_mpidr
+ .globl plat_reset_handler
+ .globl plat_panic_handler
+
+ /* -----------------------------------------------------
+ * unsigned int plat_qti_core_pos_by_mpidr(uint64_t mpidr)
+ * Helper function to calculate the core position.
+ * With this function:
+ * CorePos = (ClusterId * 4) + CoreId
+ * - In ARM v8 (MPIDR_EL1[24]=0)
+ * ClusterId = MPIDR_EL1[15:8]
+ * CoreId = MPIDR_EL1[7:0]
+ * - In ARM v8.1 (MPIDR_EL1[24]=1)
+ * ClusterId = MPIDR_EL1[23:15]
+ * CoreId = MPIDR_EL1[15:8]
+ * Clobbers: x0 & x1.
+ * -----------------------------------------------------
+ */
+func plat_qti_core_pos_by_mpidr
+ mrs x1, mpidr_el1
+ tst x1, #MPIDR_MT_MASK
+ beq plat_qti_core_pos_by_mpidr_no_mt
+ /* Right shift mpidr by one affinity level when MT=1. */
+ lsr x0, x0, #MPIDR_AFFINITY_BITS
+plat_qti_core_pos_by_mpidr_no_mt:
+ and x1, x0, #MPIDR_CPU_MASK
+ and x0, x0, #MPIDR_CLUSTER_MASK
+ add x0, x1, x0, LSR #6
+ ret
+endfunc plat_qti_core_pos_by_mpidr
+
+ /* --------------------------------------------------------------------
+ * void plat_panic_handler(void)
+ * calls SDI and reset system
+ * --------------------------------------------------------------------
+ */
+func plat_panic_handler
+ msr spsel, #0
+ bl plat_set_my_stack
+ b qtiseclib_panic
+endfunc plat_panic_handler
+
+ /* -----------------------------------------------------
+ * unsigned int plat_my_core_pos(void)
+ * This function uses the plat_qti_calc_core_pos()
+ * definition to get the index of the calling CPU
+ * Clobbers: x0 & x1.
+ * -----------------------------------------------------
+ */
+func plat_my_core_pos
+ mrs x0, mpidr_el1
+ b plat_qti_core_pos_by_mpidr
+endfunc plat_my_core_pos
+
+func plat_reset_handler
+ /* save the lr */
+ mov x18, x30
+
+ /* Serialize CPUSS boot setup. Multi core enter simultaneously. */
+ ldr x0, =g_qti_cpuss_boot_lock
+ bl spin_lock
+
+ /* pass cold boot status. */
+ ldr w0, g_qti_bl31_cold_booted
+ /* Execuete CPUSS boot set up on every core. */
+ bl qtiseclib_cpuss_reset_asm
+
+ ldr x0, =g_qti_cpuss_boot_lock
+ bl spin_unlock
+
+ ret x18
+endfunc plat_reset_handler
diff --git a/plat/qti/common/src/aarch64/qti_kryo4_gold.S b/plat/qti/common/src/aarch64/qti_kryo4_gold.S
new file mode 100644
index 0000000..a1b40c8
--- /dev/null
+++ b/plat/qti/common/src/aarch64/qti_kryo4_gold.S
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <cpu_macros.S>
+
+#include <plat_macros.S>
+#include <qti_cpu.h>
+
+ .p2align 3
+
+/* -------------------------------------------------
+ * The CPU Ops reset function for Kryo-3 Gold
+ * -------------------------------------------------
+ */
+func qti_kryo4_gold_reset_func
+#if IMAGE_BL31 && WORKAROUND_CVE_2017_5715
+ adr x0, wa_cve_2017_5715_bpiall_vbar
+ msr vbar_el3, x0
+ isb
+#endif
+
+ mov x19, x30
+
+ bl qtiseclib_kryo4_gold_reset_asm
+
+ ret x19
+
+endfunc qti_kryo4_gold_reset_func
+
+/* ----------------------------------------------------
+ * The CPU Ops core power down function for Kryo-3 Gold
+ * ----------------------------------------------------
+ */
+func qti_kryo4_gold_core_pwr_dwn
+ ret
+endfunc qti_kryo4_gold_core_pwr_dwn
+
+/* -------------------------------------------------------
+ * The CPU Ops cluster power down function for Kryo-3 Gold
+ * -------------------------------------------------------
+ */
+func qti_kryo4_gold_cluster_pwr_dwn
+ ret
+endfunc qti_kryo4_gold_cluster_pwr_dwn
+
+#if REPORT_ERRATA
+/*
+ * Errata printing function for Kryo4 Gold. Must follow AAPCS.
+ */
+func qti_kryo4_gold_errata_report
+ /* TODO : Need to add support. Required only for debug bl31 image.*/
+ ret
+endfunc qti_kryo4_gold_errata_report
+#endif
+
+/* ---------------------------------------------
+ * This function provides kryo4_gold specific
+ * register information for crash reporting.
+ * It needs to return with x6 pointing to
+ * a list of register names in ASCII and
+ * x8 - x15 having values of registers to be
+ * reported.
+ * ---------------------------------------------
+ */
+.section .rodata.qti_kryo4_gold_regs, "aS"
+qti_kryo4_gold_regs: /* The ASCII list of register names to be reported */
+ .asciz ""
+
+func qti_kryo4_gold_cpu_reg_dump
+ adr x6, qti_kryo4_gold_regs
+ ret
+endfunc qti_kryo4_gold_cpu_reg_dump
+
+declare_cpu_ops qti_kryo4_gold, QTI_KRYO4_GOLD_MIDR, \
+ qti_kryo4_gold_reset_func, \
+ qti_kryo4_gold_core_pwr_dwn, \
+ qti_kryo4_gold_cluster_pwr_dwn
diff --git a/plat/qti/common/src/aarch64/qti_kryo4_silver.S b/plat/qti/common/src/aarch64/qti_kryo4_silver.S
new file mode 100644
index 0000000..183eeb0
--- /dev/null
+++ b/plat/qti/common/src/aarch64/qti_kryo4_silver.S
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <cpu_macros.S>
+
+#include <plat_macros.S>
+#include <qti_cpu.h>
+
+ .p2align 3
+
+/* -------------------------------------------------
+ * The CPU Ops reset function for Kryo-3 Silver
+ * -------------------------------------------------
+ */
+func qti_kryo4_silver_reset_func
+ mov x19, x30
+
+ bl qtiseclib_kryo4_silver_reset_asm
+
+ ret x19
+
+endfunc qti_kryo4_silver_reset_func
+
+/* ------------------------------------------------------
+ * The CPU Ops core power down function for Kryo-3 Silver
+ * ------------------------------------------------------
+ */
+func qti_kryo4_silver_core_pwr_dwn
+ ret
+endfunc qti_kryo4_silver_core_pwr_dwn
+
+/* ---------------------------------------------------------
+ * The CPU Ops cluster power down function for Kryo-3 Silver
+ * ---------------------------------------------------------
+ */
+func qti_kryo4_silver_cluster_pwr_dwn
+ ret
+endfunc qti_kryo4_silver_cluster_pwr_dwn
+
+#if REPORT_ERRATA
+/*
+ * Errata printing function for Kryo4 Silver. Must follow AAPCS.
+ */
+func qti_kryo4_silver_errata_report
+ /* TODO : Need to add support. Required only for debug bl31 image.*/
+ ret
+endfunc qti_kryo4_silver_errata_report
+#endif
+
+
+/* ---------------------------------------------
+ * This function provides kryo4_silver specific
+ * register information for crash reporting.
+ * It needs to return with x6 pointing to
+ * a list of register names in ASCII and
+ * x8 - x15 having values of registers to be
+ * reported.
+ * ---------------------------------------------
+ */
+.section .rodata.qti_kryo4_silver_regs, "aS"
+qti_kryo4_silver_regs: /* The ASCII list of register names to be reported */
+ .asciz ""
+
+func qti_kryo4_silver_cpu_reg_dump
+ adr x6, qti_kryo4_silver_regs
+ ret
+endfunc qti_kryo4_silver_cpu_reg_dump
+
+
+declare_cpu_ops qti_kryo4_silver, QTI_KRYO4_SILVER_MIDR, \
+ qti_kryo4_silver_reset_func, \
+ qti_kryo4_silver_core_pwr_dwn, \
+ qti_kryo4_silver_cluster_pwr_dwn
diff --git a/plat/qti/common/src/aarch64/qti_uart_console.S b/plat/qti/common/src/aarch64/qti_uart_console.S
new file mode 100644
index 0000000..2eb33d9
--- /dev/null
+++ b/plat/qti/common/src/aarch64/qti_uart_console.S
@@ -0,0 +1,102 @@
+/*
+ * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018,2020 The Linux Foundation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <asm_macros.S>
+#include <console_macros.S>
+
+#include <platform_def.h>
+#include <qti_uart_console.h>
+
+/*
+ * This driver implements console logging into a ring buffer.
+ */
+
+ .globl qti_console_uart_register
+
+ /* -----------------------------------------------
+ * int qti_console_uart_register(console_t *console,
+ * uintptr_t uart_base_addr)
+ * Registers uart console instance.
+ * In: x0 - pointer to empty console_t struct
+ * x1 - start address of uart block.
+ * Out: x0 - 1 to indicate success
+ * Clobber list: x0, x1, x14
+ * -----------------------------------------------
+ */
+func qti_console_uart_register
+ str x1, [x0, #CONSOLE_T_BASE] /* Save UART base. */
+ finish_console_register uart putc=1, flush=1
+endfunc qti_console_uart_register
+
+ /* -----------------------------------------------
+ * int qti_console_uart_puts(int c, console_t *console)
+ * Writes a character to the UART console.
+ * The character must be preserved in x0.
+ * In: x0 - character to be stored
+ * x1 - pointer to console_t struct
+ * Clobber list: x1, x2
+ * -----------------------------------------------
+ */
+func console_uart_putc
+ /* set x1 = UART base. */
+ ldr x1, [x1, #CONSOLE_T_BASE]
+
+ /* Loop until M_GENI_CMD_ACTIVE bit not clear. */
+1: ldr w2, [x1, #GENI_STATUS_REG]
+ and w2, w2, #GENI_STATUS_M_GENI_CMD_ACTIVE_MASK
+ cmp w2, #GENI_STATUS_M_GENI_CMD_ACTIVE_MASK
+ b.eq 1b
+
+ /* Transmit data. */
+ cmp w0, #0xA
+ b.ne 3f
+
+ /* Add '\r' when input char is '\n' */
+ mov w2, #0x1
+ mov w0, #0xD
+ str w2, [x1, #UART_TX_TRANS_LEN_REG]
+ mov w2, #GENI_M_CMD_TX
+ str w2, [x1, #GENI_M_CMD0_REG]
+ str w0, [x1, #GENI_TX_FIFOn_REG]
+ mov w0, #0xA
+
+ /* Loop until M_GENI_CMD_ACTIVE bit not clear. */
+2: ldr w2, [x1, #GENI_STATUS_REG]
+ and w2, w2, #GENI_STATUS_M_GENI_CMD_ACTIVE_MASK
+ cmp w2, #GENI_STATUS_M_GENI_CMD_ACTIVE_MASK
+ b.eq 2b
+
+ /* Transmit i/p data. */
+3: mov w2, #0x1
+ str w2, [x1, #UART_TX_TRANS_LEN_REG]
+ mov w2, #GENI_M_CMD_TX
+ str w2, [x1, #GENI_M_CMD0_REG]
+ str w0, [x1, #GENI_TX_FIFOn_REG]
+
+ ret
+endfunc console_uart_putc
+
+ /* -----------------------------------------------
+ * int qti_console_uart_flush(console_t *console)
+ * In: x0 - pointer to console_t struct
+ * Out: x0 - 0 for success
+ * Clobber list: x0, x1
+ * -----------------------------------------------
+ */
+func console_uart_flush
+ /* set x0 = UART base. */
+ ldr x0, [x0, #CONSOLE_T_BASE]
+
+ /* Loop until M_GENI_CMD_ACTIVE bit not clear. */
+1: ldr w1, [x0, #GENI_STATUS_REG]
+ and w1, w1, #GENI_STATUS_M_GENI_CMD_ACTIVE_MASK
+ cmp w1, #GENI_STATUS_M_GENI_CMD_ACTIVE_MASK
+ b.eq 1b
+
+ mov w0, #0
+ ret
+endfunc console_uart_flush