commit 6f980020283c1fd8405db5aefa79fd1ed60f0ccb
author Norbert Werner <opensource@lab-w.org> Sun Jan 19 14:51:01 2020 +0100
committer Olivier Deprez <olivier.deprez@arm.com> Wed Jan 22 10:36:23 2020 +0000
tree b53d006be4e12d9b97f922e567cb733919f377b9
parent b610dd3c5e6282603db6ce06f2085f329587214f

Xilinx zynqmp: add missing pin control group for ethernet 0.

Signed-off-by: Norbert Werner <opensource@lab-w.org>
Change-Id: I3264515e5901689328861964ff664ff08b6e852c

plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c

diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c b/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c
index a900057..4b8dfb6 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c
+++ b/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -1477,6 +1477,7 @@
 	},
 	[PINCTRL_PIN_26] = {
 		.groups = &((uint16_t []) {
+			PINCTRL_GRP_ETHERNET0_0,
 			PINCTRL_GRP_GEMTSU0_0,
 			PINCTRL_GRP_NAND0_1_CE,
 			PINCTRL_GRP_PMU0_0,