Merge pull request #953 from vwadekar/tegra-misra-fixes-v1
Tegra misra fixes v1
diff --git a/plat/arm/css/drivers/scp/css_pm_scmi.c b/plat/arm/css/drivers/scp/css_pm_scmi.c
index b4c0a7d..1ca70a2 100644
--- a/plat/arm/css/drivers/scp/css_pm_scmi.c
+++ b/plat/arm/css/drivers/scp/css_pm_scmi.c
@@ -189,7 +189,7 @@
*/
void css_scp_on(u_register_t mpidr)
{
- int lvl = 0, ret;
+ int lvl = 0, ret, core_pos;
uint32_t scmi_pwr_state = 0;
for (; lvl <= PLAT_MAX_PWR_LVL; lvl++)
@@ -198,8 +198,11 @@
SCMI_SET_PWR_STATE_MAX_PWR_LVL(scmi_pwr_state, lvl - 1);
+ core_pos = plat_core_pos_by_mpidr(mpidr);
+ assert(core_pos >= 0 && core_pos < PLATFORM_CORE_COUNT);
+
ret = scmi_pwr_state_set(scmi_handle,
- plat_css_core_pos_to_scmi_dmn_id_map[plat_core_pos_by_mpidr(mpidr)],
+ plat_css_core_pos_to_scmi_dmn_id_map[core_pos],
scmi_pwr_state);
if (ret != SCMI_E_QUEUED && ret != SCMI_E_SUCCESS) {
diff --git a/plat/arm/css/drivers/scp/css_pm_scpi.c b/plat/arm/css/drivers/scp/css_pm_scpi.c
index 8678d20..545c3fb 100644
--- a/plat/arm/css/drivers/scp/css_pm_scpi.c
+++ b/plat/arm/css/drivers/scp/css_pm_scpi.c
@@ -93,7 +93,16 @@
* The CPU state returned by SCP is an 8-bit bit mask
* corresponding to each CPU in the cluster
*/
+#if ARM_PLAT_MT
+ /*
+ * The current SCPI driver only caters for single-threaded
+ * platforms. Hence we ignore the thread ID (which is always 0)
+ * for such platforms.
+ */
+ element = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK;
+#else
element = mpidr & MPIDR_AFFLVL_MASK;
+#endif /* ARM_PLAT_MT */
return CSS_CPU_PWR_STATE(cpu_state, element) ==
CSS_CPU_PWR_STATE_ON ? HW_ON : HW_OFF;
} else {
diff --git a/plat/arm/css/drivers/scpi/css_scpi.c b/plat/arm/css/drivers/scpi/css_scpi.c
index 4a9d9cf..3e92c86 100644
--- a/plat/arm/css/drivers/scpi/css_scpi.c
+++ b/plat/arm/css/drivers/scpi/css_scpi.c
@@ -183,8 +183,17 @@
* Extract CPU and cluster membership of the given MPIDR. SCPI caters
* for only up to 0xf clusters, and 8 CPUs per cluster
*/
+#if ARM_PLAT_MT
+ /*
+ * The current SCPI driver only caters for single-threaded platforms.
+ * Hence we ignore the thread ID (which is always 0) for such platforms.
+ */
+ cpu = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK;
+ cluster = (mpidr >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK;
+#else
cpu = mpidr & MPIDR_AFFLVL_MASK;
cluster = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK;
+#endif /* ARM_PLAT_MT */
if (cpu >= 8 || cluster >= 0xf)
return -1;
diff --git a/plat/hisilicon/hikey960/hi3660_mailbox.c b/plat/hisilicon/hikey960/hi3660_mailbox.c
deleted file mode 100644
index aa12932..0000000
--- a/plat/hisilicon/hikey960/hi3660_mailbox.c
+++ /dev/null
@@ -1,166 +0,0 @@
-/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-#include <assert.h>
-#include <debug.h>
-#include <errno.h>
-#include <hi3660_mailbox.h>
-#include <mailbox.h>
-#include <mmio.h>
-#include <string.h>
-
-typedef struct hi3660_chan {
- unsigned char src;
- unsigned char dst;
- unsigned char used;
-} hi3660_chan_t;
-
-static hi3660_chan_t chan_map[MBX_MAX_CHANNELS];
-
-static void hi3660_mbox_check_state(int chan, unsigned int state)
-{
- unsigned int data;
-
- data = mmio_read_32(MBX_MODE(chan));
- assert((data & (MBX_MODE_AUTO_ANSWER | MBX_MODE_AUTO_LINK)) == 0);
-
- data &= MBX_MODE_STATE_STATUS_MASK;
- assert(data == state);
- (void)state;
-}
-
-static int hi3660_mbox_send(int chan, void *message, int len)
-{
- int i;
- unsigned int *buf;
- unsigned int data;
-
- assert((chan >= 0) && (chan < MBX_MAX_CHANNELS) &&
- (message != NULL) && (len <= MBX_MAX_DATA_LEN));
- assert((chan_map[chan].used != 0) &&
- (chan_map[chan].src != 0) &&
- (chan_map[chan].dst != 0));
-
- buf = (unsigned int *)message;
- len = ((len + 3) >> 2); /* convert to word count */
- for (i = 0; i < len; i++)
- mmio_write_32(MBX_DATA0(chan) + (i << 2), *(buf + i));
- /* send out */
- mmio_write_32(MBX_SEND(chan), chan_map[chan].src);
-
- do {
- data = mmio_read_32(MBX_ICLR(chan));
- } while ((data & chan_map[chan].src) == 0);
- /* ack */
- mmio_write_32(MBX_ICLR(chan), chan_map[chan].src);
- return 0;
-}
-
-static int hi3660_mbox_recv(int chan, void *message, int *len)
-{
- unsigned int *buf, data;
- int i;
-
- assert((chan >= 0) && (chan < MBX_MAX_CHANNELS) &&
- (message != NULL) && (len != NULL));
- assert((chan_map[chan].used != 0) &&
- (chan_map[chan].src != 0) &&
- (chan_map[chan].dst != 0));
- /* wait IPC event */
- do {
- data = mmio_read_32(MBX_MODE(chan));
- } while ((data & MBX_MODE_STATE_STATUS_MASK) != MBX_MODE_STATE_DEST);
- /* wait to clear interrupt */
- do {
- data = mmio_read_32(MBX_ICLR(chan));
- } while (data == 0);
- do {
- mmio_write_32(MBX_ICLR(chan), chan_map[chan].dst);
- data = mmio_read_32(MBX_ICLR(chan));
- } while (data);
-
- /* read data from IPC */
- buf = (unsigned int *)message;
- for (i = 0; i < MBX_MAX_DATA_LEN; i += 4)
- *(buf + (i >> 2)) = mmio_read_32(MBX_DATA0(chan) + i);
- *len = MBX_MAX_DATA_LEN;
- /* ack */
- mmio_write_32(MBX_SEND(chan), chan_map[chan].dst);
- return 0;
-}
-
-static int hi3660_mbox_request(int chan, int direction)
-{
- unsigned int data;
- unsigned int src, dst;
-
- assert((chan >= 0) && (chan < MBX_MAX_CHANNELS));
-
- if (direction == MAILBOX_DIR_TX) {
- src = CPU_A53;
- dst = CPU_LPM3;
- } else if (direction == MAILBOX_DIR_RX) {
- src = CPU_LPM3;
- dst = CPU_A53;
- } else
- assert(0);
- mmio_write_32(MBX_SOURCE(chan), src);
- data = mmio_read_32(MBX_SOURCE(chan));
- assert(data == src);
-
- /* mask all interrupts */
- mmio_write_32(MBX_IMASK(chan), CPU_MASK);
- /* unmask interrupt */
- mmio_write_32(MBX_IMASK(chan), ~(src | dst));
-
- /* set destination */
- mmio_write_32(MBX_DCLEAR(chan), (~dst) & CPU_MASK);
- mmio_write_32(MBX_DSET(chan), dst);
- data = mmio_read_32(MBX_DSTATUS(chan));
- assert((data & dst) != 0);
-
- /* clear auto link & auto answer */
- data = mmio_read_32(MBX_MODE(chan));
- data &= ~(MBX_MODE_AUTO_ANSWER | MBX_MODE_AUTO_LINK);
- mmio_write_32(MBX_MODE(chan), data);
-
- hi3660_mbox_check_state(chan, MBX_MODE_STATE_SOURCE);
- chan_map[chan].used = 1;
- chan_map[chan].src = src;
- chan_map[chan].dst = dst;
- return 0;
-}
-
-static void hi3660_mbox_free(int chan)
-{
- assert((chan >= 0) && (chan < MBX_MAX_CHANNELS));
-}
-
-static mbox_ops_t hi3660_mbox_ops = {
- .send = hi3660_mbox_send,
- .recv = hi3660_mbox_recv,
- .request = hi3660_mbox_request,
- .free = hi3660_mbox_free,
-};
-
-int hi3660_mbox_init(mbox_params_t *params)
-{
- int result;
- unsigned int data;
-
- assert(params != NULL);
- result = mbox_init(&hi3660_mbox_ops, params);
- assert(result == 0);
- memset(&chan_map, 0, sizeof(chan_map));
-
- /* unlock mailbox */
- data = mmio_read_32(IPC_LOCK);
- while (data == MBX_IPC_LOCKED) {
- mmio_write_32(IPC_LOCK, MBX_IPC_UNLOCK_MAGIC);
- data = mmio_read_32(IPC_LOCK);
- }
- (void)result;
- return 0;
-}
diff --git a/plat/socionext/uniphier/uniphier_nand.c b/plat/socionext/uniphier/uniphier_nand.c
index acf6a74..88f906c 100644
--- a/plat/socionext/uniphier/uniphier_nand.c
+++ b/plat/socionext/uniphier/uniphier_nand.c
@@ -106,8 +106,9 @@
is_bad = bbm != 0xff;
- /* save the result for future re-use */
- nand->bbt[block] = is_bad;
+ /* if possible, save the result for future re-use */
+ if (block < ARRAY_SIZE(nand->bbt))
+ nand->bbt[block] = is_bad;
if (is_bad)
WARN("found bad block at %d. skip.\n", block);
diff --git a/tools/cert_create/Makefile b/tools/cert_create/Makefile
index efd1f25..eae76df 100644
--- a/tools/cert_create/Makefile
+++ b/tools/cert_create/Makefile
@@ -6,7 +6,7 @@
PROJECT := cert_create
PLAT := none
-V := 0
+V ?= 0
DEBUG := 0
BINARY := ${PROJECT}${BIN_EXT}
OPENSSL_DIR := /usr
@@ -50,9 +50,9 @@
CFLAGS += -O2 -DLOG_LEVEL=20
endif
ifeq (${V},0)
- Q := @
+ Q := @
else
- Q :=
+ Q :=
endif
$(eval $(call add_define,USE_TBBR_DEFS))
diff --git a/tools/fiptool/Makefile b/tools/fiptool/Makefile
index ee674b7..5e2ecc1 100644
--- a/tools/fiptool/Makefile
+++ b/tools/fiptool/Makefile
@@ -10,7 +10,7 @@
PROJECT := fiptool${BIN_EXT}
OBJECTS := fiptool.o tbbr_config.o
-V := 0
+V ?= 0
override CPPFLAGS += -D_GNU_SOURCE -D_XOPEN_SOURCE=700
CFLAGS := -Wall -Werror -pedantic -std=c99