tree 0f1fc7589dfee2b37bdc03805b02125d63b1f3f5
parent 25886847a11da822b6476da74cb167b3d9a7f46c
author Icenowy Zheng <icenowy@sipeed.com> 1626917719 +0800
committer Icenowy Zheng <icenowy@aosc.io> 1629822839 +0800

refactor(plat/allwinner): allow new AA64nAA32 position

In newer Allwiner SoCs, the AA64nAA32 wires are mapped to a new register
called "General Control Register0" in the manual rather than the
"Cluster 0 Control Register0" in older SoCs.

Now the position of AA64nAA32 (reg and bit offset) is defined in a few
macros instead assumed to be at bit offset 24 of
SUNXI_CPUCFG_CLS_CTRL_REG0.

Change-Id: I933d00b9a914bf7103e3a9dadbc6d7be1a409668
Signed-off-by: Icenowy Zheng <icenowy@sipeed.com>