PSCI: Fix types of definitions
Also change header guards to fix defects of MISRA C-2012 Rule 21.1.
Change-Id: Ied0d4b0e557ef6119ab669d106d2ac5d99620c57
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Acked-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h
index 7385b5d..397013e 100644
--- a/include/lib/aarch64/arch.h
+++ b/include/lib/aarch64/arch.h
@@ -4,8 +4,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
-#ifndef __ARCH_H__
-#define __ARCH_H__
+#ifndef ARCH_H
+#define ARCH_H
#include <utils_def.h>
@@ -37,10 +37,10 @@
#define MPIDR_AFF3_SHIFT U(32)
#define MPIDR_AFFINITY_MASK ULL(0xff00ffffff)
#define MPIDR_AFFLVL_SHIFT U(3)
-#define MPIDR_AFFLVL0 ULL(0x0)
-#define MPIDR_AFFLVL1 ULL(0x1)
-#define MPIDR_AFFLVL2 ULL(0x2)
-#define MPIDR_AFFLVL3 ULL(0x3)
+#define MPIDR_AFFLVL0 U(0x0)
+#define MPIDR_AFFLVL1 U(0x1)
+#define MPIDR_AFFLVL2 U(0x2)
+#define MPIDR_AFFLVL3 U(0x3)
#define MPIDR_AFFLVL0_VAL(mpidr) \
(((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK)
#define MPIDR_AFFLVL1_VAL(mpidr) \
@@ -739,4 +739,4 @@
#define ERXMISC0_EL1 S3_0_C5_C4_4
#define ERXMISC1_EL1 S3_0_C5_C4_5
-#endif /* __ARCH_H__ */
+#endif /* ARCH_H */
diff --git a/include/lib/psci/psci.h b/include/lib/psci/psci.h
index 1aa9633..f2ee62e 100644
--- a/include/lib/psci/psci.h
+++ b/include/lib/psci/psci.h
@@ -22,14 +22,14 @@
#ifdef PLAT_NUM_PWR_DOMAINS
#define PSCI_NUM_PWR_DOMAINS PLAT_NUM_PWR_DOMAINS
#else
-#define PSCI_NUM_PWR_DOMAINS (U(2) * PLATFORM_CORE_COUNT)
+#define PSCI_NUM_PWR_DOMAINS (2 * PLATFORM_CORE_COUNT)
#endif
#define PSCI_NUM_NON_CPU_PWR_DOMAINS (PSCI_NUM_PWR_DOMAINS - \
PLATFORM_CORE_COUNT)
/* This is the power level corresponding to a CPU */
-#define PSCI_CPU_PWR_LVL (0)
+#define PSCI_CPU_PWR_LVL U(0)
/*
* The maximum power level supported by PSCI. Since PSCI CPU_SUSPEND
@@ -89,9 +89,9 @@
/*******************************************************************************
* PSCI Migrate and friends
******************************************************************************/
-#define PSCI_TOS_UP_MIG_CAP U(0)
-#define PSCI_TOS_NOT_UP_MIG_CAP U(1)
-#define PSCI_TOS_NOT_PRESENT_MP U(2)
+#define PSCI_TOS_UP_MIG_CAP 0
+#define PSCI_TOS_NOT_UP_MIG_CAP 1
+#define PSCI_TOS_NOT_PRESENT_MP 2
/*******************************************************************************
* PSCI CPU_SUSPEND 'power_state' parameter specific defines
@@ -163,10 +163,10 @@
/*
* SYSTEM_RESET2 macros
*/
-#define PSCI_RESET2_TYPE_VENDOR_SHIFT 31
-#define PSCI_RESET2_TYPE_VENDOR (1U << PSCI_RESET2_TYPE_VENDOR_SHIFT)
-#define PSCI_RESET2_TYPE_ARCH (0U << PSCI_RESET2_TYPE_VENDOR_SHIFT)
-#define PSCI_RESET2_SYSTEM_WARM_RESET (PSCI_RESET2_TYPE_ARCH | 0)
+#define PSCI_RESET2_TYPE_VENDOR_SHIFT U(31)
+#define PSCI_RESET2_TYPE_VENDOR (U(1) << PSCI_RESET2_TYPE_VENDOR_SHIFT)
+#define PSCI_RESET2_TYPE_ARCH (U(0) << PSCI_RESET2_TYPE_VENDOR_SHIFT)
+#define PSCI_RESET2_SYSTEM_WARM_RESET (PSCI_RESET2_TYPE_ARCH | U(0))
#ifndef __ASSEMBLY__
@@ -214,11 +214,9 @@
* specified CPU. The definitions of these states can be found in Section 5.15.3
* of PSCI specification (ARM DEN 0022C).
*/
-typedef enum {
- HW_ON = U(0),
- HW_OFF = U(1),
- HW_STANDBY = U(2)
-} node_hw_state_t;
+#define HW_ON 0
+#define HW_OFF 1
+#define HW_STANDBY 2
/*
* Macro to represent invalid affinity level within PSCI.
@@ -231,7 +229,7 @@
typedef uint8_t plat_local_state_t;
/* The local state macro used to represent RUN state. */
-#define PSCI_LOCAL_STATE_RUN U(0)
+#define PSCI_LOCAL_STATE_RUN U(0)
/*
* Function to test whether the plat_local_state is RUN state
@@ -288,7 +286,7 @@
* Highest power level which takes part in a power management
* operation.
*/
- unsigned char target_pwrlvl;
+ unsigned int target_pwrlvl;
/* The local power state of this CPU */
plat_local_state_t local_state;
diff --git a/include/lib/psci/psci_compat.h b/include/lib/psci/psci_compat.h
index 65ac15f..11ed16d 100644
--- a/include/lib/psci/psci_compat.h
+++ b/include/lib/psci/psci_compat.h
@@ -1,14 +1,15 @@
/*
- * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
-#ifndef __PSCI_COMPAT_H__
-#define __PSCI_COMPAT_H__
+#ifndef PSCI_COMPAT_H
+#define PSCI_COMPAT_H
#include <arch.h>
#include <platform_def.h>
+#include <utils_def.h>
#ifndef __ASSEMBLY__
/*
@@ -25,10 +26,10 @@
#define PSCI_AFF_ABSENT 0x0
#define PSCI_AFF_PRESENT 0x1
-#define PSCI_STATE_ON 0x0
-#define PSCI_STATE_OFF 0x1
-#define PSCI_STATE_ON_PENDING 0x2
-#define PSCI_STATE_SUSPEND 0x3
+#define PSCI_STATE_ON U(0x0)
+#define PSCI_STATE_OFF U(0x1)
+#define PSCI_STATE_ON_PENDING U(0x2)
+#define PSCI_STATE_SUSPEND U(0x3)
/*
* Using the compatibility platform interfaces means that the local states
@@ -38,8 +39,8 @@
* involved. Hence if we assume 3 generic states viz, run, standby and
* power down, we can assign 1 and 2 to standby and power down respectively.
*/
-#define PLAT_MAX_RET_STATE 1
-#define PLAT_MAX_OFF_STATE 2
+#define PLAT_MAX_RET_STATE U(1)
+#define PLAT_MAX_OFF_STATE U(2)
/*
* Macro to represent invalid affinity level within PSCI.
@@ -89,4 +90,4 @@
int psci_get_suspend_afflvl(void);
#endif /* ____ASSEMBLY__ */
-#endif /* __PSCI_COMPAT_H__ */
+#endif /* PSCI_COMPAT_H */