diff --git a/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c b/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c
index 0a6515e..355a547 100644
--- a/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c
+++ b/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c
@@ -16,12 +16,25 @@
 #include <mce_private.h>
 #include <mmio.h>
 #include <platform_def.h>
+#include <stdbool.h>
 #include <string.h>
 #include <errno.h>
 #include <t194_nvg.h>
 #include <tegra_def.h>
 #include <tegra_platform.h>
 
+/* Handler to check if MCE firmware is supported */
+static bool mce_firmware_not_supported(void)
+{
+	bool status;
+
+	/* these platforms do not load MCE firmware */
+	status = tegra_platform_is_linsim() || tegra_platform_is_qt() ||
+		 tegra_platform_is_virt_dev_kit();
+
+	return status;
+}
+
 /*******************************************************************************
  * Common handler for all MCE commands
  ******************************************************************************/
@@ -174,7 +187,18 @@
  ******************************************************************************/
 int32_t mce_update_gsc_videomem(void)
 {
-	return nvg_update_ccplex_gsc((uint32_t)TEGRA_NVG_GSC_VPR_IDX);
+	int32_t ret;
+
+	/*
+	 * MCE firmware is not running on simulation platforms.
+	 */
+	if (mce_firmware_not_supported()) {
+		ret = -EINVAL;
+	} else {
+		ret = nvg_update_ccplex_gsc((uint32_t)TEGRA_NVG_CHANNEL_UPDATE_GSC_VPR);
+	}
+
+	return ret;
 }
 
 /*******************************************************************************
@@ -182,7 +206,18 @@
  ******************************************************************************/
 int32_t mce_update_gsc_tzdram(void)
 {
-	return nvg_update_ccplex_gsc((uint32_t)TEGRA_NVG_GSC_TZ_DRAM_IDX);
+	int32_t ret;
+
+	/*
+	 * MCE firmware is not running on simulation platforms.
+	 */
+	if (mce_firmware_not_supported()) {
+		ret = -EINVAL;
+	} else {
+		ret = nvg_update_ccplex_gsc((uint32_t)TEGRA_NVG_CHANNEL_UPDATE_GSC_TZ_DRAM);
+	}
+
+	return ret;
 }
 
 /*******************************************************************************
@@ -190,7 +225,18 @@
  ******************************************************************************/
 int32_t mce_update_gsc_tzram(void)
 {
-	return nvg_update_ccplex_gsc((uint32_t)TEGRA_NVG_GSC_TZRAM);
+	int32_t ret;
+
+	/*
+	 * MCE firmware is not running on simulation platforms.
+	 */
+	if (mce_firmware_not_supported()) {
+		ret = -EINVAL;
+	} else {
+		ret = nvg_update_ccplex_gsc((uint32_t)TEGRA_NVG_CHANNEL_UPDATE_GSC_TZRAM);
+	}
+
+	return ret;
 }
 
 /*******************************************************************************
@@ -215,9 +261,7 @@
 	/*
 	 * MCE firmware is not running on simulation platforms.
 	 */
-	if ((tegra_platform_is_linsim() == 1U) ||
-		(tegra_platform_is_virt_dev_kit() == 1U) ||
-		(tegra_platform_is_qt() == 1U)) {
+	if (mce_firmware_not_supported()) {
 		return;
 	}
 
diff --git a/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c b/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c
index 2eba1d3..6451f02 100644
--- a/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c
+++ b/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c
@@ -142,26 +142,26 @@
  * Indices gives MTS the crossover point in TSC ticks for when it becomes
  * no longer viable to enter the named state
  *
- * Type 0 : NVGDATA[0:31]: C6 Lower bound
- * Type 1 : NVGDATA[0:31]: CC6 Lower bound
- * Type 2 : NVGDATA[0:31]: CG7 Lower bound
+ * Type 5 : NVGDATA[0:31]: C6 Lower bound
+ * Type 6 : NVGDATA[0:31]: CC6 Lower bound
+ * Type 8 : NVGDATA[0:31]: CG7 Lower bound
  */
 int32_t nvg_update_crossover_time(uint32_t type, uint32_t time)
 {
 	int32_t ret = 0;
 
 	switch (type) {
-	case TEGRA_NVG_CROSSOVER_C6:
+	case TEGRA_NVG_CHANNEL_CROSSOVER_C6_LOWER_BOUND:
 		nvg_set_request_data(TEGRA_NVG_CHANNEL_CROSSOVER_C6_LOWER_BOUND,
 			(uint64_t)time);
 		break;
 
-	case TEGRA_NVG_CROSSOVER_CC6:
+	case TEGRA_NVG_CHANNEL_CROSSOVER_CC6_LOWER_BOUND:
 		nvg_set_request_data(TEGRA_NVG_CHANNEL_CROSSOVER_CC6_LOWER_BOUND,
 			(uint64_t)time);
 		break;
 
-	case TEGRA_NVG_CROSSOVER_CG7:
+	case TEGRA_NVG_CHANNEL_CROSSOVER_CG7_LOWER_BOUND:
 		nvg_set_request_data(TEGRA_NVG_CHANNEL_CROSSOVER_CG7_LOWER_BOUND,
 			(uint64_t)time);
 		break;
@@ -288,11 +288,11 @@
  */
 int32_t nvg_update_ccplex_gsc(uint32_t gsc_idx)
 {
-	int32_t ret = 0;
+	int32_t ret;
 
 	/* sanity check GSC ID */
-	if (gsc_idx > (uint32_t)TEGRA_NVG_GSC_VPR_IDX) {
-		ERROR("%s: unknown gsc_idx (%d)\n", __func__, gsc_idx);
+	if (gsc_idx > (uint32_t)TEGRA_NVG_CHANNEL_UPDATE_GSC_VPR) {
+		ERROR("%s: unknown gsc_idx (%u)\n", __func__, gsc_idx);
 		ret = EINVAL;
 	} else {
 		nvg_set_request_data(TEGRA_NVG_CHANNEL_UPDATE_CCPLEX_GSC,