diff --git a/fdts/tc.dts b/fdts/tc.dts
index e0e2df5..53bb267 100644
--- a/fdts/tc.dts
+++ b/fdts/tc.dts
@@ -8,6 +8,7 @@
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
+#include "tc_vers.dtsi"
 
 / {
 	compatible = "arm,tc";
@@ -254,21 +255,21 @@
 		};
 	};
 
-	mbox_db_rx: mhu@45010000 {
+	mbox_db_rx: mhu@MHU_RX_ADDR() {
 		compatible = "arm,mhuv2-rx","arm,primecell";
-		reg = <0x0 0x45010000 0x0 0x1000>;
+		reg = <0x0 MHU_RX_ADDR(0x) 0x0 0x1000>;
 		clocks = <&soc_refclk>;
 		clock-names = "apb_pclk";
 		#mbox-cells = <2>;
-		interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI INT_MBOX_RX IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-names = "mhu_rx";
 		mhu-protocol = "doorbell";
 		arm,mhuv2-protocols = <0 1>;
 	};
 
-	mbox_db_tx: mhu@45000000 {
+	mbox_db_tx: mhu@MHU_TX_ADDR() {
 		compatible = "arm,mhuv2-tx","arm,primecell";
-		reg = <0x0 0x45000000 0x0 0x1000>;
+		reg = <0x0 MHU_TX_ADDR(0x) 0x0 0x1000>;
 		clocks = <&soc_refclk>;
 		clock-names = "apb_pclk";
 		#mbox-cells = <2>;
@@ -277,12 +278,6 @@
 		arm,mhuv2-protocols = <0 1>;
 	};
 
-	cmn-pmu {
-		compatible = "arm,ci-700";
-		reg = <0x0 0x50000000 0x0 0x10000000>;
-		interrupts = <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
 	scmi {
 		compatible = "arm,scmi";
 		mbox-names = "tx", "rx";
@@ -344,7 +339,7 @@
 	soc_uartclk: uartclk {
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
-		clock-frequency = <50000000>;
+		clock-frequency = <UARTCLK_FREQ>;
 		clock-output-names = "uartclk";
 	};
 
@@ -552,7 +547,7 @@
 	 */
 	msc0 {
 		compatible = "arm,mpam-msc";
-		reg = <0x1 0x00010000 0x0 0x2000>;
+		reg = <MPAM_ADDR 0x0 0x2000>;
 	};
 
 	ete0 {
diff --git a/fdts/tc_vers.dtsi b/fdts/tc_vers.dtsi
new file mode 100644
index 0000000..14e6c12
--- /dev/null
+++ b/fdts/tc_vers.dtsi
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2023-2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+#if TARGET_PLATFORM <= 2
+#define INT_MBOX_RX		317
+#define MHU_TX_ADDR(pref)	pref##45000000 /* hex */
+#define MHU_RX_ADDR(pref)	pref##45010000 /* hex */
+#define MPAM_ADDR		0x1 0x00010000 /* 0x1_0001_0000 */
+#define UARTCLK_FREQ		5000000
+#elif TARGET_PLATFORM == 3
+#define INT_MBOX_RX		300
+#define MHU_TX_ADDR(pref)	pref##46040000 /* hex */
+#define MHU_RX_ADDR(pref)	pref##46140000 /* hex */
+#define MPAM_ADDR		0x0 0x5f010000 /* 0x5f01_0000 */
+#define UARTCLK_FREQ		3750000
+#endif /* TARGET_PLATFORM == 3 */
+
+/ {
+#if TARGET_PLATFORM <= 2
+	cmn-pmu {
+		compatible = "arm,ci-700";
+		reg = <0x0 0x50000000 0x0 0x10000000>;
+		interrupts = <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>;
+	};
+#endif /* TARGET_PLATFORM <= 2 */
+};