plat/arm/board/arm_fpga: Add PSCI implementation for FPGA images
This adds a basic PSCI implementation allow secondary CPUs to be
released from an initial state and continue through to the warm boot
entrypoint.
Each secondary CPU is kept in a holding pen, whereby it polls the value
representing its hold state, by reading this from an array that acts as
a table for all the PEs. The hold states are initially set to 0 for all
cores to indicate that the executing core should continue polling.
To prevent the secondary CPUs from interfering with the platform's
initialization, they are only updated by the primary CPU once the cold
boot sequence has completed and fpga_pwr_domain_on(mpidr) is called.
The polling target CPU will then read 1 (which indicates that it should
branch to the warm reset entrypoint) and then jump to that address
rather than continue polling.
In addition to the initial polling behaviour of the secondary CPUs
before their warm boot reset sequence, they are also placed in a
low-power wfe() state at the end of each poll; accordingly, the PSCI
fpga_pwr_domain_on(mpidr) function also signals an event to all cores
(after updating the target CPU's hold entry) to wake them from this
state, allowing any secondary CPUs that are still polling to check
their hold state again.
This method is in accordance with both the PSCI and Linux kernel
recommendations, as the lessened overhead reduces the energy
consumption associated with the busy-loop.
The table of hold entries is implemented by a global array as shared SRAM
(which is used by other platforms in similar implementations) is not
available on the FPGA images.
Signed-off-by: Oliver Swede <oli.swede@arm.com>
Change-Id: I65cfd1892f8be1dfcb285f0e1e94e7a9870cdf5a
diff --git a/plat/arm/board/arm_fpga/fpga_topology.c b/plat/arm/board/arm_fpga/fpga_topology.c
index 5458376..a705429 100644
--- a/plat/arm/board/arm_fpga/fpga_topology.c
+++ b/plat/arm/board/arm_fpga/fpga_topology.c
@@ -9,17 +9,63 @@
#include "fpga_private.h"
#include <platform_def.h>
+static unsigned char fpga_power_domain_tree_desc[FPGA_MAX_CLUSTER_COUNT + 2];
+
const unsigned char *plat_get_power_domain_tree_desc(void)
{
- /* TODO: add description of power domain topology and PSCI implementation */
- return NULL;
+ int i;
+ /*
+ * The highest level is the system level. The next level is constituted
+ * by clusters and then cores in clusters.
+ *
+ * This description of the power domain topology is aligned with the CPU
+ * indices returned by the plat_core_pos_by_mpidr() and plat_my_core_pos()
+ * APIs.
+ */
+ fpga_power_domain_tree_desc[0] = 1;
+ fpga_power_domain_tree_desc[1] = FPGA_MAX_CLUSTER_COUNT;
+
+ for (i = 0; i < FPGA_MAX_CLUSTER_COUNT; i++) {
+ fpga_power_domain_tree_desc[i + 2] = FPGA_MAX_CPUS_PER_CLUSTER;
+ }
+
+ return fpga_power_domain_tree_desc;
}
int plat_core_pos_by_mpidr(u_register_t mpidr)
{
+ unsigned int cluster_id, cpu_id, thread_id;
+
+ mpidr &= MPIDR_AFFINITY_MASK;
+ if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) {
+ return -1;
+ }
+
+ if (mpidr & MPIDR_MT_MASK) {
+ thread_id = MPIDR_AFFLVL0_VAL(mpidr);
+ } else {
+ thread_id = 0;
+ }
+
+ cpu_id = MPIDR_AFFLVL1_VAL(mpidr);
+ cluster_id = MPIDR_AFFLVL2_VAL(mpidr);
+
+ if (cluster_id >= FPGA_MAX_CLUSTER_COUNT) {
+ return -1;
+ } else if (cpu_id >= FPGA_MAX_CPUS_PER_CLUSTER) {
+ return -1;
+ } else if (thread_id >= FPGA_MAX_PE_PER_CPU) {
+ return -1;
+ }
+
/*
- * TODO: calculate core position in a way that accounts for CPUs that
- * potentially implement multithreading
+ * The image running on the FPGA may or may not implement multithreading,
+ * and it shouldn't be assumed this is consistent across all CPUs.
+ * This ensures that any passed mpidr values reflect the status of the
+ * primary CPU's MT bit.
*/
+ mpidr |= (read_mpidr_el1() & MPIDR_MT_MASK);
+
+ /* Calculate the correct core, catering for multi-threaded images */
return (int) plat_fpga_calc_core_pos(mpidr);
}