feat(intel): add in QSPI ECC for Linux
Add QSPI ECC new opcodes for Linux to access to SDM register
Change-Id: If9ac35afdddb91db6bad6b474060cd001f6d89e6
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
diff --git a/plat/intel/soc/agilex5/include/agilex5_system_manager.h b/plat/intel/soc/agilex5/include/agilex5_system_manager.h
index 9a58cdb..8987a63 100644
--- a/plat/intel/soc/agilex5/include/agilex5_system_manager.h
+++ b/plat/intel/soc/agilex5/include/agilex5_system_manager.h
@@ -143,6 +143,18 @@
#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_8 0x278
#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_9 0x27C
+/* QSPI ECC from SDM register */
+#define SOCFPGA_ECC_QSPI_CTRL 0x08
+#define SOCFPGA_ECC_QSPI_ERRINTEN 0x10
+#define SOCFPGA_ECC_QSPI_ERRINTENS 0x14
+#define SOCFPGA_ECC_QSPI_ERRINTENR 0x18
+#define SOCFPGA_ECC_QSPI_INTMODE 0x1C
+#define SOCFPGA_ECC_QSPI_INTSTAT 0x20
+#define SOCFPGA_ECC_QSPI_INTTEST 0x24
+#define SOCFPGA_ECC_QSPI_ECC_ACCCTRL 0x78
+#define SOCFPGA_ECC_QSPI_ECC_STARTACC 0x7C
+#define SOCFPGA_ECC_QSPI_ECC_WDCTRL 0x80
+
#define DMA0_STREAM_CTRL_REG 0x10D1217C
#define DMA1_STREAM_CTRL_REG 0x10D12180
#define SDM_STREAM_CTRL_REG 0x10D12184
@@ -187,9 +199,10 @@
#define RMMUSECSID_REG_VAL BIT(5)
/* Macros */
+#define SOCFPGA_ECC_QSPI(_reg) (SOCFPGA_ECC_QSPI_REG_BASE \
+ + (SOCFPGA_ECC_QSPI_##_reg))
#define SOCFPGA_SYSMGR(_reg) (SOCFPGA_SYSMGR_REG_BASE \
+ (SOCFPGA_SYSMGR_##_reg))
-
#define ENABLE_STREAMID WSTREAMIDEN_REG_CTRL \
| RSTREAMIDEN_REG_CTRL
#define ENABLE_STREAMID_SECURE_TX WSTREAMIDEN_REG_CTRL \