diff --git a/lib/extensions/spe/spe.c b/lib/extensions/spe/spe.c
index 236b102..2c25a9d 100644
--- a/lib/extensions/spe/spe.c
+++ b/lib/extensions/spe/spe.c
@@ -26,10 +26,13 @@
 	uint64_t v;
 
 	/*
-	 * MDCR_EL2.NSPB (ARM v8.2): SPE enabled in Non-secure state
+	 * MDCR_EL3.NSPB (ARM v8.2): SPE enabled in Non-secure state
 	 * and disabled in secure state. Accesses to SPE registers at
 	 * S-EL1 generate trap exceptions to EL3.
 	 *
+	 * MDCR_EL3.NSPBE: Profiling Buffer uses Non-secure Virtual Addresses.
+	 * When FEAT_RME is not implemented, this field is RES0.
+	 *
 	 * MDCR_EL3.EnPMSN (ARM v8.7): Do not trap access to PMSNEVFR_EL1
 	 * register at NS-EL1 or NS-EL2 to EL3 if FEAT_SPEv1p2 is implemented.
 	 * Setting this bit to 1 doesn't have any effect on it when
@@ -37,6 +40,7 @@
 	 */
 	v = read_mdcr_el3();
 	v |= MDCR_NSPB(MDCR_NSPB_EL1) | MDCR_EnPMSN_BIT;
+	v &= ~(MDCR_NSPBE_BIT);
 	write_mdcr_el3(v);
 }