Tegra: add tzdram_base to plat_params_from_bl2 struct
This patch adds another member, tzdram_base, to the plat_params_from_bl2 struct
in order to store the TZDRAM carveout base address used to load the Trusted OS.
The monitor programs the memory controller with the TZDRAM base and size in order
to deny any accesses from the NS world.
Change-Id: If39b8674d548175d7ccb6525c18d196ae8a8506c
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
diff --git a/plat/nvidia/tegra/common/tegra_bl31_setup.c b/plat/nvidia/tegra/common/tegra_bl31_setup.c
index 1635bfb..f762d6a 100644
--- a/plat/nvidia/tegra/common/tegra_bl31_setup.c
+++ b/plat/nvidia/tegra/common/tegra_bl31_setup.c
@@ -130,17 +130,18 @@
* Copy BL3-3, BL3-2 entry point information.
* They are stored in Secure RAM, in BL2's address space.
*/
- if (from_bl2->bl33_ep_info)
- bl33_image_ep_info = *from_bl2->bl33_ep_info;
+ assert(from_bl2->bl33_ep_info);
+ bl33_image_ep_info = *from_bl2->bl33_ep_info;
if (from_bl2->bl32_ep_info)
bl32_image_ep_info = *from_bl2->bl32_ep_info;
/*
- * Parse platform specific parameters - TZDRAM aperture size
+ * Parse platform specific parameters - TZDRAM aperture base and size
*/
- if (plat_params)
- plat_bl31_params_from_bl2.tzdram_size = plat_params->tzdram_size;
+ assert(plat_params);
+ plat_bl31_params_from_bl2.tzdram_base = plat_params->tzdram_base;
+ plat_bl31_params_from_bl2.tzdram_size = plat_params->tzdram_size;
}
/*******************************************************************************
@@ -168,7 +169,7 @@
/*
* Do initial security configuration to allow DRAM/device access.
*/
- tegra_memctrl_tzdram_setup(tegra_bl31_phys_base,
+ tegra_memctrl_tzdram_setup(plat_bl31_params_from_bl2.tzdram_base,
plat_bl31_params_from_bl2.tzdram_size);
/* Set the next EL to be AArch64 */
diff --git a/plat/nvidia/tegra/common/tegra_pm.c b/plat/nvidia/tegra/common/tegra_pm.c
index 6fb3e9c..8b7a059 100644
--- a/plat/nvidia/tegra/common/tegra_pm.c
+++ b/plat/nvidia/tegra/common/tegra_pm.c
@@ -174,7 +174,7 @@
* Security configuration to allow DRAM/device access.
*/
plat_params = bl31_get_plat_params();
- tegra_memctrl_tzdram_setup(tegra_bl31_phys_base,
+ tegra_memctrl_tzdram_setup(plat_params->tzdram_base,
plat_params->tzdram_size);
}
diff --git a/plat/nvidia/tegra/include/tegra_private.h b/plat/nvidia/tegra/include/tegra_private.h
index cf75d9f..9e66023 100644
--- a/plat/nvidia/tegra/include/tegra_private.h
+++ b/plat/nvidia/tegra/include/tegra_private.h
@@ -43,7 +43,10 @@
#define TEGRA_DRAM_END 0x27FFFFFFF
typedef struct plat_params_from_bl2 {
+ /* TZ memory size */
uint64_t tzdram_size;
+ /* TZ memory base */
+ uint64_t tzdram_base;
} plat_params_from_bl2_t;
/* Declarations for plat_psci_handlers.c */