diff --git a/plat/intel/soc/agilex/bl2_plat_setup.c b/plat/intel/soc/agilex/bl2_plat_setup.c
index 022ead6..9587d48 100644
--- a/plat/intel/soc/agilex/bl2_plat_setup.c
+++ b/plat/intel/soc/agilex/bl2_plat_setup.c
@@ -75,7 +75,9 @@
 	init_ncore_ccu();
 	init_hard_memory_controller();
 	mailbox_init();
-	socfpga_bridges_enable();
+
+	if (!intel_mailbox_is_fpga_not_ready())
+		socfpga_bridges_enable();
 }
 
 
diff --git a/plat/intel/soc/common/include/socfpga_mailbox.h b/plat/intel/soc/common/include/socfpga_mailbox.h
index c5f2fbe..c4b9e59 100644
--- a/plat/intel/soc/common/include/socfpga_mailbox.h
+++ b/plat/intel/soc/common/include/socfpga_mailbox.h
@@ -120,5 +120,6 @@
 void mailbox_clear_response(void);
 
 uint32_t intel_mailbox_get_config_status(uint32_t cmd);
+int intel_mailbox_is_fpga_not_ready(void);
 
 #endif /* SOCFPGA_MBOX_H */
diff --git a/plat/intel/soc/common/soc/socfpga_mailbox.c b/plat/intel/soc/common/soc/socfpga_mailbox.c
index eb35c4a..8d7c1d6 100644
--- a/plat/intel/soc/common/soc/socfpga_mailbox.c
+++ b/plat/intel/soc/common/soc/socfpga_mailbox.c
@@ -316,3 +316,13 @@
 
 	return MBOX_CFGSTAT_STATE_CONFIG;
 }
+
+int intel_mailbox_is_fpga_not_ready(void)
+{
+	int ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS);
+
+	if (ret && ret != MBOX_CFGSTAT_STATE_CONFIG)
+		ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS);
+
+	return ret;
+}
diff --git a/plat/intel/soc/common/soc/socfpga_reset_manager.c b/plat/intel/soc/common/soc/socfpga_reset_manager.c
index 7f63169..32604c9 100644
--- a/plat/intel/soc/common/soc/socfpga_reset_manager.c
+++ b/plat/intel/soc/common/soc/socfpga_reset_manager.c
@@ -101,29 +101,19 @@
 
 int socfpga_bridges_enable(void)
 {
-	uint32_t status, poll_addr;
+	/* Clear idle request */
+	mmio_setbits_32(SOCFPGA_SYSMGR(NOC_IDLEREQ_CLR), ~0);
 
-	status = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS);
+	/* De-assert all bridges */
+	mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST), ~0);
 
-	if (!status) {
-		/* Clear idle request */
-		mmio_setbits_32(SOCFPGA_SYSMGR(NOC_IDLEREQ_CLR), ~0);
-
-		/* De-assert all bridges */
-		mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST), ~0);
-
-		/* Wait until idle ack becomes 0 */
-		poll_addr = SOCFPGA_SYSMGR(NOC_IDLEACK);
-
-		return poll_idle_status(poll_addr, IDLE_DATA_MASK, 0);
-	}
-	return status;
+	/* Wait until idle ack becomes 0 */
+	return poll_idle_status(SOCFPGA_SYSMGR(NOC_IDLEACK),
+				IDLE_DATA_MASK, 0);
 }
 
 int socfpga_bridges_disable(void)
 {
-	uint32_t poll_addr;
-
 	/* Set idle request */
 	mmio_write_32(SOCFPGA_SYSMGR(NOC_IDLEREQ_SET), ~0);
 
@@ -131,13 +121,13 @@
 	mmio_setbits_32(SOCFPGA_SYSMGR(NOC_TIMEOUT), 1);
 
 	/* Wait until each idle ack bit toggle to 1 */
-	poll_addr = SOCFPGA_SYSMGR(NOC_IDLEACK);
-	if (poll_idle_status(poll_addr, IDLE_DATA_MASK, IDLE_DATA_MASK))
+	if (poll_idle_status(SOCFPGA_SYSMGR(NOC_IDLEACK),
+				IDLE_DATA_MASK, IDLE_DATA_MASK))
 		return -ETIMEDOUT;
 
 	/* Wait until each idle status bit toggle to 1 */
-	poll_addr = SOCFPGA_SYSMGR(NOC_IDLESTATUS);
-	if (poll_idle_status(poll_addr, IDLE_DATA_MASK, IDLE_DATA_MASK))
+	if (poll_idle_status(SOCFPGA_SYSMGR(NOC_IDLESTATUS),
+				IDLE_DATA_MASK, IDLE_DATA_MASK))
 		return -ETIMEDOUT;
 
 	/* Assert all bridges */
diff --git a/plat/intel/soc/stratix10/bl2_plat_setup.c b/plat/intel/soc/stratix10/bl2_plat_setup.c
index 5eb7969..7d183db 100644
--- a/plat/intel/soc/stratix10/bl2_plat_setup.c
+++ b/plat/intel/soc/stratix10/bl2_plat_setup.c
@@ -73,7 +73,9 @@
 	socfpga_delay_timer_init();
 	init_hard_memory_controller();
 	mailbox_init();
-	socfpga_bridges_enable();
+
+	if (!intel_mailbox_is_fpga_not_ready())
+		socfpga_bridges_enable();
 }