refactor(cpus): convert the Cortex-A53 to use cpu helpers
Also, convert checker functions of errata which are enabled for all cpu
revisions to report correctly in preparation of the errata ABI.
Although the script from commit 250919 was used to check that errata
code did not change, this CPU only loosely adhered to convention and its
output was not particularly useful. Nevertheless, the discrepancies were
manually verified. All errata have been checked that they get invoked.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I988db6e7b6d1732f1d2258dbdf945cb475781894
diff --git a/lib/cpus/aarch64/cortex_a53.S b/lib/cpus/aarch64/cortex_a53.S
index 369ddeb..e6fb08a 100644
--- a/lib/cpus/aarch64/cortex_a53.S
+++ b/lib/cpus/aarch64/cortex_a53.S
@@ -17,9 +17,7 @@
* ---------------------------------------------
*/
func cortex_a53_disable_dcache
- mrs x1, sctlr_el3
- bic x1, x1, #SCTLR_C_BIT
- msr sctlr_el3, x1
+ sysreg_bit_clear sctlr_el3, SCTLR_C_BIT
isb
ret
endfunc cortex_a53_disable_dcache
@@ -29,39 +27,19 @@
* ---------------------------------------------
*/
func cortex_a53_disable_smp
- mrs x0, CORTEX_A53_ECTLR_EL1
- bic x0, x0, #CORTEX_A53_ECTLR_SMP_BIT
- msr CORTEX_A53_ECTLR_EL1, x0
+ sysreg_bit_clear CORTEX_A53_ECTLR_EL1, CORTEX_A53_ECTLR_SMP_BIT
isb
dsb sy
ret
endfunc cortex_a53_disable_smp
/* Due to the nature of the errata it is applied unconditionally when chosen */
-check_erratum_custom_start cortex_a53, ERRATUM(819472)
-#if ERRATA_A53_819472
- mov x0, #ERRATA_APPLIES
- ret
-#else
- mov x1, #0x01
- b cpu_rev_var_ls
-#endif
-check_erratum_custom_end cortex_a53, ERRATUM(819472)
-
+check_erratum_ls cortex_a53, ERRATUM(819472), CPU_REV(0, 1)
/* erratum workaround is interleaved with generic code */
add_erratum_entry cortex_a53, ERRATUM(819472), ERRATUM_ALWAYS_CHOSEN, NO_APPLY_AT_RESET
/* Due to the nature of the errata it is applied unconditionally when chosen */
-check_erratum_custom_start cortex_a53, ERRATUM(824069)
-#if ERRATA_A53_824069
- mov x0, #ERRATA_APPLIES
- ret
-#else
- mov x1, #0x02
- b cpu_rev_var_ls
-#endif
-check_erratum_custom_end cortex_a53, ERRATUM(824069)
-
+check_erratum_ls cortex_a53, ERRATUM(824069), CPU_REV(0, 2)
/* erratum workaround is interleaved with generic code */
add_erratum_entry cortex_a53, ERRATUM(824069), ERRATUM_ALWAYS_CHOSEN, NO_APPLY_AT_RESET
@@ -75,21 +53,12 @@
check_erratum_ls cortex_a53, ERRATUM(826319), CPU_REV(0, 2)
/* Due to the nature of the errata it is applied unconditionally when chosen */
-check_erratum_custom_start cortex_a53, ERRATUM(827319)
-#if ERRATA_A53_827319
- mov x0, #ERRATA_APPLIES
- ret
-#else
- mov x1, #0x02
- b cpu_rev_var_ls
-#endif
-check_erratum_custom_end cortex_a53, ERRATUM(827319)
-
+check_erratum_ls cortex_a53, ERRATUM(827319), CPU_REV(0, 2)
/* erratum workaround is interleaved with generic code */
add_erratum_entry cortex_a53, ERRATUM(827319), ERRATUM_ALWAYS_CHOSEN, NO_APPLY_AT_RESET
check_erratum_custom_start cortex_a53, ERRATUM(835769)
- cmp x0, #0x04
+ cmp x0, CPU_REV(0, 4)
b.hi errata_not_applies
/*
* Fix potentially available for revisions r0p2, r0p3 and r0p4.
@@ -120,9 +89,7 @@
* equivalent LDP and STP instructions.
*/
workaround_reset_start cortex_a53, ERRATUM(836870), ERRATA_A53_836870 | A53_DISABLE_NON_TEMPORAL_HINT
- mrs x1, CORTEX_A53_CPUACTLR_EL1
- orr x1, x1, #CORTEX_A53_CPUACTLR_EL1_DTAH
- msr CORTEX_A53_CPUACTLR_EL1, x1
+ sysreg_bit_set CORTEX_A53_CPUACTLR_EL1, CORTEX_A53_CPUACTLR_EL1_DTAH
workaround_reset_end cortex_a53, ERRATUM(836870)
check_erratum_ls cortex_a53, ERRATUM(836870), CPU_REV(0, 3)
@@ -130,7 +97,7 @@
check_erratum_custom_start cortex_a53, ERRATUM(843419)
mov x1, #ERRATA_APPLIES
mov x2, #ERRATA_NOT_APPLIES
- cmp x0, #0x04
+ cmp x0, CPU_REV(0, 4)
csel x0, x1, x2, ls
/*
* Fix potentially available for revision r0p4.
@@ -156,9 +123,7 @@
* shared with other erratas in those revisions of the CPU.
*/
workaround_reset_start cortex_a53, ERRATUM(855873), ERRATA_A53_855873
- mrs x1, CORTEX_A53_CPUACTLR_EL1
- orr x1, x1, #CORTEX_A53_CPUACTLR_EL1_ENDCCASCI
- msr CORTEX_A53_CPUACTLR_EL1, x1
+ sysreg_bit_set CORTEX_A53_CPUACTLR_EL1, CORTEX_A53_CPUACTLR_EL1_ENDCCASCI
workaround_reset_end cortex_a53, ERRATUM(855873)
check_erratum_hs cortex_a53, ERRATUM(855873), CPU_REV(0, 3)
@@ -169,13 +134,8 @@
add_erratum_entry cortex_a53, ERRATUM(1530924), ERRATA_A53_1530924, NO_APPLY_AT_RESET
cpu_reset_func_start cortex_a53
- /* ---------------------------------------------
- * Enable the SMP bit.
- * ---------------------------------------------
- */
- mrs x0, CORTEX_A53_ECTLR_EL1
- orr x0, x0, #CORTEX_A53_ECTLR_SMP_BIT
- msr CORTEX_A53_ECTLR_EL1, x0
+ /* Enable the SMP bit. */
+ sysreg_bit_set CORTEX_A53_ECTLR_EL1, CORTEX_A53_ECTLR_SMP_BIT
cpu_reset_func_end cortex_a53
func cortex_a53_core_pwr_dwn