diff --git a/Makefile b/Makefile
index 18c4873..cb7eb08 100644
--- a/Makefile
+++ b/Makefile
@@ -550,6 +550,7 @@
 $(eval $(call assert_boolean,EL3_EXCEPTION_HANDLING))
 $(eval $(call assert_boolean,ENABLE_AMU))
 $(eval $(call assert_boolean,ENABLE_ASSERTIONS))
+$(eval $(call assert_boolean,ENABLE_MPAM_FOR_LOWER_ELS))
 $(eval $(call assert_boolean,ENABLE_PLAT_COMPAT))
 $(eval $(call assert_boolean,ENABLE_PMF))
 $(eval $(call assert_boolean,ENABLE_PSCI_STAT))
@@ -601,6 +602,7 @@
 $(eval $(call add_define,EL3_EXCEPTION_HANDLING))
 $(eval $(call add_define,ENABLE_AMU))
 $(eval $(call add_define,ENABLE_ASSERTIONS))
+$(eval $(call add_define,ENABLE_MPAM_FOR_LOWER_ELS))
 $(eval $(call add_define,ENABLE_PLAT_COMPAT))
 $(eval $(call add_define,ENABLE_PMF))
 $(eval $(call add_define,ENABLE_PSCI_STAT))
diff --git a/bl1/bl1.mk b/bl1/bl1.mk
index 9a46a34..ec7d728 100644
--- a/bl1/bl1.mk
+++ b/bl1/bl1.mk
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -17,7 +17,8 @@
 				${MBEDTLS_SOURCES}
 
 ifeq (${ARCH},aarch64)
-BL1_SOURCES		+=	lib/el3_runtime/aarch64/context.S
+BL1_SOURCES		+=	lib/cpus/aarch64/dsu_helpers.S		\
+				lib/el3_runtime/aarch64/context.S
 endif
 
 ifeq (${TRUSTED_BOARD_BOOT},1)
diff --git a/bl2/bl2.mk b/bl2/bl2.mk
index 7e33703..af30a81 100644
--- a/bl2/bl2.mk
+++ b/bl2/bl2.mk
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -29,5 +29,10 @@
 				bl2/${ARCH}/bl2_el3_exceptions.S	\
 				lib/cpus/${ARCH}/cpu_helpers.S		\
 				lib/cpus/errata_report.c
+
+ifeq (${ARCH},aarch64)
+BL2_SOURCES		+=	lib/cpus/aarch64/dsu_helpers.S
+endif
+
 BL2_LINKERFILE		:=	bl2/bl2_el3.ld.S
 endif
diff --git a/bl31/bl31.mk b/bl31/bl31.mk
index bff9653..7777954 100644
--- a/bl31/bl31.mk
+++ b/bl31/bl31.mk
@@ -24,6 +24,7 @@
 				bl31/bl31_context_mgmt.c			\
 				common/runtime_svc.c				\
 				lib/aarch64/setjmp.S				\
+				lib/cpus/aarch64/dsu_helpers.S			\
 				plat/common/aarch64/platform_mp_stack.S		\
 				services/arm_arch_svc/arm_arch_svc_setup.c	\
 				services/std_svc/std_svc_setup.c		\
@@ -63,6 +64,10 @@
 BL31_SOURCES		+=	lib/extensions/sve/sve.c
 endif
 
+ifeq (${ENABLE_MPAM_FOR_LOWER_ELS},1)
+BL31_SOURCES		+=	lib/extensions/mpam/mpam.c
+endif
+
 ifeq (${WORKAROUND_CVE_2017_5715},1)
 BL31_SOURCES		+=	lib/cpus/aarch64/wa_cve_2017_5715_bpiall.S	\
 				lib/cpus/aarch64/wa_cve_2017_5715_mmu.S
diff --git a/docs/cpu-specific-build-macros.rst b/docs/cpu-specific-build-macros.rst
index c11f640..151c99e 100644
--- a/docs/cpu-specific-build-macros.rst
+++ b/docs/cpu-specific-build-macros.rst
@@ -68,10 +68,10 @@
 with different revisions of a processor has no runtime mechanism available
 for it to specify which errata workarounds should be enabled or not.
 
-The value of the build flags are 0 by default, that is, disabled. Any other
-value will enable it.
+The value of the build flags is 0 by default, that is, disabled. A value of 1
+will enable it.
 
-For Cortex-A53, following errata build flags are defined :
+For Cortex-A53, the following errata build flags are defined :
 
 -  ``ERRATA_A53_826319``: This applies errata 826319 workaround to Cortex-A53
    CPU. This needs to be enabled only for revision <= r0p2 of the CPU.
@@ -97,7 +97,7 @@
    Earlier revisions of the CPU have other errata which require the same
    workaround in software, so they should be covered anyway.
 
-For Cortex-A57, following errata build flags are defined :
+For Cortex-A57, the following errata build flags are defined :
 
 -  ``ERRATA_A57_806969``: This applies errata 806969 workaround to Cortex-A57
    CPU. This needs to be enabled only for revision r0p0 of the CPU.
@@ -127,11 +127,33 @@
    CPU. This needs to be enabled only for revision <= r1p3 of the CPU.
 
 
-For Cortex-A72, following errata build flags are defined :
+For Cortex-A72, the following errata build flags are defined :
 
 -  ``ERRATA_A72_859971``: This applies errata 859971 workaround to Cortex-A72
    CPU. This needs to be enabled only for revision <= r0p3 of the CPU.
 
+DSU Errata Workarounds
+----------------------
+
+Similar to CPU errata, TF-A also implements workarounds for DSU (DynamIQ
+Shared Unit) errata. The DSU errata details can be found in the respective Arm
+documentation:
+
+- `Arm DSU Software Developers Errata Notice`_.
+
+Each erratum is identified by an ``ID``, as defined in the DSU errata notice
+document. Thus, the build flags which enable/disable the errata workarounds
+have the format ``ERRATA_DSU_<ID>``. The implementation and application logic
+of DSU errata workarounds are similar to `CPU errata workarounds`_.
+
+For DSU errata, the following build flags are defined:
+
+-  ``ERRATA_DSU_936184``: This applies errata 936184 workaround for the
+   affected DSU configurations. This errata applies only for those DSUs that
+   contain the ACP interface **and** the DSU revision is older than r2p0 (on
+   r2p0 it is fixed). However, please note that this workaround results in
+   increased DSU power consumption on idle.
+
 CPU Specific optimizations
 --------------------------
 
@@ -171,3 +193,4 @@
 .. _Cortex-A72 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm012079/index.html
 .. _Firmware Design guide: firmware-design.rst
 .. _Cortex-A57 Software Optimization Guide: http://infocenter.arm.com/help/topic/com.arm.doc.uan0015b/Cortex_A57_Software_Optimization_Guide_external.pdf
+.. _Arm DSU Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm138168/index.html
\ No newline at end of file
diff --git a/docs/user-guide.rst b/docs/user-guide.rst
index 2b90bec..3f8170f 100644
--- a/docs/user-guide.rst
+++ b/docs/user-guide.rst
@@ -67,8 +67,9 @@
 
 In addition, the following optional packages and tools may be needed:
 
--  ``device-tree-compiler`` package if you need to rebuild the Flattened Device
-   Tree (FDT) source files (``.dts`` files) provided with this software.
+-  ``device-tree-compiler`` (dtc) package if you need to rebuild the Flattened Device
+   Tree (FDT) source files (``.dts`` files) provided with this software. The
+   version of dtc must be 1.4.6 or above.
 
 -  For debugging, Arm `Development Studio 5 (DS-5)`_.
 
@@ -350,6 +351,17 @@
    that is only required for the assertion and does not fit in the assertion
    itself.
 
+-  ``ENABLE_MPAM_FOR_LOWER_ELS``: Boolean option to enable lower ELs to use MPAM
+   feature. MPAM is an optional Armv8.4 extension that enables various memory
+   system components and resources to define partitions; software running at
+   various ELs can assign themselves to desired partition to control their
+   performance aspects.
+
+   When this option is set to ``1``, EL3 allows lower ELs to access their own
+   MPAM registers without trapping into EL3. This option doesn't make use of
+   partitioning in EL3, however. Platform initialisation code should configure
+   and use partitions in EL3 as required. This option defaults to ``0``.
+
 -  ``ENABLE_PMF``: Boolean option to enable support for optional Performance
    Measurement Framework(PMF). Default is 0.
 
diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h
index c9619f6..cccb286 100644
--- a/include/lib/aarch64/arch.h
+++ b/include/lib/aarch64/arch.h
@@ -117,6 +117,8 @@
 #define ID_AA64PFR0_SVE_SHIFT	U(32)
 #define ID_AA64PFR0_SVE_MASK	ULL(0xf)
 #define ID_AA64PFR0_SVE_LENGTH	U(4)
+#define ID_AA64PFR0_MPAM_SHIFT	U(40)
+#define ID_AA64PFR0_MPAM_MASK	ULL(0xf)
 #define ID_AA64PFR0_CSV2_SHIFT	U(56)
 #define ID_AA64PFR0_CSV2_MASK	ULL(0xf)
 #define ID_AA64PFR0_CSV2_LENGTH	U(4)
@@ -658,6 +660,14 @@
 #define PMBLIMITR_EL1		S3_0_C9_C10_0
 
 /*******************************************************************************
+ * Definitions for system register interface to MPAM
+ ******************************************************************************/
+#define MPAMIDR_EL1		S3_0_C10_C4_4
+#define MPAM2_EL2		S3_4_C10_C5_0
+#define MPAMHCR_EL2		S3_4_C10_C4_0
+#define MPAM3_EL3		S3_6_C10_C5_0
+
+/*******************************************************************************
  * Definitions for system register interface to AMU for ARMv8.4 onwards
  ******************************************************************************/
 #define AMCR_EL0		S3_3_C13_C2_0
@@ -722,6 +732,11 @@
 #define AMCGCR_EL0_CG1NC_LENGTH	U(8)
 #define AMCGCR_EL0_CG1NC_MASK	U(0xff)
 
+/* MPAM register definitions */
+#define MPAM3_EL3_MPAMEN_BIT		(ULL(1) << 63)
+
+#define MPAMIDR_HAS_HCR_BIT		(ULL(1) << 17)
+
 /*******************************************************************************
  * RAS system registers
  *******************************************************************************/
diff --git a/include/lib/aarch64/arch_helpers.h b/include/lib/aarch64/arch_helpers.h
index 58ec943..8e82dbd 100644
--- a/include/lib/aarch64/arch_helpers.h
+++ b/include/lib/aarch64/arch_helpers.h
@@ -328,6 +328,11 @@
 DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenclr1_el0, AMCNTENCLR1_EL0)
 DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenset1_el0, AMCNTENSET1_EL0)
 
+DEFINE_RENAME_SYSREG_READ_FUNC(mpamidr_el1, MPAMIDR_EL1)
+DEFINE_RENAME_SYSREG_RW_FUNCS(mpam3_el3, MPAM3_EL3)
+DEFINE_RENAME_SYSREG_RW_FUNCS(mpam2_el2, MPAM2_EL2)
+DEFINE_RENAME_SYSREG_RW_FUNCS(mpamhcr_el2, MPAMHCR_EL2)
+
 DEFINE_RENAME_SYSREG_RW_FUNCS(pmblimitr_el1, PMBLIMITR_EL1)
 
 DEFINE_RENAME_SYSREG_WRITE_FUNC(zcr_el3, ZCR_EL3)
diff --git a/include/lib/cpus/aarch64/dsu_def.h b/include/lib/cpus/aarch64/dsu_def.h
new file mode 100644
index 0000000..0e2d93a
--- /dev/null
+++ b/include/lib/cpus/aarch64/dsu_def.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef DSU_DEF_H
+#define DSU_DEF_H
+
+#include <utils_def.h>
+
+/********************************************************************
+ * DSU control registers definitions				    *
+ ********************************************************************/
+#define CLUSTERCFR_EL1		S3_0_C15_C3_0
+#define CLUSTERIDR_EL1		S3_0_C15_C3_1
+#define CLUSTERACTLR_EL1	S3_0_C15_C3_3
+
+/********************************************************************
+ * DSU control registers bit fields				    *
+ ********************************************************************/
+#define CLUSTERIDR_REV_SHIFT	U(0)
+#define CLUSTERIDR_REV_BITS	U(4)
+#define CLUSTERIDR_VAR_SHIFT	U(4)
+#define CLUSTERIDR_VAR_BITS	U(4)
+#define CLUSTERCFR_ACP_SHIFT	U(11)
+
+/********************************************************************
+ * Masks applied for DSU errata workarounds			    *
+ ********************************************************************/
+#define DSU_ERRATA_936184_MASK	(ULL(0x3) << 15)
+
+#endif /* DSU_DEF_H */
diff --git a/include/lib/extensions/mpam.h b/include/lib/extensions/mpam.h
new file mode 100644
index 0000000..571b96b
--- /dev/null
+++ b/include/lib/extensions/mpam.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MPAM_H
+#define MPAM_H
+
+#include <stdbool.h>
+
+bool mpam_supported(void);
+void mpam_enable(int el2_unused);
+
+#endif /* MPAM_H */
diff --git a/lib/cpus/aarch64/cortex_a55.S b/lib/cpus/aarch64/cortex_a55.S
index 741c773..4e9bd9f 100644
--- a/lib/cpus/aarch64/cortex_a55.S
+++ b/lib/cpus/aarch64/cortex_a55.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -11,6 +11,14 @@
 #include <cpu_macros.S>
 #include <plat_macros.S>
 
+func cortex_a55_reset_func
+	mov	x19, x30
+#if ERRATA_DSU_936184
+	bl	errata_dsu_936184_wa
+#endif
+	ret	x19
+endfunc cortex_a55_reset_func
+
 	/* ---------------------------------------------
 	 * HW will do the cache maintenance while powering down
 	 * ---------------------------------------------
@@ -27,6 +35,26 @@
 	ret
 endfunc cortex_a55_core_pwr_dwn
 
+#if REPORT_ERRATA
+/*
+ * Errata printing function for Cortex A55. Must follow AAPCS & can use stack.
+ */
+func cortex_a55_errata_report
+	stp	x8, x30, [sp, #-16]!
+	bl	cpu_get_rev_var
+	mov	x8, x0
+
+	/*
+	 * Report all errata. The revision variant information is at x8, where
+	 * "report_errata" is expecting it and it doesn't corrupt it.
+	 */
+	report_errata ERRATA_DSU_936184, cortex_a55, dsu_936184
+
+	ldp	x8, x30, [sp], #16
+	ret
+endfunc cortex_a55_errata_report
+#endif
+
 	/* ---------------------------------------------
 	 * This function provides cortex_a55 specific
 	 * register information for crash reporting.
@@ -47,5 +75,5 @@
 endfunc cortex_a55_cpu_reg_dump
 
 declare_cpu_ops cortex_a55, CORTEX_A55_MIDR, \
-	CPU_NO_RESET_FUNC, \
+	cortex_a55_reset_func, \
 	cortex_a55_core_pwr_dwn
diff --git a/lib/cpus/aarch64/cortex_a75.S b/lib/cpus/aarch64/cortex_a75.S
index 73f566f..e121b7d 100644
--- a/lib/cpus/aarch64/cortex_a75.S
+++ b/lib/cpus/aarch64/cortex_a75.S
@@ -11,6 +11,7 @@
 #include <cpu_macros.S>
 
 func cortex_a75_reset_func
+	mov	x19, x30
 #if IMAGE_BL31 && WORKAROUND_CVE_2017_5715
 	cpu_check_csv2	x0, 1f
 	adr	x0, wa_cve_2017_5715_bpiall_vbar
@@ -26,6 +27,10 @@
 	isb
 #endif
 
+#if ERRATA_DSU_936184
+	bl	errata_dsu_936184_wa
+#endif
+
 #if ENABLE_AMU
 	/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
 	mrs	x0, actlr_el3
@@ -49,7 +54,7 @@
 	msr	CPUAMCNTENSET_EL0, x0
 	isb
 #endif
-	ret
+	ret	x19
 endfunc cortex_a75_reset_func
 
 func check_errata_cve_2017_5715
@@ -106,6 +111,7 @@
 	 */
 	report_errata WORKAROUND_CVE_2017_5715, cortex_a75, cve_2017_5715
 	report_errata WORKAROUND_CVE_2018_3639, cortex_a75, cve_2018_3639
+	report_errata ERRATA_DSU_936184, cortex_a75, dsu_936184
 
 	ldp	x8, x30, [sp], #16
 	ret
diff --git a/lib/cpus/aarch64/cortex_a76.S b/lib/cpus/aarch64/cortex_a76.S
index 51d0b15..1697c55 100644
--- a/lib/cpus/aarch64/cortex_a76.S
+++ b/lib/cpus/aarch64/cortex_a76.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -207,6 +207,7 @@
 endfunc cortex_a76_disable_wa_cve_2018_3639
 
 func cortex_a76_reset_func
+	mov	x19, x30
 #if WORKAROUND_CVE_2018_3639
 	mrs	x0, CORTEX_A76_CPUACTLR2_EL1
 	orr	x0, x0, #CORTEX_A76_CPUACTLR2_EL1_DISABLE_LOAD_PASS_STORE
@@ -224,7 +225,11 @@
 	msr	vbar_el3, x0
 	isb
 #endif
-	ret
+
+#if ERRATA_DSU_936184
+	bl	errata_dsu_936184_wa
+#endif
+	ret	x19
 endfunc cortex_a76_reset_func
 
 	/* ---------------------------------------------
@@ -258,6 +263,7 @@
 	 * checking functions of each errata.
 	 */
 	report_errata WORKAROUND_CVE_2018_3639, cortex_a76, cve_2018_3639
+	report_errata ERRATA_DSU_936184, cortex_a76, dsu_936184
 
 	ldp	x8, x30, [sp], #16
 	ret
diff --git a/lib/cpus/aarch64/denver.S b/lib/cpus/aarch64/denver.S
index f04dbd6..a981d02 100644
--- a/lib/cpus/aarch64/denver.S
+++ b/lib/cpus/aarch64/denver.S
@@ -189,6 +189,25 @@
 	ret
 endfunc denver_disable_dco
 
+func check_errata_cve_2017_5715
+	mov	x0, #ERRATA_MISSING
+#if WORKAROUND_CVE_2017_5715
+	/*
+	 * Check if the CPU supports the special instruction
+	 * required to flush the indirect branch predictor and
+	 * RSB. Support for this operation can be determined by
+	 * comparing bits 19:16 of ID_AFR0_EL1 with 0b0001.
+	 */
+	mrs	x1, id_afr0_el1
+	mov	x2, #0x10000
+	and	x1, x1, x2
+	cbz	x1, 1f
+	mov	x0, #ERRATA_APPLIES
+1:
+#endif
+	ret
+endfunc check_errata_cve_2017_5715
+
 	/* -------------------------------------------------
 	 * The CPU Ops reset function for Denver.
 	 * -------------------------------------------------
@@ -248,6 +267,27 @@
 	ret
 endfunc denver_cluster_pwr_dwn
 
+#if REPORT_ERRATA
+	/*
+	 * Errata printing function for Denver. Must follow AAPCS.
+	 */
+func denver_errata_report
+	stp	x8, x30, [sp, #-16]!
+
+	bl	cpu_get_rev_var
+	mov	x8, x0
+
+	/*
+	 * Report all errata. The revision-variant information is passed to
+	 * checking functions of each errata.
+	 */
+	report_errata WORKAROUND_CVE_2017_5715, denver, cve_2017_5715
+
+	ldp	x8, x30, [sp], #16
+	ret
+endfunc denver_errata_report
+#endif
+
 	/* ---------------------------------------------
 	 * This function provides Denver specific
 	 * register information for crash reporting.
@@ -267,27 +307,37 @@
 	ret
 endfunc denver_cpu_reg_dump
 
-declare_cpu_ops denver, DENVER_MIDR_PN0, \
+declare_cpu_ops_wa denver, DENVER_MIDR_PN0, \
 	denver_reset_func, \
+	check_errata_cve_2017_5715, \
+	CPU_NO_EXTRA2_FUNC, \
 	denver_core_pwr_dwn, \
 	denver_cluster_pwr_dwn
 
-declare_cpu_ops denver, DENVER_MIDR_PN1, \
+declare_cpu_ops_wa denver, DENVER_MIDR_PN1, \
 	denver_reset_func, \
+	check_errata_cve_2017_5715, \
+	CPU_NO_EXTRA2_FUNC, \
 	denver_core_pwr_dwn, \
 	denver_cluster_pwr_dwn
 
-declare_cpu_ops denver, DENVER_MIDR_PN2, \
+declare_cpu_ops_wa denver, DENVER_MIDR_PN2, \
 	denver_reset_func, \
+	check_errata_cve_2017_5715, \
+	CPU_NO_EXTRA2_FUNC, \
 	denver_core_pwr_dwn, \
 	denver_cluster_pwr_dwn
 
-declare_cpu_ops denver, DENVER_MIDR_PN3, \
+declare_cpu_ops_wa denver, DENVER_MIDR_PN3, \
 	denver_reset_func, \
+	check_errata_cve_2017_5715, \
+	CPU_NO_EXTRA2_FUNC, \
 	denver_core_pwr_dwn, \
 	denver_cluster_pwr_dwn
 
-declare_cpu_ops denver, DENVER_MIDR_PN4, \
+declare_cpu_ops_wa denver, DENVER_MIDR_PN4, \
 	denver_reset_func, \
+	check_errata_cve_2017_5715, \
+	CPU_NO_EXTRA2_FUNC, \
 	denver_core_pwr_dwn, \
 	denver_cluster_pwr_dwn
diff --git a/lib/cpus/aarch64/dsu_helpers.S b/lib/cpus/aarch64/dsu_helpers.S
new file mode 100644
index 0000000..293ed24
--- /dev/null
+++ b/lib/cpus/aarch64/dsu_helpers.S
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <asm_macros.S>
+#include <dsu_def.h>
+#include <errata_report.h>
+
+/*
+ * DSU erratum 936184
+ * Check the DSU variant, revision and configuration to determine if the
+ * erratum applies. This erratum was fixed in r2p0.
+ *
+ * This function is called from both assembly and C environment. So it
+ * follows AAPCS.
+ *
+ * Clobbers: x0-x3
+ */
+	.globl	check_errata_dsu_936184
+	.globl	errata_dsu_936184_wa
+
+func check_errata_dsu_936184
+	mov	x2, #ERRATA_NOT_APPLIES
+	mov	x3, #ERRATA_APPLIES
+
+	/* Erratum applies only if ACP interface is present in DSU */
+	mov	x0, x2
+	mrs	x1, CLUSTERCFR_EL1
+	ubfx	x1, x1, #CLUSTERCFR_ACP_SHIFT, #1
+	cbz	x1, 1f
+
+	/* If ACP is present, check if DSU is older than r2p0 */
+	mrs	x1, CLUSTERIDR_EL1
+
+	/* DSU variant and revision bitfields in CLUSTERIDR are adjacent */
+	ubfx	x0, x1, #CLUSTERIDR_REV_SHIFT,\
+			#(CLUSTERIDR_REV_BITS + CLUSTERIDR_VAR_BITS)
+	mov	x1, #(0x2 << CLUSTERIDR_REV_BITS)
+	cmp	x0, x1
+	csel	x0, x2, x3, hs
+1:
+	ret
+endfunc check_errata_dsu_936184
+
+func errata_dsu_936184_wa
+	mov	x20, x30
+	bl	check_errata_dsu_936184
+	cbz	x0, 1f
+
+	/* If erratum applies, we set a mask to a DSU control register */
+	mrs	x0, CLUSTERACTLR_EL1
+	ldr	x1, =DSU_ERRATA_936184_MASK
+	orr	x0, x0, x1
+	msr	CLUSTERACTLR_EL1, x0
+	isb
+1:
+	ret	x20
+endfunc errata_dsu_936184_wa
diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index 456e3e5..40a8ac7 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -123,6 +123,11 @@
 # only to r0p0 and r1p0 of the Ares cpu.
 ERRATA_ARES_1043202	?=1
 
+# Flag to apply DSU erratum 936184. This erratum applies to DSUs containing
+# the ACP interface and revision < r2p0. Applying the workaround results in
+# higher DSU power consumption on idle.
+ERRATA_DSU_936184	?=0
+
 # Process ERRATA_A53_826319 flag
 $(eval $(call assert_boolean,ERRATA_A53_826319))
 $(eval $(call add_define,ERRATA_A53_826319))
@@ -187,6 +192,10 @@
 $(eval $(call assert_boolean,ERRATA_ARES_1043202))
 $(eval $(call add_define,ERRATA_ARES_1043202))
 
+# Process ERRATA_DSU_936184 flag
+$(eval $(call assert_boolean,ERRATA_DSU_936184))
+$(eval $(call add_define,ERRATA_DSU_936184))
+
 # Errata build flags
 ifneq (${ERRATA_A53_843419},0)
 TF_LDFLAGS_aarch64	+= --fix-cortex-a53-843419
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index f389368..2812bda 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -12,6 +12,7 @@
 #include <context.h>
 #include <context_mgmt.h>
 #include <interrupt_mgmt.h>
+#include <mpam.h>
 #include <platform.h>
 #include <platform_def.h>
 #include <pubsub_events.h>
@@ -244,6 +245,10 @@
 #if ENABLE_SVE_FOR_NS
 	sve_enable(el2_unused);
 #endif
+
+#if ENABLE_MPAM_FOR_LOWER_ELS
+	mpam_enable(el2_unused);
+#endif
 #endif
 }
 
diff --git a/lib/extensions/mpam/mpam.c b/lib/extensions/mpam/mpam.c
new file mode 100644
index 0000000..e628827
--- /dev/null
+++ b/lib/extensions/mpam/mpam.c
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <arch_helpers.h>
+#include <mpam.h>
+#include <stdbool.h>
+
+bool mpam_supported(void)
+{
+	uint64_t features = read_id_aa64dfr0_el1() >> ID_AA64PFR0_MPAM_SHIFT;
+
+	return ((features & ID_AA64PFR0_MPAM_MASK) != 0U);
+}
+
+void mpam_enable(int el2_unused)
+{
+	if (!mpam_supported())
+		return;
+
+	/*
+	 * Enable MPAM, and disable trapping to EL3 when lower ELs access their
+	 * own MPAM registers.
+	 */
+	write_mpam3_el3(MPAM3_EL3_MPAMEN_BIT);
+
+	/*
+	 * If EL2 is implemented but unused, disable trapping to EL2 when lower
+	 * ELs access their own MPAM registers.
+	 */
+	if (el2_unused != 0) {
+		write_mpam2_el2(0);
+
+		if ((read_mpamidr_el1() & MPAMIDR_HAS_HCR_BIT) != 0U)
+			write_mpamhcr_el2(0);
+	}
+}
diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk
index e4b5bdc..49f403d 100644
--- a/make_helpers/defaults.mk
+++ b/make_helpers/defaults.mk
@@ -62,6 +62,9 @@
 # development platforms.
 DYN_DISABLE_AUTH		:= 0
 
+# Build option to enable MPAM for lower ELs
+ENABLE_MPAM_FOR_LOWER_ELS	:= 0
+
 # Flag to enable Performance Measurement Framework
 ENABLE_PMF			:= 0
 
diff --git a/plat/arm/board/common/board_common.mk b/plat/arm/board/common/board_common.mk
index d63ae9a..af47c0d 100644
--- a/plat/arm/board/common/board_common.mk
+++ b/plat/arm/board/common/board_common.mk
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -12,13 +12,7 @@
 
 BL1_SOURCES		+=	plat/arm/board/common/drivers/norflash/norflash.c
 
-BL2_SOURCES		+=	lib/utils/mem_region.c					\
-				plat/arm/common/arm_nor_psci_mem_protect.c		\
-				plat/arm/board/common/drivers/norflash/norflash.c
-
-BL31_SOURCES		+=	lib/utils/mem_region.c					\
-				plat/arm/board/common/drivers/norflash/norflash.c	\
-				plat/arm/common/arm_nor_psci_mem_protect.c
+BL2_SOURCES		+=	plat/arm/board/common/drivers/norflash/norflash.c
 
 ifneq (${TRUSTED_BOARD_BOOT},0)
   ifneq (${ARM_CRYPTOCELL_INTEG}, 1)
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index 2b1e0ac..fd93b99 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -134,13 +134,17 @@
 
 
 BL2_SOURCES		+=	drivers/io/io_semihosting.c			\
+				lib/utils/mem_region.c				\
 				lib/semihosting/semihosting.c			\
 				lib/semihosting/${ARCH}/semihosting_call.S	\
 				plat/arm/board/fvp/fvp_bl2_setup.c		\
 				plat/arm/board/fvp/fvp_io_storage.c		\
 				plat/arm/board/fvp/fvp_trusted_boot.c		\
+				plat/arm/common/arm_nor_psci_mem_protect.c	\
 				${FVP_SECURITY_SOURCES}
 
+
+
 ifeq (${BL2_AT_EL3},1)
 BL2_SOURCES		+=	plat/arm/board/fvp/${ARCH}/fvp_helpers.S	\
 				plat/arm/board/fvp/fvp_bl2_el3_setup.c		\
@@ -156,11 +160,14 @@
 				${FVP_SECURITY_SOURCES}
 
 BL31_SOURCES		+=	drivers/arm/smmu/smmu_v3.c			\
+				lib/utils/mem_region.c				\
 				plat/arm/board/fvp/fvp_bl31_setup.c		\
 				plat/arm/board/fvp/fvp_pm.c			\
 				plat/arm/board/fvp/fvp_topology.c		\
 				plat/arm/board/fvp/aarch64/fvp_helpers.S	\
 				plat/arm/board/fvp/drivers/pwrc/fvp_pwrc.c	\
+				plat/arm/board/common/drivers/norflash/norflash.c \
+				plat/arm/common/arm_nor_psci_mem_protect.c	\
 				${FVP_CPU_LIBS}					\
 				${FVP_GIC_SOURCES}				\
 				${FVP_INTERCONNECT_SOURCES}			\
diff --git a/plat/arm/board/juno/platform.mk b/plat/arm/board/juno/platform.mk
index 3ab99ef..16390fa 100644
--- a/plat/arm/board/juno/platform.mk
+++ b/plat/arm/board/juno/platform.mk
@@ -59,7 +59,9 @@
 				${JUNO_INTERCONNECT_SOURCES}		\
 				${JUNO_SECURITY_SOURCES}
 
-BL2_SOURCES		+=	plat/arm/board/juno/juno_bl2_setup.c	\
+BL2_SOURCES		+=	lib/utils/mem_region.c			\
+				plat/arm/board/juno/juno_bl2_setup.c	\
+				plat/arm/common/arm_nor_psci_mem_protect.c \
 				${JUNO_SECURITY_SOURCES}
 
 BL2U_SOURCES		+=	${JUNO_SECURITY_SOURCES}
@@ -67,7 +69,10 @@
 BL31_SOURCES		+=	lib/cpus/aarch64/cortex_a53.S		\
 				lib/cpus/aarch64/cortex_a57.S		\
 				lib/cpus/aarch64/cortex_a72.S		\
+				lib/utils/mem_region.c			\
 				plat/arm/board/juno/juno_topology.c	\
+				plat/arm/board/common/drivers/norflash/norflash.c \
+				plat/arm/common/arm_nor_psci_mem_protect.c \
 				${JUNO_GIC_SOURCES}			\
 				${JUNO_INTERCONNECT_SOURCES}		\
 				${JUNO_SECURITY_SOURCES}
diff --git a/plat/arm/board/sgi575/platform.mk b/plat/arm/board/sgi575/platform.mk
index 9893ba5..284bae8 100644
--- a/plat/arm/board/sgi575/platform.mk
+++ b/plat/arm/board/sgi575/platform.mk
@@ -5,3 +5,10 @@
 #
 
 include plat/arm/css/sgi/sgi-common.mk
+
+BL2_SOURCES		+=	lib/utils/mem_region.c			\
+				plat/arm/common/arm_nor_psci_mem_protect.c
+
+BL31_SOURCES		+=	lib/utils/mem_region.c			\
+				plat/arm/board/common/drivers/norflash/norflash.c \
+				plat/arm/common/arm_nor_psci_mem_protect.c
diff --git a/plat/arm/board/sgm775/platform.mk b/plat/arm/board/sgm775/platform.mk
index 71e71e1..633cee6 100644
--- a/plat/arm/board/sgm775/platform.mk
+++ b/plat/arm/board/sgm775/platform.mk
@@ -11,3 +11,10 @@
 FDT_SOURCES += ${SGM775_BASE}/fdts/sgm775_tb_fw_config.dts
 
 PLAT_INCLUDES +=-I${SGM775_BASE}/include/
+
+BL2_SOURCES		+=	lib/utils/mem_region.c                  \
+				plat/arm/common/arm_nor_psci_mem_protect.c
+
+BL31_SOURCES		+=	lib/utils/mem_region.c                  \
+				plat/arm/board/common/drivers/norflash/norflash.c \
+				plat/arm/common/arm_nor_psci_mem_protect.c
diff --git a/plat/rockchip/common/aarch64/plat_helpers.S b/plat/rockchip/common/aarch64/plat_helpers.S
index f415f87..f0136b0 100644
--- a/plat/rockchip/common/aarch64/plat_helpers.S
+++ b/plat/rockchip/common/aarch64/plat_helpers.S
@@ -18,7 +18,7 @@
 	.globl	platform_cpu_warmboot
 	.globl	plat_secondary_cold_boot_setup
 	.globl	plat_report_exception
-	.globl	platform_is_primary_cpu
+	.globl	plat_is_my_cpu_primary
 	.globl	plat_my_core_pos
 	.globl	plat_reset_handler
 	.globl	plat_panic_handler
@@ -73,12 +73,13 @@
 	b	cb_panic
 endfunc plat_secondary_cold_boot_setup
 
-func platform_is_primary_cpu
+func plat_is_my_cpu_primary
+	mrs	x0, mpidr_el1
 	and	x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
 	cmp	x0, #PLAT_RK_PRIMARY_CPU
 	cset	x0, eq
 	ret
-endfunc platform_is_primary_cpu
+endfunc plat_is_my_cpu_primary
 
 	/* --------------------------------------------------------------------
 	 * void plat_panic_handler(void)
diff --git a/plat/rpi3/include/platform_def.h b/plat/rpi3/include/platform_def.h
index 1950376..76a5ff4 100644
--- a/plat/rpi3/include/platform_def.h
+++ b/plat/rpi3/include/platform_def.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -215,7 +215,8 @@
 /*
  * Other memory-related defines.
  */
-#define ADDR_SPACE_SIZE			(ULL(1) << 32)
+#define PLAT_PHY_ADDR_SPACE_SIZE	(ULL(1) << 32)
+#define PLAT_VIRT_ADDR_SPACE_SIZE	(ULL(1) << 32)
 
 #define MAX_MMAP_REGIONS		8
 #define MAX_XLAT_TABLES			4
diff --git a/plat/rpi3/platform.mk b/plat/rpi3/platform.mk
index 55201ef..d6d0d56 100644
--- a/plat/rpi3/platform.mk
+++ b/plat/rpi3/platform.mk
@@ -33,7 +33,7 @@
 				plat/rpi3/rpi3_io_storage.c
 
 BL31_SOURCES		+=	lib/cpus/aarch64/cortex_a53.S		\
-				plat/common/aarch64/plat_psci_common.c	\
+				plat/common/plat_psci_common.c		\
 				plat/rpi3/aarch64/plat_helpers.S	\
 				plat/rpi3/rpi3_bl31_setup.c		\
 				plat/rpi3/rpi3_pm.c			\
diff --git a/plat/rpi3/rpi3_bl2_setup.c b/plat/rpi3/rpi3_bl2_setup.c
index 13e8c01..c78024e 100644
--- a/plat/rpi3/rpi3_bl2_setup.c
+++ b/plat/rpi3/rpi3_bl2_setup.c
@@ -24,8 +24,12 @@
  * in x0. This memory layout is sitting at the base of the free trusted SRAM.
  * Copy it to a safe location before its reclaimed by later BL2 functionality.
  ******************************************************************************/
-void bl2_early_platform_setup(meminfo_t *mem_layout)
+
+void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1,
+			       u_register_t arg2, u_register_t arg3)
 {
+	meminfo_t *mem_layout = (meminfo_t *) arg1;
+
 	/* Initialize the console to provide early debug support */
 	rpi3_console_init();
 
diff --git a/plat/rpi3/rpi3_bl31_setup.c b/plat/rpi3/rpi3_bl31_setup.c
index 5bbb13c..306f26b 100644
--- a/plat/rpi3/rpi3_bl31_setup.c
+++ b/plat/rpi3/rpi3_bl31_setup.c
@@ -53,23 +53,21 @@
  * tables. BL2 has flushed this information to memory, so we are guaranteed
  * to pick up good data.
  ******************************************************************************/
-void bl31_early_platform_setup(void *from_bl2,
-			       void *plat_params_from_bl2)
+void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
+				u_register_t arg2, u_register_t arg3)
+
 {
 	/* Initialize the console to provide early debug support */
 	rpi3_console_init();
 
 	/*
-	 * In debug builds, we pass a special value in 'plat_params_from_bl2'
-	 * to verify platform parameters from BL2 to BL31.
-	 * In release builds, it's not used.
+	 * In debug builds, a special value is passed in 'arg1' to verify
+	 * platform parameters from BL2 to BL31. Not used in release builds.
 	 */
-	assert(((uintptr_t)plat_params_from_bl2) == RPI3_BL31_PLAT_PARAM_VAL);
+	assert(arg1 == RPI3_BL31_PLAT_PARAM_VAL);
 
-	/*
-	 * Check params passed from BL2 should not be NULL,
-	 */
-	bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2;
+	/* Check that params passed from BL2 are not NULL. */
+	bl_params_t *params_from_bl2 = (bl_params_t *) arg0;
 
 	assert(params_from_bl2 != NULL);
 	assert(params_from_bl2->h.type == PARAM_BL_PARAMS);