fix(nxp-mmc): fix the clock rate calculation
Based on the reference manual's description of SYS_CTRL.SDCLKFS and
SYS_CTRL.DVS, the clock rate can be adjusted using a two-stage divider.
The value of SYS_CTRL.DVS should be set considering the value of
SYS_CTRL.SDCLKFS (pre_div). Consequently, the resulting clock rate is
calculated as input_rate / (SYS_CTRL.SDCLKFS * SYS_CTRL.DVS).
Change-Id: I65a5372b8baf9def97e612ee29f99202c0fdc579
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
diff --git a/drivers/imx/usdhc/imx_usdhc.c b/drivers/imx/usdhc/imx_usdhc.c
index 037de05..5ff947d 100644
--- a/drivers/imx/usdhc/imx_usdhc.c
+++ b/drivers/imx/usdhc/imx_usdhc.c
@@ -104,20 +104,20 @@
}
#define IMX7_MMC_SRC_CLK_RATE (200 * 1000 * 1000)
-static void imx_usdhc_set_clk(int clk)
+static void imx_usdhc_set_clk(unsigned int clk)
{
- int div = 1;
- int pre_div = 1;
unsigned int sdhc_clk = IMX7_MMC_SRC_CLK_RATE;
uintptr_t reg_base = imx_usdhc_params.reg_base;
+ unsigned int pre_div = 1U, div = 1U;
assert(clk > 0);
while (sdhc_clk / (16 * pre_div) > clk && pre_div < 256)
pre_div *= 2;
- while (sdhc_clk / div > clk && div < 16)
+ while (((sdhc_clk / (div * pre_div)) > clk) && (div < 16U)) {
div++;
+ }
pre_div >>= 1;
div -= 1;