commit 691b49da5123e8ac40477fd6b144614089b9bc59
author Heyi Guo <guoheyi@linux.alibaba.com> Tue May 19 16:45:17 2020 +0800
committer Manish Pandey <manish.pandey2@arm.com> Wed Feb 03 11:12:30 2021 +0000
tree 3cbc53eb4f6d34eb7b971c4a6060247e0c55e3c2
parent ce380250c2b6aa89c2721a5f7f8c948064c14173

drivers/gicv3: also shift eSPI register offset in GICD_OFFSET_64()

ESPI register offset should also be shifted right by REG##R_SHIFT to
keep consistent.

It is not a functional issue, for GICD_OFFSET_64() is only used for
GICD_IROUTER<E>, and IROUTER_SHIFT is 0.

Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com>
Change-Id: I76eee5c50e4300890e78e80bddde135ce88daa2d

drivers/arm/gic/v3/gicv3_private.h

diff --git a/drivers/arm/gic/v3/gicv3_private.h b/drivers/arm/gic/v3/gicv3_private.h
index c5d027d..416cdd0 100644
--- a/drivers/arm/gic/v3/gicv3_private.h
+++ b/drivers/arm/gic/v3/gicv3_private.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -48,7 +48,8 @@
 #define	GICD_OFFSET_64(REG, id)						\
 	(((id) <= MAX_SPI_ID) ?						\
 	GICD_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 3) :	\
-	GICD_##REG##RE + (((uintptr_t)(id) - MIN_ESPI_ID) << 3))
+	GICD_##REG##RE + ((((uintptr_t)(id) - MIN_ESPI_ID) >>		\
+					REG##R_SHIFT) << 3))
 
 #else	/* GICv3 */
 #define	GICD_OFFSET_8(REG, id)	\