feat(tc): add MCN PMU nodes in dts for TC4
Add MCN PMU nodes in dts for TC4 to use MCN PMU driver in
kernel with perf.
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
Change-Id: I1a85ba646604336ce3f16c28171589af78f65251
diff --git a/fdts/tc3-4-base.dtsi b/fdts/tc3-4-base.dtsi
index 5ccfebb..c7f3084 100644
--- a/fdts/tc3-4-base.dtsi
+++ b/fdts/tc3-4-base.dtsi
@@ -120,4 +120,24 @@
compatible = "arm,dsu-pmu";
cpus = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>, <&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>;
};
+
+ cs-pmu@0 {
+ compatible = "arm,coresight-pmu";
+ reg = <0x0 MCN_PMU_ADDR(0) 0x0 0xffc>;
+ };
+
+ cs-pmu@1 {
+ compatible = "arm,coresight-pmu";
+ reg = <0x0 MCN_PMU_ADDR(1) 0x0 0xffc>;
+ };
+
+ cs-pmu@2 {
+ compatible = "arm,coresight-pmu";
+ reg = <0x0 MCN_PMU_ADDR(2) 0x0 0xffc>;
+ };
+
+ cs-pmu@3 {
+ compatible = "arm,coresight-pmu";
+ reg = <0x0 MCN_PMU_ADDR(3) 0x0 0xffc>;
+ };
};
diff --git a/fdts/tc3.dts b/fdts/tc3.dts
index bce1a54..b8fe587 100644
--- a/fdts/tc3.dts
+++ b/fdts/tc3.dts
@@ -58,26 +58,6 @@
kaslr-seed = <0x0 0x0>;
};
- cs-pmu@0 {
- compatible = "arm,coresight-pmu";
- reg = <0x0 MCN_PMU_ADDR(0) 0x0 0xffc>;
- };
-
- cs-pmu@1 {
- compatible = "arm,coresight-pmu";
- reg = <0x0 MCN_PMU_ADDR(1) 0x0 0xffc>;
- };
-
- cs-pmu@2 {
- compatible = "arm,coresight-pmu";
- reg = <0x0 MCN_PMU_ADDR(2) 0x0 0xffc>;
- };
-
- cs-pmu@3 {
- compatible = "arm,coresight-pmu";
- reg = <0x0 MCN_PMU_ADDR(3) 0x0 0xffc>;
- };
-
spe-pmu-mid {
status = "okay";
};
diff --git a/fdts/tc4.dts b/fdts/tc4.dts
index 8b73b49..5ab58d5 100644
--- a/fdts/tc4.dts
+++ b/fdts/tc4.dts
@@ -71,4 +71,24 @@
dsu-pmu {
interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>;
};
+
+ cs-pmu@4 {
+ compatible = "arm,coresight-pmu";
+ reg = <0x0 MCN_PMU_ADDR(4) 0x0 0xffc>;
+ };
+
+ cs-pmu@5 {
+ compatible = "arm,coresight-pmu";
+ reg = <0x0 MCN_PMU_ADDR(5) 0x0 0xffc>;
+ };
+
+ cs-pmu@6 {
+ compatible = "arm,coresight-pmu";
+ reg = <0x0 MCN_PMU_ADDR(6) 0x0 0xffc>;
+ };
+
+ cs-pmu@7 {
+ compatible = "arm,coresight-pmu";
+ reg = <0x0 MCN_PMU_ADDR(7) 0x0 0xffc>;
+ };
};