refactor(tc): move out platform specific DT binding from tc-base.dtsi
The main purpose of 'tc-base.dtsi' is for common DT bindings, however,
it contains bindings for platform specific.
This patch moves out these plaform specific bindings to 'tc2.dts' and
'tc3.dts' respectively.
Change-Id: I9355eeff539a3f2940190aef399b4fb4828cbbac
Signed-off-by: Leo Yan <leo.yan@arm.com>
diff --git a/fdts/tc-base.dtsi b/fdts/tc-base.dtsi
index 09809f0..7d5a8dd 100644
--- a/fdts/tc-base.dtsi
+++ b/fdts/tc-base.dtsi
@@ -62,26 +62,6 @@
core7 {
cpu = <&CPU7>;
};
-#if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2
- core8 {
- cpu = <&CPU8>;
- };
- core9 {
- cpu = <&CPU9>;
- };
- core10 {
- cpu = <&CPU10>;
- };
- core11 {
- cpu = <&CPU11>;
- };
- core12 {
- cpu = <&CPU12>;
- };
- core13 {
- cpu = <&CPU13>;
- };
-#endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 */
};
};
@@ -162,13 +142,6 @@
reg = <0x200>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
-#if TARGET_PLATFORM <= 2
- clocks = <&scmi_dvfs 0>;
- capacity-dmips-mhz = <LIT_CAPACITY>;
-#elif TARGET_PLATFORM == 3
- clocks = <&scmi_dvfs 1>;
- capacity-dmips-mhz = <MID_CAPACITY>;
-#endif /* TARGET_PLATFORM == 3 */
amu = <&amu>;
supports-mpmm;
};
@@ -179,13 +152,6 @@
reg = <0x300>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
-#if TARGET_PLATFORM <= 2
- clocks = <&scmi_dvfs 0>;
- capacity-dmips-mhz = <LIT_CAPACITY>;
-#elif TARGET_PLATFORM == 3
- clocks = <&scmi_dvfs 1>;
- capacity-dmips-mhz = <MID_CAPACITY>;
-#endif /* TARGET_PLATFORM == 3 */
amu = <&amu>;
supports-mpmm;
};
@@ -220,13 +186,6 @@
reg = <0x600>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
-#if TARGET_PLATFORM <= 2
- clocks = <&scmi_dvfs 1>;
- capacity-dmips-mhz = <MID_CAPACITY>;
-#elif TARGET_PLATFORM == 3
- clocks = <&scmi_dvfs 2>;
- capacity-dmips-mhz = <BIG_CAPACITY>;
-#endif /* TARGET_PLATFORM == 3 */
amu = <&amu>;
supports-mpmm;
};
@@ -237,84 +196,9 @@
reg = <0x700>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
-#if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2
- clocks = <&scmi_dvfs 1>;
- capacity-dmips-mhz = <MID_CAPACITY>;
-#else
- clocks = <&scmi_dvfs 2>;
- capacity-dmips-mhz = <BIG_CAPACITY>;
-#endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 */
- amu = <&amu>;
- supports-mpmm;
- };
-
-#if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2
- CPU8:cpu@800 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x800>;
- enable-method = "psci";
- clocks = <&scmi_dvfs 1>;
- capacity-dmips-mhz = <MID_CAPACITY>;
- amu = <&amu>;
- supports-mpmm;
- };
-
- CPU9:cpu@900 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x900>;
- enable-method = "psci";
- clocks = <&scmi_dvfs 2>;
- capacity-dmips-mhz = <BIG2_CAPACITY>;
- amu = <&amu>;
- supports-mpmm;
- };
-
- CPU10:cpu@A00 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0xA00>;
- enable-method = "psci";
- clocks = <&scmi_dvfs 2>;
- capacity-dmips-mhz = <BIG2_CAPACITY>;
- amu = <&amu>;
- supports-mpmm;
- };
-
- CPU11:cpu@B00 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0xB00>;
- enable-method = "psci";
- clocks = <&scmi_dvfs 2>;
- capacity-dmips-mhz = <BIG2_CAPACITY>;
- amu = <&amu>;
- supports-mpmm;
- };
-
- CPU12:cpu@C00 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0xC00>;
- enable-method = "psci";
- clocks = <&scmi_dvfs 3>;
- capacity-dmips-mhz = <BIG_CAPACITY>;
- amu = <&amu>;
- supports-mpmm;
- };
-
- CPU13:cpu@D00 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0xD00>;
- enable-method = "psci";
- clocks = <&scmi_dvfs 3>;
- capacity-dmips-mhz = <BIG_CAPACITY>;
amu = <&amu>;
supports-mpmm;
};
-#endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 */
};
reserved-memory {
@@ -355,13 +239,6 @@
cpu-pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-affinity = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>,
- <&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>
-#if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2
- ,<&CPU8>, <&CPU9>, <&CPU10>, <&CPU11>,
- <&CPU12>, <&CPU13>
-#endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 */
- ;
};
sram: sram@6000000 {
@@ -609,9 +486,6 @@
#if TC_IOMMU_EN
iommus = <&smmu_700 0x100>;
#endif /* TC_IOMMU_EN */
-#if TC_SCMI_PD_CTRL_EN && (TARGET_PLATFORM != 3)
- power-domains = <&scmi_devpd DPU_SCMI_PD_IDX>;
-#endif /* TC_SCMI_PD_CTRL_EN && (TARGET_PLATFORM != 3) */
pl0: pipeline@0 {
reg = <0>;
@@ -691,38 +565,6 @@
compatible = "arm,embedded-trace-extension";
cpu = <&CPU7>;
};
-
-#if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2
- ete8 {
- compatible = "arm,embedded-trace-extension";
- cpu = <&CPU8>;
- };
-
- ete9 {
- compatible = "arm,embedded-trace-extension";
- cpu = <&CPU9>;
- };
-
- ete10 {
- compatible = "arm,embedded-trace-extension";
- cpu = <&CPU10>;
- };
-
- ete11 {
- compatible = "arm,embedded-trace-extension";
- cpu = <&CPU11>;
- };
-
- ete12 {
- compatible = "arm,embedded-trace-extension";
- cpu = <&CPU12>;
- };
-
- ete13 {
- compatible = "arm,embedded-trace-extension";
- cpu = <&CPU13>;
- };
-#endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 */
trbe {
compatible = "arm,trace-buffer-extension";
diff --git a/fdts/tc2.dts b/fdts/tc2.dts
index bff3f1a..b6acdaa 100644
--- a/fdts/tc2.dts
+++ b/fdts/tc2.dts
@@ -36,9 +36,174 @@
#include "tc-base.dtsi"
/ {
+ cpus {
+#if TARGET_FLAVOUR_FPGA
+ cpu-map {
+ cluster0 {
+ core8 {
+ cpu = <&CPU8>;
+ };
+ core9 {
+ cpu = <&CPU9>;
+ };
+ core10 {
+ cpu = <&CPU10>;
+ };
+ core11 {
+ cpu = <&CPU11>;
+ };
+ core12 {
+ cpu = <&CPU12>;
+ };
+ core13 {
+ cpu = <&CPU13>;
+ };
+ };
+ };
+#endif
+
+ CPU2:cpu@200 {
+ clocks = <&scmi_dvfs 0>;
+ capacity-dmips-mhz = <LIT_CAPACITY>;
+ };
+
+ CPU3:cpu@300 {
+ clocks = <&scmi_dvfs 0>;
+ capacity-dmips-mhz = <LIT_CAPACITY>;
+ };
+
+ CPU6:cpu@600 {
+ clocks = <&scmi_dvfs 1>;
+ capacity-dmips-mhz = <MID_CAPACITY>;
+ };
+
+ CPU7:cpu@700 {
+ clocks = <&scmi_dvfs 1>;
+ capacity-dmips-mhz = <MID_CAPACITY>;
+ };
+
+#if TARGET_FLAVOUR_FPGA
+ CPU8:cpu@800 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x800>;
+ enable-method = "psci";
+ clocks = <&scmi_dvfs 1>;
+ capacity-dmips-mhz = <MID_CAPACITY>;
+ amu = <&amu>;
+ supports-mpmm;
+ };
+
+ CPU9:cpu@900 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x900>;
+ enable-method = "psci";
+ clocks = <&scmi_dvfs 2>;
+ capacity-dmips-mhz = <BIG2_CAPACITY>;
+ amu = <&amu>;
+ supports-mpmm;
+ };
+
+ CPU10:cpu@A00 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0xA00>;
+ enable-method = "psci";
+ clocks = <&scmi_dvfs 2>;
+ capacity-dmips-mhz = <BIG2_CAPACITY>;
+ amu = <&amu>;
+ supports-mpmm;
+ };
+
+ CPU11:cpu@B00 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0xB00>;
+ enable-method = "psci";
+ clocks = <&scmi_dvfs 2>;
+ capacity-dmips-mhz = <BIG2_CAPACITY>;
+ amu = <&amu>;
+ supports-mpmm;
+ };
+
+ CPU12:cpu@C00 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0xC00>;
+ enable-method = "psci";
+ clocks = <&scmi_dvfs 3>;
+ capacity-dmips-mhz = <BIG_CAPACITY>;
+ amu = <&amu>;
+ supports-mpmm;
+ };
+
+ CPU13:cpu@D00 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0xD00>;
+ enable-method = "psci";
+ clocks = <&scmi_dvfs 3>;
+ capacity-dmips-mhz = <BIG_CAPACITY>;
+ amu = <&amu>;
+ supports-mpmm;
+ };
+#endif
+ };
+
+#if TARGET_FLAVOUR_FPGA
+ ete8 {
+ compatible = "arm,embedded-trace-extension";
+ cpu = <&CPU8>;
+ };
+
+ ete9 {
+ compatible = "arm,embedded-trace-extension";
+ cpu = <&CPU9>;
+ };
+
+ ete10 {
+ compatible = "arm,embedded-trace-extension";
+ cpu = <&CPU10>;
+ };
+
+ ete11 {
+ compatible = "arm,embedded-trace-extension";
+ cpu = <&CPU11>;
+ };
+
+ ete12 {
+ compatible = "arm,embedded-trace-extension";
+ cpu = <&CPU12>;
+ };
+
+ ete13 {
+ compatible = "arm,embedded-trace-extension";
+ cpu = <&CPU13>;
+ };
+#endif /* TARGET_FLAVOUR_FPGA */
+
+ cpu-pmu {
+#if TARGET_FLAVOUR_FPGA
+ interrupt-affinity = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>,
+ <&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>,
+ <&CPU8>, <&CPU9>, <&CPU10>, <&CPU11>,
+ <&CPU12>, <&CPU13>;
+#else
+ interrupt-affinity = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>,
+ <&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>;
+#endif
+ };
+
cmn-pmu {
compatible = "arm,ci-700";
reg = <0x0 0x50000000 0x0 0x10000000>;
interrupts = <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>;
};
+
+ dp0: display@DPU_ADDR {
+#if TC_SCMI_PD_CTRL_EN
+ power-domains = <&scmi_devpd (PLAT_MAX_CPUS_PER_CLUSTER + 2)>;
+#endif
+ };
};
diff --git a/fdts/tc3.dts b/fdts/tc3.dts
index 2432b81..5522210 100644
--- a/fdts/tc3.dts
+++ b/fdts/tc3.dts
@@ -33,3 +33,32 @@
#include "tc-fvp.dtsi"
#endif /* TARGET_FLAVOUR_FVP */
#include "tc-base.dtsi"
+
+/ {
+ cpus {
+ CPU2:cpu@200 {
+ clocks = <&scmi_dvfs 1>;
+ capacity-dmips-mhz = <MID_CAPACITY>;
+ };
+
+ CPU3:cpu@300 {
+ clocks = <&scmi_dvfs 1>;
+ capacity-dmips-mhz = <MID_CAPACITY>;
+ };
+
+ CPU6:cpu@600 {
+ clocks = <&scmi_dvfs 2>;
+ capacity-dmips-mhz = <BIG_CAPACITY>;
+ };
+
+ CPU7:cpu@700 {
+ clocks = <&scmi_dvfs 2>;
+ capacity-dmips-mhz = <BIG_CAPACITY>;
+ };
+ };
+
+ cpu-pmu {
+ interrupt-affinity = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>,
+ <&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>;
+ };
+};