diff --git a/plat/nvidia/tegra/common/tegra_pm.c b/plat/nvidia/tegra/common/tegra_pm.c
index 9445019..6f841ef 100644
--- a/plat/nvidia/tegra/common/tegra_pm.c
+++ b/plat/nvidia/tegra/common/tegra_pm.c
@@ -107,7 +107,7 @@
 void tegra_get_sys_suspend_power_state(psci_power_state_t *req_state)
 {
 	/* all affinities use system suspend state id */
-	for (int i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++)
+	for (uint32_t i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++)
 		req_state->pwr_domain_state[i] = PSTATE_ID_SOC_POWERDN;
 }
 
diff --git a/plat/nvidia/tegra/platform.mk b/plat/nvidia/tegra/platform.mk
index f5af408..eaf1091 100644
--- a/plat/nvidia/tegra/platform.mk
+++ b/plat/nvidia/tegra/platform.mk
@@ -34,3 +34,6 @@
 
 # modify BUILD_PLAT to point to SoC specific build directory
 BUILD_PLAT	:=	${BUILD_BASE}/${PLAT}/${TARGET_SOC}/${BUILD_TYPE}
+
+# enable signed comparison checks
+CFLAGS		+= -Wsign-compare
diff --git a/plat/nvidia/tegra/soc/t132/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t132/plat_psci_handlers.c
index 56ce91b..9b7dc85 100644
--- a/plat/nvidia/tegra/soc/t132/plat_psci_handlers.c
+++ b/plat/nvidia/tegra/soc/t132/plat_psci_handlers.c
@@ -49,7 +49,7 @@
 	}
 
 	/* Set lower power states to PLAT_MAX_OFF_STATE */
-	for (int i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++)
+	for (uint32_t i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++)
 		req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE;
 
 	/* Set the SYSTEM_SUSPEND state-id */
diff --git a/plat/nvidia/tegra/soc/t186/drivers/mce/ari.c b/plat/nvidia/tegra/soc/t186/drivers/mce/ari.c
index 4765ba0..05b30fc 100644
--- a/plat/nvidia/tegra/soc/t186/drivers/mce/ari.c
+++ b/plat/nvidia/tegra/soc/t186/drivers/mce/ari.c
@@ -291,7 +291,7 @@
 
 int ari_online_core(uint32_t ari_base, uint32_t core)
 {
-	int cpu = read_mpidr() & MPIDR_CPU_MASK;
+	uint32_t cpu = read_mpidr() & MPIDR_CPU_MASK;
 	int cluster = (read_mpidr() & MPIDR_CLUSTER_MASK) >>
 			MPIDR_AFFINITY_BITS;
 	int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK;
@@ -300,7 +300,7 @@
 	cpu |= (cluster << 2);
 
 	/* sanity check target core id */
-	if ((core >= MCE_CORE_ID_MAX) || (cpu == core)) {
+	if ((core >= (uint32_t)MCE_CORE_ID_MAX) || (cpu == core)) {
 		ERROR("%s: unsupported core id (%d)\n", __func__, core);
 		return EINVAL;
 	}
diff --git a/plat/nvidia/tegra/soc/t186/drivers/mce/nvg.c b/plat/nvidia/tegra/soc/t186/drivers/mce/nvg.c
index 0be1af1..8c6f67c 100644
--- a/plat/nvidia/tegra/soc/t186/drivers/mce/nvg.c
+++ b/plat/nvidia/tegra/soc/t186/drivers/mce/nvg.c
@@ -168,11 +168,11 @@
 
 int nvg_online_core(uint32_t ari_base, uint32_t core)
 {
-	int cpu = read_mpidr() & MPIDR_CPU_MASK;
+	uint32_t cpu = read_mpidr() & MPIDR_CPU_MASK;
 	int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK;
 
 	/* sanity check code id */
-	if ((core >= MCE_CORE_ID_MAX) || (cpu == core)) {
+	if ((core >= (uint32_t)MCE_CORE_ID_MAX) || (cpu == core)) {
 		ERROR("%s: unsupported core id (%d)\n", __func__, core);
 		return EINVAL;
 	}
diff --git a/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c
index 44b99dc..095614e 100644
--- a/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c
+++ b/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c
@@ -256,8 +256,8 @@
 
 int tegra_soc_pwr_domain_on(u_register_t mpidr)
 {
-	int target_cpu = mpidr & MPIDR_CPU_MASK;
-	int target_cluster = (mpidr & MPIDR_CLUSTER_MASK) >>
+	uint32_t target_cpu = mpidr & MPIDR_CPU_MASK;
+	uint32_t target_cluster = (mpidr & MPIDR_CLUSTER_MASK) >>
 			MPIDR_AFFINITY_BITS;
 
 	if (target_cluster > MPIDR_AFFLVL1) {
diff --git a/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c
index bcaade6..3dff653 100644
--- a/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c
+++ b/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c
@@ -60,7 +60,7 @@
 		/*
 		 * System powerdown request only for afflvl 2
 		 */
-		for (int i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++)
+		for (uint32_t i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++)
 			req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE;
 
 		req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] =