fix(cpus): workaround for Cortex-A710 erratum 1927200
Cortex-A710 erratum 1927200 is a Cat B erratum that applies
to revisions r0p0 and r1p0 and is fixed in r2p0.
The fix is to insert DMB ST before acquire atomic instructions
without release semantics via instruction patching.
SDEN documentation:
https://developer.arm.com/documentation/SDEN1775101
Change-Id: I53c4aa17c1c2dc85b68f17d58f93bb1ee6b3d488
Signed-off-by: John Powell <john.powell@arm.com>
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index 8b0ab4b..853b703 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -585,6 +585,10 @@
Cortex-A710 CPU. This needs to be enabled only for revisions r0p0 and r1p0.
It has been fixed in r2p0.
+- ``ERRATA_A710_1927200``: This applies errata 1927200 workaround to
+ Cortex-A710 CPU. This needs to be enabled only for revisions r0p0 and r1p0.
+ It has been fixed in r2p0.
+
- ``ERRATA_A710_1987031``: This applies errata 1987031 workaround to
Cortex-A710 CPU. This needs to be enabled only for revisions r0p0, r1p0 and
r2p0 of the CPU. It is still open.
diff --git a/lib/cpus/aarch64/cortex_a710.S b/lib/cpus/aarch64/cortex_a710.S
index 728c51f..59b6244 100644
--- a/lib/cpus/aarch64/cortex_a710.S
+++ b/lib/cpus/aarch64/cortex_a710.S
@@ -49,6 +49,37 @@
check_erratum_ls cortex_a710, ERRATUM(1917258), CPU_REV(1, 0)
+workaround_reset_start cortex_a710, ERRATUM(1927200), ERRATA_A710_1927200
+ mov x0, #0
+ msr S3_6_C15_C8_0, x0
+ ldr x0, =0x10E3900002
+ msr S3_6_C15_C8_2, x0
+ ldr x0, =0x10FFF00083
+ msr S3_6_C15_C8_3, x0
+ ldr x0, =0x2001003FF
+ msr S3_6_C15_C8_1, x0
+
+ mov x0, #1
+ msr S3_6_C15_C8_0, x0
+ ldr x0, =0x10E3800082
+ msr S3_6_C15_C8_2, x0
+ ldr x0, =0x10FFF00083
+ msr S3_6_C15_C8_3, x0
+ ldr x0, =0x2001003FF
+ msr S3_6_C15_C8_1, x0
+
+ mov x0, #2
+ msr S3_6_C15_C8_0, x0
+ ldr x0, =0x10E3800200
+ msr S3_6_C15_C8_2, x0
+ ldr x0, =0x10FFF003E0
+ msr S3_6_C15_C8_3, x0
+ ldr x0, =0x2001003FF
+ msr S3_6_C15_C8_1, x0
+workaround_reset_end cortex_a710, ERRATUM(1927200)
+
+check_erratum_ls cortex_a710, ERRATUM(1927200), CPU_REV(1, 0)
+
workaround_reset_start cortex_a710, ERRATUM(1987031), ERRATA_A710_1987031
ldr x0,=0x6
msr S3_6_c15_c8_0,x0
diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index 7cf86a2..c8fb8b7 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -573,6 +573,10 @@
# to revisions r0p0 and r1p0 of the Cortex-A710 CPU and is fixed in r2p0.
CPU_FLAG_LIST += ERRATA_A710_1917258
+# Flag to apply erratum 1927200 workaround during reset. This erratum applies
+# to revisions r0p0 and r1p0 of the Cortex-A710 CPU and is fixed in r2p0.
+CPU_FLAG_LIST += ERRATA_A710_1927200
+
# Flag to apply erratum 1987031 workaround during reset. This erratum applies
# to revisions r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is still open.
CPU_FLAG_LIST += ERRATA_A710_1987031