diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_clock.h b/plat/xilinx/zynqmp/pm_service/pm_api_clock.h
index db476e8..cc0dacc 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_api_clock.h
+++ b/plat/xilinx/zynqmp/pm_service/pm_api_clock.h
@@ -57,224 +57,224 @@
 
 //CLock Ids
 enum clock_id {
-	CLK_IOPLL,
-	CLK_RPLL,
-	CLK_APLL,
-	CLK_DPLL,
-	CLK_VPLL,
-	CLK_IOPLL_TO_FPD,
-	CLK_RPLL_TO_FPD,
-	CLK_APLL_TO_LPD,
-	CLK_DPLL_TO_LPD,
-	CLK_VPLL_TO_LPD,
-	CLK_ACPU,
-	CLK_ACPU_HALF,
-	CLK_DBG_FPD,
-	CLK_DBG_LPD,
-	CLK_DBG_TRACE,
-	CLK_DBG_TSTMP,
-	CLK_DP_VIDEO_REF,
-	CLK_DP_AUDIO_REF,
-	CLK_DP_STC_REF,
-	CLK_GDMA_REF,
-	CLK_DPDMA_REF,
-	CLK_DDR_REF,
-	CLK_SATA_REF,
-	CLK_PCIE_REF,
-	CLK_GPU_REF,
-	CLK_GPU_PP0_REF,
-	CLK_GPU_PP1_REF,
-	CLK_TOPSW_MAIN,
-	CLK_TOPSW_LSBUS,
-	CLK_GTGREF0_REF,
-	CLK_LPD_SWITCH,
-	CLK_LPD_LSBUS,
-	CLK_USB0_BUS_REF,
-	CLK_USB1_BUS_REF,
-	CLK_USB3_DUAL_REF,
-	CLK_USB0,
-	CLK_USB1,
-	CLK_CPU_R5,
-	CLK_CPU_R5_CORE,
-	CLK_CSU_SPB,
-	CLK_CSU_PLL,
-	CLK_PCAP,
-	CLK_IOU_SWITCH,
-	CLK_GEM_TSU_REF,
-	CLK_GEM_TSU,
-	CLK_GEM0_TX,
-	CLK_GEM1_TX,
-	CLK_GEM2_TX,
-	CLK_GEM3_TX,
-	CLK_GEM0_RX,
-	CLK_GEM1_RX,
-	CLK_GEM2_RX,
-	CLK_GEM3_RX,
-	CLK_QSPI_REF,
-	CLK_SDIO0_REF,
-	CLK_SDIO1_REF,
-	CLK_UART0_REF,
-	CLK_UART1_REF,
-	CLK_SPI0_REF,
-	CLK_SPI1_REF,
-	CLK_NAND_REF,
-	CLK_I2C0_REF,
-	CLK_I2C1_REF,
-	CLK_CAN0_REF,
-	CLK_CAN1_REF,
-	CLK_CAN0,
-	CLK_CAN1,
-	CLK_DLL_REF,
-	CLK_ADMA_REF,
-	CLK_TIMESTAMP_REF,
-	CLK_AMS_REF,
-	CLK_PL0_REF,
-	CLK_PL1_REF,
-	CLK_PL2_REF,
-	CLK_PL3_REF,
-	CLK_FPD_WDT,
-	CLK_IOPLL_INT,
-	CLK_IOPLL_PRE_SRC,
-	CLK_IOPLL_HALF,
-	CLK_IOPLL_INT_MUX,
-	CLK_IOPLL_POST_SRC,
-	CLK_RPLL_INT,
-	CLK_RPLL_PRE_SRC,
-	CLK_RPLL_HALF,
-	CLK_RPLL_INT_MUX,
-	CLK_RPLL_POST_SRC,
-	CLK_APLL_INT,
-	CLK_APLL_PRE_SRC,
-	CLK_APLL_HALF,
-	CLK_APLL_INT_MUX,
-	CLK_APLL_POST_SRC,
-	CLK_DPLL_INT,
-	CLK_DPLL_PRE_SRC,
-	CLK_DPLL_HALF,
-	CLK_DPLL_INT_MUX,
-	CLK_DPLL_POST_SRC,
-	CLK_VPLL_INT,
-	CLK_VPLL_PRE_SRC,
-	CLK_VPLL_HALF,
-	CLK_VPLL_INT_MUX,
-	CLK_VPLL_POST_SRC,
-	CLK_CAN0_MIO,
-	CLK_CAN1_MIO,
-	CLK_ACPU_FULL,
-	CLK_GEM0_REF,
-	CLK_GEM1_REF,
-	CLK_GEM2_REF,
-	CLK_GEM3_REF,
-	CLK_GEM0_REF_UNGATED,
-	CLK_GEM1_REF_UNGATED,
-	CLK_GEM2_REF_UNGATED,
-	CLK_GEM3_REF_UNGATED,
-	CLK_LPD_WDT,
-	END_OF_OUTPUT_CLKS,
+	CLK_IOPLL = (0U),
+	CLK_RPLL  = (1U),
+	CLK_APLL  = (2U),
+	CLK_DPLL  = (3U),
+	CLK_VPLL  = (4U),
+	CLK_IOPLL_TO_FPD = (5U),
+	CLK_RPLL_TO_FPD = (6U),
+	CLK_APLL_TO_LPD = (7U),
+	CLK_DPLL_TO_LPD = (8U),
+	CLK_VPLL_TO_LPD = (9U),
+	CLK_ACPU = (10U),
+	CLK_ACPU_HALF = (11U),
+	CLK_DBG_FPD = (12U),
+	CLK_DBG_LPD = (13U),
+	CLK_DBG_TRACE = (14U),
+	CLK_DBG_TSTMP = (15U),
+	CLK_DP_VIDEO_REF = (16U),
+	CLK_DP_AUDIO_REF = (17U),
+	CLK_DP_STC_REF = (18U),
+	CLK_GDMA_REF = (19U),
+	CLK_DPDMA_REF = (20U),
+	CLK_DDR_REF = (21U),
+	CLK_SATA_REF = (22U),
+	CLK_PCIE_REF = (23U),
+	CLK_GPU_REF = (24U),
+	CLK_GPU_PP0_REF = (25U),
+	CLK_GPU_PP1_REF = (26U),
+	CLK_TOPSW_MAIN = (27U),
+	CLK_TOPSW_LSBUS = (28U),
+	CLK_GTGREF0_REF = (29U),
+	CLK_LPD_SWITCH = (30U),
+	CLK_LPD_LSBUS = (31U),
+	CLK_USB0_BUS_REF = (32U),
+	CLK_USB1_BUS_REF = (33U),
+	CLK_USB3_DUAL_REF = (34U),
+	CLK_USB0 = (35U),
+	CLK_USB1 = (36U),
+	CLK_CPU_R5 = (37U),
+	CLK_CPU_R5_CORE = (38U),
+	CLK_CSU_SPB = (39U),
+	CLK_CSU_PLL = (40U),
+	CLK_PCAP = (41U),
+	CLK_IOU_SWITCH = (42U),
+	CLK_GEM_TSU_REF = (43U),
+	CLK_GEM_TSU = (44U),
+	CLK_GEM0_TX = (45U),
+	CLK_GEM1_TX = (46U),
+	CLK_GEM2_TX = (47U),
+	CLK_GEM3_TX = (48U),
+	CLK_GEM0_RX = (49U),
+	CLK_GEM1_RX = (50U),
+	CLK_GEM2_RX = (51U),
+	CLK_GEM3_RX = (52U),
+	CLK_QSPI_REF = (53U),
+	CLK_SDIO0_REF = (54U),
+	CLK_SDIO1_REF = (55U),
+	CLK_UART0_REF = (56U),
+	CLK_UART1_REF = (57U),
+	CLK_SPI0_REF = (58U),
+	CLK_SPI1_REF = (59U),
+	CLK_NAND_REF = (60U),
+	CLK_I2C0_REF = (61U),
+	CLK_I2C1_REF = (62U),
+	CLK_CAN0_REF = (63U),
+	CLK_CAN1_REF = (64U),
+	CLK_CAN0 = (65U),
+	CLK_CAN1 = (66U),
+	CLK_DLL_REF = (67U),
+	CLK_ADMA_REF = (68U),
+	CLK_TIMESTAMP_REF = (69U),
+	CLK_AMS_REF = (70U),
+	CLK_PL0_REF = (71U),
+	CLK_PL1_REF = (72U),
+	CLK_PL2_REF = (73U),
+	CLK_PL3_REF = (74U),
+	CLK_FPD_WDT = (75U),
+	CLK_IOPLL_INT = (76U),
+	CLK_IOPLL_PRE_SRC = (77U),
+	CLK_IOPLL_HALF = (78U),
+	CLK_IOPLL_INT_MUX = (79U),
+	CLK_IOPLL_POST_SRC = (80U),
+	CLK_RPLL_INT = (81U),
+	CLK_RPLL_PRE_SRC = (82U),
+	CLK_RPLL_HALF = (83U),
+	CLK_RPLL_INT_MUX = (84U),
+	CLK_RPLL_POST_SRC = (85U),
+	CLK_APLL_INT = (86U),
+	CLK_APLL_PRE_SRC = (87U),
+	CLK_APLL_HALF = (88U),
+	CLK_APLL_INT_MUX = (89U),
+	CLK_APLL_POST_SRC = (90U),
+	CLK_DPLL_INT = (91U),
+	CLK_DPLL_PRE_SRC = (92U),
+	CLK_DPLL_HALF = (93U),
+	CLK_DPLL_INT_MUX = (94U),
+	CLK_DPLL_POST_SRC = (95U),
+	CLK_VPLL_INT = (96U),
+	CLK_VPLL_PRE_SRC = (97U),
+	CLK_VPLL_HALF = (98U),
+	CLK_VPLL_INT_MUX = (99U),
+	CLK_VPLL_POST_SRC = (100U),
+	CLK_CAN0_MIO = (101U),
+	CLK_CAN1_MIO = (102U),
+	CLK_ACPU_FULL = (103U),
+	CLK_GEM0_REF = (104U),
+	CLK_GEM1_REF = (105U),
+	CLK_GEM2_REF = (106U),
+	CLK_GEM3_REF = (107U),
+	CLK_GEM0_REF_UNGATED = (108U),
+	CLK_GEM1_REF_UNGATED = (109U),
+	CLK_GEM2_REF_UNGATED = (110U),
+	CLK_GEM3_REF_UNGATED = (111U),
+	CLK_LPD_WDT = (112U),
+	END_OF_OUTPUT_CLKS = (113U),
 };
 
-#define CLK_MAX_OUTPUT_CLK (unsigned int)(END_OF_OUTPUT_CLKS)
+#define CLK_MAX_OUTPUT_CLK END_OF_OUTPUT_CLKS
 
 //External clock ids
 enum {
 	EXT_CLK_PSS_REF = END_OF_OUTPUT_CLKS,
-	EXT_CLK_VIDEO,
-	EXT_CLK_PSS_ALT_REF,
-	EXT_CLK_AUX_REF,
-	EXT_CLK_GT_CRX_REF,
-	EXT_CLK_SWDT0,
-	EXT_CLK_SWDT1,
-	EXT_CLK_GEM0_TX_EMIO,
-	EXT_CLK_GEM1_TX_EMIO,
-	EXT_CLK_GEM2_TX_EMIO,
-	EXT_CLK_GEM3_TX_EMIO,
-	EXT_CLK_GEM0_RX_EMIO,
-	EXT_CLK_GEM1_RX_EMIO,
-	EXT_CLK_GEM2_RX_EMIO,
-	EXT_CLK_GEM3_RX_EMIO,
-	EXT_CLK_MIO50_OR_MIO51,
-	EXT_CLK_MIO0,
-	EXT_CLK_MIO1,
-	EXT_CLK_MIO2,
-	EXT_CLK_MIO3,
-	EXT_CLK_MIO4,
-	EXT_CLK_MIO5,
-	EXT_CLK_MIO6,
-	EXT_CLK_MIO7,
-	EXT_CLK_MIO8,
-	EXT_CLK_MIO9,
-	EXT_CLK_MIO10,
-	EXT_CLK_MIO11,
-	EXT_CLK_MIO12,
-	EXT_CLK_MIO13,
-	EXT_CLK_MIO14,
-	EXT_CLK_MIO15,
-	EXT_CLK_MIO16,
-	EXT_CLK_MIO17,
-	EXT_CLK_MIO18,
-	EXT_CLK_MIO19,
-	EXT_CLK_MIO20,
-	EXT_CLK_MIO21,
-	EXT_CLK_MIO22,
-	EXT_CLK_MIO23,
-	EXT_CLK_MIO24,
-	EXT_CLK_MIO25,
-	EXT_CLK_MIO26,
-	EXT_CLK_MIO27,
-	EXT_CLK_MIO28,
-	EXT_CLK_MIO29,
-	EXT_CLK_MIO30,
-	EXT_CLK_MIO31,
-	EXT_CLK_MIO32,
-	EXT_CLK_MIO33,
-	EXT_CLK_MIO34,
-	EXT_CLK_MIO35,
-	EXT_CLK_MIO36,
-	EXT_CLK_MIO37,
-	EXT_CLK_MIO38,
-	EXT_CLK_MIO39,
-	EXT_CLK_MIO40,
-	EXT_CLK_MIO41,
-	EXT_CLK_MIO42,
-	EXT_CLK_MIO43,
-	EXT_CLK_MIO44,
-	EXT_CLK_MIO45,
-	EXT_CLK_MIO46,
-	EXT_CLK_MIO47,
-	EXT_CLK_MIO48,
-	EXT_CLK_MIO49,
-	EXT_CLK_MIO50,
-	EXT_CLK_MIO51,
-	EXT_CLK_MIO52,
-	EXT_CLK_MIO53,
-	EXT_CLK_MIO54,
-	EXT_CLK_MIO55,
-	EXT_CLK_MIO56,
-	EXT_CLK_MIO57,
-	EXT_CLK_MIO58,
-	EXT_CLK_MIO59,
-	EXT_CLK_MIO60,
-	EXT_CLK_MIO61,
-	EXT_CLK_MIO62,
-	EXT_CLK_MIO63,
-	EXT_CLK_MIO64,
-	EXT_CLK_MIO65,
-	EXT_CLK_MIO66,
-	EXT_CLK_MIO67,
-	EXT_CLK_MIO68,
-	EXT_CLK_MIO69,
-	EXT_CLK_MIO70,
-	EXT_CLK_MIO71,
-	EXT_CLK_MIO72,
-	EXT_CLK_MIO73,
-	EXT_CLK_MIO74,
-	EXT_CLK_MIO75,
-	EXT_CLK_MIO76,
-	EXT_CLK_MIO77,
-	END_OF_CLKS,
+	EXT_CLK_VIDEO = (114U),
+	EXT_CLK_PSS_ALT_REF = (115U),
+	EXT_CLK_AUX_REF = (116U),
+	EXT_CLK_GT_CRX_REF = (117U),
+	EXT_CLK_SWDT0 = (118U),
+	EXT_CLK_SWDT1 = (119U),
+	EXT_CLK_GEM0_TX_EMIO = (120U),
+	EXT_CLK_GEM1_TX_EMIO = (121U),
+	EXT_CLK_GEM2_TX_EMIO = (122U),
+	EXT_CLK_GEM3_TX_EMIO = (123U),
+	EXT_CLK_GEM0_RX_EMIO = (124U),
+	EXT_CLK_GEM1_RX_EMIO = (125U),
+	EXT_CLK_GEM2_RX_EMIO = (126U),
+	EXT_CLK_GEM3_RX_EMIO = (127U),
+	EXT_CLK_MIO50_OR_MIO51 = (128U),
+	EXT_CLK_MIO0 = (129U),
+	EXT_CLK_MIO1 = (130U),
+	EXT_CLK_MIO2 = (131U),
+	EXT_CLK_MIO3 = (132U),
+	EXT_CLK_MIO4 = (133U),
+	EXT_CLK_MIO5 = (134U),
+	EXT_CLK_MIO6 = (135U),
+	EXT_CLK_MIO7 = (136U),
+	EXT_CLK_MIO8 = (137U),
+	EXT_CLK_MIO9 = (138U),
+	EXT_CLK_MIO10 = (139U),
+	EXT_CLK_MIO11 = (140U),
+	EXT_CLK_MIO12 = (141U),
+	EXT_CLK_MIO13 = (142U),
+	EXT_CLK_MIO14 = (143U),
+	EXT_CLK_MIO15 = (144U),
+	EXT_CLK_MIO16 = (145U),
+	EXT_CLK_MIO17 = (146U),
+	EXT_CLK_MIO18 = (147U),
+	EXT_CLK_MIO19 = (148U),
+	EXT_CLK_MIO20 = (149U),
+	EXT_CLK_MIO21 = (150U),
+	EXT_CLK_MIO22 = (151U),
+	EXT_CLK_MIO23 = (152U),
+	EXT_CLK_MIO24 = (153U),
+	EXT_CLK_MIO25 = (154U),
+	EXT_CLK_MIO26 = (155U),
+	EXT_CLK_MIO27 = (156U),
+	EXT_CLK_MIO28 = (157U),
+	EXT_CLK_MIO29 = (158U),
+	EXT_CLK_MIO30 = (159U),
+	EXT_CLK_MIO31 = (160U),
+	EXT_CLK_MIO32 = (161U),
+	EXT_CLK_MIO33 = (162U),
+	EXT_CLK_MIO34 = (163U),
+	EXT_CLK_MIO35 = (164U),
+	EXT_CLK_MIO36 = (165U),
+	EXT_CLK_MIO37 = (166U),
+	EXT_CLK_MIO38 = (167U),
+	EXT_CLK_MIO39 = (168U),
+	EXT_CLK_MIO40 = (169U),
+	EXT_CLK_MIO41 = (170U),
+	EXT_CLK_MIO42 = (171U),
+	EXT_CLK_MIO43 = (172U),
+	EXT_CLK_MIO44 = (173U),
+	EXT_CLK_MIO45 = (174U),
+	EXT_CLK_MIO46 = (175U),
+	EXT_CLK_MIO47 = (176U),
+	EXT_CLK_MIO48 = (177U),
+	EXT_CLK_MIO49 = (178U),
+	EXT_CLK_MIO50 = (179U),
+	EXT_CLK_MIO51 = (180U),
+	EXT_CLK_MIO52 = (181U),
+	EXT_CLK_MIO53 = (182U),
+	EXT_CLK_MIO54 = (183U),
+	EXT_CLK_MIO55 = (184U),
+	EXT_CLK_MIO56 = (185U),
+	EXT_CLK_MIO57 = (186U),
+	EXT_CLK_MIO58 = (187U),
+	EXT_CLK_MIO59 = (188U),
+	EXT_CLK_MIO60 = (189U),
+	EXT_CLK_MIO61 = (190U),
+	EXT_CLK_MIO62 = (191U),
+	EXT_CLK_MIO63 = (192U),
+	EXT_CLK_MIO64 = (193U),
+	EXT_CLK_MIO65 = (194U),
+	EXT_CLK_MIO66 = (195U),
+	EXT_CLK_MIO67 = (196U),
+	EXT_CLK_MIO68 = (197U),
+	EXT_CLK_MIO69 = (198U),
+	EXT_CLK_MIO70 = (199U),
+	EXT_CLK_MIO71 = (200U),
+	EXT_CLK_MIO72 = (201U),
+	EXT_CLK_MIO73 = (202U),
+	EXT_CLK_MIO74 = (203U),
+	EXT_CLK_MIO75 = (204U),
+	EXT_CLK_MIO76 = (205U),
+	EXT_CLK_MIO77 = (206U),
+	END_OF_CLKS = (207U),
 };
 
-#define CLK_MAX (unsigned int)(END_OF_CLKS)
+#define CLK_MAX END_OF_CLKS
 
 //CLock types
 #define CLK_TYPE_OUTPUT 0U