refactor(sgi): replace references to "SGI"/"sgi" for neoverse_rd
Currently, there are several reference to "SGI" or "sgi" in comments or
as macro prefix within the neoverse_rd directory. As part of the
migration to neoverse_rd, rename all occurences of "SGI/sgi" to
"Neoverse-RD" or the "NRD" prefix accordingly. All references in
comments are rephrased as "Neoverse RD platforms". References in code
are renamed as "NRD"/"nrd" accordingly.
Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Change-Id: Iec195427ff2bee565cb4a325a1a22892be95ae16
diff --git a/plat/arm/board/neoverse_rd/platform/rdn2/platform.mk b/plat/arm/board/neoverse_rd/platform/rdn2/platform.mk
index 3216813..12e7db4 100644
--- a/plat/arm/board/neoverse_rd/platform/rdn2/platform.mk
+++ b/plat/arm/board/neoverse_rd/platform/rdn2/platform.mk
@@ -34,12 +34,12 @@
PLAT_INCLUDES += -I${RDN2_BASE}/include/
-SGI_CPU_SOURCES := lib/cpus/aarch64/neoverse_n2.S \
+NRD_CPU_SOURCES := lib/cpus/aarch64/neoverse_n2.S \
lib/cpus/aarch64/neoverse_v2.S
PLAT_BL_COMMON_SOURCES += ${NRD_COMMON_BASE}/nrd_plat_v2.c
-BL1_SOURCES += ${SGI_CPU_SOURCES} \
+BL1_SOURCES += ${NRD_CPU_SOURCES} \
${RDN2_BASE}/rdn2_err.c
BL2_SOURCES += ${RDN2_BASE}/rdn2_plat.c \
@@ -50,7 +50,7 @@
plat/arm/common/arm_tzc400.c \
plat/arm/common/arm_nor_psci_mem_protect.c
-BL31_SOURCES += ${SGI_CPU_SOURCES} \
+BL31_SOURCES += ${NRD_CPU_SOURCES} \
${RDN2_BASE}/rdn2_plat.c \
${RDN2_BASE}/rdn2_topology.c \
drivers/cfi/v2m/v2m_flash.c \
diff --git a/plat/arm/board/neoverse_rd/platform/rdn2/rdn2_ras.c b/plat/arm/board/neoverse_rd/platform/rdn2/rdn2_ras.c
index d18f1c9..d046a1f 100644
--- a/plat/arm/board/neoverse_rd/platform/rdn2/rdn2_ras.c
+++ b/plat/arm/board/neoverse_rd/platform/rdn2/rdn2_ras.c
@@ -11,13 +11,13 @@
struct nrd_ras_ev_map plat_ras_map[] = {
/* Non Secure base RAM ECC CE interrupt */
- {SGI_SDEI_DS_EVENT_0, NS_RAM_ECC_CE_INT, SGI_RAS_INTR_TYPE_SPI},
+ {NRD_SDEI_DS_EVENT_0, NS_RAM_ECC_CE_INT, NRD_RAS_INTR_TYPE_SPI},
/* Non Secure base RAM ECC UE interrupt */
- {SGI_SDEI_DS_EVENT_0, NS_RAM_ECC_UE_INT, SGI_RAS_INTR_TYPE_SPI},
+ {NRD_SDEI_DS_EVENT_0, NS_RAM_ECC_UE_INT, NRD_RAS_INTR_TYPE_SPI},
/* CPU 1-bit ECC CE error interrupt */
- {SGI_SDEI_DS_EVENT_1, PLAT_CORE_FAULT_IRQ, SGI_RAS_INTR_TYPE_PPI}
+ {NRD_SDEI_DS_EVENT_1, PLAT_CORE_FAULT_IRQ, NRD_RAS_INTR_TYPE_PPI}
};
/* RAS error record list definition, used by the common RAS framework. */
diff --git a/plat/arm/board/neoverse_rd/platform/rdn2/rdn2_security.c b/plat/arm/board/neoverse_rd/platform/rdn2/rdn2_security.c
index 8ec8345..41172ea 100644
--- a/plat/arm/board/neoverse_rd/platform/rdn2/rdn2_security.c
+++ b/plat/arm/board/neoverse_rd/platform/rdn2/rdn2_security.c
@@ -25,20 +25,20 @@
static const arm_tzc_regions_info_t tzc_regions_mc[][NRD_CHIP_COUNT - 1] = {
{
/* TZC memory regions for second chip */
- SGI_PLAT_TZC_NS_REMOTE_REGIONS_DEF(1),
+ NRD_PLAT_TZC_NS_REMOTE_REGIONS_DEF(1),
{}
},
#if NRD_CHIP_COUNT > 2
{
/* TZC memory regions for third chip */
- SGI_PLAT_TZC_NS_REMOTE_REGIONS_DEF(2),
+ NRD_PLAT_TZC_NS_REMOTE_REGIONS_DEF(2),
{}
},
#endif
#if NRD_CHIP_COUNT > 3
{
/* TZC memory regions for fourth chip */
- SGI_PLAT_TZC_NS_REMOTE_REGIONS_DEF(3),
+ NRD_PLAT_TZC_NS_REMOTE_REGIONS_DEF(3),
{}
},
#endif