commit | 64e2ba73188728107a2948df45dc320edc16ed07 | [log] [tgz] |
---|---|---|
author | Jiafei Pan <Jiafei.Pan@nxp.com> | Mon Sep 27 12:18:41 2021 +0800 |
committer | Jiafei Pan <jiafei.pan@nxp.com> | Sat Oct 09 10:57:46 2021 +0200 |
tree | 257cda27a71df4744cab26ff0b97096fe1d290ee | |
parent | 6f85ef20a4abf20260dd4e92f6d4507d371b9253 [diff] |
feat(plat/nxp/common): add EESR register definition Add OCRAM bit mask to be used in OCRAM driver. Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Change-Id: If82542cc6c1c243d8f998b193954dd72312ee1a4
diff --git a/plat/nxp/common/include/default/ch_2/soc_default_helper_macros.h b/plat/nxp/common/include/default/ch_2/soc_default_helper_macros.h index 789b112..84f07e6 100644 --- a/plat/nxp/common/include/default/ch_2/soc_default_helper_macros.h +++ b/plat/nxp/common/include/default/ch_2/soc_default_helper_macros.h
@@ -56,6 +56,11 @@ #define RCPM_POWMGTCSR_OFFSET 0x130 #define RCPM_IPPDEXPCR0_OFFSET 0x140 #define RCPM_POWMGTCSR_LPM20_REQ 0x00100000 -#endif +#endif /* NXP_RCPM_ADDR */ + +#define DCFG_SBEESR2_ADDR 0x20140534 +#define DCFG_MBEESR2_ADDR 0x20140544 +/* SBEESR and MBEESR bit mask */ +#define OCRAM_EESR_MASK 0x00000060 #endif /* SOC_DEFAULT_HELPER_MACROS_H */
diff --git a/plat/nxp/common/include/default/ch_3_2/soc_default_helper_macros.h b/plat/nxp/common/include/default/ch_3_2/soc_default_helper_macros.h index 8de516e..1edd28d 100644 --- a/plat/nxp/common/include/default/ch_3_2/soc_default_helper_macros.h +++ b/plat/nxp/common/include/default/ch_3_2/soc_default_helper_macros.h
@@ -79,4 +79,9 @@ #define ENABLE_WUO 0x10 #endif /* NXP_CCN_ADDR */ +#define DCFG_SBEESR2_ADDR 0x00100534 +#define DCFG_MBEESR2_ADDR 0x00100544 +/* SBEESR and MBEESR bit mask */ +#define OCRAM_EESR_MASK 0x00000008 + #endif /* SOC_DEFAULT_HELPER_MACROS_H */