diff --git a/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h b/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h
index 9741d08..b6572ff 100644
--- a/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h
+++ b/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h
@@ -45,10 +45,6 @@
 
 /* declarations for NVG handler functions */
 uint64_t nvg_get_version(void);
-int32_t nvg_enable_power_perf_mode(void);
-int32_t nvg_disable_power_perf_mode(void);
-int32_t nvg_enable_power_saver_modes(void);
-int32_t nvg_disable_power_saver_modes(void);
 void nvg_set_wake_time(uint32_t wake_time);
 void nvg_update_cstate_info(uint32_t cluster, uint32_t ccplex,
 		uint32_t system, uint32_t wake_mask, uint8_t update_wake_mask);
@@ -57,19 +53,20 @@
 int32_t nvg_is_sc7_allowed(void);
 int32_t nvg_online_core(uint32_t core);
 int32_t nvg_update_ccplex_gsc(uint32_t gsc_idx);
-int32_t nvg_roc_clean_cache(void);
-int32_t nvg_roc_flush_cache(void);
 int32_t nvg_roc_clean_cache_trbits(void);
 int32_t nvg_enter_cstate(uint32_t state, uint32_t wake_time);
+int32_t nvg_roc_clean_cache_trbits(void);
+void nvg_enable_strict_checking_mode(void);
+void nvg_system_shutdown(void);
+void nvg_system_reboot(void);
+
+/* declarations for assembly functions */
 void nvg_set_request_data(uint64_t req, uint64_t data);
 void nvg_set_request(uint64_t req);
 uint64_t nvg_get_result(void);
 uint64_t nvg_cache_clean(void);
 uint64_t nvg_cache_clean_inval(void);
 uint64_t nvg_cache_inval_all(void);
-void nvg_enable_strict_checking_mode(void);
-void nvg_system_shutdown(void);
-void nvg_system_reboot(void);
 
 /* MCE helper functions */
 void mce_enable_strict_checking(void);
diff --git a/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c b/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c
index a095fdd..1012cdf 100644
--- a/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c
+++ b/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c
@@ -31,54 +31,6 @@
 }
 
 /*
- * Enable the perf per watt mode.
- *
- * NVGDATA[0]: SW(RW), 1 = enable perf per watt mode
- */
-int32_t nvg_enable_power_perf_mode(void)
-{
-	nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_POWER_PERF, 1U);
-
-	return 0;
-}
-
-/*
- * Disable the perf per watt mode.
- *
- * NVGDATA[0]: SW(RW), 0 = disable perf per watt mode
- */
-int32_t nvg_disable_power_perf_mode(void)
-{
-	nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_POWER_PERF, 0U);
-
-	return 0;
-}
-
-/*
- * Enable the battery saver mode.
- *
- * NVGDATA[2]: SW(RW), 1 = enable battery saver mode
- */
-int32_t nvg_enable_power_saver_modes(void)
-{
-	nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_POWER_MODES, 1U);
-
-	return 0;
-}
-
-/*
- * Disable the battery saver mode.
- *
- * NVGDATA[2]: SW(RW), 0 = disable battery saver mode
- */
-int32_t nvg_disable_power_saver_modes(void)
-{
-	nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_POWER_MODES, 0U);
-
-	return 0;
-}
-
-/*
  * Set the expected wake time in TSC ticks for the next low-power state the
  * core enters.
  *
@@ -198,48 +150,6 @@
 }
 
 /*
- * Cache clean operation for all CCPLEX caches.
- */
-int32_t nvg_roc_clean_cache(void)
-{
-	int32_t ret = 0;
-
-	/* check if cache flush through mts is supported */
-	if (((read_id_afr0_el1() >> ID_AFR0_EL1_CACHE_OPS_SHIFT) &
-			ID_AFR0_EL1_CACHE_OPS_MASK) == 1U) {
-		if (nvg_cache_clean() == 0U) {
-			ERROR("%s: failed\n", __func__);
-			ret = -ENODEV;
-		}
-	} else {
-		ret = -ENOTSUP;
-	}
-
-	return ret;
-}
-
-/*
- * Cache clean and invalidate operation for all CCPLEX caches.
- */
-int32_t nvg_roc_flush_cache(void)
-{
-	int32_t ret = 0;
-
-	/* check if cache flush through mts is supported */
-	if (((read_id_afr0_el1() >> ID_AFR0_EL1_CACHE_OPS_SHIFT) &
-			ID_AFR0_EL1_CACHE_OPS_MASK) == 1U) {
-		if (nvg_cache_clean_inval() == 0U) {
-			ERROR("%s: failed\n", __func__);
-			ret = -ENODEV;
-		}
-	} else {
-		ret = -ENOTSUP;
-	}
-
-	return ret;
-}
-
-/*
  * Cache clean and invalidate, clear TR-bit operation for all CCPLEX caches.
  */
 int32_t nvg_roc_clean_cache_trbits(void)