refactor(cpufeat): separate the EL2 and EL3 enablement code
Combining the EL2 and EL3 enablement code necessitates that it must be
called at el3_exit, which is the only place with enough context to make
the decision of what needs to be set.
Decouple them to allow them to be called from elsewhere.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I147764c42771e7d4100699ec8fae98dac0a505c0
diff --git a/include/lib/extensions/brbe.h b/include/lib/extensions/brbe.h
index 9ee2444..194efba 100644
--- a/include/lib/extensions/brbe.h
+++ b/include/lib/extensions/brbe.h
@@ -8,9 +8,9 @@
#define BRBE_H
#if ENABLE_BRBE_FOR_NS
-void brbe_enable(void);
+void brbe_init_el3(void);
#else
-static inline void brbe_enable(void)
+static inline void brbe_init_el3(void)
{
}
#endif /* ENABLE_BRBE_FOR_NS */
diff --git a/include/lib/extensions/mpam.h b/include/lib/extensions/mpam.h
index 4327278..e5438ce 100644
--- a/include/lib/extensions/mpam.h
+++ b/include/lib/extensions/mpam.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -10,11 +10,15 @@
#include <stdbool.h>
#if ENABLE_MPAM_FOR_LOWER_ELS
-void mpam_enable(bool el2_unused);
+void mpam_init_el3(void);
+void mpam_init_el2_unused(void);
#else
-static inline void mpam_enable(bool el2_unused)
+static inline void mpam_init_el3(void)
{
}
-#endif
+static inline void mpam_init_el2_unused(void)
+{
+}
+#endif /* ENABLE_MPAM_FOR_LOWER_ELS */
#endif /* MPAM_H */
diff --git a/include/lib/extensions/pmuv3.h b/include/lib/extensions/pmuv3.h
index 5d5d055..62fee7b 100644
--- a/include/lib/extensions/pmuv3.h
+++ b/include/lib/extensions/pmuv3.h
@@ -9,7 +9,7 @@
#include <context.h>
-void pmuv3_disable_el3(void);
+void pmuv3_init_el3(void);
#ifdef __aarch64__
void pmuv3_enable(cpu_context_t *ctx);
diff --git a/include/lib/extensions/sme.h b/include/lib/extensions/sme.h
index 0e9c4b9..dbefdfc 100644
--- a/include/lib/extensions/sme.h
+++ b/include/lib/extensions/sme.h
@@ -22,11 +22,19 @@
#if ENABLE_SME_FOR_NS
void sme_enable(cpu_context_t *context);
+void sme_init_el3(void);
+void sme_init_el2_unused(void);
void sme_disable(cpu_context_t *context);
#else
static inline void sme_enable(cpu_context_t *context)
{
}
+static inline void sme_init_el3(void)
+{
+}
+static inline void sme_init_el2_unused(void)
+{
+}
static inline void sme_disable(cpu_context_t *context)
{
}
diff --git a/include/lib/extensions/spe.h b/include/lib/extensions/spe.h
index 02fccae..7b39037 100644
--- a/include/lib/extensions/spe.h
+++ b/include/lib/extensions/spe.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -10,15 +10,19 @@
#include <stdbool.h>
#if ENABLE_SPE_FOR_NS
-void spe_enable(bool el2_unused);
+void spe_init_el3(void);
+void spe_init_el2_unused(void);
void spe_disable(void);
#else
-static inline void spe_enable(bool el2_unused)
+static inline void spe_init_el3(void)
{
}
+static inline void spe_init_el2_unused(void)
+{
+}
static inline void spe_disable(void)
{
}
-#endif
+#endif /* ENABLE_SPE_FOR_NS */
#endif /* SPE_H */
diff --git a/include/lib/extensions/sve.h b/include/lib/extensions/sve.h
index 1faed2d..fc76a16 100644
--- a/include/lib/extensions/sve.h
+++ b/include/lib/extensions/sve.h
@@ -11,11 +11,15 @@
#if (ENABLE_SME_FOR_NS || ENABLE_SVE_FOR_NS)
void sve_enable(cpu_context_t *context);
+void sve_init_el2_unused(void);
void sve_disable(cpu_context_t *context);
#else
static inline void sve_enable(cpu_context_t *context)
{
}
+static inline void sve_init_el2_unused(void)
+{
+}
static inline void sve_disable(cpu_context_t *context)
{
}
diff --git a/include/lib/extensions/sys_reg_trace.h b/include/lib/extensions/sys_reg_trace.h
index 5915c55..d9f7f1b 100644
--- a/include/lib/extensions/sys_reg_trace.h
+++ b/include/lib/extensions/sys_reg_trace.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -10,10 +10,12 @@
#include <context.h>
#if ENABLE_SYS_REG_TRACE_FOR_NS
+
#if __aarch64__
void sys_reg_trace_enable(cpu_context_t *context);
+void sys_reg_trace_init_el2_unused(void);
#else
-void sys_reg_trace_enable(void);
+void sys_reg_trace_init_el3(void);
#endif /* __aarch64__ */
#else /* !ENABLE_SYS_REG_TRACE_FOR_NS */
@@ -22,11 +24,18 @@
static inline void sys_reg_trace_enable(cpu_context_t *context)
{
}
+static inline void sys_reg_trace_disable(cpu_context_t *context)
+{
+}
+static inline void sys_reg_trace_init_el2_unused(void)
+{
+}
#else
-static inline void sys_reg_trace_enable(void)
+static inline void sys_reg_trace_init_el3(void)
{
}
#endif /* __aarch64__ */
+
#endif /* ENABLE_SYS_REG_TRACE_FOR_NS */
#endif /* SYS_REG_TRACE_H */
diff --git a/include/lib/extensions/trbe.h b/include/lib/extensions/trbe.h
index 861a4ad..0bed433 100644
--- a/include/lib/extensions/trbe.h
+++ b/include/lib/extensions/trbe.h
@@ -8,9 +8,13 @@
#define TRBE_H
#if ENABLE_TRBE_FOR_NS
-void trbe_enable(void);
+void trbe_init_el3(void);
+void trbe_init_el2_unused(void);
#else
-static inline void trbe_enable(void)
+static inline void trbe_init_el3(void)
+{
+}
+static inline void trbe_init_el2_unused(void)
{
}
#endif /* ENABLE_TRBE_FOR_NS */
diff --git a/include/lib/extensions/trf.h b/include/lib/extensions/trf.h
index 91a9615..1ac7cda 100644
--- a/include/lib/extensions/trf.h
+++ b/include/lib/extensions/trf.h
@@ -8,9 +8,13 @@
#define TRF_H
#if ENABLE_TRF_FOR_NS
-void trf_enable(void);
+void trf_init_el3(void);
+void trf_init_el2_unused(void);
#else
-static inline void trf_enable(void)
+static inline void trf_init_el3(void)
+{
+}
+static inline void trf_init_el2_unused(void)
{
}
#endif /* ENABLE_TRF_FOR_NS */
diff --git a/lib/el3_runtime/aarch32/context_mgmt.c b/lib/el3_runtime/aarch32/context_mgmt.c
index 6414aaa..b60b8e0 100644
--- a/lib/el3_runtime/aarch32/context_mgmt.c
+++ b/lib/el3_runtime/aarch32/context_mgmt.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -142,19 +142,19 @@
}
if (is_feat_sys_reg_trace_supported()) {
- sys_reg_trace_enable();
+ sys_reg_trace_init_el3();
}
if (is_feat_trf_supported()) {
- trf_enable();
+ trf_init_el3();
}
/*
* Also applies to PMU < v3. The PMU is only disabled for EL3 and Secure
* state execution. This does not affect lower NS ELs.
*/
- pmuv3_disable_el3();
-#endif
+ pmuv3_init_el3();
+#endif /* IMAGE_BL32 */
}
/*******************************************************************************
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index 4a6598a..b7d014a 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -505,54 +505,45 @@
static void manage_extensions_nonsecure_mixed(bool el2_unused, cpu_context_t *ctx)
{
#if IMAGE_BL31
- if (is_feat_spe_supported()) {
- spe_enable(el2_unused);
- }
-
if (is_feat_amu_supported()) {
amu_enable(el2_unused, ctx);
}
+#endif /* IMAGE_BL31 */
+}
- /* Enable SVE and FPU/SIMD */
- if (is_feat_sve_supported()) {
- sve_enable(ctx);
+/*******************************************************************************
+ * Enable architecture extensions for EL3 execution. This function only updates
+ * registers in-place which are expected to either never change or be
+ * overwritten by el3_exit.
+ ******************************************************************************/
+#if IMAGE_BL31
+void cm_manage_extensions_el3(void)
+{
+ if (is_feat_spe_supported()) {
+ spe_init_el3();
}
if (is_feat_sme_supported()) {
- sme_enable(ctx);
+ sme_init_el3();
}
if (is_feat_mpam_supported()) {
- mpam_enable(el2_unused);
+ mpam_init_el3();
}
if (is_feat_trbe_supported()) {
- trbe_enable();
+ trbe_init_el3();
}
if (is_feat_brbe_supported()) {
- brbe_enable();
+ brbe_init_el3();
}
- if (is_feat_sys_reg_trace_supported()) {
- sys_reg_trace_enable(ctx);
- }
-
if (is_feat_trf_supported()) {
- trf_enable();
+ trf_init_el3();
}
-#endif
-}
-/*******************************************************************************
- * Enable architecture extensions for EL3 execution. This function only updates
- * registers in-place which are expected to either never change or be
- * overwritten by el3_exit.
- ******************************************************************************/
-#if IMAGE_BL31
-void cm_manage_extensions_el3(void)
-{
- pmuv3_disable_el3();
+ pmuv3_init_el3();
}
#endif /* IMAGE_BL31 */
@@ -562,6 +553,19 @@
static void manage_extensions_nonsecure(cpu_context_t *ctx)
{
#if IMAGE_BL31
+ /* Enable SVE and FPU/SIMD */
+ if (is_feat_sve_supported()) {
+ sve_enable(ctx);
+ }
+
+ if (is_feat_sme_supported()) {
+ sme_enable(ctx);
+ }
+
+ if (is_feat_sys_reg_trace_supported()) {
+ sys_reg_trace_enable(ctx);
+ }
+
pmuv3_enable(ctx);
#endif /* IMAGE_BL31 */
}
@@ -573,7 +577,35 @@
static void manage_extensions_nonsecure_el2_unused(void)
{
#if IMAGE_BL31
+ if (is_feat_spe_supported()) {
+ spe_init_el2_unused();
+ }
+
+ if (is_feat_mpam_supported()) {
+ mpam_init_el2_unused();
+ }
+
+ if (is_feat_trbe_supported()) {
+ trbe_init_el2_unused();
+ }
+
+ if (is_feat_sys_reg_trace_supported()) {
+ sys_reg_trace_init_el2_unused();
+ }
+
+ if (is_feat_trf_supported()) {
+ trf_init_el2_unused();
+ }
+
pmuv3_init_el2_unused();
+
+ if (is_feat_sve_supported()) {
+ sve_init_el2_unused();
+ }
+
+ if (is_feat_sme_supported()) {
+ sme_init_el2_unused();
+ }
#endif /* IMAGE_BL31 */
}
@@ -606,6 +638,7 @@
* Enable SME, SVE, FPU/SIMD in secure context, secure manager
* must ensure SME, SVE, and FPU/SIMD context properly managed.
*/
+ sme_init_el3();
sme_enable(ctx);
} else {
/*
@@ -719,24 +752,8 @@
* Initialise CPTR_EL2 setting all fields rather than
* relying on the hw. All fields have architecturally
* UNKNOWN reset values.
- *
- * CPTR_EL2.TCPAC: Set to zero so that Non-secure EL1
- * accesses to the CPACR_EL1 or CPACR from both
- * Execution states do not trap to EL2.
- *
- * CPTR_EL2.TTA: Set to zero so that Non-secure System
- * register accesses to the trace registers from both
- * Execution states do not trap to EL2.
- * If PE trace unit System registers are not implemented
- * then this bit is reserved, and must be set to zero.
- *
- * CPTR_EL2.TFP: Set to zero so that Non-secure accesses
- * to SIMD and floating-point functionality from both
- * Execution states do not trap to EL2.
*/
- write_cptr_el2(CPTR_EL2_RESET_VAL &
- ~(CPTR_EL2_TCPAC_BIT | CPTR_EL2_TTA_BIT
- | CPTR_EL2_TFP_BIT));
+ write_cptr_el2(CPTR_EL2_RESET_VAL);
/*
* Initialise CNTHCTL_EL2. All fields are
@@ -787,16 +804,6 @@
* relying on hw. Some fields are architecturally
* UNKNOWN on reset.
*
- * MDCR_EL2.TTRF: Set to zero so that access to Trace
- * Filter Control register TRFCR_EL1 at EL1 is not
- * trapped to EL2. This bit is RES0 in versions of
- * the architecture earlier than ARMv8.4.
- *
- * MDCR_EL2.TPMS: Set to zero so that accesses to
- * Statistical Profiling control registers from EL1
- * do not trap to EL2. This bit is RES0 when SPE is
- * not implemented.
- *
* MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and
* EL1 System register accesses to the Debug ROM
* registers are not trapped to EL2.
@@ -810,16 +817,10 @@
*
* MDCR_EL2.TDE: Set to zero so that debug exceptions
* are not routed to EL2.
- *
- * MDCR_EL2.E2TB: Set to zero so that the trace Buffer
- * owning exception level is NS-EL1 and, tracing is
- * prohibited at NS-EL2. These bits are RES0 when
- * FEAT_TRBE is not implemented.
*/
- mdcr_el2 = ((MDCR_EL2_RESET_VAL) & ~(MDCR_EL2_TTRF |
- MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT |
- MDCR_EL2_TDA_BIT | MDCR_EL2_TDE_BIT |
- MDCR_EL2_E2TB(MDCR_EL2_E2TB_EL1)));
+ mdcr_el2 = ((MDCR_EL2_RESET_VAL) &
+ ~(MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT |
+ MDCR_EL2_TDA_BIT | MDCR_EL2_TDE_BIT));
write_mdcr_el2(mdcr_el2);
diff --git a/lib/extensions/brbe/brbe.c b/lib/extensions/brbe/brbe.c
index 329cf98..37bd834 100644
--- a/lib/extensions/brbe/brbe.c
+++ b/lib/extensions/brbe/brbe.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2022-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,8 +7,9 @@
#include <arch.h>
#include <arch_features.h>
#include <arch_helpers.h>
+#include <lib/extensions/brbe.h>
-void brbe_enable(void)
+void brbe_init_el3(void)
{
uint64_t val;
diff --git a/lib/extensions/mpam/mpam.c b/lib/extensions/mpam/mpam.c
index 62533fc..6462c97 100644
--- a/lib/extensions/mpam/mpam.c
+++ b/lib/extensions/mpam/mpam.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -11,7 +11,7 @@
#include <arch_helpers.h>
#include <lib/extensions/mpam.h>
-void mpam_enable(bool el2_unused)
+void mpam_init_el3(void)
{
/*
* Enable MPAM, and disable trapping to EL3 when lower ELs access their
@@ -19,15 +19,18 @@
*/
write_mpam3_el3(MPAM3_EL3_MPAMEN_BIT);
- /*
- * If EL2 is implemented but unused, disable trapping to EL2 when lower
- * ELs access their own MPAM registers.
- */
- if (el2_unused) {
- write_mpam2_el2(0ULL);
+}
+
+/*
+ * If EL2 is implemented but unused, disable trapping to EL2 when lower ELs
+ * access their own MPAM registers.
+ */
+void mpam_init_el2_unused(void)
+{
+ write_mpam2_el2(0ULL);
- if ((read_mpamidr_el1() & MPAMIDR_HAS_HCR_BIT) != 0U) {
- write_mpamhcr_el2(0ULL);
- }
+ if ((read_mpamidr_el1() & MPAMIDR_HAS_HCR_BIT) != 0U) {
+ write_mpamhcr_el2(0ULL);
}
+
}
diff --git a/lib/extensions/pmuv3/aarch32/pmuv3.c b/lib/extensions/pmuv3/aarch32/pmuv3.c
index fe4205e..effb7e0 100644
--- a/lib/extensions/pmuv3/aarch32/pmuv3.c
+++ b/lib/extensions/pmuv3/aarch32/pmuv3.c
@@ -29,7 +29,7 @@
* Applies to all PMU versions. Name is PMUv3 for compatibility with aarch64 and
* to not clash with platforms which reuse the PMU name
*/
-void pmuv3_disable_el3(void)
+void pmuv3_init_el3(void)
{
u_register_t sdcr = read_sdcr();
diff --git a/lib/extensions/pmuv3/aarch64/pmuv3.c b/lib/extensions/pmuv3/aarch64/pmuv3.c
index f83a5ee..fda71aa 100644
--- a/lib/extensions/pmuv3/aarch64/pmuv3.c
+++ b/lib/extensions/pmuv3/aarch64/pmuv3.c
@@ -48,7 +48,7 @@
return mdcr_el3;
}
-void pmuv3_disable_el3(void)
+void pmuv3_init_el3(void)
{
u_register_t mdcr_el3 = read_mdcr_el3();
diff --git a/lib/extensions/sme/sme.c b/lib/extensions/sme/sme.c
index 3423dba..d705b64 100644
--- a/lib/extensions/sme/sme.c
+++ b/lib/extensions/sme/sme.c
@@ -17,7 +17,6 @@
void sme_enable(cpu_context_t *context)
{
u_register_t reg;
- u_register_t cptr_el3;
el3_state_t *state;
/* Get the context state. */
@@ -32,9 +31,14 @@
reg = read_ctx_reg(state, CTX_SCR_EL3);
reg |= SCR_ENTP2_BIT;
write_ctx_reg(state, CTX_SCR_EL3, reg);
+}
- /* Set CPTR_EL3.ESM bit so we can write SMCR_EL3 without trapping. */
- cptr_el3 = read_cptr_el3();
+void sme_init_el3(void)
+{
+ u_register_t cptr_el3 = read_cptr_el3();
+ u_register_t smcr_el3;
+
+ /* Set CPTR_EL3.ESM bit so we can access SMCR_EL3 without trapping. */
write_cptr_el3(cptr_el3 | ESM_BIT);
isb();
@@ -43,11 +47,10 @@
* to be the least restrictive, then lower ELs can restrict as needed
* using SMCR_EL2 and SMCR_EL1.
*/
- reg = SMCR_ELX_LEN_MAX;
-
+ smcr_el3 = SMCR_ELX_LEN_MAX;
if (read_feat_sme_fa64_id_field() != 0U) {
VERBOSE("[SME] FA64 enabled\n");
- reg |= SMCR_ELX_FA64_BIT;
+ smcr_el3 |= SMCR_ELX_FA64_BIT;
}
/*
@@ -58,15 +61,24 @@
*/
if (is_feat_sme2_supported()) {
VERBOSE("SME2 enabled\n");
- reg |= SMCR_ELX_EZT0_BIT;
+ smcr_el3 |= SMCR_ELX_EZT0_BIT;
}
- write_smcr_el3(reg);
+ write_smcr_el3(smcr_el3);
/* Reset CPTR_EL3 value. */
write_cptr_el3(cptr_el3);
isb();
}
+void sme_init_el2_unused(void)
+{
+ /*
+ * CPTR_EL2.TCPAC: Set to zero so that Non-secure EL1 accesses to the
+ * CPACR_EL1 or CPACR from both Execution states do not trap to EL2.
+ */
+ write_cptr_el2(read_cptr_el2() & ~CPTR_EL2_TCPAC_BIT);
+}
+
void sme_disable(cpu_context_t *context)
{
u_register_t reg;
diff --git a/lib/extensions/spe/spe.c b/lib/extensions/spe/spe.c
index b1fe39f..236b102 100644
--- a/lib/extensions/spe/spe.c
+++ b/lib/extensions/spe/spe.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2022, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -21,25 +21,10 @@
__asm__ volatile("hint #17");
}
-void spe_enable(bool el2_unused)
+void spe_init_el3(void)
{
uint64_t v;
- if (el2_unused) {
- /*
- * MDCR_EL2.TPMS (ARM v8.2): Do not trap statistical
- * profiling controls to EL2.
- *
- * MDCR_EL2.E2PB (ARM v8.2): SPE enabled in Non-secure
- * state. Accesses to profiling buffer controls at
- * Non-secure EL1 are not trapped to EL2.
- */
- v = read_mdcr_el2();
- v &= ~MDCR_EL2_TPMS;
- v |= MDCR_EL2_E2PB(MDCR_EL2_E2PB_EL1);
- write_mdcr_el2(v);
- }
-
/*
* MDCR_EL2.NSPB (ARM v8.2): SPE enabled in Non-secure state
* and disabled in secure state. Accesses to SPE registers at
@@ -55,6 +40,24 @@
write_mdcr_el3(v);
}
+void spe_init_el2_unused(void)
+{
+ uint64_t v;
+
+ /*
+ * MDCR_EL2.TPMS (ARM v8.2): Do not trap statistical
+ * profiling controls to EL2.
+ *
+ * MDCR_EL2.E2PB (ARM v8.2): SPE enabled in Non-secure
+ * state. Accesses to profiling buffer controls at
+ * Non-secure EL1 are not trapped to EL2.
+ */
+ v = read_mdcr_el2();
+ v &= ~MDCR_EL2_TPMS;
+ v |= MDCR_EL2_E2PB(MDCR_EL2_E2PB_EL1);
+ write_mdcr_el2(v);
+}
+
void spe_disable(void)
{
uint64_t v;
diff --git a/lib/extensions/sve/sve.c b/lib/extensions/sve/sve.c
index f551ca7..eb4ac8d 100644
--- a/lib/extensions/sve/sve.c
+++ b/lib/extensions/sve/sve.c
@@ -37,6 +37,16 @@
(ZCR_EL3_LEN_MASK & CONVERT_SVE_LENGTH(SVE_VECTOR_LEN)));
}
+void sve_init_el2_unused(void)
+{
+ /*
+ * CPTR_EL2.TFP: Set to zero so that Non-secure accesses to Advanced
+ * SIMD and floating-point functionality from both Execution states do
+ * not trap to EL2.
+ */
+ write_cptr_el2(read_cptr_el2() & ~CPTR_EL2_TFP_BIT);
+}
+
void sve_disable(cpu_context_t *context)
{
u_register_t reg;
diff --git a/lib/extensions/sys_reg_trace/aarch32/sys_reg_trace.c b/lib/extensions/sys_reg_trace/aarch32/sys_reg_trace.c
index b3f44b7..6da504e 100644
--- a/lib/extensions/sys_reg_trace/aarch32/sys_reg_trace.c
+++ b/lib/extensions/sys_reg_trace/aarch32/sys_reg_trace.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -10,7 +10,7 @@
#include <arch_helpers.h>
#include <lib/extensions/sys_reg_trace.h>
-void sys_reg_trace_enable(void)
+void sys_reg_trace_init_el3(void)
{
uint32_t val;
diff --git a/lib/extensions/sys_reg_trace/aarch64/sys_reg_trace.c b/lib/extensions/sys_reg_trace/aarch64/sys_reg_trace.c
index e61cb90..4b57f67 100644
--- a/lib/extensions/sys_reg_trace/aarch64/sys_reg_trace.c
+++ b/lib/extensions/sys_reg_trace/aarch64/sys_reg_trace.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -24,3 +24,14 @@
val &= ~TTA_BIT;
write_ctx_reg(get_el3state_ctx(ctx), CTX_CPTR_EL3, val);
}
+
+void sys_reg_trace_init_el2_unused(void)
+{
+ /*
+ * CPTR_EL2.TTA: Set to zero so that Non-secure System register accesses
+ * to the trace registers from both Execution states do not trap to
+ * EL2. If PE trace unit System registers are not implemented then this
+ * bit is reserved, and must be set to zero.
+ */
+ write_cptr_el2(read_cptr_el2() & ~CPTR_EL2_TTA_BIT);
+}
diff --git a/lib/extensions/trbe/trbe.c b/lib/extensions/trbe/trbe.c
index fa139ca..461ea73 100644
--- a/lib/extensions/trbe/trbe.c
+++ b/lib/extensions/trbe/trbe.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -19,9 +19,9 @@
__asm__ volatile("hint #18");
}
-void trbe_enable(void)
+void trbe_init_el3(void)
{
- uint64_t val;
+ u_register_t val;
/*
* MDCR_EL3.NSTB = 0b11
@@ -34,6 +34,17 @@
write_mdcr_el3(val);
}
+void trbe_init_el2_unused(void)
+{
+ /*
+ * MDCR_EL2.E2TB: Set to zero so that the trace Buffer
+ * owning exception level is NS-EL1 and, tracing is
+ * prohibited at NS-EL2. These bits are RES0 when
+ * FEAT_TRBE is not implemented.
+ */
+ write_mdcr_el2(read_mdcr_el2() & ~MDCR_EL2_E2TB(MDCR_EL2_E2TB_EL1));
+}
+
static void *trbe_drain_trace_buffers_hook(const void *arg __unused)
{
if (is_feat_trbe_supported()) {
diff --git a/lib/extensions/trf/aarch32/trf.c b/lib/extensions/trf/aarch32/trf.c
index 0c63efa..e13b4db 100644
--- a/lib/extensions/trf/aarch32/trf.c
+++ b/lib/extensions/trf/aarch32/trf.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -10,7 +10,7 @@
#include <arch_helpers.h>
#include <lib/extensions/trf.h>
-void trf_enable(void)
+void trf_init_el3(void)
{
uint32_t val;
diff --git a/lib/extensions/trf/aarch64/trf.c b/lib/extensions/trf/aarch64/trf.c
index 941692b..f681b28 100644
--- a/lib/extensions/trf/aarch64/trf.c
+++ b/lib/extensions/trf/aarch64/trf.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -9,9 +9,9 @@
#include <arch_helpers.h>
#include <lib/extensions/trf.h>
-void trf_enable(void)
+void trf_init_el3(void)
{
- uint64_t val;
+ u_register_t val;
/*
* MDCR_EL3.TTRF = b0
@@ -22,3 +22,15 @@
val &= ~MDCR_TTRF_BIT;
write_mdcr_el3(val);
}
+
+void trf_init_el2_unused(void)
+{
+ /*
+ * MDCR_EL2.TTRF: Set to zero so that access to Trace
+ * Filter Control register TRFCR_EL1 at EL1 is not
+ * trapped to EL2. This bit is RES0 in versions of
+ * the architecture earlier than ARMv8.4.
+ *
+ */
+ write_mdcr_el2(read_mdcr_el2() & ~MDCR_EL2_TTRF);
+}