feat(qemu-sbsa): configure GPT based on system RAM
The amount of memory supported by the SBSA platform is dynamic
and dependent on user input. Since the configuration of the GPT
needs to reflect the system memory, QEMU_PAS_NS0 needs to be set
based on the information found in the device tree.
Change-Id: I5d1411ac00020b7b38a652ba2904c8a70fa64d18
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
diff --git a/plat/qemu/common/qemu_bl31_setup.c b/plat/qemu/common/qemu_bl31_setup.c
index c047640..e502e7b 100644
--- a/plat/qemu/common/qemu_bl31_setup.c
+++ b/plat/qemu/common/qemu_bl31_setup.c
@@ -12,8 +12,12 @@
#include <lib/transfer_list.h>
#include <plat/common/platform.h>
#if ENABLE_RME
+#ifdef PLAT_qemu
#include <qemu_pas_def.h>
-#endif
+#elif PLAT_qemu_sbsa
+#include <qemu_sbsa_pas_def.h>
+#endif /* PLAT_qemu */
+#endif /* ENABLE_RME */
#ifdef PLAT_qemu_sbsa
#include <sbsa_platform.h>
#endif
@@ -117,21 +121,65 @@
}
#if ENABLE_RME
-static void bl31_plat_gpt_setup(void)
+#if PLAT_qemu
+/*
+ * The GPT library might modify the gpt regions structure to optimize
+ * the layout, so the array cannot be constant.
+ */
+static pas_region_t pas_regions[] = {
+ QEMU_PAS_ROOT,
+ QEMU_PAS_SECURE,
+ QEMU_PAS_GPTS,
+ QEMU_PAS_NS0,
+ QEMU_PAS_REALM,
+ QEMU_PAS_NS1,
+};
+
+static inline void bl31_adjust_pas_regions(void) {}
+#elif PLAT_qemu_sbsa
+/*
+ * The GPT library might modify the gpt regions structure to optimize
+ * the layout, so the array cannot be constant.
+ */
+static pas_region_t pas_regions[] = {
+ QEMU_PAS_ROOT,
+ QEMU_PAS_SECURE,
+ QEMU_PAS_GPTS,
+ QEMU_PAS_REALM,
+ QEMU_PAS_NS0,
+};
+
+static void bl31_adjust_pas_regions(void)
{
+ uint64_t base_addr = 0, total_size = 0;
+ struct platform_memory_data data;
+ uint32_t node;
+
/*
- * The GPT library might modify the gpt regions structure to optimize
- * the layout, so the array cannot be constant.
+ * The amount of memory supported by the SBSA platform is dynamic
+ * and dependent on user input. Since the configuration of the GPT
+ * needs to reflect the system memory, QEMU_PAS_NS0 needs to be set
+ * based on the information found in the device tree.
*/
- pas_region_t pas_regions[] = {
- QEMU_PAS_ROOT,
- QEMU_PAS_SECURE,
- QEMU_PAS_GPTS,
- QEMU_PAS_NS0,
- QEMU_PAS_REALM,
- QEMU_PAS_NS1,
- };
+ for (node = 0; node < sbsa_platform_num_memnodes(); node++) {
+ data = sbsa_platform_memory_node(node);
+
+ if (data.nodeid == 0) {
+ base_addr = data.addr_base;
+ }
+
+ total_size += data.addr_size;
+ }
+
+ /* Index '4' correspond to QEMU_PAS_NS0, see pas_regions[] above */
+ pas_regions[4].base_pa = base_addr;
+ pas_regions[4].size = total_size;
+}
+#endif /* PLAT_qemu */
+
+static void bl31_plat_gpt_setup(void)
+{
/*
* Initialize entire protected space to GPT_GPI_ANY. With each L0 entry
* covering 1GB (currently the only supported option), then covering
@@ -145,6 +193,8 @@
panic();
}
+ bl31_adjust_pas_regions();
+
/* Carve out defined PAS ranges. */
if (gpt_init_pas_l1_tables(GPCCR_PGS_4K,
PLAT_QEMU_L1_GPT_BASE,