diff --git a/docs/design/interrupt-framework-design.rst b/docs/design/interrupt-framework-design.rst
index f68cf21..4a864f9 100644
--- a/docs/design/interrupt-framework-design.rst
+++ b/docs/design/interrupt-framework-design.rst
@@ -381,8 +381,8 @@
                                   uint32_t value);
 
 ``cm_get_scr_el3()`` returns the value of the ``SCR_EL3`` register for the specified
-security state of the current CPU. ``cm_write_scr_el3()`` writes a ``0`` or ``1`` to
-the bit specified by ``bit_pos``. ``register_interrupt_type_handler()`` invokes
+security state of the current CPU. ``cm_write_scr_el3_bit()`` writes a ``0`` or ``1``
+to the bit specified by ``bit_pos``. ``register_interrupt_type_handler()`` invokes
 ``set_routing_model()`` API which programs the ``SCR_EL3`` according to the routing
 model using the ``cm_get_scr_el3()`` and ``cm_write_scr_el3_bit()`` APIs.
 
diff --git a/drivers/intel/soc/stratix10/io/s10_memmap_qspi.c b/drivers/intel/soc/stratix10/io/s10_memmap_qspi.c
index 7d7d55f..a0fc034 100644
--- a/drivers/intel/soc/stratix10/io/s10_memmap_qspi.c
+++ b/drivers/intel/soc/stratix10/io/s10_memmap_qspi.c
@@ -15,7 +15,7 @@
 #include <drivers/io/io_storage.h>
 #include <lib/utils.h>
 
-#include "drivers/qspi/cadence_qspi.h"
+#include "qspi/cadence_qspi.h"
 
 /* As we need to be able to keep state for seek, only one file can be open
  * at a time. Make this a structure and point to the entity->info. When we
diff --git a/drivers/renesas/rcar/pfc/D3/pfc_init_d3.c b/drivers/renesas/rcar/pfc/D3/pfc_init_d3.c
new file mode 100644
index 0000000..7e9bde9
--- /dev/null
+++ b/drivers/renesas/rcar/pfc/D3/pfc_init_d3.c
@@ -0,0 +1,667 @@
+/*
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+#include <lib/mmio.h>
+#include "pfc_init_d3.h"
+#include "rcar_def.h"
+#include "../pfc_regs.h"
+
+/* PFC */
+#define GPSR0_D15		BIT(15)
+#define GPSR0_D14		BIT(14)
+#define GPSR0_D13		BIT(13)
+#define GPSR0_D12		BIT(12)
+#define GPSR0_D11		BIT(11)
+#define GPSR0_D10		BIT(10)
+#define GPSR0_D9		BIT(9)
+#define GPSR0_D8		BIT(8)
+#define GPSR0_D7		BIT(7)
+#define GPSR0_D6		BIT(6)
+#define GPSR0_D5		BIT(5)
+#define GPSR0_D4		BIT(4)
+#define GPSR0_D3		BIT(3)
+#define GPSR0_D2		BIT(2)
+#define GPSR0_D1		BIT(1)
+#define GPSR0_D0		BIT(0)
+#define GPSR1_CLKOUT		BIT(28)
+#define GPSR1_EX_WAIT0_A	BIT(27)
+#define GPSR1_WE1		BIT(26)
+#define GPSR1_WE0		BIT(25)
+#define GPSR1_RD_WR		BIT(24)
+#define GPSR1_RD		BIT(23)
+#define GPSR1_BS		BIT(22)
+#define GPSR1_CS1_A26		BIT(21)
+#define GPSR1_CS0		BIT(20)
+#define GPSR1_A19		BIT(19)
+#define GPSR1_A18		BIT(18)
+#define GPSR1_A17		BIT(17)
+#define GPSR1_A16		BIT(16)
+#define GPSR1_A15		BIT(15)
+#define GPSR1_A14		BIT(14)
+#define GPSR1_A13		BIT(13)
+#define GPSR1_A12		BIT(12)
+#define GPSR1_A11		BIT(11)
+#define GPSR1_A10		BIT(10)
+#define GPSR1_A9		BIT(9)
+#define GPSR1_A8		BIT(8)
+#define GPSR1_A7		BIT(7)
+#define GPSR1_A6		BIT(6)
+#define GPSR1_A5		BIT(5)
+#define GPSR1_A4		BIT(4)
+#define GPSR1_A3		BIT(3)
+#define GPSR1_A2		BIT(2)
+#define GPSR1_A1		BIT(1)
+#define GPSR1_A0		BIT(0)
+#define GPSR2_AVB_AVTP_CAPTURE_A	BIT(14)
+#define GPSR2_AVB_AVTP_MATCH_A	BIT(13)
+#define GPSR2_AVB_LINK		BIT(12)
+#define GPSR2_AVB_PHY_INT	BIT(11)
+#define GPSR2_AVB_MAGIC		BIT(10)
+#define GPSR2_AVB_MDC		BIT(9)
+#define GPSR2_PWM2_A		BIT(8)
+#define GPSR2_PWM1_A		BIT(7)
+#define GPSR2_PWM0		BIT(6)
+#define GPSR2_IRQ5		BIT(5)
+#define GPSR2_IRQ4		BIT(4)
+#define GPSR2_IRQ3		BIT(3)
+#define GPSR2_IRQ2		BIT(2)
+#define GPSR2_IRQ1		BIT(1)
+#define GPSR2_IRQ0		BIT(0)
+#define GPSR3_SD1_WP		BIT(15)
+#define GPSR3_SD1_CD		BIT(14)
+#define GPSR3_SD0_WP		BIT(13)
+#define GPSR3_SD0_CD		BIT(12)
+#define GPSR3_SD1_DAT3		BIT(11)
+#define GPSR3_SD1_DAT2		BIT(10)
+#define GPSR3_SD1_DAT1		BIT(9)
+#define GPSR3_SD1_DAT0		BIT(8)
+#define GPSR3_SD1_CMD		BIT(7)
+#define GPSR3_SD1_CLK		BIT(6)
+#define GPSR3_SD0_DAT3		BIT(5)
+#define GPSR3_SD0_DAT2		BIT(4)
+#define GPSR3_SD0_DAT1		BIT(3)
+#define GPSR3_SD0_DAT0		BIT(2)
+#define GPSR3_SD0_CMD		BIT(1)
+#define GPSR3_SD0_CLK		BIT(0)
+#define GPSR4_SD3_DS		BIT(17)
+#define GPSR4_SD3_DAT7		BIT(16)
+#define GPSR4_SD3_DAT6		BIT(15)
+#define GPSR4_SD3_DAT5		BIT(14)
+#define GPSR4_SD3_DAT4		BIT(13)
+#define GPSR4_SD3_DAT3		BIT(12)
+#define GPSR4_SD3_DAT2		BIT(11)
+#define GPSR4_SD3_DAT1		BIT(10)
+#define GPSR4_SD3_DAT0		BIT(9)
+#define GPSR4_SD3_CMD		BIT(8)
+#define GPSR4_SD3_CLK		BIT(7)
+#define GPSR4_SD2_DS		BIT(6)
+#define GPSR4_SD2_DAT3		BIT(5)
+#define GPSR4_SD2_DAT2		BIT(4)
+#define GPSR4_SD2_DAT1		BIT(3)
+#define GPSR4_SD2_DAT0		BIT(2)
+#define GPSR4_SD2_CMD		BIT(1)
+#define GPSR4_SD2_CLK		BIT(0)
+#define GPSR5_MLB_DAT		BIT(25)
+#define GPSR5_MLB_SIG		BIT(24)
+#define GPSR5_MLB_CLK		BIT(23)
+#define GPSR5_MSIOF0_RXD	BIT(22)
+#define GPSR5_MSIOF0_SS2	BIT(21)
+#define GPSR5_MSIOF0_TXD	BIT(20)
+#define GPSR5_MSIOF0_SS1	BIT(19)
+#define GPSR5_MSIOF0_SYNC	BIT(18)
+#define GPSR5_MSIOF0_SCK	BIT(17)
+#define GPSR5_HRTS0		BIT(16)
+#define GPSR5_HCTS0		BIT(15)
+#define GPSR5_HTX0		BIT(14)
+#define GPSR5_HRX0		BIT(13)
+#define GPSR5_HSCK0		BIT(12)
+#define GPSR5_RX2_A		BIT(11)
+#define GPSR5_TX2_A		BIT(10)
+#define GPSR5_SCK2		BIT(9)
+#define GPSR5_RTS1_TANS		BIT(8)
+#define GPSR5_CTS1		BIT(7)
+#define GPSR5_TX1_A		BIT(6)
+#define GPSR5_RX1_A		BIT(5)
+#define GPSR5_RTS0_TANS		BIT(4)
+#define GPSR5_CTS0		BIT(3)
+#define GPSR5_TX0		BIT(2)
+#define GPSR5_RX0		BIT(1)
+#define GPSR5_SCK0		BIT(0)
+#define GPSR6_USB31_OVC		BIT(31)
+#define GPSR6_USB31_PWEN	BIT(30)
+#define GPSR6_USB30_OVC		BIT(29)
+#define GPSR6_USB30_PWEN	BIT(28)
+#define GPSR6_USB1_OVC		BIT(27)
+#define GPSR6_USB1_PWEN		BIT(26)
+#define GPSR6_USB0_OVC		BIT(25)
+#define GPSR6_USB0_PWEN		BIT(24)
+#define GPSR6_AUDIO_CLKB_B	BIT(23)
+#define GPSR6_AUDIO_CLKA_A	BIT(22)
+#define GPSR6_SSI_SDATA9_A	BIT(21)
+#define GPSR6_SSI_SDATA8	BIT(20)
+#define GPSR6_SSI_SDATA7	BIT(19)
+#define GPSR6_SSI_WS78		BIT(18)
+#define GPSR6_SSI_SCK78		BIT(17)
+#define GPSR6_SSI_SDATA6	BIT(16)
+#define GPSR6_SSI_WS6		BIT(15)
+#define GPSR6_SSI_SCK6		BIT(14)
+#define GPSR6_SSI_SDATA5	BIT(13)
+#define GPSR6_SSI_WS5		BIT(12)
+#define GPSR6_SSI_SCK5		BIT(11)
+#define GPSR6_SSI_SDATA4	BIT(10)
+#define GPSR6_SSI_WS4		BIT(9)
+#define GPSR6_SSI_SCK4		BIT(8)
+#define GPSR6_SSI_SDATA3	BIT(7)
+#define GPSR6_SSI_WS34		BIT(6)
+#define GPSR6_SSI_SCK34		BIT(5)
+#define GPSR6_SSI_SDATA2_A	BIT(4)
+#define GPSR6_SSI_SDATA1_A	BIT(3)
+#define GPSR6_SSI_SDATA0	BIT(2)
+#define GPSR6_SSI_WS0129	BIT(1)
+#define GPSR6_SSI_SCK0129	BIT(0)
+#define GPSR7_HDMI1_CEC		BIT(3)
+#define GPSR7_HDMI0_CEC		BIT(2)
+#define GPSR7_AVS2		BIT(1)
+#define GPSR7_AVS1		BIT(0)
+
+#define IPSR_28_FUNC(x)		((uint32_t)(x) << 28U)
+#define IPSR_24_FUNC(x)		((uint32_t)(x) << 24U)
+#define IPSR_20_FUNC(x)		((uint32_t)(x) << 20U)
+#define IPSR_16_FUNC(x)		((uint32_t)(x) << 16U)
+#define IPSR_12_FUNC(x)		((uint32_t)(x) << 12U)
+#define IPSR_8_FUNC(x)		((uint32_t)(x) << 8U)
+#define IPSR_4_FUNC(x)		((uint32_t)(x) << 4U)
+#define IPSR_0_FUNC(x)		((uint32_t)(x) << 0U)
+
+#define POC_SD3_DS_33V		BIT(29)
+#define POC_SD3_DAT7_33V	BIT(28)
+#define POC_SD3_DAT6_33V	BIT(27)
+#define POC_SD3_DAT5_33V	BIT(26)
+#define POC_SD3_DAT4_33V	BIT(25)
+#define POC_SD3_DAT3_33V	BIT(24)
+#define POC_SD3_DAT2_33V	BIT(23)
+#define POC_SD3_DAT1_33V	BIT(22)
+#define POC_SD3_DAT0_33V	BIT(21)
+#define POC_SD3_CMD_33V		BIT(20)
+#define POC_SD3_CLK_33V		BIT(19)
+#define POC_SD2_DS_33V		BIT(18)
+#define POC_SD2_DAT3_33V	BIT(17)
+#define POC_SD2_DAT2_33V	BIT(16)
+#define POC_SD2_DAT1_33V	BIT(15)
+#define POC_SD2_DAT0_33V	BIT(14)
+#define POC_SD2_CMD_33V		BIT(13)
+#define POC_SD2_CLK_33V		BIT(12)
+#define POC_SD1_DAT3_33V	BIT(11)
+#define POC_SD1_DAT2_33V	BIT(10)
+#define POC_SD1_DAT1_33V	BIT(9)
+#define POC_SD1_DAT0_33V	BIT(8)
+#define POC_SD1_CMD_33V		BIT(7)
+#define POC_SD1_CLK_33V		BIT(6)
+#define POC_SD0_DAT3_33V	BIT(5)
+#define POC_SD0_DAT2_33V	BIT(4)
+#define POC_SD0_DAT1_33V	BIT(3)
+#define POC_SD0_DAT0_33V	BIT(2)
+#define POC_SD0_CMD_33V		BIT(1)
+#define POC_SD0_CLK_33V		BIT(0)
+
+#define DRVCTRL0_MASK		(0xCCCCCCCCU)
+#define DRVCTRL1_MASK		(0xCCCCCCC8U)
+#define DRVCTRL2_MASK		(0x88888888U)
+#define DRVCTRL3_MASK		(0x88888888U)
+#define DRVCTRL4_MASK		(0x88888888U)
+#define DRVCTRL5_MASK		(0x88888888U)
+#define DRVCTRL6_MASK		(0x88888888U)
+#define DRVCTRL7_MASK		(0x88888888U)
+#define DRVCTRL8_MASK		(0x88888888U)
+#define DRVCTRL9_MASK		(0x88888888U)
+#define DRVCTRL10_MASK		(0x88888888U)
+#define DRVCTRL11_MASK		(0x888888CCU)
+#define DRVCTRL12_MASK		(0xCCCFFFCFU)
+#define DRVCTRL13_MASK		(0xCC888888U)
+#define DRVCTRL14_MASK		(0x88888888U)
+#define DRVCTRL15_MASK		(0x88888888U)
+#define DRVCTRL16_MASK		(0x88888888U)
+#define DRVCTRL17_MASK		(0x88888888U)
+#define DRVCTRL18_MASK		(0x88888888U)
+#define DRVCTRL19_MASK		(0x88888888U)
+#define DRVCTRL20_MASK		(0x88888888U)
+#define DRVCTRL21_MASK		(0x88888888U)
+#define DRVCTRL22_MASK		(0x88888888U)
+#define DRVCTRL23_MASK		(0x88888888U)
+#define DRVCTRL24_MASK		(0x8888888FU)
+
+#define DRVCTRL0_QSPI0_SPCLK(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL0_QSPI0_MOSI_IO0(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL0_QSPI0_MISO_IO1(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL0_QSPI0_IO2(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL0_QSPI0_IO3(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL0_QSPI0_SSL(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL0_QSPI1_SPCLK(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL0_QSPI1_MOSI_IO0(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL1_QSPI1_MISO_IO1(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL1_QSPI1_IO2(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL1_QSPI1_IO3(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL1_QSPI1_SS(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL1_RPC_INT(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL1_RPC_WP(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL1_RPC_RESET(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL1_AVB_RX_CTL(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL2_AVB_RXC(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL2_AVB_RD0(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL2_AVB_RD1(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL2_AVB_RD2(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL2_AVB_RD3(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL2_AVB_TX_CTL(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL2_AVB_TXC(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL2_AVB_TD0(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL3_AVB_TD1(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL3_AVB_TD2(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL3_AVB_TD3(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL3_AVB_TXCREFCLK(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL3_AVB_MDIO(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL3_AVB_MDC(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL3_AVB_MAGIC(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL3_AVB_PHY_INT(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL4_AVB_LINK(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL4_AVB_AVTP_MATCH(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL4_AVB_AVTP_CAPTURE(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL4_IRQ0(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL4_IRQ1(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL4_IRQ2(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL4_IRQ3(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL4_IRQ4(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL5_IRQ5(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL5_PWM0(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL5_PWM1(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL5_PWM2(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL5_A0(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL5_A1(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL5_A2(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL5_A3(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL6_A4(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL6_A5(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL6_A6(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL6_A7(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL6_A8(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL6_A9(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL6_A10(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL6_A11(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL7_A12(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL7_A13(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL7_A14(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL7_A15(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL7_A16(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL7_A17(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL7_A18(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL7_A19(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL8_CLKOUT(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL8_CS0(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL8_CS1_A2(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL8_BS(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL8_RD(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL8_RD_W(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL8_WE0(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL8_WE1(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL9_EX_WAIT0(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL9_PRESETOU(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL9_D0(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL9_D1(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL9_D2(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL9_D3(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL9_D4(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL9_D5(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL10_D6(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL10_D7(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL10_D8(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL10_D9(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL10_D10(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL10_D11(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL10_D12(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL10_D13(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL11_D14(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL11_D15(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL11_AVS1(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL11_AVS2(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL11_HDMI0_CEC(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL11_HDMI1_CEC(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL11_DU_DOTCLKIN0(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL11_DU_DOTCLKIN1(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL12_DU_DOTCLKIN2(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL12_DU_DOTCLKIN3(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL12_DU_FSCLKST(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL12_DU_TMS(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL13_TDO(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL13_ASEBRK(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL13_SD0_CLK(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL13_SD0_CMD(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL13_SD0_DAT0(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL13_SD0_DAT1(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL13_SD0_DAT2(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL13_SD0_DAT3(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL14_SD1_CLK(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL14_SD1_CMD(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL14_SD1_DAT0(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL14_SD1_DAT1(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL14_SD1_DAT2(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL14_SD1_DAT3(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL14_SD2_CLK(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL14_SD2_CMD(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL15_SD2_DAT0(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL15_SD2_DAT1(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL15_SD2_DAT2(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL15_SD2_DAT3(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL15_SD2_DS(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL15_SD3_CLK(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL15_SD3_CMD(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL15_SD3_DAT0(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL16_SD3_DAT1(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL16_SD3_DAT2(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL16_SD3_DAT3(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL16_SD3_DAT4(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL16_SD3_DAT5(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL16_SD3_DAT6(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL16_SD3_DAT7(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL16_SD3_DS(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL17_SD0_CD(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL17_SD0_WP(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL17_SD1_CD(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL17_SD1_WP(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL17_SCK0(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL17_RX0(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL17_TX0(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL17_CTS0(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL18_RTS0_TANS(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL18_RX1(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL18_TX1(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL18_CTS1(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL18_RTS1_TANS(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL18_SCK2(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL18_TX2(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL18_RX2(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL19_HSCK0(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL19_HRX0(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL19_HTX0(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL19_HCTS0(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL19_HRTS0(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL19_MSIOF0_SCK(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL19_MSIOF0_SYNC(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL19_MSIOF0_SS1(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL20_MSIOF0_TXD(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL20_MSIOF0_SS2(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL20_MSIOF0_RXD(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL20_MLB_CLK(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL20_MLB_SIG(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL20_MLB_DAT(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL20_MLB_REF(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL20_SSI_SCK0129(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL21_SSI_WS0129(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL21_SSI_SDATA0(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL21_SSI_SDATA1(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL21_SSI_SDATA2(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL21_SSI_SCK34(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL21_SSI_WS34(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL21_SSI_SDATA3(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL21_SSI_SCK4(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL22_SSI_WS4(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL22_SSI_SDATA4(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL22_SSI_SCK5(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL22_SSI_WS5(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL22_SSI_SDATA5(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL22_SSI_SCK6(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL22_SSI_WS6(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL22_SSI_SDATA6(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL23_SSI_SCK78(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL23_SSI_WS78(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL23_SSI_SDATA7(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL23_SSI_SDATA8(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL23_SSI_SDATA9(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL23_AUDIO_CLKA(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL23_AUDIO_CLKB(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL23_USB0_PWEN(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL24_USB0_OVC(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL24_USB1_PWEN(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL24_USB1_OVC(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL24_USB30_PWEN(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL24_USB30_OVC(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL24_USB31_PWEN(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL24_USB31_OVC(x)	((uint32_t)(x) << 4U)
+
+#define MOD_SEL0_MSIOF3_A	((uint32_t)0U << 29U)
+#define MOD_SEL0_MSIOF3_B	((uint32_t)1U << 29U)
+#define MOD_SEL0_MSIOF3_C	((uint32_t)2U << 29U)
+#define MOD_SEL0_MSIOF3_D	((uint32_t)3U << 29U)
+#define MOD_SEL0_MSIOF3_E	((uint32_t)4U << 29U)
+#define MOD_SEL0_MSIOF2_A	((uint32_t)0U << 27U)
+#define MOD_SEL0_MSIOF2_B	((uint32_t)1U << 27U)
+#define MOD_SEL0_MSIOF2_C	((uint32_t)2U << 27U)
+#define MOD_SEL0_MSIOF2_D	((uint32_t)3U << 27U)
+#define MOD_SEL0_MSIOF1_A	((uint32_t)0U << 24U)
+#define MOD_SEL0_MSIOF1_B	((uint32_t)1U << 24U)
+#define MOD_SEL0_MSIOF1_C	((uint32_t)2U << 24U)
+#define MOD_SEL0_MSIOF1_D	((uint32_t)3U << 24U)
+#define MOD_SEL0_MSIOF1_E	((uint32_t)4U << 24U)
+#define MOD_SEL0_MSIOF1_F	((uint32_t)5U << 24U)
+#define MOD_SEL0_MSIOF1_G	((uint32_t)6U << 24U)
+#define MOD_SEL0_LBSC_A		((uint32_t)0U << 23U)
+#define MOD_SEL0_LBSC_B		((uint32_t)1U << 23U)
+#define MOD_SEL0_IEBUS_A	((uint32_t)0U << 22U)
+#define MOD_SEL0_IEBUS_B	((uint32_t)1U << 22U)
+#define MOD_SEL0_I2C2_A		((uint32_t)0U << 21U)
+#define MOD_SEL0_I2C2_B		((uint32_t)1U << 21U)
+#define MOD_SEL0_I2C1_A		((uint32_t)0U << 20U)
+#define MOD_SEL0_I2C1_B		((uint32_t)1U << 20U)
+#define MOD_SEL0_HSCIF4_A	((uint32_t)0U << 19U)
+#define MOD_SEL0_HSCIF4_B	((uint32_t)1U << 19U)
+#define MOD_SEL0_HSCIF3_A	((uint32_t)0U << 17U)
+#define MOD_SEL0_HSCIF3_B	((uint32_t)1U << 17U)
+#define MOD_SEL0_HSCIF3_C	((uint32_t)2U << 17U)
+#define MOD_SEL0_HSCIF3_D	((uint32_t)3U << 17U)
+#define MOD_SEL0_HSCIF1_A	((uint32_t)0U << 16U)
+#define MOD_SEL0_HSCIF1_B	((uint32_t)1U << 16U)
+#define MOD_SEL0_FSO_A		((uint32_t)0U << 15U)
+#define MOD_SEL0_FSO_B		((uint32_t)1U << 15U)
+#define MOD_SEL0_HSCIF2_A	((uint32_t)0U << 13U)
+#define MOD_SEL0_HSCIF2_B	((uint32_t)1U << 13U)
+#define MOD_SEL0_HSCIF2_C	((uint32_t)2U << 13U)
+#define MOD_SEL0_ETHERAVB_A	((uint32_t)0U << 12U)
+#define MOD_SEL0_ETHERAVB_B	((uint32_t)1U << 12U)
+#define MOD_SEL0_DRIF3_A	((uint32_t)0U << 11U)
+#define MOD_SEL0_DRIF3_B	((uint32_t)1U << 11U)
+#define MOD_SEL0_DRIF2_A	((uint32_t)0U << 10U)
+#define MOD_SEL0_DRIF2_B	((uint32_t)1U << 10U)
+#define MOD_SEL0_DRIF1_A	((uint32_t)0U << 8U)
+#define MOD_SEL0_DRIF1_B	((uint32_t)1U << 8U)
+#define MOD_SEL0_DRIF1_C	((uint32_t)2U << 8U)
+#define MOD_SEL0_DRIF0_A	((uint32_t)0U << 6U)
+#define MOD_SEL0_DRIF0_B	((uint32_t)1U << 6U)
+#define MOD_SEL0_DRIF0_C	((uint32_t)2U << 6U)
+#define MOD_SEL0_CANFD0_A	((uint32_t)0U << 5U)
+#define MOD_SEL0_CANFD0_B	((uint32_t)1U << 5U)
+#define MOD_SEL0_ADG_A_A	((uint32_t)0U << 3U)
+#define MOD_SEL0_ADG_A_B	((uint32_t)1U << 3U)
+#define MOD_SEL0_ADG_A_C	((uint32_t)2U << 3U)
+#define MOD_SEL1_TSIF1_A	((uint32_t)0U << 30U)
+#define MOD_SEL1_TSIF1_B	((uint32_t)1U << 30U)
+#define MOD_SEL1_TSIF1_C	((uint32_t)2U << 30U)
+#define MOD_SEL1_TSIF1_D	((uint32_t)3U << 30U)
+#define MOD_SEL1_TSIF0_A	((uint32_t)0U << 27U)
+#define MOD_SEL1_TSIF0_B	((uint32_t)1U << 27U)
+#define MOD_SEL1_TSIF0_C	((uint32_t)2U << 27U)
+#define MOD_SEL1_TSIF0_D	((uint32_t)3U << 27U)
+#define MOD_SEL1_TSIF0_E	((uint32_t)4U << 27U)
+#define MOD_SEL1_TIMER_TMU_A	((uint32_t)0U << 26U)
+#define MOD_SEL1_TIMER_TMU_B	((uint32_t)1U << 26U)
+#define MOD_SEL1_SSP1_1_A	((uint32_t)0U << 24U)
+#define MOD_SEL1_SSP1_1_B	((uint32_t)1U << 24U)
+#define MOD_SEL1_SSP1_1_C	((uint32_t)2U << 24U)
+#define MOD_SEL1_SSP1_1_D	((uint32_t)3U << 24U)
+#define MOD_SEL1_SSP1_0_A	((uint32_t)0U << 21U)
+#define MOD_SEL1_SSP1_0_B	((uint32_t)1U << 21U)
+#define MOD_SEL1_SSP1_0_C	((uint32_t)2U << 21U)
+#define MOD_SEL1_SSP1_0_D	((uint32_t)3U << 21U)
+#define MOD_SEL1_SSP1_0_E	((uint32_t)4U << 21U)
+#define MOD_SEL1_SSI_A		((uint32_t)0U << 20U)
+#define MOD_SEL1_SSI_B		((uint32_t)1U << 20U)
+#define MOD_SEL1_SPEED_PULSE_IF_A	((uint32_t)0U << 19U)
+#define MOD_SEL1_SPEED_PULSE_IF_B	((uint32_t)1U << 19U)
+#define MOD_SEL1_SIMCARD_A	((uint32_t)0U << 17U)
+#define MOD_SEL1_SIMCARD_B	((uint32_t)1U << 17U)
+#define MOD_SEL1_SIMCARD_C	((uint32_t)2U << 17U)
+#define MOD_SEL1_SIMCARD_D	((uint32_t)3U << 17U)
+#define MOD_SEL1_SDHI2_A	((uint32_t)0U << 16U)
+#define MOD_SEL1_SDHI2_B	((uint32_t)1U << 16U)
+#define MOD_SEL1_SCIF4_A	((uint32_t)0U << 14U)
+#define MOD_SEL1_SCIF4_B	((uint32_t)1U << 14U)
+#define MOD_SEL1_SCIF4_C	((uint32_t)2U << 14U)
+#define MOD_SEL1_SCIF3_A	((uint32_t)0U << 13U)
+#define MOD_SEL1_SCIF3_B	((uint32_t)1U << 13U)
+#define MOD_SEL1_SCIF2_A	((uint32_t)0U << 12U)
+#define MOD_SEL1_SCIF2_B	((uint32_t)1U << 12U)
+#define MOD_SEL1_SCIF1_A	((uint32_t)0U << 11U)
+#define MOD_SEL1_SCIF1_B	((uint32_t)1U << 11U)
+#define MOD_SEL1_SCIF_A		((uint32_t)0U << 10U)
+#define MOD_SEL1_SCIF_B		((uint32_t)1U << 10U)
+#define MOD_SEL1_REMOCON_A	((uint32_t)0U << 9U)
+#define MOD_SEL1_REMOCON_B	((uint32_t)1U << 9U)
+#define MOD_SEL1_RCAN0_A	((uint32_t)0U << 6U)
+#define MOD_SEL1_RCAN0_B	((uint32_t)1U << 6U)
+#define MOD_SEL1_PWM6_A		((uint32_t)0U << 5U)
+#define MOD_SEL1_PWM6_B		((uint32_t)1U << 5U)
+#define MOD_SEL1_PWM5_A		((uint32_t)0U << 4U)
+#define MOD_SEL1_PWM5_B		((uint32_t)1U << 4U)
+#define MOD_SEL1_PWM4_A		((uint32_t)0U << 3U)
+#define MOD_SEL1_PWM4_B		((uint32_t)1U << 3U)
+#define MOD_SEL1_PWM3_A		((uint32_t)0U << 2U)
+#define MOD_SEL1_PWM3_B		((uint32_t)1U << 2U)
+#define MOD_SEL1_PWM2_A		((uint32_t)0U << 1U)
+#define MOD_SEL1_PWM2_B		((uint32_t)1U << 1U)
+#define MOD_SEL1_PWM1_A		((uint32_t)0U << 0U)
+#define MOD_SEL1_PWM1_B		((uint32_t)1U << 0U)
+#define MOD_SEL2_I2C_5_A	((uint32_t)0U << 31U)
+#define MOD_SEL2_I2C_5_B	((uint32_t)1U << 31U)
+#define MOD_SEL2_I2C_3_A	((uint32_t)0U << 30U)
+#define MOD_SEL2_I2C_3_B	((uint32_t)1U << 30U)
+#define MOD_SEL2_I2C_0_A	((uint32_t)0U << 29U)
+#define MOD_SEL2_I2C_0_B	((uint32_t)1U << 29U)
+#define MOD_SEL2_FM_A		((uint32_t)0U << 27U)
+#define MOD_SEL2_FM_B		((uint32_t)1U << 27U)
+#define MOD_SEL2_FM_C		((uint32_t)2U << 27U)
+#define MOD_SEL2_FM_D		((uint32_t)3U << 27U)
+#define MOD_SEL2_SCIF5_A	((uint32_t)0U << 26U)
+#define MOD_SEL2_SCIF5_B	((uint32_t)1U << 26U)
+#define MOD_SEL2_I2C6_A		((uint32_t)0U << 23U)
+#define MOD_SEL2_I2C6_B		((uint32_t)1U << 23U)
+#define MOD_SEL2_I2C6_C		((uint32_t)2U << 23U)
+#define MOD_SEL2_NDF_A		((uint32_t)0U << 22U)
+#define MOD_SEL2_NDF_B		((uint32_t)1U << 22U)
+#define MOD_SEL2_SSI2_A		((uint32_t)0U << 21U)
+#define MOD_SEL2_SSI2_B		((uint32_t)1U << 21U)
+#define MOD_SEL2_SSI9_A		((uint32_t)0U << 20U)
+#define MOD_SEL2_SSI9_B		((uint32_t)1U << 20U)
+#define MOD_SEL2_TIMER_TMU2_A	((uint32_t)0U << 19U)
+#define MOD_SEL2_TIMER_TMU2_B	((uint32_t)1U << 19U)
+#define MOD_SEL2_ADG_B_A	((uint32_t)0U << 18U)
+#define MOD_SEL2_ADG_B_B	((uint32_t)1U << 18U)
+#define MOD_SEL2_ADG_C_A	((uint32_t)0U << 17U)
+#define MOD_SEL2_ADG_C_B	((uint32_t)1U << 17U)
+#define MOD_SEL2_VIN4_A		((uint32_t)0U << 0U)
+#define MOD_SEL2_VIN4_B		((uint32_t)1U << 0U)
+
+static void pfc_reg_write(uint32_t addr, uint32_t data)
+{
+	mmio_write_32(PFC_PMMR, ~data);
+	mmio_write_32((uintptr_t)addr, data);
+}
+
+void pfc_init_d3(void)
+{
+	/* initialize module select */
+	pfc_reg_write(PFC_MOD_SEL0, 0x00000000U);
+	pfc_reg_write(PFC_MOD_SEL1, 0x00000000U);
+
+	/* initialize peripheral function select */
+	pfc_reg_write(PFC_IPSR0,  0x00000001U);
+	pfc_reg_write(PFC_IPSR1,  0x00000000U);
+	pfc_reg_write(PFC_IPSR2,  0x00000000U);
+	pfc_reg_write(PFC_IPSR3,  0x00000000U);
+	pfc_reg_write(PFC_IPSR4,  0x00002000U);
+	pfc_reg_write(PFC_IPSR5,  0x00000000U);
+	pfc_reg_write(PFC_IPSR6,  0x00000000U);
+	pfc_reg_write(PFC_IPSR7,  0x00000000U);
+	pfc_reg_write(PFC_IPSR8,  0x11003301U);
+	pfc_reg_write(PFC_IPSR9,  0x11111111U);
+	pfc_reg_write(PFC_IPSR10, 0x00020000U);
+	pfc_reg_write(PFC_IPSR11, 0x40001110U);
+	pfc_reg_write(PFC_IPSR12, 0x00000000U);
+	pfc_reg_write(PFC_IPSR13, 0x00000000U);
+
+	/* initialize GPIO/perihperal function select */
+	pfc_reg_write(PFC_GPSR0, 0x0000001FU);
+	pfc_reg_write(PFC_GPSR1, 0x3FFFFFFFU);
+	pfc_reg_write(PFC_GPSR2, 0xFFFFFFFFU);
+	pfc_reg_write(PFC_GPSR3, 0x000003FFU);
+	pfc_reg_write(PFC_GPSR4, 0xFC7F0F7EU);
+	pfc_reg_write(PFC_GPSR5, 0x001BFFFBU);
+	pfc_reg_write(PFC_GPSR6, 0x00003FFFU);
+
+	/* initialize POC control register */
+	pfc_reg_write(PFC_POCCTRL0,   0xC00FFFFFU);
+	pfc_reg_write(PFC_POCCTRL1,   0XFFFFFFFEU);
+	pfc_reg_write(PFC_TDSELCTRL0, 0x00000000U);
+
+	/* initialize LSI pin pull-up/down control */
+	pfc_reg_write(PFC_PUD0, 0x0047C1A2U);
+	pfc_reg_write(PFC_PUD1, 0x4E13ABFFU);
+	pfc_reg_write(PFC_PUD2, 0xFFFFFFFFU);
+	pfc_reg_write(PFC_PUD3, 0xFF0FFFFFU);
+	pfc_reg_write(PFC_PUD4, 0xE0000000U);
+	pfc_reg_write(PFC_PUD5, 0x60000000U);
+
+	/* initialize LSI pin pull-enable register */
+	pfc_reg_write(PFC_PUEN0, 0x00000000U);
+	pfc_reg_write(PFC_PUEN1, 0x00000000U);
+	pfc_reg_write(PFC_PUEN2, 0x00000000U);
+	pfc_reg_write(PFC_PUEN3, 0x000F008CU);
+	pfc_reg_write(PFC_PUEN4, 0x00000000U);
+	pfc_reg_write(PFC_PUEN5, 0x00000000U);
+
+	/* initialize positive/negative logic select */
+	mmio_write_32(GPIO_POSNEG0, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG1, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG2, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG3, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG4, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG5, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG6, 0x00000000U);
+
+	/* initialize general IO/interrupt switching */
+	mmio_write_32(GPIO_IOINTSEL0, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL1, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL2, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL3, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL4, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL5, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL6, 0x00000000U);
+
+	/* initialize general output register */
+	mmio_write_32(GPIO_OUTDT0, 0x00000000U);
+	mmio_write_32(GPIO_OUTDT1, 0x00000000U);
+	mmio_write_32(GPIO_OUTDT2, 0x00000400U);
+	mmio_write_32(GPIO_OUTDT3, 0x00000000U);
+	mmio_write_32(GPIO_OUTDT4, 0x00000000U);
+	mmio_write_32(GPIO_OUTDT5, 0x00000006U);
+	mmio_write_32(GPIO_OUTDT6, 0x00003880U);
+
+	/* initialize general input/output switching */
+	mmio_write_32(GPIO_INOUTSEL0, 0x00000000U);
+	mmio_write_32(GPIO_INOUTSEL1, 0x00000000U);
+	mmio_write_32(GPIO_INOUTSEL2, 0x00000000U);
+	mmio_write_32(GPIO_INOUTSEL3, 0x00000000U);
+	mmio_write_32(GPIO_INOUTSEL4, 0x00802000U);
+	mmio_write_32(GPIO_INOUTSEL5, 0x00000000U);
+	mmio_write_32(GPIO_INOUTSEL6, 0x00000000U);
+}
diff --git a/drivers/staging/renesas/rcar/pfc/D3/pfc_init_d3.h b/drivers/renesas/rcar/pfc/D3/pfc_init_d3.h
similarity index 66%
rename from drivers/staging/renesas/rcar/pfc/D3/pfc_init_d3.h
rename to drivers/renesas/rcar/pfc/D3/pfc_init_d3.h
index ee1fada..b7b1754 100644
--- a/drivers/staging/renesas/rcar/pfc/D3/pfc_init_d3.h
+++ b/drivers/renesas/rcar/pfc/D3/pfc_init_d3.h
@@ -4,9 +4,9 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef PFC_INIT_D3_H__
-#define PFC_INIT_D3_H__
+#ifndef PFC_INIT_D3_H
+#define PFC_INIT_D3_H
 
 void pfc_init_d3(void);
 
-#endif	/* PFC_INIT_D3_H__ */
+#endif	/* PFC_INIT_D3_H */
diff --git a/drivers/renesas/rcar/pfc/E3/pfc_init_e3.c b/drivers/renesas/rcar/pfc/E3/pfc_init_e3.c
new file mode 100644
index 0000000..2946cba
--- /dev/null
+++ b/drivers/renesas/rcar/pfc/E3/pfc_init_e3.c
@@ -0,0 +1,651 @@
+/*
+ * Copyright (c) 2018-2019, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>		/* for uint32_t */
+#include <lib/mmio.h>
+#include "pfc_init_e3.h"
+#include "rcar_def.h"
+#include "../pfc_regs.h"
+
+/* PFC */
+#define GPSR0_SDA4		BIT(17)
+#define GPSR0_SCL4		BIT(16)
+#define GPSR0_D15		BIT(15)
+#define GPSR0_D14		BIT(14)
+#define GPSR0_D13		BIT(13)
+#define GPSR0_D12		BIT(12)
+#define GPSR0_D11		BIT(11)
+#define GPSR0_D10		BIT(10)
+#define GPSR0_D9		BIT(9)
+#define GPSR0_D8		BIT(8)
+#define GPSR0_D7		BIT(7)
+#define GPSR0_D6		BIT(6)
+#define GPSR0_D5		BIT(5)
+#define GPSR0_D4		BIT(4)
+#define GPSR0_D3		BIT(3)
+#define GPSR0_D2		BIT(2)
+#define GPSR0_D1		BIT(1)
+#define GPSR0_D0		BIT(0)
+#define GPSR1_WE0		BIT(22)
+#define GPSR1_CS0		BIT(21)
+#define GPSR1_CLKOUT		BIT(20)
+#define GPSR1_A19		BIT(19)
+#define GPSR1_A18		BIT(18)
+#define GPSR1_A17		BIT(17)
+#define GPSR1_A16		BIT(16)
+#define GPSR1_A15		BIT(15)
+#define GPSR1_A14		BIT(14)
+#define GPSR1_A13		BIT(13)
+#define GPSR1_A12		BIT(12)
+#define GPSR1_A11		BIT(11)
+#define GPSR1_A10		BIT(10)
+#define GPSR1_A9		BIT(9)
+#define GPSR1_A8		BIT(8)
+#define GPSR1_A7		BIT(7)
+#define GPSR1_A6		BIT(6)
+#define GPSR1_A5		BIT(5)
+#define GPSR1_A4		BIT(4)
+#define GPSR1_A3		BIT(3)
+#define GPSR1_A2		BIT(2)
+#define GPSR1_A1		BIT(1)
+#define GPSR1_A0		BIT(0)
+#define GPSR2_BIT27_REVERSED	BIT(27)
+#define GPSR2_BIT26_REVERSED	BIT(26)
+#define GPSR2_EX_WAIT0		BIT(25)
+#define GPSR2_RD_WR		BIT(24)
+#define GPSR2_RD		BIT(23)
+#define GPSR2_BS		BIT(22)
+#define GPSR2_AVB_PHY_INT	BIT(21)
+#define GPSR2_AVB_TXCREFCLK	BIT(20)
+#define GPSR2_AVB_RD3		BIT(19)
+#define GPSR2_AVB_RD2		BIT(18)
+#define GPSR2_AVB_RD1		BIT(17)
+#define GPSR2_AVB_RD0		BIT(16)
+#define GPSR2_AVB_RXC		BIT(15)
+#define GPSR2_AVB_RX_CTL	BIT(14)
+#define GPSR2_RPC_RESET		BIT(13)
+#define GPSR2_RPC_RPC_INT	BIT(12)
+#define GPSR2_QSPI1_SSL		BIT(11)
+#define GPSR2_QSPI1_IO3		BIT(10)
+#define GPSR2_QSPI1_IO2		BIT(9)
+#define GPSR2_QSPI1_MISO_IO1	BIT(8)
+#define GPSR2_QSPI1_MOSI_IO0	BIT(7)
+#define GPSR2_QSPI1_SPCLK	BIT(6)
+#define GPSR2_QSPI0_SSL		BIT(5)
+#define GPSR2_QSPI0_IO3		BIT(4)
+#define GPSR2_QSPI0_IO2		BIT(3)
+#define GPSR2_QSPI0_MISO_IO1	BIT(2)
+#define GPSR2_QSPI0_MOSI_IO0	BIT(1)
+#define GPSR2_QSPI0_SPCLK	BIT(0)
+#define GPSR3_SD1_WP		BIT(15)
+#define GPSR3_SD1_CD		BIT(14)
+#define GPSR3_SD0_WP		BIT(13)
+#define GPSR3_SD0_CD		BIT(12)
+#define GPSR3_SD1_DAT3		BIT(11)
+#define GPSR3_SD1_DAT2		BIT(10)
+#define GPSR3_SD1_DAT1		BIT(9)
+#define GPSR3_SD1_DAT0		BIT(8)
+#define GPSR3_SD1_CMD		BIT(7)
+#define GPSR3_SD1_CLK		BIT(6)
+#define GPSR3_SD0_DAT3		BIT(5)
+#define GPSR3_SD0_DAT2		BIT(4)
+#define GPSR3_SD0_DAT1		BIT(3)
+#define GPSR3_SD0_DAT0		BIT(2)
+#define GPSR3_SD0_CMD		BIT(1)
+#define GPSR3_SD0_CLK		BIT(0)
+#define GPSR4_SD3_DS		BIT(10)
+#define GPSR4_SD3_DAT7		BIT(9)
+#define GPSR4_SD3_DAT6		BIT(8)
+#define GPSR4_SD3_DAT5		BIT(7)
+#define GPSR4_SD3_DAT4		BIT(6)
+#define GPSR4_SD3_DAT3		BIT(5)
+#define GPSR4_SD3_DAT2		BIT(4)
+#define GPSR4_SD3_DAT1		BIT(3)
+#define GPSR4_SD3_DAT0		BIT(2)
+#define GPSR4_SD3_CMD		BIT(1)
+#define GPSR4_SD3_CLK		BIT(0)
+#define GPSR5_MLB_DAT		BIT(19)
+#define GPSR5_MLB_SIG		BIT(18)
+#define GPSR5_MLB_CLK		BIT(17)
+#define GPSR5_SSI_SDATA9	BIT(16)
+#define GPSR5_MSIOF0_SS2	BIT(15)
+#define GPSR5_MSIOF0_SS1	BIT(14)
+#define GPSR5_MSIOF0_SYNC	BIT(13)
+#define GPSR5_MSIOF0_TXD	BIT(12)
+#define GPSR5_MSIOF0_RXD	BIT(11)
+#define GPSR5_MSIOF0_SCK	BIT(10)
+#define GPSR5_RX2_A		BIT(9)
+#define GPSR5_TX2_A		BIT(8)
+#define GPSR5_SCK2_A		BIT(7)
+#define GPSR5_TX1		BIT(6)
+#define GPSR5_RX1		BIT(5)
+#define GPSR5_RTS0_TANS_A	BIT(4)
+#define GPSR5_CTS0_A		BIT(3)
+#define GPSR5_TX0_A		BIT(2)
+#define GPSR5_RX0_A		BIT(1)
+#define GPSR5_SCK0_A		BIT(0)
+#define GPSR6_USB30_PWEN	BIT(17)
+#define GPSR6_SSI_SDATA6	BIT(16)
+#define GPSR6_SSI_WS6		BIT(15)
+#define GPSR6_SSI_SCK6		BIT(14)
+#define GPSR6_SSI_SDATA5	BIT(13)
+#define GPSR6_SSI_WS5		BIT(12)
+#define GPSR6_SSI_SCK5		BIT(11)
+#define GPSR6_SSI_SDATA4	BIT(10)
+#define GPSR6_USB30_OVC		BIT(9)
+#define GPSR6_AUDIO_CLKA	BIT(8)
+#define GPSR6_SSI_SDATA3	BIT(7)
+#define GPSR6_SSI_WS349		BIT(6)
+#define GPSR6_SSI_SCK349	BIT(5)
+#define GPSR6_SSI_SDATA2	BIT(4)
+#define GPSR6_SSI_SDATA1	BIT(3)
+#define GPSR6_SSI_SDATA0	BIT(2)
+#define GPSR6_SSI_WS01239	BIT(1)
+#define GPSR6_SSI_SCK01239	BIT(0)
+
+#define IPSR_28_FUNC(x)		((uint32_t)(x) << 28U)
+#define IPSR_24_FUNC(x)		((uint32_t)(x) << 24U)
+#define IPSR_20_FUNC(x)		((uint32_t)(x) << 20U)
+#define IPSR_16_FUNC(x)		((uint32_t)(x) << 16U)
+#define IPSR_12_FUNC(x)		((uint32_t)(x) << 12U)
+#define IPSR_8_FUNC(x)		((uint32_t)(x) << 8U)
+#define IPSR_4_FUNC(x)		((uint32_t)(x) << 4U)
+#define IPSR_0_FUNC(x)		((uint32_t)(x) << 0U)
+
+#define IOCTRL30_MASK		(0x0007F000U)
+#define POC_SD3_DS_33V		BIT(29)
+#define POC_SD3_DAT7_33V	BIT(28)
+#define POC_SD3_DAT6_33V	BIT(27)
+#define POC_SD3_DAT5_33V	BIT(26)
+#define POC_SD3_DAT4_33V	BIT(25)
+#define POC_SD3_DAT3_33V	BIT(24)
+#define POC_SD3_DAT2_33V	BIT(23)
+#define POC_SD3_DAT1_33V	BIT(22)
+#define POC_SD3_DAT0_33V	BIT(21)
+#define POC_SD3_CMD_33V		BIT(20)
+#define POC_SD3_CLK_33V		BIT(19)
+#define POC_SD1_DAT3_33V	BIT(11)
+#define POC_SD1_DAT2_33V	BIT(10)
+#define POC_SD1_DAT1_33V	BIT(9)
+#define POC_SD1_DAT0_33V	BIT(8)
+#define POC_SD1_CMD_33V		BIT(7)
+#define POC_SD1_CLK_33V		BIT(6)
+#define POC_SD0_DAT3_33V	BIT(5)
+#define POC_SD0_DAT2_33V	BIT(4)
+#define POC_SD0_DAT1_33V	BIT(3)
+#define POC_SD0_DAT0_33V	BIT(2)
+#define POC_SD0_CMD_33V		BIT(1)
+#define POC_SD0_CLK_33V		BIT(0)
+
+#define IOCTRL32_MASK		(0xFFFFFFFEU)
+#define POC2_VREF_33V		BIT(0)
+
+#define MOD_SEL0_ADGB_A		((uint32_t)0U << 29U)
+#define MOD_SEL0_ADGB_B		((uint32_t)1U << 29U)
+#define MOD_SEL0_ADGB_C		((uint32_t)2U << 29U)
+#define MOD_SEL0_DRIF0_A	((uint32_t)0U << 28U)
+#define MOD_SEL0_DRIF0_B	((uint32_t)1U << 28U)
+#define MOD_SEL0_FM_A		((uint32_t)0U << 26U)
+#define MOD_SEL0_FM_B		((uint32_t)1U << 26U)
+#define MOD_SEL0_FM_C		((uint32_t)2U << 26U)
+#define MOD_SEL0_FSO_A		((uint32_t)0U << 25U)
+#define MOD_SEL0_FSO_B		((uint32_t)1U << 25U)
+#define MOD_SEL0_HSCIF0_A	((uint32_t)0U << 24U)
+#define MOD_SEL0_HSCIF0_B	((uint32_t)1U << 24U)
+#define MOD_SEL0_HSCIF1_A	((uint32_t)0U << 23U)
+#define MOD_SEL0_HSCIF1_B	((uint32_t)1U << 23U)
+#define MOD_SEL0_HSCIF2_A	((uint32_t)0U << 22U)
+#define MOD_SEL0_HSCIF2_B	((uint32_t)1U << 22U)
+#define MOD_SEL0_I2C1_A		((uint32_t)0U << 20U)
+#define MOD_SEL0_I2C1_B		((uint32_t)1U << 20U)
+#define MOD_SEL0_I2C1_C		((uint32_t)2U << 20U)
+#define MOD_SEL0_I2C1_D		((uint32_t)3U << 20U)
+#define MOD_SEL0_I2C2_A		((uint32_t)0U << 17U)
+#define MOD_SEL0_I2C2_B		((uint32_t)1U << 17U)
+#define MOD_SEL0_I2C2_C		((uint32_t)2U << 17U)
+#define MOD_SEL0_I2C2_D		((uint32_t)3U << 17U)
+#define MOD_SEL0_I2C2_E		((uint32_t)4U << 17U)
+#define MOD_SEL0_NDFC_A		((uint32_t)0U << 16U)
+#define MOD_SEL0_NDFC_B		((uint32_t)1U << 16U)
+#define MOD_SEL0_PWM0_A		((uint32_t)0U << 15U)
+#define MOD_SEL0_PWM0_B		((uint32_t)1U << 15U)
+#define MOD_SEL0_PWM1_A		((uint32_t)0U << 14U)
+#define MOD_SEL0_PWM1_B		((uint32_t)1U << 14U)
+#define MOD_SEL0_PWM2_A		((uint32_t)0U << 12U)
+#define MOD_SEL0_PWM2_B		((uint32_t)1U << 12U)
+#define MOD_SEL0_PWM2_C		((uint32_t)2U << 12U)
+#define MOD_SEL0_PWM3_A		((uint32_t)0U << 10U)
+#define MOD_SEL0_PWM3_B		((uint32_t)1U << 10U)
+#define MOD_SEL0_PWM3_C		((uint32_t)2U << 10U)
+#define MOD_SEL0_PWM4_A		((uint32_t)0U << 9U)
+#define MOD_SEL0_PWM4_B		((uint32_t)1U << 9U)
+#define MOD_SEL0_PWM5_A		((uint32_t)0U << 8U)
+#define MOD_SEL0_PWM5_B		((uint32_t)1U << 8U)
+#define MOD_SEL0_PWM6_A		((uint32_t)0U << 7U)
+#define MOD_SEL0_PWM6_B		((uint32_t)1U << 7U)
+#define MOD_SEL0_REMOCON_A	((uint32_t)0U << 5U)
+#define MOD_SEL0_REMOCON_B	((uint32_t)1U << 5U)
+#define MOD_SEL0_REMOCON_C	((uint32_t)2U << 5U)
+#define MOD_SEL0_SCIF_A		((uint32_t)0U << 4U)
+#define MOD_SEL0_SCIF_B		((uint32_t)1U << 4U)
+#define MOD_SEL0_SCIF0_A	((uint32_t)0U << 3U)
+#define MOD_SEL0_SCIF0_B	((uint32_t)1U << 3U)
+#define MOD_SEL0_SCIF2_A	((uint32_t)0U << 2U)
+#define MOD_SEL0_SCIF2_B	((uint32_t)1U << 2U)
+#define MOD_SEL0_SPEED_PULSE_IF_A	((uint32_t)0U << 0U)
+#define MOD_SEL0_SPEED_PULSE_IF_B	((uint32_t)1U << 0U)
+#define MOD_SEL0_SPEED_PULSE_IF_C	((uint32_t)2U << 0U)
+#define MOD_SEL1_SIMCARD_A	((uint32_t)0U << 31U)
+#define MOD_SEL1_SIMCARD_B	((uint32_t)1U << 31U)
+#define MOD_SEL1_SSI2_A		((uint32_t)0U << 30U)
+#define MOD_SEL1_SSI2_B		((uint32_t)1U << 30U)
+#define MOD_SEL1_TIMER_TMU_A	((uint32_t)0U << 29U)
+#define MOD_SEL1_TIMER_TMU_B	((uint32_t)1U << 29U)
+#define MOD_SEL1_USB20_CH0_A	((uint32_t)0U << 28U)
+#define MOD_SEL1_USB20_CH0_B	((uint32_t)1U << 28U)
+#define MOD_SEL1_DRIF2_A	((uint32_t)0U << 26U)
+#define MOD_SEL1_DRIF2_B	((uint32_t)1U << 26U)
+#define MOD_SEL1_DRIF3_A	((uint32_t)0U << 25U)
+#define MOD_SEL1_DRIF3_B	((uint32_t)1U << 25U)
+#define MOD_SEL1_HSCIF3_A	((uint32_t)0U << 22U)
+#define MOD_SEL1_HSCIF3_B	((uint32_t)1U << 22U)
+#define MOD_SEL1_HSCIF3_C	((uint32_t)2U << 22U)
+#define MOD_SEL1_HSCIF3_D	((uint32_t)3U << 22U)
+#define MOD_SEL1_HSCIF3_E	((uint32_t)4U << 22U)
+#define MOD_SEL1_HSCIF4_A	((uint32_t)0U << 19U)
+#define MOD_SEL1_HSCIF4_B	((uint32_t)1U << 19U)
+#define MOD_SEL1_HSCIF4_C	((uint32_t)2U << 19U)
+#define MOD_SEL1_HSCIF4_D	((uint32_t)3U << 19U)
+#define MOD_SEL1_HSCIF4_E	((uint32_t)4U << 19U)
+#define MOD_SEL1_I2C6_A		((uint32_t)0U << 18U)
+#define MOD_SEL1_I2C6_B		((uint32_t)1U << 18U)
+#define MOD_SEL1_I2C7_A		((uint32_t)0U << 17U)
+#define MOD_SEL1_I2C7_B		((uint32_t)1U << 17U)
+#define MOD_SEL1_MSIOF2_A	((uint32_t)0U << 16U)
+#define MOD_SEL1_MSIOF2_B	((uint32_t)1U << 16U)
+#define MOD_SEL1_MSIOF3_A	((uint32_t)0U << 15U)
+#define MOD_SEL1_MSIOF3_B	((uint32_t)1U << 15U)
+#define MOD_SEL1_SCIF3_A	((uint32_t)0U << 13U)
+#define MOD_SEL1_SCIF3_B	((uint32_t)1U << 13U)
+#define MOD_SEL1_SCIF3_C	((uint32_t)2U << 13U)
+#define MOD_SEL1_SCIF4_A	((uint32_t)0U << 11U)
+#define MOD_SEL1_SCIF4_B	((uint32_t)1U << 11U)
+#define MOD_SEL1_SCIF4_C	((uint32_t)2U << 11U)
+#define MOD_SEL1_SCIF5_A	((uint32_t)0U << 9U)
+#define MOD_SEL1_SCIF5_B	((uint32_t)1U << 9U)
+#define MOD_SEL1_SCIF5_C	((uint32_t)2U << 9U)
+#define MOD_SEL1_VIN4_A		((uint32_t)0U << 8U)
+#define MOD_SEL1_VIN4_B		((uint32_t)1U << 8U)
+#define MOD_SEL1_VIN5_A		((uint32_t)0U << 7U)
+#define MOD_SEL1_VIN5_B		((uint32_t)1U << 7U)
+#define MOD_SEL1_ADGC_A		((uint32_t)0U << 5U)
+#define MOD_SEL1_ADGC_B		((uint32_t)1U << 5U)
+#define MOD_SEL1_ADGC_C		((uint32_t)2U << 5U)
+#define MOD_SEL1_SSI9_A		((uint32_t)0U << 4U)
+#define MOD_SEL1_SSI9_B		((uint32_t)1U << 4U)
+
+static void pfc_reg_write(uint32_t addr, uint32_t data)
+{
+	mmio_write_32(PFC_PMMR, ~data);
+	mmio_write_32((uintptr_t)addr, data);
+}
+
+void pfc_init_e3(void)
+{
+	uint32_t reg;
+
+	/* initialize module select */
+	pfc_reg_write(PFC_MOD_SEL0, MOD_SEL0_ADGB_A
+		      | MOD_SEL0_DRIF0_A
+		      | MOD_SEL0_FM_A
+		      | MOD_SEL0_FSO_A
+		      | MOD_SEL0_HSCIF0_A
+		      | MOD_SEL0_HSCIF1_A
+		      | MOD_SEL0_HSCIF2_A
+		      | MOD_SEL0_I2C1_A
+		      | MOD_SEL0_I2C2_A
+		      | MOD_SEL0_NDFC_A
+		      | MOD_SEL0_PWM0_A
+		      | MOD_SEL0_PWM1_A
+		      | MOD_SEL0_PWM2_A
+		      | MOD_SEL0_PWM3_A
+		      | MOD_SEL0_PWM4_A
+		      | MOD_SEL0_PWM5_A
+		      | MOD_SEL0_PWM6_A
+		      | MOD_SEL0_REMOCON_A
+		      | MOD_SEL0_SCIF_A
+		      | MOD_SEL0_SCIF0_A
+		      | MOD_SEL0_SCIF2_A
+		      | MOD_SEL0_SPEED_PULSE_IF_A);
+	pfc_reg_write(PFC_MOD_SEL1, MOD_SEL1_SIMCARD_A
+		      | MOD_SEL1_SSI2_A
+		      | MOD_SEL1_TIMER_TMU_A
+		      | MOD_SEL1_USB20_CH0_B
+		      | MOD_SEL1_DRIF2_A
+		      | MOD_SEL1_DRIF3_A
+		      | MOD_SEL1_HSCIF3_A
+		      | MOD_SEL1_HSCIF4_A
+		      | MOD_SEL1_I2C6_A
+		      | MOD_SEL1_I2C7_A
+		      | MOD_SEL1_MSIOF2_A
+		      | MOD_SEL1_MSIOF3_A
+		      | MOD_SEL1_SCIF3_A
+		      | MOD_SEL1_SCIF4_A
+		      | MOD_SEL1_SCIF5_A
+		      | MOD_SEL1_VIN4_A
+		      | MOD_SEL1_VIN5_A
+		      | MOD_SEL1_ADGC_A
+		      | MOD_SEL1_SSI9_A);
+
+	/* initialize peripheral function select */
+	pfc_reg_write(PFC_IPSR0, IPSR_28_FUNC(0)	/* QSPI1_MISO/IO1 */
+		      | IPSR_24_FUNC(0)	/* QSPI1_MOSI/IO0 */
+		      | IPSR_20_FUNC(0)	/* QSPI1_SPCLK */
+		      | IPSR_16_FUNC(0)	/* QSPI0_IO3 */
+		      | IPSR_12_FUNC(0)	/* QSPI0_IO2 */
+		      | IPSR_8_FUNC(0)	/* QSPI0_MISO/IO1 */
+		      | IPSR_4_FUNC(0)	/* QSPI0_MOSI/IO0 */
+		      | IPSR_0_FUNC(0));	/* QSPI0_SPCLK */
+	pfc_reg_write(PFC_IPSR1, IPSR_28_FUNC(0)	/* AVB_RD2 */
+		      | IPSR_24_FUNC(0)	/* AVB_RD1 */
+		      | IPSR_20_FUNC(0)	/* AVB_RD0 */
+		      | IPSR_16_FUNC(0)	/* RPC_RESET# */
+		      | IPSR_12_FUNC(0)	/* RPC_INT# */
+		      | IPSR_8_FUNC(0)	/* QSPI1_SSL */
+		      | IPSR_4_FUNC(0)	/* QSPI1_IO3 */
+		      | IPSR_0_FUNC(0));	/* QSPI1_IO2 */
+	pfc_reg_write(PFC_IPSR2, IPSR_28_FUNC(1)	/* IRQ0 */
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(2)	/* AVB_LINK */
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(0)	/* AVB_MDC */
+		      | IPSR_4_FUNC(0)	/* AVB_MDIO */
+		      | IPSR_0_FUNC(0));	/* AVB_TXCREFCLK */
+	pfc_reg_write(PFC_IPSR3, IPSR_28_FUNC(5)	/* DU_HSYNC */
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(5)	/* DU_DG4 */
+		      | IPSR_8_FUNC(5)	/* DU_DOTCLKOUT0 */
+		      | IPSR_4_FUNC(5)	/* DU_DISP */
+		      | IPSR_0_FUNC(1));	/* IRQ1 */
+	pfc_reg_write(PFC_IPSR4, IPSR_28_FUNC(5)	/* DU_DB5 */
+		      | IPSR_24_FUNC(5)	/* DU_DB4 */
+		      | IPSR_20_FUNC(5)	/* DU_DB3 */
+		      | IPSR_16_FUNC(5)	/* DU_DB2 */
+		      | IPSR_12_FUNC(5)	/* DU_DG6 */
+		      | IPSR_8_FUNC(5)	/* DU_VSYNC */
+		      | IPSR_4_FUNC(5)	/* DU_DG5 */
+		      | IPSR_0_FUNC(5));	/* DU_DG7 */
+	pfc_reg_write(PFC_IPSR5, IPSR_28_FUNC(5)	/* DU_DR3 */
+		      | IPSR_24_FUNC(5)	/* DU_DB7 */
+		      | IPSR_20_FUNC(5)	/* DU_DR2 */
+		      | IPSR_16_FUNC(5)	/* DU_DR1 */
+		      | IPSR_12_FUNC(5)	/* DU_DR0 */
+		      | IPSR_8_FUNC(5)	/* DU_DB1 */
+		      | IPSR_4_FUNC(5)	/* DU_DB0 */
+		      | IPSR_0_FUNC(5));	/* DU_DB6 */
+	pfc_reg_write(PFC_IPSR6, IPSR_28_FUNC(5)	/* DU_DG1 */
+		      | IPSR_24_FUNC(5)	/* DU_DG0 */
+		      | IPSR_20_FUNC(5)	/* DU_DR7 */
+		      | IPSR_16_FUNC(2)	/* IRQ5 */
+		      | IPSR_12_FUNC(5)	/* DU_DR6 */
+		      | IPSR_8_FUNC(5)	/* DU_DR5 */
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(5));	/* DU_DR4 */
+	pfc_reg_write(PFC_IPSR7, IPSR_28_FUNC(0)	/* SD0_CLK */
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(5)	/* DU_DOTCLKIN0 */
+		      | IPSR_16_FUNC(5)	/* DU_DG3 */
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(5));	/* DU_DG2 */
+	pfc_reg_write(PFC_IPSR8, IPSR_28_FUNC(0)	/* SD1_DAT0 */
+		      | IPSR_24_FUNC(0)	/* SD1_CMD */
+		      | IPSR_20_FUNC(0)	/* SD1_CLK */
+		      | IPSR_16_FUNC(0)	/* SD0_DAT3 */
+		      | IPSR_12_FUNC(0)	/* SD0_DAT2 */
+		      | IPSR_8_FUNC(0)	/* SD0_DAT1 */
+		      | IPSR_4_FUNC(0)	/* SD0_DAT0 */
+		      | IPSR_0_FUNC(0));	/* SD0_CMD */
+	pfc_reg_write(PFC_IPSR9, IPSR_28_FUNC(0)	/* SD3_DAT2 */
+		      | IPSR_24_FUNC(0)	/* SD3_DAT1 */
+		      | IPSR_20_FUNC(0)	/* SD3_DAT0 */
+		      | IPSR_16_FUNC(0)	/* SD3_CMD */
+		      | IPSR_12_FUNC(0)	/* SD3_CLK */
+		      | IPSR_8_FUNC(0)	/* SD1_DAT3 */
+		      | IPSR_4_FUNC(0)	/* SD1_DAT2 */
+		      | IPSR_0_FUNC(0));	/* SD1_DAT1 */
+	pfc_reg_write(PFC_IPSR10, IPSR_28_FUNC(0)	/* SD0_WP */
+		      | IPSR_24_FUNC(0)	/* SD0_CD */
+		      | IPSR_20_FUNC(0)	/* SD3_DS */
+		      | IPSR_16_FUNC(0)	/* SD3_DAT7 */
+		      | IPSR_12_FUNC(0)	/* SD3_DAT6 */
+		      | IPSR_8_FUNC(0)	/* SD3_DAT5 */
+		      | IPSR_4_FUNC(0)	/* SD3_DAT4 */
+		      | IPSR_0_FUNC(0));	/* SD3_DAT3 */
+	pfc_reg_write(PFC_IPSR11, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(2)	/* AUDIO_CLKOUT1_A */
+		      | IPSR_16_FUNC(2)	/* AUDIO_CLKOUT_A */
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(0)	/* SD1_WP */
+		      | IPSR_0_FUNC(0));	/* SD1_CD */
+	pfc_reg_write(PFC_IPSR12, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)	/* RX2_A */
+		      | IPSR_8_FUNC(0)	/* TX2_A */
+		      | IPSR_4_FUNC(2)	/* AUDIO_CLKB_A */
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR13, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(2)	/* AUDIO_CLKC_A */
+		      | IPSR_4_FUNC(1)	/* HTX2_A */
+		      | IPSR_0_FUNC(1));	/* HRX2_A */
+	pfc_reg_write(PFC_IPSR14, IPSR_28_FUNC(3)	/* USB0_PWEN_B */
+		      | IPSR_24_FUNC(0)	/* SSI_SDATA4 */
+		      | IPSR_20_FUNC(0)	/* SSI_SDATA3 */
+		      | IPSR_16_FUNC(0)	/* SSI_WS349 */
+		      | IPSR_12_FUNC(0)	/* SSI_SCK349 */
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(0)	/* SSI_SDATA1 */
+		      | IPSR_0_FUNC(0));	/* SSI_SDATA0 */
+	pfc_reg_write(PFC_IPSR15, IPSR_28_FUNC(0)	/* USB30_OVC */
+		      | IPSR_24_FUNC(0)	/* USB30_PWEN */
+		      | IPSR_20_FUNC(0)	/* AUDIO_CLKA */
+		      | IPSR_16_FUNC(1)	/* HRTS2#_A */
+		      | IPSR_12_FUNC(1)	/* HCTS2#_A */
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(3));	/* USB0_OVC_B */
+
+	/* initialize GPIO/perihperal function select */
+	pfc_reg_write(PFC_GPSR0, GPSR0_SCL4
+		      | GPSR0_D15
+		      | GPSR0_D11
+		      | GPSR0_D10
+		      | GPSR0_D9
+		      | GPSR0_D8
+		      | GPSR0_D7
+		      | GPSR0_D6
+		      | GPSR0_D5
+		      | GPSR0_D3
+		      | GPSR0_D2
+		      | GPSR0_D1
+		      | GPSR0_D0);
+	pfc_reg_write(PFC_GPSR1, GPSR1_WE0
+		      | GPSR1_CS0
+		      | GPSR1_A19
+		      | GPSR1_A18
+		      | GPSR1_A17
+		      | GPSR1_A16
+		      | GPSR1_A15
+		      | GPSR1_A14
+		      | GPSR1_A13
+		      | GPSR1_A12
+		      | GPSR1_A11
+		      | GPSR1_A10
+		      | GPSR1_A9
+		      | GPSR1_A8
+		      | GPSR1_A4
+		      | GPSR1_A3
+		      | GPSR1_A2
+		      | GPSR1_A1
+		      | GPSR1_A0);
+	pfc_reg_write(PFC_GPSR2, GPSR2_BIT27_REVERSED
+		      | GPSR2_BIT26_REVERSED
+		      | GPSR2_RD
+		      | GPSR2_AVB_PHY_INT
+		      | GPSR2_AVB_TXCREFCLK
+		      | GPSR2_AVB_RD3
+		      | GPSR2_AVB_RD2
+		      | GPSR2_AVB_RD1
+		      | GPSR2_AVB_RD0
+		      | GPSR2_AVB_RXC
+		      | GPSR2_AVB_RX_CTL
+		      | GPSR2_RPC_RESET
+		      | GPSR2_RPC_RPC_INT
+		      | GPSR2_QSPI1_SSL
+		      | GPSR2_QSPI1_IO3
+		      | GPSR2_QSPI1_IO2
+		      | GPSR2_QSPI1_MISO_IO1
+		      | GPSR2_QSPI1_MOSI_IO0
+		      | GPSR2_QSPI1_SPCLK
+		      | GPSR2_QSPI0_SSL
+		      | GPSR2_QSPI0_IO3
+		      | GPSR2_QSPI0_IO2
+		      | GPSR2_QSPI0_MISO_IO1
+		      | GPSR2_QSPI0_MOSI_IO0
+		      | GPSR2_QSPI0_SPCLK);
+	pfc_reg_write(PFC_GPSR3, GPSR3_SD1_WP
+		      | GPSR3_SD1_CD
+		      | GPSR3_SD0_WP
+		      | GPSR3_SD0_CD
+		      | GPSR3_SD1_DAT3
+		      | GPSR3_SD1_DAT2
+		      | GPSR3_SD1_DAT1
+		      | GPSR3_SD1_DAT0
+		      | GPSR3_SD1_CMD
+		      | GPSR3_SD1_CLK
+		      | GPSR3_SD0_DAT3
+		      | GPSR3_SD0_DAT2
+		      | GPSR3_SD0_DAT1
+		      | GPSR3_SD0_DAT0
+		      | GPSR3_SD0_CMD
+		      | GPSR3_SD0_CLK);
+	pfc_reg_write(PFC_GPSR4, GPSR4_SD3_DS
+		      | GPSR4_SD3_DAT7
+		      | GPSR4_SD3_DAT6
+		      | GPSR4_SD3_DAT5
+		      | GPSR4_SD3_DAT4
+		      | GPSR4_SD3_DAT3
+		      | GPSR4_SD3_DAT2
+		      | GPSR4_SD3_DAT1
+		      | GPSR4_SD3_DAT0
+		      | GPSR4_SD3_CMD
+		      | GPSR4_SD3_CLK);
+	pfc_reg_write(PFC_GPSR5, GPSR5_SSI_SDATA9
+		      | GPSR5_MSIOF0_SS2
+		      | GPSR5_MSIOF0_SS1
+		      | GPSR5_RX2_A
+		      | GPSR5_TX2_A
+		      | GPSR5_SCK2_A
+		      | GPSR5_RTS0_TANS_A
+		      | GPSR5_CTS0_A);
+	pfc_reg_write(PFC_GPSR6, GPSR6_USB30_PWEN
+		      | GPSR6_SSI_SDATA6
+		      | GPSR6_SSI_WS6
+		      | GPSR6_SSI_WS5
+		      | GPSR6_SSI_SCK5
+		      | GPSR6_SSI_SDATA4
+		      | GPSR6_USB30_OVC
+		      | GPSR6_AUDIO_CLKA
+		      | GPSR6_SSI_SDATA3
+		      | GPSR6_SSI_WS349
+		      | GPSR6_SSI_SCK349
+		      | GPSR6_SSI_SDATA1
+		      | GPSR6_SSI_SDATA0
+		      | GPSR6_SSI_WS01239
+		      | GPSR6_SSI_SCK01239);
+
+	/* initialize POC control */
+	reg = mmio_read_32(PFC_POCCTRL0);
+	reg = ((reg & IOCTRL30_MASK) | POC_SD1_DAT3_33V
+	       | POC_SD1_DAT2_33V
+	       | POC_SD1_DAT1_33V
+	       | POC_SD1_DAT0_33V
+	       | POC_SD1_CMD_33V
+	       | POC_SD1_CLK_33V
+	       | POC_SD0_DAT3_33V
+	       | POC_SD0_DAT2_33V
+	       | POC_SD0_DAT1_33V
+	       | POC_SD0_DAT0_33V
+	       | POC_SD0_CMD_33V
+	       | POC_SD0_CLK_33V);
+	pfc_reg_write(PFC_POCCTRL0, reg);
+	reg = mmio_read_32(PFC_POCCTRL1);
+	reg = (reg & IOCTRL32_MASK);
+	pfc_reg_write(PFC_POCCTRL1, reg);
+
+	/* initialize LSI pin pull-up/down control */
+	pfc_reg_write(PFC_PUD0, 0xFDF80000U);
+	pfc_reg_write(PFC_PUD1, 0xCE298464U);
+	pfc_reg_write(PFC_PUD2, 0xA4C380F4U);
+	pfc_reg_write(PFC_PUD3, 0x0000079FU);
+	pfc_reg_write(PFC_PUD4, 0xFFF0FFFFU);
+	pfc_reg_write(PFC_PUD5, 0x40000000U);
+
+	/* initialize LSI pin pull-enable register */
+	pfc_reg_write(PFC_PUEN0, 0xFFF00000U);
+	pfc_reg_write(PFC_PUEN1, 0x00000000U);
+	pfc_reg_write(PFC_PUEN2, 0x00000004U);
+	pfc_reg_write(PFC_PUEN3, 0x00000000U);
+	pfc_reg_write(PFC_PUEN4, 0x07800010U);
+	pfc_reg_write(PFC_PUEN5, 0x00000000U);
+
+	/* initialize positive/negative logic select */
+	mmio_write_32(GPIO_POSNEG0, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG1, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG2, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG3, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG4, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG5, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG6, 0x00000000U);
+
+	/* initialize general IO/interrupt switching */
+	mmio_write_32(GPIO_IOINTSEL0, 0x00020000U);
+	mmio_write_32(GPIO_IOINTSEL1, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL2, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL3, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL4, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL5, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL6, 0x00000000U);
+
+	/* initialize general output register */
+	mmio_write_32(GPIO_OUTDT0, 0x00000010U);
+	mmio_write_32(GPIO_OUTDT1, 0x00100000U);
+	mmio_write_32(GPIO_OUTDT2, 0x00000000U);
+	mmio_write_32(GPIO_OUTDT3, 0x00008000U);
+	mmio_write_32(GPIO_OUTDT5, 0x00060000U);
+	mmio_write_32(GPIO_OUTDT6, 0x00000000U);
+
+	/* initialize general input/output switching */
+	mmio_write_32(GPIO_INOUTSEL0, 0x00000010U);
+	mmio_write_32(GPIO_INOUTSEL1, 0x00100020U);
+	mmio_write_32(GPIO_INOUTSEL2, 0x03000000U);
+	mmio_write_32(GPIO_INOUTSEL3, 0x00008000U);
+	mmio_write_32(GPIO_INOUTSEL4, 0x00000000U);
+	mmio_write_32(GPIO_INOUTSEL5, 0x00060000U);
+	mmio_write_32(GPIO_INOUTSEL6, 0x00004000U);
+}
diff --git a/drivers/staging/renesas/rcar/pfc/E3/pfc_init_e3.h b/drivers/renesas/rcar/pfc/E3/pfc_init_e3.h
similarity index 100%
rename from drivers/staging/renesas/rcar/pfc/E3/pfc_init_e3.h
rename to drivers/renesas/rcar/pfc/E3/pfc_init_e3.h
diff --git a/drivers/renesas/rcar/pfc/H3/pfc_init_h3_v1.c b/drivers/renesas/rcar/pfc/H3/pfc_init_h3_v1.c
new file mode 100644
index 0000000..7287c83
--- /dev/null
+++ b/drivers/renesas/rcar/pfc/H3/pfc_init_h3_v1.c
@@ -0,0 +1,1185 @@
+/*
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+#include <lib/mmio.h>
+#include "rcar_def.h"
+#include "../pfc_regs.h"
+
+#define GPSR0_D15		BIT(15)
+#define GPSR0_D14		BIT(14)
+#define GPSR0_D13		BIT(13)
+#define GPSR0_D12		BIT(12)
+#define GPSR0_D11		BIT(11)
+#define GPSR0_D10		BIT(10)
+#define GPSR0_D9		BIT(9)
+#define GPSR0_D8		BIT(8)
+#define GPSR0_D7		BIT(7)
+#define GPSR0_D6		BIT(6)
+#define GPSR0_D5		BIT(5)
+#define GPSR0_D4		BIT(4)
+#define GPSR0_D3		BIT(3)
+#define GPSR0_D2		BIT(2)
+#define GPSR0_D1		BIT(1)
+#define GPSR0_D0		BIT(0)
+#define GPSR1_EX_WAIT0_A	BIT(27)
+#define GPSR1_WE1		BIT(26)
+#define GPSR1_WE0		BIT(25)
+#define GPSR1_RD_WR		BIT(24)
+#define GPSR1_RD		BIT(23)
+#define GPSR1_BS		BIT(22)
+#define GPSR1_CS1_A26		BIT(21)
+#define GPSR1_CS0		BIT(20)
+#define GPSR1_A19		BIT(19)
+#define GPSR1_A18		BIT(18)
+#define GPSR1_A17		BIT(17)
+#define GPSR1_A16		BIT(16)
+#define GPSR1_A15		BIT(15)
+#define GPSR1_A14		BIT(14)
+#define GPSR1_A13		BIT(13)
+#define GPSR1_A12		BIT(12)
+#define GPSR1_A11		BIT(11)
+#define GPSR1_A10		BIT(10)
+#define GPSR1_A9		BIT(9)
+#define GPSR1_A8		BIT(8)
+#define GPSR1_A7		BIT(7)
+#define GPSR1_A6		BIT(6)
+#define GPSR1_A5		BIT(5)
+#define GPSR1_A4		BIT(4)
+#define GPSR1_A3		BIT(3)
+#define GPSR1_A2		BIT(2)
+#define GPSR1_A1		BIT(1)
+#define GPSR1_A0		BIT(0)
+#define GPSR2_AVB_AVTP_CAPTURE_A	BIT(14)
+#define GPSR2_AVB_AVTP_MATCH_A	BIT(13)
+#define GPSR2_AVB_LINK		BIT(12)
+#define GPSR2_AVB_PHY_INT	BIT(11)
+#define GPSR2_AVB_MAGIC		BIT(10)
+#define GPSR2_AVB_MDC		BIT(9)
+#define GPSR2_PWM2_A		BIT(8)
+#define GPSR2_PWM1_A		BIT(7)
+#define GPSR2_PWM0		BIT(6)
+#define GPSR2_IRQ5		BIT(5)
+#define GPSR2_IRQ4		BIT(4)
+#define GPSR2_IRQ3		BIT(3)
+#define GPSR2_IRQ2		BIT(2)
+#define GPSR2_IRQ1		BIT(1)
+#define GPSR2_IRQ0		BIT(0)
+#define GPSR3_SD1_WP		BIT(15)
+#define GPSR3_SD1_CD		BIT(14)
+#define GPSR3_SD0_WP		BIT(13)
+#define GPSR3_SD0_CD		BIT(12)
+#define GPSR3_SD1_DAT3		BIT(11)
+#define GPSR3_SD1_DAT2		BIT(10)
+#define GPSR3_SD1_DAT1		BIT(9)
+#define GPSR3_SD1_DAT0		BIT(8)
+#define GPSR3_SD1_CMD		BIT(7)
+#define GPSR3_SD1_CLK		BIT(6)
+#define GPSR3_SD0_DAT3		BIT(5)
+#define GPSR3_SD0_DAT2		BIT(4)
+#define GPSR3_SD0_DAT1		BIT(3)
+#define GPSR3_SD0_DAT0		BIT(2)
+#define GPSR3_SD0_CMD		BIT(1)
+#define GPSR3_SD0_CLK		BIT(0)
+#define GPSR4_SD3_DS		BIT(17)
+#define GPSR4_SD3_DAT7		BIT(16)
+#define GPSR4_SD3_DAT6		BIT(15)
+#define GPSR4_SD3_DAT5		BIT(14)
+#define GPSR4_SD3_DAT4		BIT(13)
+#define GPSR4_SD3_DAT3		BIT(12)
+#define GPSR4_SD3_DAT2		BIT(11)
+#define GPSR4_SD3_DAT1		BIT(10)
+#define GPSR4_SD3_DAT0		BIT(9)
+#define GPSR4_SD3_CMD		BIT(8)
+#define GPSR4_SD3_CLK		BIT(7)
+#define GPSR4_SD2_DS		BIT(6)
+#define GPSR4_SD2_DAT3		BIT(5)
+#define GPSR4_SD2_DAT2		BIT(4)
+#define GPSR4_SD2_DAT1		BIT(3)
+#define GPSR4_SD2_DAT0		BIT(2)
+#define GPSR4_SD2_CMD		BIT(1)
+#define GPSR4_SD2_CLK		BIT(0)
+#define GPSR5_MLB_DAT		BIT(25)
+#define GPSR5_MLB_SIG		BIT(24)
+#define GPSR5_MLB_CLK		BIT(23)
+#define GPSR5_MSIOF0_RXD	BIT(22)
+#define GPSR5_MSIOF0_SS2	BIT(21)
+#define GPSR5_MSIOF0_TXD	BIT(20)
+#define GPSR5_MSIOF0_SS1	BIT(19)
+#define GPSR5_MSIOF0_SYNC	BIT(18)
+#define GPSR5_MSIOF0_SCK	BIT(17)
+#define GPSR5_HRTS0		BIT(16)
+#define GPSR5_HCTS0		BIT(15)
+#define GPSR5_HTX0		BIT(14)
+#define GPSR5_HRX0		BIT(13)
+#define GPSR5_HSCK0		BIT(12)
+#define GPSR5_RX2_A		BIT(11)
+#define GPSR5_TX2_A		BIT(10)
+#define GPSR5_SCK2		BIT(9)
+#define GPSR5_RTS1_TANS		BIT(8)
+#define GPSR5_CTS1		BIT(7)
+#define GPSR5_TX1_A		BIT(6)
+#define GPSR5_RX1_A		BIT(5)
+#define GPSR5_RTS0_TANS		BIT(4)
+#define GPSR5_CTS0		BIT(3)
+#define GPSR5_TX0		BIT(2)
+#define GPSR5_RX0		BIT(1)
+#define GPSR5_SCK0		BIT(0)
+#define GPSR6_USB31_OVC		BIT(31)
+#define GPSR6_USB31_PWEN	BIT(30)
+#define GPSR6_USB30_OVC		BIT(29)
+#define GPSR6_USB30_PWEN	BIT(28)
+#define GPSR6_USB1_OVC		BIT(27)
+#define GPSR6_USB1_PWEN		BIT(26)
+#define GPSR6_USB0_OVC		BIT(25)
+#define GPSR6_USB0_PWEN		BIT(24)
+#define GPSR6_AUDIO_CLKB_B	BIT(23)
+#define GPSR6_AUDIO_CLKA_A	BIT(22)
+#define GPSR6_SSI_SDATA9_A	BIT(21)
+#define GPSR6_SSI_SDATA8	BIT(20)
+#define GPSR6_SSI_SDATA7	BIT(19)
+#define GPSR6_SSI_WS78		BIT(18)
+#define GPSR6_SSI_SCK78		BIT(17)
+#define GPSR6_SSI_SDATA6	BIT(16)
+#define GPSR6_SSI_WS6		BIT(15)
+#define GPSR6_SSI_SCK6		BIT(14)
+#define GPSR6_SSI_SDATA5	BIT(13)
+#define GPSR6_SSI_WS5		BIT(12)
+#define GPSR6_SSI_SCK5		BIT(11)
+#define GPSR6_SSI_SDATA4	BIT(10)
+#define GPSR6_SSI_WS4		BIT(9)
+#define GPSR6_SSI_SCK4		BIT(8)
+#define GPSR6_SSI_SDATA3	BIT(7)
+#define GPSR6_SSI_WS34		BIT(6)
+#define GPSR6_SSI_SCK34		BIT(5)
+#define GPSR6_SSI_SDATA2_A	BIT(4)
+#define GPSR6_SSI_SDATA1_A	BIT(3)
+#define GPSR6_SSI_SDATA0	BIT(2)
+#define GPSR6_SSI_WS0129	BIT(1)
+#define GPSR6_SSI_SCK0129	BIT(0)
+#define GPSR7_HDMI1_CEC		BIT(3)
+#define GPSR7_HDMI0_CEC		BIT(2)
+#define GPSR7_AVS2		BIT(1)
+#define GPSR7_AVS1		BIT(0)
+
+#define IPSR_28_FUNC(x)		((uint32_t)(x) << 28U)
+#define IPSR_24_FUNC(x)		((uint32_t)(x) << 24U)
+#define IPSR_20_FUNC(x)		((uint32_t)(x) << 20U)
+#define IPSR_16_FUNC(x)		((uint32_t)(x) << 16U)
+#define IPSR_12_FUNC(x)		((uint32_t)(x) << 12U)
+#define IPSR_8_FUNC(x)		((uint32_t)(x) << 8U)
+#define IPSR_4_FUNC(x)		((uint32_t)(x) << 4U)
+#define IPSR_0_FUNC(x)		((uint32_t)(x) << 0U)
+
+#define POC_SD3_DS_33V		BIT(29)
+#define POC_SD3_DAT7_33V	BIT(28)
+#define POC_SD3_DAT6_33V	BIT(27)
+#define POC_SD3_DAT5_33V	BIT(26)
+#define POC_SD3_DAT4_33V	BIT(25)
+#define POC_SD3_DAT3_33V	BIT(24)
+#define POC_SD3_DAT2_33V	BIT(23)
+#define POC_SD3_DAT1_33V	BIT(22)
+#define POC_SD3_DAT0_33V	BIT(21)
+#define POC_SD3_CMD_33V		BIT(20)
+#define POC_SD3_CLK_33V		BIT(19)
+#define POC_SD2_DS_33V		BIT(18)
+#define POC_SD2_DAT3_33V	BIT(17)
+#define POC_SD2_DAT2_33V	BIT(16)
+#define POC_SD2_DAT1_33V	BIT(15)
+#define POC_SD2_DAT0_33V	BIT(14)
+#define POC_SD2_CMD_33V		BIT(13)
+#define POC_SD2_CLK_33V		BIT(12)
+#define POC_SD1_DAT3_33V	BIT(11)
+#define POC_SD1_DAT2_33V	BIT(10)
+#define POC_SD1_DAT1_33V	BIT(9)
+#define POC_SD1_DAT0_33V	BIT(8)
+#define POC_SD1_CMD_33V		BIT(7)
+#define POC_SD1_CLK_33V		BIT(6)
+#define POC_SD0_DAT3_33V	BIT(5)
+#define POC_SD0_DAT2_33V	BIT(4)
+#define POC_SD0_DAT1_33V	BIT(3)
+#define POC_SD0_DAT0_33V	BIT(2)
+#define POC_SD0_CMD_33V		BIT(1)
+#define POC_SD0_CLK_33V		BIT(0)
+
+#define DRVCTRL0_MASK		(0xCCCCCCCCU)
+#define DRVCTRL1_MASK		(0xCCCCCCC8U)
+#define DRVCTRL2_MASK		(0x88888888U)
+#define DRVCTRL3_MASK		(0x88888888U)
+#define DRVCTRL4_MASK		(0x88888888U)
+#define DRVCTRL5_MASK		(0x88888888U)
+#define DRVCTRL6_MASK		(0x88888888U)
+#define DRVCTRL7_MASK		(0x88888888U)
+#define DRVCTRL8_MASK		(0x88888888U)
+#define DRVCTRL9_MASK		(0x88888888U)
+#define DRVCTRL10_MASK		(0x88888888U)
+#define DRVCTRL11_MASK		(0x888888CCU)
+#define DRVCTRL12_MASK		(0xCCCFFFCFU)
+#define DRVCTRL13_MASK		(0xCC888888U)
+#define DRVCTRL14_MASK		(0x88888888U)
+#define DRVCTRL15_MASK		(0x88888888U)
+#define DRVCTRL16_MASK		(0x88888888U)
+#define DRVCTRL17_MASK		(0x88888888U)
+#define DRVCTRL18_MASK		(0x88888888U)
+#define DRVCTRL19_MASK		(0x88888888U)
+#define DRVCTRL20_MASK		(0x88888888U)
+#define DRVCTRL21_MASK		(0x88888888U)
+#define DRVCTRL22_MASK		(0x88888888U)
+#define DRVCTRL23_MASK		(0x88888888U)
+#define DRVCTRL24_MASK		(0x8888888FU)
+
+#define DRVCTRL0_QSPI0_SPCLK(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL0_QSPI0_MOSI_IO0(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL0_QSPI0_MISO_IO1(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL0_QSPI0_IO2(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL0_QSPI0_IO3(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL0_QSPI0_SSL(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL0_QSPI1_SPCLK(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL0_QSPI1_MOSI_IO0(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL1_QSPI1_MISO_IO1(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL1_QSPI1_IO2(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL1_QSPI1_IO3(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL1_QSPI1_SS(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL1_RPC_INT(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL1_RPC_WP(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL1_RPC_RESET(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL1_AVB_RX_CTL(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL2_AVB_RXC(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL2_AVB_RD0(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL2_AVB_RD1(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL2_AVB_RD2(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL2_AVB_RD3(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL2_AVB_TX_CTL(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL2_AVB_TXC(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL2_AVB_TD0(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL3_AVB_TD1(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL3_AVB_TD2(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL3_AVB_TD3(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL3_AVB_TXCREFCLK(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL3_AVB_MDIO(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL3_AVB_MDC(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL3_AVB_MAGIC(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL3_AVB_PHY_INT(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL4_AVB_LINK(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL4_AVB_AVTP_MATCH(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL4_AVB_AVTP_CAPTURE(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL4_IRQ0(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL4_IRQ1(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL4_IRQ2(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL4_IRQ3(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL4_IRQ4(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL5_IRQ5(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL5_PWM0(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL5_PWM1(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL5_PWM2(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL5_A0(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL5_A1(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL5_A2(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL5_A3(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL6_A4(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL6_A5(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL6_A6(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL6_A7(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL6_A8(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL6_A9(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL6_A10(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL6_A11(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL7_A12(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL7_A13(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL7_A14(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL7_A15(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL7_A16(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL7_A17(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL7_A18(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL7_A19(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL8_CLKOUT(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL8_CS0(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL8_CS1_A2(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL8_BS(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL8_RD(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL8_RD_W(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL8_WE0(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL8_WE1(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL9_EX_WAIT0(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL9_PRESETOU(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL9_D0(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL9_D1(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL9_D2(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL9_D3(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL9_D4(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL9_D5(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL10_D6(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL10_D7(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL10_D8(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL10_D9(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL10_D10(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL10_D11(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL10_D12(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL10_D13(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL11_D14(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL11_D15(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL11_AVS1(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL11_AVS2(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL11_HDMI0_CEC(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL11_HDMI1_CEC(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL11_DU_DOTCLKIN0(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL11_DU_DOTCLKIN1(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL12_DU_DOTCLKIN2(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL12_DU_DOTCLKIN3(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL12_DU_FSCLKST(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL12_DU_TMS(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL13_TDO(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL13_ASEBRK(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL13_SD0_CLK(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL13_SD0_CMD(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL13_SD0_DAT0(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL13_SD0_DAT1(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL13_SD0_DAT2(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL13_SD0_DAT3(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL14_SD1_CLK(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL14_SD1_CMD(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL14_SD1_DAT0(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL14_SD1_DAT1(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL14_SD1_DAT2(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL14_SD1_DAT3(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL14_SD2_CLK(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL14_SD2_CMD(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL15_SD2_DAT0(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL15_SD2_DAT1(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL15_SD2_DAT2(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL15_SD2_DAT3(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL15_SD2_DS(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL15_SD3_CLK(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL15_SD3_CMD(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL15_SD3_DAT0(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL16_SD3_DAT1(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL16_SD3_DAT2(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL16_SD3_DAT3(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL16_SD3_DAT4(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL16_SD3_DAT5(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL16_SD3_DAT6(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL16_SD3_DAT7(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL16_SD3_DS(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL17_SD0_CD(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL17_SD0_WP(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL17_SD1_CD(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL17_SD1_WP(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL17_SCK0(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL17_RX0(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL17_TX0(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL17_CTS0(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL18_RTS0_TANS(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL18_RX1(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL18_TX1(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL18_CTS1(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL18_RTS1_TANS(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL18_SCK2(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL18_TX2(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL18_RX2(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL19_HSCK0(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL19_HRX0(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL19_HTX0(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL19_HCTS0(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL19_HRTS0(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL19_MSIOF0_SCK(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL19_MSIOF0_SYNC(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL19_MSIOF0_SS1(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL20_MSIOF0_TXD(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL20_MSIOF0_SS2(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL20_MSIOF0_RXD(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL20_MLB_CLK(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL20_MLB_SIG(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL20_MLB_DAT(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL20_MLB_REF(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL20_SSI_SCK0129(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL21_SSI_WS0129(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL21_SSI_SDATA0(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL21_SSI_SDATA1(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL21_SSI_SDATA2(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL21_SSI_SCK34(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL21_SSI_WS34(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL21_SSI_SDATA3(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL21_SSI_SCK4(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL22_SSI_WS4(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL22_SSI_SDATA4(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL22_SSI_SCK5(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL22_SSI_WS5(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL22_SSI_SDATA5(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL22_SSI_SCK6(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL22_SSI_WS6(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL22_SSI_SDATA6(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL23_SSI_SCK78(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL23_SSI_WS78(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL23_SSI_SDATA7(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL23_SSI_SDATA8(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL23_SSI_SDATA9(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL23_AUDIO_CLKA(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL23_AUDIO_CLKB(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL23_USB0_PWEN(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL24_USB0_OVC(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL24_USB1_PWEN(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL24_USB1_OVC(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL24_USB30_PWEN(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL24_USB30_OVC(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL24_USB31_PWEN(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL24_USB31_OVC(x)	((uint32_t)(x) << 4U)
+
+#define MOD_SEL0_MSIOF3_A	((uint32_t)0U << 29U)
+#define MOD_SEL0_MSIOF3_B	((uint32_t)1U << 29U)
+#define MOD_SEL0_MSIOF3_C	((uint32_t)2U << 29U)
+#define MOD_SEL0_MSIOF3_D	((uint32_t)3U << 29U)
+#define MOD_SEL0_MSIOF2_A	((uint32_t)0U << 27U)
+#define MOD_SEL0_MSIOF2_B	((uint32_t)1U << 27U)
+#define MOD_SEL0_MSIOF2_C	((uint32_t)2U << 27U)
+#define MOD_SEL0_MSIOF2_D	((uint32_t)3U << 27U)
+#define MOD_SEL0_MSIOF1_A	((uint32_t)0U << 24U)
+#define MOD_SEL0_MSIOF1_B	((uint32_t)1U << 24U)
+#define MOD_SEL0_MSIOF1_C	((uint32_t)2U << 24U)
+#define MOD_SEL0_MSIOF1_D	((uint32_t)3U << 24U)
+#define MOD_SEL0_MSIOF1_E	((uint32_t)4U << 24U)
+#define MOD_SEL0_MSIOF1_F	((uint32_t)5U << 24U)
+#define MOD_SEL0_MSIOF1_G	((uint32_t)6U << 24U)
+#define MOD_SEL0_LBSC_A		((uint32_t)0U << 23U)
+#define MOD_SEL0_LBSC_B		((uint32_t)1U << 23U)
+#define MOD_SEL0_IEBUS_A	((uint32_t)0U << 22U)
+#define MOD_SEL0_IEBUS_B	((uint32_t)1U << 22U)
+#define MOD_SEL0_I2C6_A		((uint32_t)0U << 20U)
+#define MOD_SEL0_I2C6_B		((uint32_t)1U << 20U)
+#define MOD_SEL0_I2C6_C		((uint32_t)2U << 20U)
+#define MOD_SEL0_I2C2_A		((uint32_t)0U << 19U)
+#define MOD_SEL0_I2C2_B		((uint32_t)1U << 19U)
+#define MOD_SEL0_I2C1_A		((uint32_t)0U << 18U)
+#define MOD_SEL0_I2C1_B		((uint32_t)1U << 18U)
+#define MOD_SEL0_HSCIF4_A	((uint32_t)0U << 17U)
+#define MOD_SEL0_HSCIF4_B	((uint32_t)1U << 17U)
+#define MOD_SEL0_HSCIF3_A	((uint32_t)0U << 15U)
+#define MOD_SEL0_HSCIF3_B	((uint32_t)1U << 15U)
+#define MOD_SEL0_HSCIF3_C	((uint32_t)2U << 15U)
+#define MOD_SEL0_HSCIF3_D	((uint32_t)3U << 15U)
+#define MOD_SEL0_HSCIF2_A	((uint32_t)0U << 14U)
+#define MOD_SEL0_HSCIF2_B	((uint32_t)1U << 14U)
+#define MOD_SEL0_HSCIF1_A	((uint32_t)0U << 13U)
+#define MOD_SEL0_HSCIF1_B	((uint32_t)1U << 13U)
+#define MOD_SEL0_FSO_A		((uint32_t)0U << 12U)
+#define MOD_SEL0_FSO_B		((uint32_t)1U << 12U)
+#define MOD_SEL0_FM_A		((uint32_t)0U << 11U)
+#define MOD_SEL0_FM_B		((uint32_t)1U << 11U)
+#define MOD_SEL0_ETHERAVB_A	((uint32_t)0U << 10U)
+#define MOD_SEL0_ETHERAVB_B	((uint32_t)1U << 10U)
+#define MOD_SEL0_DRIF3_A	((uint32_t)0U << 9U)
+#define MOD_SEL0_DRIF3_B	((uint32_t)1U << 9U)
+#define MOD_SEL0_DRIF2_A	((uint32_t)0U << 8U)
+#define MOD_SEL0_DRIF2_B	((uint32_t)1U << 8U)
+#define MOD_SEL0_DRIF1_A	((uint32_t)0U << 6U)
+#define MOD_SEL0_DRIF1_B	((uint32_t)1U << 6U)
+#define MOD_SEL0_DRIF1_C	((uint32_t)2U << 6U)
+#define MOD_SEL0_DRIF0_A	((uint32_t)0U << 4U)
+#define MOD_SEL0_DRIF0_B	((uint32_t)1U << 4U)
+#define MOD_SEL0_DRIF0_C	((uint32_t)2U << 4U)
+#define MOD_SEL0_CANFD0_A	((uint32_t)0U << 3U)
+#define MOD_SEL0_CANFD0_B	((uint32_t)1U << 3U)
+#define MOD_SEL0_ADG_A		((uint32_t)0U << 1U)
+#define MOD_SEL0_ADG_B		((uint32_t)1U << 1U)
+#define MOD_SEL0_ADG_C		((uint32_t)2U << 1U)
+#define MOD_SEL0_ADG_D		((uint32_t)3U << 1U)
+#define MOD_SEL0_5LINE_A	((uint32_t)0U << 0U)
+#define MOD_SEL0_5LINE_B	((uint32_t)1U << 0U)
+#define MOD_SEL1_TSIF1_A	((uint32_t)0U << 30U)
+#define MOD_SEL1_TSIF1_B	((uint32_t)1U << 30U)
+#define MOD_SEL1_TSIF1_C	((uint32_t)2U << 30U)
+#define MOD_SEL1_TSIF1_D	((uint32_t)3U << 30U)
+#define MOD_SEL1_TSIF0_A	((uint32_t)0U << 27U)
+#define MOD_SEL1_TSIF0_B	((uint32_t)1U << 27U)
+#define MOD_SEL1_TSIF0_C	((uint32_t)2U << 27U)
+#define MOD_SEL1_TSIF0_D	((uint32_t)3U << 27U)
+#define MOD_SEL1_TSIF0_E	((uint32_t)4U << 27U)
+#define MOD_SEL1_TIMER_TMU_A	((uint32_t)0U << 26U)
+#define MOD_SEL1_TIMER_TMU_B	((uint32_t)1U << 26U)
+#define MOD_SEL1_SSP1_1_A	((uint32_t)0U << 24U)
+#define MOD_SEL1_SSP1_1_B	((uint32_t)1U << 24U)
+#define MOD_SEL1_SSP1_1_C	((uint32_t)2U << 24U)
+#define MOD_SEL1_SSP1_1_D	((uint32_t)3U << 24U)
+#define MOD_SEL1_SSP1_0_A	((uint32_t)0U << 21U)
+#define MOD_SEL1_SSP1_0_B	((uint32_t)1U << 21U)
+#define MOD_SEL1_SSP1_0_C	((uint32_t)2U << 21U)
+#define MOD_SEL1_SSP1_0_D	((uint32_t)3U << 21U)
+#define MOD_SEL1_SSP1_0_E	((uint32_t)4U << 21U)
+#define MOD_SEL1_SSI_A		((uint32_t)0U << 20U)
+#define MOD_SEL1_SSI_B		((uint32_t)1U << 20U)
+#define MOD_SEL1_SPEED_PULSE_IF_A	((uint32_t)0U << 19U)
+#define MOD_SEL1_SPEED_PULSE_IF_B	((uint32_t)1U << 19U)
+#define MOD_SEL1_SIMCARD_A	((uint32_t)0U << 17U)
+#define MOD_SEL1_SIMCARD_B	((uint32_t)1U << 17U)
+#define MOD_SEL1_SIMCARD_C	((uint32_t)2U << 17U)
+#define MOD_SEL1_SIMCARD_D	((uint32_t)3U << 17U)
+#define MOD_SEL1_SDHI2_A	((uint32_t)0U << 16U)
+#define MOD_SEL1_SDHI2_B	((uint32_t)1U << 16U)
+#define MOD_SEL1_SCIF4_A	((uint32_t)0U << 14U)
+#define MOD_SEL1_SCIF4_B	((uint32_t)1U << 14U)
+#define MOD_SEL1_SCIF4_C	((uint32_t)2U << 14U)
+#define MOD_SEL1_SCIF3_A	((uint32_t)0U << 13U)
+#define MOD_SEL1_SCIF3_B	((uint32_t)1U << 13U)
+#define MOD_SEL1_SCIF2_A	((uint32_t)0U << 12U)
+#define MOD_SEL1_SCIF2_B	((uint32_t)1U << 12U)
+#define MOD_SEL1_SCIF1_A	((uint32_t)0U << 11U)
+#define MOD_SEL1_SCIF1_B	((uint32_t)1U << 11U)
+#define MOD_SEL1_SCIF_A		((uint32_t)0U << 10U)
+#define MOD_SEL1_SCIF_B		((uint32_t)1U << 10U)
+#define MOD_SEL1_REMOCON_A	((uint32_t)0U << 9U)
+#define MOD_SEL1_REMOCON_B	((uint32_t)1U << 9U)
+#define MOD_SEL1_RCAN0_A	((uint32_t)0U << 6U)
+#define MOD_SEL1_RCAN0_B	((uint32_t)1U << 6U)
+#define MOD_SEL1_PWM6_A		((uint32_t)0U << 5U)
+#define MOD_SEL1_PWM6_B		((uint32_t)1U << 5U)
+#define MOD_SEL1_PWM5_A		((uint32_t)0U << 4U)
+#define MOD_SEL1_PWM5_B		((uint32_t)1U << 4U)
+#define MOD_SEL1_PWM4_A		((uint32_t)0U << 3U)
+#define MOD_SEL1_PWM4_B		((uint32_t)1U << 3U)
+#define MOD_SEL1_PWM3_A		((uint32_t)0U << 2U)
+#define MOD_SEL1_PWM3_B		((uint32_t)1U << 2U)
+#define MOD_SEL1_PWM2_A		((uint32_t)0U << 1U)
+#define MOD_SEL1_PWM2_B		((uint32_t)1U << 1U)
+#define MOD_SEL1_PWM1_A		((uint32_t)0U << 0U)
+#define MOD_SEL1_PWM1_B		((uint32_t)1U << 0U)
+#define MOD_SEL2_I2C_5_A	((uint32_t)0U << 31U)
+#define MOD_SEL2_I2C_5_B	((uint32_t)1U << 31U)
+#define MOD_SEL2_I2C_3_A	((uint32_t)0U << 30U)
+#define MOD_SEL2_I2C_3_B	((uint32_t)1U << 30U)
+#define MOD_SEL2_I2C_0_A	((uint32_t)0U << 29U)
+#define MOD_SEL2_I2C_0_B	((uint32_t)1U << 29U)
+#define MOD_SEL2_VIN4_A		((uint32_t)0U << 0U)
+#define MOD_SEL2_VIN4_B		((uint32_t)1U << 0U)
+
+static void pfc_reg_write(uint32_t addr, uint32_t data)
+{
+	mmio_write_32(PFC_PMMR, ~data);
+	mmio_write_32((uintptr_t)addr, data);
+}
+
+void pfc_init_h3_v1(void)
+{
+	uint32_t reg;
+
+	/* initialize module select */
+	pfc_reg_write(PFC_MOD_SEL0, MOD_SEL0_MSIOF3_A
+		      | MOD_SEL0_MSIOF2_A
+		      | MOD_SEL0_MSIOF1_A
+		      | MOD_SEL0_LBSC_A
+		      | MOD_SEL0_IEBUS_A
+		      | MOD_SEL0_I2C6_A
+		      | MOD_SEL0_I2C2_A
+		      | MOD_SEL0_I2C1_A
+		      | MOD_SEL0_HSCIF4_A
+		      | MOD_SEL0_HSCIF3_A
+		      | MOD_SEL0_HSCIF2_A
+		      | MOD_SEL0_HSCIF1_A
+		      | MOD_SEL0_FM_A
+		      | MOD_SEL0_ETHERAVB_A
+		      | MOD_SEL0_DRIF3_A
+		      | MOD_SEL0_DRIF2_A
+		      | MOD_SEL0_DRIF1_A
+		      | MOD_SEL0_DRIF0_A
+		      | MOD_SEL0_CANFD0_A
+		      | MOD_SEL0_ADG_A
+		      | MOD_SEL0_5LINE_A);
+	pfc_reg_write(PFC_MOD_SEL1, MOD_SEL1_TSIF1_A
+		      | MOD_SEL1_TSIF0_A
+		      | MOD_SEL1_TIMER_TMU_A
+		      | MOD_SEL1_SSP1_1_A
+		      | MOD_SEL1_SSP1_0_A
+		      | MOD_SEL1_SSI_A
+		      | MOD_SEL1_SPEED_PULSE_IF_A
+		      | MOD_SEL1_SIMCARD_A
+		      | MOD_SEL1_SDHI2_A
+		      | MOD_SEL1_SCIF4_A
+		      | MOD_SEL1_SCIF3_A
+		      | MOD_SEL1_SCIF2_A
+		      | MOD_SEL1_SCIF1_A
+		      | MOD_SEL1_SCIF_A
+		      | MOD_SEL1_REMOCON_A
+		      | MOD_SEL1_RCAN0_A
+		      | MOD_SEL1_PWM6_A
+		      | MOD_SEL1_PWM5_A
+		      | MOD_SEL1_PWM4_A
+		      | MOD_SEL1_PWM3_A
+		      | MOD_SEL1_PWM2_A
+		      | MOD_SEL1_PWM1_A);
+	pfc_reg_write(PFC_MOD_SEL2, MOD_SEL2_I2C_5_A
+		      | MOD_SEL2_I2C_3_A
+		      | MOD_SEL2_I2C_0_A
+		      | MOD_SEL2_VIN4_A);
+
+	/* initialize peripheral function select */
+	pfc_reg_write(PFC_IPSR0, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR1, IPSR_28_FUNC(6)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(3)
+		      | IPSR_8_FUNC(3)
+		      | IPSR_4_FUNC(3)
+		      | IPSR_0_FUNC(3));
+	pfc_reg_write(PFC_IPSR2, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(6)
+		      | IPSR_20_FUNC(6)
+		      | IPSR_16_FUNC(6)
+		      | IPSR_12_FUNC(6)
+		      | IPSR_8_FUNC(6)
+		      | IPSR_4_FUNC(6)
+		      | IPSR_0_FUNC(6));
+	pfc_reg_write(PFC_IPSR3, IPSR_28_FUNC(6)
+		      | IPSR_24_FUNC(6)
+		      | IPSR_20_FUNC(6)
+		      | IPSR_16_FUNC(6)
+		      | IPSR_12_FUNC(6)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR4, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(6)
+		      | IPSR_4_FUNC(6)
+		      | IPSR_0_FUNC(6));
+	pfc_reg_write(PFC_IPSR5, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(6)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR6, IPSR_28_FUNC(6)
+		      | IPSR_24_FUNC(6)
+		      | IPSR_20_FUNC(6)
+		      | IPSR_16_FUNC(6)
+		      | IPSR_12_FUNC(6)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR7, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(6)
+		      | IPSR_4_FUNC(6)
+		      | IPSR_0_FUNC(6));
+	pfc_reg_write(PFC_IPSR8, IPSR_28_FUNC(1)
+		      | IPSR_24_FUNC(1)
+		      | IPSR_20_FUNC(1)
+		      | IPSR_16_FUNC(1)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR9, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR10, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(4)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(1)
+		      | IPSR_0_FUNC(1));
+	pfc_reg_write(PFC_IPSR11, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(4)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR12, IPSR_28_FUNC(8)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(3)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR13, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(3)
+		      | IPSR_0_FUNC(8));
+	pfc_reg_write(PFC_IPSR14, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR15, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(1)
+		      | IPSR_0_FUNC(1));
+	pfc_reg_write(PFC_IPSR16, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(1)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR17, IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+
+	/* initialize GPIO/perihperal function select */
+	pfc_reg_write(PFC_GPSR0, GPSR0_D15
+		      | GPSR0_D14
+		      | GPSR0_D13
+		      | GPSR0_D12
+		      | GPSR0_D11
+		      | GPSR0_D10
+		      | GPSR0_D9
+		      | GPSR0_D8);
+	pfc_reg_write(PFC_GPSR1, GPSR1_EX_WAIT0_A
+		      | GPSR1_A19
+		      | GPSR1_A18
+		      | GPSR1_A17
+		      | GPSR1_A16
+		      | GPSR1_A15
+		      | GPSR1_A14
+		      | GPSR1_A13
+		      | GPSR1_A12
+		      | GPSR1_A7
+		      | GPSR1_A6
+		      | GPSR1_A5
+		      | GPSR1_A4
+		      | GPSR1_A3
+		      | GPSR1_A2
+		      | GPSR1_A1
+		      | GPSR1_A0);
+	pfc_reg_write(PFC_GPSR2, GPSR2_AVB_AVTP_CAPTURE_A
+		      | GPSR2_AVB_AVTP_MATCH_A
+		      | GPSR2_AVB_LINK
+		      | GPSR2_AVB_PHY_INT
+		      | GPSR2_AVB_MDC
+		      | GPSR2_PWM2_A
+		      | GPSR2_PWM1_A
+		      | GPSR2_IRQ5
+		      | GPSR2_IRQ4
+		      | GPSR2_IRQ3
+		      | GPSR2_IRQ2
+		      | GPSR2_IRQ1
+		      | GPSR2_IRQ0);
+	pfc_reg_write(PFC_GPSR3, GPSR3_SD0_WP
+		      | GPSR3_SD0_CD
+		      | GPSR3_SD1_DAT3
+		      | GPSR3_SD1_DAT2
+		      | GPSR3_SD1_DAT1
+		      | GPSR3_SD1_DAT0
+		      | GPSR3_SD0_DAT3
+		      | GPSR3_SD0_DAT2
+		      | GPSR3_SD0_DAT1
+		      | GPSR3_SD0_DAT0
+		      | GPSR3_SD0_CMD
+		      | GPSR3_SD0_CLK);
+	pfc_reg_write(PFC_GPSR4, GPSR4_SD3_DAT7
+		      | GPSR4_SD3_DAT6
+		      | GPSR4_SD3_DAT3
+		      | GPSR4_SD3_DAT2
+		      | GPSR4_SD3_DAT1
+		      | GPSR4_SD3_DAT0
+		      | GPSR4_SD3_CMD
+		      | GPSR4_SD3_CLK
+		      | GPSR4_SD2_DS
+		      | GPSR4_SD2_DAT3
+		      | GPSR4_SD2_DAT2
+		      | GPSR4_SD2_DAT1
+		      | GPSR4_SD2_DAT0
+		      | GPSR4_SD2_CMD
+		      | GPSR4_SD2_CLK);
+	pfc_reg_write(PFC_GPSR5, GPSR5_MSIOF0_SS2
+		      | GPSR5_MSIOF0_SS1
+		      | GPSR5_MSIOF0_SYNC
+		      | GPSR5_HRTS0
+		      | GPSR5_HCTS0
+		      | GPSR5_HTX0
+		      | GPSR5_HRX0
+		      | GPSR5_HSCK0
+		      | GPSR5_RX2_A
+		      | GPSR5_TX2_A
+		      | GPSR5_SCK2
+		      | GPSR5_RTS1_TANS
+		      | GPSR5_CTS1
+		      | GPSR5_TX1_A
+		      | GPSR5_RX1_A
+		      | GPSR5_RTS0_TANS
+		      | GPSR5_SCK0);
+	pfc_reg_write(PFC_GPSR6, GPSR6_USB30_OVC
+		      | GPSR6_USB30_PWEN
+		      | GPSR6_USB1_OVC
+		      | GPSR6_USB1_PWEN
+		      | GPSR6_USB0_OVC
+		      | GPSR6_USB0_PWEN
+		      | GPSR6_AUDIO_CLKB_B
+		      | GPSR6_AUDIO_CLKA_A
+		      | GPSR6_SSI_SDATA8
+		      | GPSR6_SSI_SDATA7
+		      | GPSR6_SSI_WS78
+		      | GPSR6_SSI_SCK78
+		      | GPSR6_SSI_WS6
+		      | GPSR6_SSI_SCK6
+		      | GPSR6_SSI_SDATA4
+		      | GPSR6_SSI_WS4
+		      | GPSR6_SSI_SCK4
+		      | GPSR6_SSI_SDATA1_A
+		      | GPSR6_SSI_SDATA0
+		      | GPSR6_SSI_WS0129
+		      | GPSR6_SSI_SCK0129);
+	pfc_reg_write(PFC_GPSR7, GPSR7_HDMI1_CEC
+		      | GPSR7_HDMI0_CEC
+		      | GPSR7_AVS2
+		      | GPSR7_AVS1);
+
+	/* initialize POC control register */
+	pfc_reg_write(PFC_POCCTRL0, POC_SD3_DS_33V
+		      | POC_SD3_DAT7_33V
+		      | POC_SD3_DAT6_33V
+		      | POC_SD3_DAT5_33V
+		      | POC_SD3_DAT4_33V
+		      | POC_SD3_DAT3_33V
+		      | POC_SD3_DAT2_33V
+		      | POC_SD3_DAT1_33V
+		      | POC_SD3_DAT0_33V
+		      | POC_SD3_CMD_33V
+		      | POC_SD3_CLK_33V
+		      | POC_SD0_DAT3_33V
+		      | POC_SD0_DAT2_33V
+		      | POC_SD0_DAT1_33V
+		      | POC_SD0_DAT0_33V
+		      | POC_SD0_CMD_33V
+		      | POC_SD0_CLK_33V);
+
+	/* initialize DRV control register */
+	reg = mmio_read_32(PFC_DRVCTRL0);
+	reg = ((reg & DRVCTRL0_MASK) | DRVCTRL0_QSPI0_SPCLK(3)
+	       | DRVCTRL0_QSPI0_MOSI_IO0(3)
+	       | DRVCTRL0_QSPI0_MISO_IO1(3)
+	       | DRVCTRL0_QSPI0_IO2(3)
+	       | DRVCTRL0_QSPI0_IO3(3)
+	       | DRVCTRL0_QSPI0_SSL(3)
+	       | DRVCTRL0_QSPI1_SPCLK(3)
+	       | DRVCTRL0_QSPI1_MOSI_IO0(3));
+	pfc_reg_write(PFC_DRVCTRL0, reg);
+	reg = mmio_read_32(PFC_DRVCTRL1);
+	reg = ((reg & DRVCTRL1_MASK) | DRVCTRL1_QSPI1_MISO_IO1(3)
+	       | DRVCTRL1_QSPI1_IO2(3)
+	       | DRVCTRL1_QSPI1_IO3(3)
+	       | DRVCTRL1_QSPI1_SS(3)
+	       | DRVCTRL1_RPC_INT(3)
+	       | DRVCTRL1_RPC_WP(3)
+	       | DRVCTRL1_RPC_RESET(3)
+	       | DRVCTRL1_AVB_RX_CTL(7));
+	pfc_reg_write(PFC_DRVCTRL1, reg);
+	reg = mmio_read_32(PFC_DRVCTRL2);
+	reg = ((reg & DRVCTRL2_MASK) | DRVCTRL2_AVB_RXC(7)
+	       | DRVCTRL2_AVB_RD0(7)
+	       | DRVCTRL2_AVB_RD1(7)
+	       | DRVCTRL2_AVB_RD2(7)
+	       | DRVCTRL2_AVB_RD3(7)
+	       | DRVCTRL2_AVB_TX_CTL(3)
+	       | DRVCTRL2_AVB_TXC(3)
+	       | DRVCTRL2_AVB_TD0(3));
+	pfc_reg_write(PFC_DRVCTRL2, reg);
+	reg = mmio_read_32(PFC_DRVCTRL3);
+	reg = ((reg & DRVCTRL3_MASK) | DRVCTRL3_AVB_TD1(3)
+	       | DRVCTRL3_AVB_TD2(3)
+	       | DRVCTRL3_AVB_TD3(3)
+	       | DRVCTRL3_AVB_TXCREFCLK(7)
+	       | DRVCTRL3_AVB_MDIO(7)
+	       | DRVCTRL3_AVB_MDC(7)
+	       | DRVCTRL3_AVB_MAGIC(7)
+	       | DRVCTRL3_AVB_PHY_INT(7));
+	pfc_reg_write(PFC_DRVCTRL3, reg);
+	reg = mmio_read_32(PFC_DRVCTRL4);
+	reg = ((reg & DRVCTRL4_MASK) | DRVCTRL4_AVB_LINK(7)
+	       | DRVCTRL4_AVB_AVTP_MATCH(7)
+	       | DRVCTRL4_AVB_AVTP_CAPTURE(7)
+	       | DRVCTRL4_IRQ0(7)
+	       | DRVCTRL4_IRQ1(7)
+	       | DRVCTRL4_IRQ2(7)
+	       | DRVCTRL4_IRQ3(7)
+	       | DRVCTRL4_IRQ4(7));
+	pfc_reg_write(PFC_DRVCTRL4, reg);
+	reg = mmio_read_32(PFC_DRVCTRL5);
+	reg = ((reg & DRVCTRL5_MASK) | DRVCTRL5_IRQ5(7)
+	       | DRVCTRL5_PWM0(7)
+	       | DRVCTRL5_PWM1(7)
+	       | DRVCTRL5_PWM2(7)
+	       | DRVCTRL5_A0(3)
+	       | DRVCTRL5_A1(3)
+	       | DRVCTRL5_A2(3)
+	       | DRVCTRL5_A3(3));
+	pfc_reg_write(PFC_DRVCTRL5, reg);
+	reg = mmio_read_32(PFC_DRVCTRL6);
+	reg = ((reg & DRVCTRL6_MASK) | DRVCTRL6_A4(3)
+	       | DRVCTRL6_A5(3)
+	       | DRVCTRL6_A6(3)
+	       | DRVCTRL6_A7(3)
+	       | DRVCTRL6_A8(7)
+	       | DRVCTRL6_A9(7)
+	       | DRVCTRL6_A10(7)
+	       | DRVCTRL6_A11(7));
+	pfc_reg_write(PFC_DRVCTRL6, reg);
+	reg = mmio_read_32(PFC_DRVCTRL7);
+	reg = ((reg & DRVCTRL7_MASK) | DRVCTRL7_A12(3)
+	       | DRVCTRL7_A13(3)
+	       | DRVCTRL7_A14(3)
+	       | DRVCTRL7_A15(3)
+	       | DRVCTRL7_A16(3)
+	       | DRVCTRL7_A17(3)
+	       | DRVCTRL7_A18(3)
+	       | DRVCTRL7_A19(3));
+	pfc_reg_write(PFC_DRVCTRL7, reg);
+	reg = mmio_read_32(PFC_DRVCTRL8);
+	reg = ((reg & DRVCTRL8_MASK) | DRVCTRL8_CLKOUT(7)
+	       | DRVCTRL8_CS0(7)
+	       | DRVCTRL8_CS1_A2(7)
+	       | DRVCTRL8_BS(7)
+	       | DRVCTRL8_RD(7)
+	       | DRVCTRL8_RD_W(7)
+	       | DRVCTRL8_WE0(7)
+	       | DRVCTRL8_WE1(7));
+	pfc_reg_write(PFC_DRVCTRL8, reg);
+	reg = mmio_read_32(PFC_DRVCTRL9);
+	reg = ((reg & DRVCTRL9_MASK) | DRVCTRL9_EX_WAIT0(7)
+	       | DRVCTRL9_PRESETOU(7)
+	       | DRVCTRL9_D0(7)
+	       | DRVCTRL9_D1(7)
+	       | DRVCTRL9_D2(7)
+	       | DRVCTRL9_D3(7)
+	       | DRVCTRL9_D4(7)
+	       | DRVCTRL9_D5(7));
+	pfc_reg_write(PFC_DRVCTRL9, reg);
+	reg = mmio_read_32(PFC_DRVCTRL10);
+	reg = ((reg & DRVCTRL10_MASK) | DRVCTRL10_D6(7)
+	       | DRVCTRL10_D7(7)
+	       | DRVCTRL10_D8(3)
+	       | DRVCTRL10_D9(3)
+	       | DRVCTRL10_D10(3)
+	       | DRVCTRL10_D11(3)
+	       | DRVCTRL10_D12(3)
+	       | DRVCTRL10_D13(3));
+	pfc_reg_write(PFC_DRVCTRL10, reg);
+	reg = mmio_read_32(PFC_DRVCTRL11);
+	reg = ((reg & DRVCTRL11_MASK) | DRVCTRL11_D14(3)
+	       | DRVCTRL11_D15(3)
+	       | DRVCTRL11_AVS1(7)
+	       | DRVCTRL11_AVS2(7)
+	       | DRVCTRL11_HDMI0_CEC(7)
+	       | DRVCTRL11_HDMI1_CEC(7)
+	       | DRVCTRL11_DU_DOTCLKIN0(3)
+	       | DRVCTRL11_DU_DOTCLKIN1(3));
+	pfc_reg_write(PFC_DRVCTRL11, reg);
+	reg = mmio_read_32(PFC_DRVCTRL12);
+	reg = ((reg & DRVCTRL12_MASK) | DRVCTRL12_DU_DOTCLKIN2(3)
+	       | DRVCTRL12_DU_DOTCLKIN3(3)
+	       | DRVCTRL12_DU_FSCLKST(3)
+	       | DRVCTRL12_DU_TMS(3));
+	pfc_reg_write(PFC_DRVCTRL12, reg);
+	reg = mmio_read_32(PFC_DRVCTRL13);
+	reg = ((reg & DRVCTRL13_MASK) | DRVCTRL13_TDO(3)
+	       | DRVCTRL13_ASEBRK(3)
+	       | DRVCTRL13_SD0_CLK(2)
+	       | DRVCTRL13_SD0_CMD(2)
+	       | DRVCTRL13_SD0_DAT0(2)
+	       | DRVCTRL13_SD0_DAT1(2)
+	       | DRVCTRL13_SD0_DAT2(2)
+	       | DRVCTRL13_SD0_DAT3(2));
+	pfc_reg_write(PFC_DRVCTRL13, reg);
+	reg = mmio_read_32(PFC_DRVCTRL14);
+	reg = ((reg & DRVCTRL14_MASK) | DRVCTRL14_SD1_CLK(7)
+	       | DRVCTRL14_SD1_CMD(7)
+	       | DRVCTRL14_SD1_DAT0(5)
+	       | DRVCTRL14_SD1_DAT1(5)
+	       | DRVCTRL14_SD1_DAT2(5)
+	       | DRVCTRL14_SD1_DAT3(5)
+	       | DRVCTRL14_SD2_CLK(5)
+	       | DRVCTRL14_SD2_CMD(5));
+	pfc_reg_write(PFC_DRVCTRL14, reg);
+	reg = mmio_read_32(PFC_DRVCTRL15);
+	reg = ((reg & DRVCTRL15_MASK) | DRVCTRL15_SD2_DAT0(5)
+	       | DRVCTRL15_SD2_DAT1(5)
+	       | DRVCTRL15_SD2_DAT2(5)
+	       | DRVCTRL15_SD2_DAT3(5)
+	       | DRVCTRL15_SD2_DS(5)
+	       | DRVCTRL15_SD3_CLK(2)
+	       | DRVCTRL15_SD3_CMD(2)
+	       | DRVCTRL15_SD3_DAT0(2));
+	pfc_reg_write(PFC_DRVCTRL15, reg);
+	reg = mmio_read_32(PFC_DRVCTRL16);
+	reg = ((reg & DRVCTRL16_MASK) | DRVCTRL16_SD3_DAT1(2)
+	       | DRVCTRL16_SD3_DAT2(2)
+	       | DRVCTRL16_SD3_DAT3(2)
+	       | DRVCTRL16_SD3_DAT4(7)
+	       | DRVCTRL16_SD3_DAT5(7)
+	       | DRVCTRL16_SD3_DAT6(7)
+	       | DRVCTRL16_SD3_DAT7(7)
+	       | DRVCTRL16_SD3_DS(7));
+	pfc_reg_write(PFC_DRVCTRL16, reg);
+	reg = mmio_read_32(PFC_DRVCTRL17);
+	reg = ((reg & DRVCTRL17_MASK) | DRVCTRL17_SD0_CD(7)
+	       | DRVCTRL17_SD0_WP(7)
+	       | DRVCTRL17_SD1_CD(7)
+	       | DRVCTRL17_SD1_WP(7)
+	       | DRVCTRL17_SCK0(7)
+	       | DRVCTRL17_RX0(7)
+	       | DRVCTRL17_TX0(7)
+	       | DRVCTRL17_CTS0(7));
+	pfc_reg_write(PFC_DRVCTRL17, reg);
+	reg = mmio_read_32(PFC_DRVCTRL18);
+	reg = ((reg & DRVCTRL18_MASK) | DRVCTRL18_RTS0_TANS(7)
+	       | DRVCTRL18_RX1(7)
+	       | DRVCTRL18_TX1(7)
+	       | DRVCTRL18_CTS1(7)
+	       | DRVCTRL18_RTS1_TANS(7)
+	       | DRVCTRL18_SCK2(7)
+	       | DRVCTRL18_TX2(7)
+	       | DRVCTRL18_RX2(7));
+	pfc_reg_write(PFC_DRVCTRL18, reg);
+	reg = mmio_read_32(PFC_DRVCTRL19);
+	reg = ((reg & DRVCTRL19_MASK) | DRVCTRL19_HSCK0(7)
+	       | DRVCTRL19_HRX0(7)
+	       | DRVCTRL19_HTX0(7)
+	       | DRVCTRL19_HCTS0(7)
+	       | DRVCTRL19_HRTS0(7)
+	       | DRVCTRL19_MSIOF0_SCK(7)
+	       | DRVCTRL19_MSIOF0_SYNC(7)
+	       | DRVCTRL19_MSIOF0_SS1(7));
+	pfc_reg_write(PFC_DRVCTRL19, reg);
+	reg = mmio_read_32(PFC_DRVCTRL20);
+	reg = ((reg & DRVCTRL20_MASK) | DRVCTRL20_MSIOF0_TXD(7)
+	       | DRVCTRL20_MSIOF0_SS2(7)
+	       | DRVCTRL20_MSIOF0_RXD(7)
+	       | DRVCTRL20_MLB_CLK(7)
+	       | DRVCTRL20_MLB_SIG(7)
+	       | DRVCTRL20_MLB_DAT(7)
+	       | DRVCTRL20_MLB_REF(7)
+	       | DRVCTRL20_SSI_SCK0129(7));
+	pfc_reg_write(PFC_DRVCTRL20, reg);
+	reg = mmio_read_32(PFC_DRVCTRL21);
+	reg = ((reg & DRVCTRL21_MASK) | DRVCTRL21_SSI_WS0129(7)
+	       | DRVCTRL21_SSI_SDATA0(7)
+	       | DRVCTRL21_SSI_SDATA1(7)
+	       | DRVCTRL21_SSI_SDATA2(7)
+	       | DRVCTRL21_SSI_SCK34(7)
+	       | DRVCTRL21_SSI_WS34(7)
+	       | DRVCTRL21_SSI_SDATA3(7)
+	       | DRVCTRL21_SSI_SCK4(7));
+	pfc_reg_write(PFC_DRVCTRL21, reg);
+	reg = mmio_read_32(PFC_DRVCTRL22);
+	reg = ((reg & DRVCTRL22_MASK) | DRVCTRL22_SSI_WS4(7)
+	       | DRVCTRL22_SSI_SDATA4(7)
+	       | DRVCTRL22_SSI_SCK5(7)
+	       | DRVCTRL22_SSI_WS5(7)
+	       | DRVCTRL22_SSI_SDATA5(7)
+	       | DRVCTRL22_SSI_SCK6(7)
+	       | DRVCTRL22_SSI_WS6(7)
+	       | DRVCTRL22_SSI_SDATA6(7));
+	pfc_reg_write(PFC_DRVCTRL22, reg);
+	reg = mmio_read_32(PFC_DRVCTRL23);
+	reg = ((reg & DRVCTRL23_MASK) | DRVCTRL23_SSI_SCK78(7)
+	       | DRVCTRL23_SSI_WS78(7)
+	       | DRVCTRL23_SSI_SDATA7(7)
+	       | DRVCTRL23_SSI_SDATA8(7)
+	       | DRVCTRL23_SSI_SDATA9(7)
+	       | DRVCTRL23_AUDIO_CLKA(7)
+	       | DRVCTRL23_AUDIO_CLKB(7)
+	       | DRVCTRL23_USB0_PWEN(7));
+	pfc_reg_write(PFC_DRVCTRL23, reg);
+	reg = mmio_read_32(PFC_DRVCTRL24);
+	reg = ((reg & DRVCTRL24_MASK) | DRVCTRL24_USB0_OVC(7)
+	       | DRVCTRL24_USB1_PWEN(7)
+	       | DRVCTRL24_USB1_OVC(7)
+	       | DRVCTRL24_USB30_PWEN(7)
+	       | DRVCTRL24_USB30_OVC(7)
+	       | DRVCTRL24_USB31_PWEN(7)
+	       | DRVCTRL24_USB31_OVC(7));
+	pfc_reg_write(PFC_DRVCTRL24, reg);
+
+	/* initialize LSI pin pull-up/down control */
+	pfc_reg_write(PFC_PUD0, 0x00005FBFU);
+	pfc_reg_write(PFC_PUD1, 0x00300FFEU);
+	pfc_reg_write(PFC_PUD2, 0x330001E6U);
+	pfc_reg_write(PFC_PUD3, 0x000002E0U);
+	pfc_reg_write(PFC_PUD4, 0xFFFFFF00U);
+	pfc_reg_write(PFC_PUD5, 0x7F5FFF87U);
+	pfc_reg_write(PFC_PUD6, 0x00000055U);
+
+	/* initialize LSI pin pull-enable register */
+	pfc_reg_write(PFC_PUEN0, 0x00000FFFU);
+	pfc_reg_write(PFC_PUEN1, 0x00100234U);
+	pfc_reg_write(PFC_PUEN2, 0x000004C4U);
+	pfc_reg_write(PFC_PUEN3, 0x00000200U);
+	pfc_reg_write(PFC_PUEN4, 0x3E000000U);
+	pfc_reg_write(PFC_PUEN5, 0x1F000805U);
+	pfc_reg_write(PFC_PUEN6, 0x00000006U);
+
+	/* initialize positive/negative logic select */
+	mmio_write_32(GPIO_POSNEG0, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG1, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG2, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG3, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG4, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG5, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG6, 0x00000000U);
+
+	/* initialize general IO/interrupt switching */
+	mmio_write_32(GPIO_IOINTSEL0, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL1, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL2, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL3, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL4, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL5, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL6, 0x00000000U);
+
+	/* initialize general output register */
+	mmio_write_32(GPIO_OUTDT1, 0x00000000U);
+	mmio_write_32(GPIO_OUTDT2, 0x00000400U);
+	mmio_write_32(GPIO_OUTDT3, 0x0000C000U);
+	mmio_write_32(GPIO_OUTDT5, 0x00000006U);
+	mmio_write_32(GPIO_OUTDT6, 0x00003880U);
+
+	/* initialize general input/output switching */
+	mmio_write_32(GPIO_INOUTSEL0, 0x00000000U);
+	mmio_write_32(GPIO_INOUTSEL1, 0x01000A00U);
+	mmio_write_32(GPIO_INOUTSEL2, 0x00000400U);
+	mmio_write_32(GPIO_INOUTSEL3, 0x0000C000U);
+	mmio_write_32(GPIO_INOUTSEL4, 0x00000000U);
+#if (RCAR_GEN3_ULCB == 1)
+	mmio_write_32(GPIO_INOUTSEL5, 0x0000000EU);
+#else
+	mmio_write_32(GPIO_INOUTSEL5, 0x0000020EU);
+#endif
+	mmio_write_32(GPIO_INOUTSEL6, 0x00013880U);
+}
diff --git a/drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v1.h b/drivers/renesas/rcar/pfc/H3/pfc_init_h3_v1.h
similarity index 100%
rename from drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v1.h
rename to drivers/renesas/rcar/pfc/H3/pfc_init_h3_v1.h
diff --git a/drivers/renesas/rcar/pfc/H3/pfc_init_h3_v2.c b/drivers/renesas/rcar/pfc/H3/pfc_init_h3_v2.c
new file mode 100644
index 0000000..8bba3c1
--- /dev/null
+++ b/drivers/renesas/rcar/pfc/H3/pfc_init_h3_v2.c
@@ -0,0 +1,1218 @@
+/*
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>		/* for uint32_t */
+#include <lib/mmio.h>
+#include "pfc_init_h3_v2.h"
+#include "rcar_def.h"
+#include "../pfc_regs.h"
+
+#define GPSR0_D15		BIT(15)
+#define GPSR0_D14		BIT(14)
+#define GPSR0_D13		BIT(13)
+#define GPSR0_D12		BIT(12)
+#define GPSR0_D11		BIT(11)
+#define GPSR0_D10		BIT(10)
+#define GPSR0_D9		BIT(9)
+#define GPSR0_D8		BIT(8)
+#define GPSR0_D7		BIT(7)
+#define GPSR0_D6		BIT(6)
+#define GPSR0_D5		BIT(5)
+#define GPSR0_D4		BIT(4)
+#define GPSR0_D3		BIT(3)
+#define GPSR0_D2		BIT(2)
+#define GPSR0_D1		BIT(1)
+#define GPSR0_D0		BIT(0)
+#define GPSR1_CLKOUT		BIT(28)
+#define GPSR1_EX_WAIT0_A	BIT(27)
+#define GPSR1_WE1		BIT(26)
+#define GPSR1_WE0		BIT(25)
+#define GPSR1_RD_WR		BIT(24)
+#define GPSR1_RD		BIT(23)
+#define GPSR1_BS		BIT(22)
+#define GPSR1_CS1_A26		BIT(21)
+#define GPSR1_CS0		BIT(20)
+#define GPSR1_A19		BIT(19)
+#define GPSR1_A18		BIT(18)
+#define GPSR1_A17		BIT(17)
+#define GPSR1_A16		BIT(16)
+#define GPSR1_A15		BIT(15)
+#define GPSR1_A14		BIT(14)
+#define GPSR1_A13		BIT(13)
+#define GPSR1_A12		BIT(12)
+#define GPSR1_A11		BIT(11)
+#define GPSR1_A10		BIT(10)
+#define GPSR1_A9		BIT(9)
+#define GPSR1_A8		BIT(8)
+#define GPSR1_A7		BIT(7)
+#define GPSR1_A6		BIT(6)
+#define GPSR1_A5		BIT(5)
+#define GPSR1_A4		BIT(4)
+#define GPSR1_A3		BIT(3)
+#define GPSR1_A2		BIT(2)
+#define GPSR1_A1		BIT(1)
+#define GPSR1_A0		BIT(0)
+#define GPSR2_AVB_AVTP_CAPTURE_A	BIT(14)
+#define GPSR2_AVB_AVTP_MATCH_A	BIT(13)
+#define GPSR2_AVB_LINK		BIT(12)
+#define GPSR2_AVB_PHY_INT	BIT(11)
+#define GPSR2_AVB_MAGIC		BIT(10)
+#define GPSR2_AVB_MDC		BIT(9)
+#define GPSR2_PWM2_A		BIT(8)
+#define GPSR2_PWM1_A		BIT(7)
+#define GPSR2_PWM0		BIT(6)
+#define GPSR2_IRQ5		BIT(5)
+#define GPSR2_IRQ4		BIT(4)
+#define GPSR2_IRQ3		BIT(3)
+#define GPSR2_IRQ2		BIT(2)
+#define GPSR2_IRQ1		BIT(1)
+#define GPSR2_IRQ0		BIT(0)
+#define GPSR3_SD1_WP		BIT(15)
+#define GPSR3_SD1_CD		BIT(14)
+#define GPSR3_SD0_WP		BIT(13)
+#define GPSR3_SD0_CD		BIT(12)
+#define GPSR3_SD1_DAT3		BIT(11)
+#define GPSR3_SD1_DAT2		BIT(10)
+#define GPSR3_SD1_DAT1		BIT(9)
+#define GPSR3_SD1_DAT0		BIT(8)
+#define GPSR3_SD1_CMD		BIT(7)
+#define GPSR3_SD1_CLK		BIT(6)
+#define GPSR3_SD0_DAT3		BIT(5)
+#define GPSR3_SD0_DAT2		BIT(4)
+#define GPSR3_SD0_DAT1		BIT(3)
+#define GPSR3_SD0_DAT0		BIT(2)
+#define GPSR3_SD0_CMD		BIT(1)
+#define GPSR3_SD0_CLK		BIT(0)
+#define GPSR4_SD3_DS		BIT(17)
+#define GPSR4_SD3_DAT7		BIT(16)
+#define GPSR4_SD3_DAT6		BIT(15)
+#define GPSR4_SD3_DAT5		BIT(14)
+#define GPSR4_SD3_DAT4		BIT(13)
+#define GPSR4_SD3_DAT3		BIT(12)
+#define GPSR4_SD3_DAT2		BIT(11)
+#define GPSR4_SD3_DAT1		BIT(10)
+#define GPSR4_SD3_DAT0		BIT(9)
+#define GPSR4_SD3_CMD		BIT(8)
+#define GPSR4_SD3_CLK		BIT(7)
+#define GPSR4_SD2_DS		BIT(6)
+#define GPSR4_SD2_DAT3		BIT(5)
+#define GPSR4_SD2_DAT2		BIT(4)
+#define GPSR4_SD2_DAT1		BIT(3)
+#define GPSR4_SD2_DAT0		BIT(2)
+#define GPSR4_SD2_CMD		BIT(1)
+#define GPSR4_SD2_CLK		BIT(0)
+#define GPSR5_MLB_DAT		BIT(25)
+#define GPSR5_MLB_SIG		BIT(24)
+#define GPSR5_MLB_CLK		BIT(23)
+#define GPSR5_MSIOF0_RXD	BIT(22)
+#define GPSR5_MSIOF0_SS2	BIT(21)
+#define GPSR5_MSIOF0_TXD	BIT(20)
+#define GPSR5_MSIOF0_SS1	BIT(19)
+#define GPSR5_MSIOF0_SYNC	BIT(18)
+#define GPSR5_MSIOF0_SCK	BIT(17)
+#define GPSR5_HRTS0		BIT(16)
+#define GPSR5_HCTS0		BIT(15)
+#define GPSR5_HTX0		BIT(14)
+#define GPSR5_HRX0		BIT(13)
+#define GPSR5_HSCK0		BIT(12)
+#define GPSR5_RX2_A		BIT(11)
+#define GPSR5_TX2_A		BIT(10)
+#define GPSR5_SCK2		BIT(9)
+#define GPSR5_RTS1_TANS		BIT(8)
+#define GPSR5_CTS1		BIT(7)
+#define GPSR5_TX1_A		BIT(6)
+#define GPSR5_RX1_A		BIT(5)
+#define GPSR5_RTS0_TANS		BIT(4)
+#define GPSR5_CTS0		BIT(3)
+#define GPSR5_TX0		BIT(2)
+#define GPSR5_RX0		BIT(1)
+#define GPSR5_SCK0		BIT(0)
+#define GPSR6_USB31_OVC		BIT(31)
+#define GPSR6_USB31_PWEN	BIT(30)
+#define GPSR6_USB30_OVC		BIT(29)
+#define GPSR6_USB30_PWEN	BIT(28)
+#define GPSR6_USB1_OVC		BIT(27)
+#define GPSR6_USB1_PWEN		BIT(26)
+#define GPSR6_USB0_OVC		BIT(25)
+#define GPSR6_USB0_PWEN		BIT(24)
+#define GPSR6_AUDIO_CLKB_B	BIT(23)
+#define GPSR6_AUDIO_CLKA_A	BIT(22)
+#define GPSR6_SSI_SDATA9_A	BIT(21)
+#define GPSR6_SSI_SDATA8	BIT(20)
+#define GPSR6_SSI_SDATA7	BIT(19)
+#define GPSR6_SSI_WS78		BIT(18)
+#define GPSR6_SSI_SCK78		BIT(17)
+#define GPSR6_SSI_SDATA6	BIT(16)
+#define GPSR6_SSI_WS6		BIT(15)
+#define GPSR6_SSI_SCK6		BIT(14)
+#define GPSR6_SSI_SDATA5	BIT(13)
+#define GPSR6_SSI_WS5		BIT(12)
+#define GPSR6_SSI_SCK5		BIT(11)
+#define GPSR6_SSI_SDATA4	BIT(10)
+#define GPSR6_SSI_WS4		BIT(9)
+#define GPSR6_SSI_SCK4		BIT(8)
+#define GPSR6_SSI_SDATA3	BIT(7)
+#define GPSR6_SSI_WS34		BIT(6)
+#define GPSR6_SSI_SCK34		BIT(5)
+#define GPSR6_SSI_SDATA2_A	BIT(4)
+#define GPSR6_SSI_SDATA1_A	BIT(3)
+#define GPSR6_SSI_SDATA0	BIT(2)
+#define GPSR6_SSI_WS0129	BIT(1)
+#define GPSR6_SSI_SCK0129	BIT(0)
+#define GPSR7_HDMI1_CEC		BIT(3)
+#define GPSR7_HDMI0_CEC		BIT(2)
+#define GPSR7_AVS2		BIT(1)
+#define GPSR7_AVS1		BIT(0)
+
+#define IPSR_28_FUNC(x)		((uint32_t)(x) << 28U)
+#define IPSR_24_FUNC(x)		((uint32_t)(x) << 24U)
+#define IPSR_20_FUNC(x)		((uint32_t)(x) << 20U)
+#define IPSR_16_FUNC(x)		((uint32_t)(x) << 16U)
+#define IPSR_12_FUNC(x)		((uint32_t)(x) << 12U)
+#define IPSR_8_FUNC(x)		((uint32_t)(x) << 8U)
+#define IPSR_4_FUNC(x)		((uint32_t)(x) << 4U)
+#define IPSR_0_FUNC(x)		((uint32_t)(x) << 0U)
+
+#define POC_SD3_DS_33V		BIT(29)
+#define POC_SD3_DAT7_33V	BIT(28)
+#define POC_SD3_DAT6_33V	BIT(27)
+#define POC_SD3_DAT5_33V	BIT(26)
+#define POC_SD3_DAT4_33V	BIT(25)
+#define POC_SD3_DAT3_33V	BIT(24)
+#define POC_SD3_DAT2_33V	BIT(23)
+#define POC_SD3_DAT1_33V	BIT(22)
+#define POC_SD3_DAT0_33V	BIT(21)
+#define POC_SD3_CMD_33V		BIT(20)
+#define POC_SD3_CLK_33V		BIT(19)
+#define POC_SD2_DS_33V		BIT(18)
+#define POC_SD2_DAT3_33V	BIT(17)
+#define POC_SD2_DAT2_33V	BIT(16)
+#define POC_SD2_DAT1_33V	BIT(15)
+#define POC_SD2_DAT0_33V	BIT(14)
+#define POC_SD2_CMD_33V		BIT(13)
+#define POC_SD2_CLK_33V		BIT(12)
+#define POC_SD1_DAT3_33V	BIT(11)
+#define POC_SD1_DAT2_33V	BIT(10)
+#define POC_SD1_DAT1_33V	BIT(9)
+#define POC_SD1_DAT0_33V	BIT(8)
+#define POC_SD1_CMD_33V		BIT(7)
+#define POC_SD1_CLK_33V		BIT(6)
+#define POC_SD0_DAT3_33V	BIT(5)
+#define POC_SD0_DAT2_33V	BIT(4)
+#define POC_SD0_DAT1_33V	BIT(3)
+#define POC_SD0_DAT0_33V	BIT(2)
+#define POC_SD0_CMD_33V		BIT(1)
+#define POC_SD0_CLK_33V		BIT(0)
+
+#define DRVCTRL0_MASK		(0xCCCCCCCCU)
+#define DRVCTRL1_MASK		(0xCCCCCCC8U)
+#define DRVCTRL2_MASK		(0x88888888U)
+#define DRVCTRL3_MASK		(0x88888888U)
+#define DRVCTRL4_MASK		(0x88888888U)
+#define DRVCTRL5_MASK		(0x88888888U)
+#define DRVCTRL6_MASK		(0x88888888U)
+#define DRVCTRL7_MASK		(0x88888888U)
+#define DRVCTRL8_MASK		(0x88888888U)
+#define DRVCTRL9_MASK		(0x88888888U)
+#define DRVCTRL10_MASK		(0x88888888U)
+#define DRVCTRL11_MASK		(0x888888CCU)
+#define DRVCTRL12_MASK		(0xCCCFFFCFU)
+#define DRVCTRL13_MASK		(0xCC888888U)
+#define DRVCTRL14_MASK		(0x88888888U)
+#define DRVCTRL15_MASK		(0x88888888U)
+#define DRVCTRL16_MASK		(0x88888888U)
+#define DRVCTRL17_MASK		(0x88888888U)
+#define DRVCTRL18_MASK		(0x88888888U)
+#define DRVCTRL19_MASK		(0x88888888U)
+#define DRVCTRL20_MASK		(0x88888888U)
+#define DRVCTRL21_MASK		(0x88888888U)
+#define DRVCTRL22_MASK		(0x88888888U)
+#define DRVCTRL23_MASK		(0x88888888U)
+#define DRVCTRL24_MASK		(0x8888888FU)
+
+#define DRVCTRL0_QSPI0_SPCLK(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL0_QSPI0_MOSI_IO0(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL0_QSPI0_MISO_IO1(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL0_QSPI0_IO2(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL0_QSPI0_IO3(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL0_QSPI0_SSL(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL0_QSPI1_SPCLK(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL0_QSPI1_MOSI_IO0(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL1_QSPI1_MISO_IO1(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL1_QSPI1_IO2(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL1_QSPI1_IO3(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL1_QSPI1_SS(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL1_RPC_INT(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL1_RPC_WP(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL1_RPC_RESET(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL1_AVB_RX_CTL(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL2_AVB_RXC(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL2_AVB_RD0(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL2_AVB_RD1(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL2_AVB_RD2(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL2_AVB_RD3(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL2_AVB_TX_CTL(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL2_AVB_TXC(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL2_AVB_TD0(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL3_AVB_TD1(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL3_AVB_TD2(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL3_AVB_TD3(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL3_AVB_TXCREFCLK(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL3_AVB_MDIO(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL3_AVB_MDC(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL3_AVB_MAGIC(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL3_AVB_PHY_INT(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL4_AVB_LINK(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL4_AVB_AVTP_MATCH(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL4_AVB_AVTP_CAPTURE(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL4_IRQ0(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL4_IRQ1(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL4_IRQ2(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL4_IRQ3(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL4_IRQ4(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL5_IRQ5(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL5_PWM0(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL5_PWM1(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL5_PWM2(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL5_A0(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL5_A1(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL5_A2(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL5_A3(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL6_A4(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL6_A5(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL6_A6(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL6_A7(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL6_A8(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL6_A9(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL6_A10(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL6_A11(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL7_A12(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL7_A13(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL7_A14(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL7_A15(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL7_A16(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL7_A17(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL7_A18(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL7_A19(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL8_CLKOUT(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL8_CS0(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL8_CS1_A2(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL8_BS(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL8_RD(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL8_RD_W(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL8_WE0(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL8_WE1(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL9_EX_WAIT0(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL9_PRESETOU(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL9_D0(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL9_D1(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL9_D2(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL9_D3(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL9_D4(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL9_D5(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL10_D6(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL10_D7(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL10_D8(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL10_D9(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL10_D10(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL10_D11(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL10_D12(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL10_D13(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL11_D14(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL11_D15(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL11_AVS1(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL11_AVS2(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL11_HDMI0_CEC(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL11_HDMI1_CEC(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL11_DU_DOTCLKIN0(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL11_DU_DOTCLKIN1(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL12_DU_DOTCLKIN2(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL12_DU_DOTCLKIN3(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL12_DU_FSCLKST(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL12_DU_TMS(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL13_TDO(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL13_ASEBRK(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL13_SD0_CLK(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL13_SD0_CMD(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL13_SD0_DAT0(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL13_SD0_DAT1(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL13_SD0_DAT2(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL13_SD0_DAT3(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL14_SD1_CLK(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL14_SD1_CMD(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL14_SD1_DAT0(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL14_SD1_DAT1(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL14_SD1_DAT2(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL14_SD1_DAT3(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL14_SD2_CLK(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL14_SD2_CMD(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL15_SD2_DAT0(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL15_SD2_DAT1(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL15_SD2_DAT2(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL15_SD2_DAT3(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL15_SD2_DS(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL15_SD3_CLK(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL15_SD3_CMD(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL15_SD3_DAT0(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL16_SD3_DAT1(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL16_SD3_DAT2(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL16_SD3_DAT3(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL16_SD3_DAT4(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL16_SD3_DAT5(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL16_SD3_DAT6(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL16_SD3_DAT7(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL16_SD3_DS(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL17_SD0_CD(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL17_SD0_WP(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL17_SD1_CD(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL17_SD1_WP(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL17_SCK0(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL17_RX0(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL17_TX0(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL17_CTS0(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL18_RTS0_TANS(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL18_RX1(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL18_TX1(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL18_CTS1(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL18_RTS1_TANS(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL18_SCK2(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL18_TX2(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL18_RX2(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL19_HSCK0(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL19_HRX0(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL19_HTX0(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL19_HCTS0(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL19_HRTS0(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL19_MSIOF0_SCK(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL19_MSIOF0_SYNC(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL19_MSIOF0_SS1(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL20_MSIOF0_TXD(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL20_MSIOF0_SS2(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL20_MSIOF0_RXD(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL20_MLB_CLK(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL20_MLB_SIG(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL20_MLB_DAT(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL20_MLB_REF(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL20_SSI_SCK0129(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL21_SSI_WS0129(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL21_SSI_SDATA0(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL21_SSI_SDATA1(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL21_SSI_SDATA2(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL21_SSI_SCK34(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL21_SSI_WS34(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL21_SSI_SDATA3(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL21_SSI_SCK4(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL22_SSI_WS4(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL22_SSI_SDATA4(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL22_SSI_SCK5(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL22_SSI_WS5(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL22_SSI_SDATA5(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL22_SSI_SCK6(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL22_SSI_WS6(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL22_SSI_SDATA6(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL23_SSI_SCK78(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL23_SSI_WS78(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL23_SSI_SDATA7(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL23_SSI_SDATA8(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL23_SSI_SDATA9(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL23_AUDIO_CLKA(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL23_AUDIO_CLKB(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL23_USB0_PWEN(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL24_USB0_OVC(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL24_USB1_PWEN(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL24_USB1_OVC(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL24_USB30_PWEN(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL24_USB30_OVC(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL24_USB31_PWEN(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL24_USB31_OVC(x)	((uint32_t)(x) << 4U)
+
+#define MOD_SEL0_MSIOF3_A	((uint32_t)0U << 29U)
+#define MOD_SEL0_MSIOF3_B	((uint32_t)1U << 29U)
+#define MOD_SEL0_MSIOF3_C	((uint32_t)2U << 29U)
+#define MOD_SEL0_MSIOF3_D	((uint32_t)3U << 29U)
+#define MOD_SEL0_MSIOF3_E	((uint32_t)4U << 29U)
+#define MOD_SEL0_MSIOF2_A	((uint32_t)0U << 27U)
+#define MOD_SEL0_MSIOF2_B	((uint32_t)1U << 27U)
+#define MOD_SEL0_MSIOF2_C	((uint32_t)2U << 27U)
+#define MOD_SEL0_MSIOF2_D	((uint32_t)3U << 27U)
+#define MOD_SEL0_MSIOF1_A	((uint32_t)0U << 24U)
+#define MOD_SEL0_MSIOF1_B	((uint32_t)1U << 24U)
+#define MOD_SEL0_MSIOF1_C	((uint32_t)2U << 24U)
+#define MOD_SEL0_MSIOF1_D	((uint32_t)3U << 24U)
+#define MOD_SEL0_MSIOF1_E	((uint32_t)4U << 24U)
+#define MOD_SEL0_MSIOF1_F	((uint32_t)5U << 24U)
+#define MOD_SEL0_MSIOF1_G	((uint32_t)6U << 24U)
+#define MOD_SEL0_LBSC_A		((uint32_t)0U << 23U)
+#define MOD_SEL0_LBSC_B		((uint32_t)1U << 23U)
+#define MOD_SEL0_IEBUS_A	((uint32_t)0U << 22U)
+#define MOD_SEL0_IEBUS_B	((uint32_t)1U << 22U)
+#define MOD_SEL0_I2C2_A		((uint32_t)0U << 21U)
+#define MOD_SEL0_I2C2_B		((uint32_t)1U << 21U)
+#define MOD_SEL0_I2C1_A		((uint32_t)0U << 20U)
+#define MOD_SEL0_I2C1_B		((uint32_t)1U << 20U)
+#define MOD_SEL0_HSCIF4_A	((uint32_t)0U << 19U)
+#define MOD_SEL0_HSCIF4_B	((uint32_t)1U << 19U)
+#define MOD_SEL0_HSCIF3_A	((uint32_t)0U << 17U)
+#define MOD_SEL0_HSCIF3_B	((uint32_t)1U << 17U)
+#define MOD_SEL0_HSCIF3_C	((uint32_t)2U << 17U)
+#define MOD_SEL0_HSCIF3_D	((uint32_t)3U << 17U)
+#define MOD_SEL0_HSCIF1_A	((uint32_t)0U << 16U)
+#define MOD_SEL0_HSCIF1_B	((uint32_t)1U << 16U)
+#define MOD_SEL0_FSO_A		((uint32_t)0U << 15U)
+#define MOD_SEL0_FSO_B		((uint32_t)1U << 15U)
+#define MOD_SEL0_HSCIF2_A	((uint32_t)0U << 13U)
+#define MOD_SEL0_HSCIF2_B	((uint32_t)1U << 13U)
+#define MOD_SEL0_HSCIF2_C	((uint32_t)2U << 13U)
+#define MOD_SEL0_ETHERAVB_A	((uint32_t)0U << 12U)
+#define MOD_SEL0_ETHERAVB_B	((uint32_t)1U << 12U)
+#define MOD_SEL0_DRIF3_A	((uint32_t)0U << 11U)
+#define MOD_SEL0_DRIF3_B	((uint32_t)1U << 11U)
+#define MOD_SEL0_DRIF2_A	((uint32_t)0U << 10U)
+#define MOD_SEL0_DRIF2_B	((uint32_t)1U << 10U)
+#define MOD_SEL0_DRIF1_A	((uint32_t)0U << 8U)
+#define MOD_SEL0_DRIF1_B	((uint32_t)1U << 8U)
+#define MOD_SEL0_DRIF1_C	((uint32_t)2U << 8U)
+#define MOD_SEL0_DRIF0_A	((uint32_t)0U << 6U)
+#define MOD_SEL0_DRIF0_B	((uint32_t)1U << 6U)
+#define MOD_SEL0_DRIF0_C	((uint32_t)2U << 6U)
+#define MOD_SEL0_CANFD0_A	((uint32_t)0U << 5U)
+#define MOD_SEL0_CANFD0_B	((uint32_t)1U << 5U)
+#define MOD_SEL0_ADG_A_A	((uint32_t)0U << 3U)
+#define MOD_SEL0_ADG_A_B	((uint32_t)1U << 3U)
+#define MOD_SEL0_ADG_A_C	((uint32_t)2U << 3U)
+#define MOD_SEL1_TSIF1_A	((uint32_t)0U << 30U)
+#define MOD_SEL1_TSIF1_B	((uint32_t)1U << 30U)
+#define MOD_SEL1_TSIF1_C	((uint32_t)2U << 30U)
+#define MOD_SEL1_TSIF1_D	((uint32_t)3U << 30U)
+#define MOD_SEL1_TSIF0_A	((uint32_t)0U << 27U)
+#define MOD_SEL1_TSIF0_B	((uint32_t)1U << 27U)
+#define MOD_SEL1_TSIF0_C	((uint32_t)2U << 27U)
+#define MOD_SEL1_TSIF0_D	((uint32_t)3U << 27U)
+#define MOD_SEL1_TSIF0_E	((uint32_t)4U << 27U)
+#define MOD_SEL1_TIMER_TMU_A	((uint32_t)0U << 26U)
+#define MOD_SEL1_TIMER_TMU_B	((uint32_t)1U << 26U)
+#define MOD_SEL1_SSP1_1_A	((uint32_t)0U << 24U)
+#define MOD_SEL1_SSP1_1_B	((uint32_t)1U << 24U)
+#define MOD_SEL1_SSP1_1_C	((uint32_t)2U << 24U)
+#define MOD_SEL1_SSP1_1_D	((uint32_t)3U << 24U)
+#define MOD_SEL1_SSP1_0_A	((uint32_t)0U << 21U)
+#define MOD_SEL1_SSP1_0_B	((uint32_t)1U << 21U)
+#define MOD_SEL1_SSP1_0_C	((uint32_t)2U << 21U)
+#define MOD_SEL1_SSP1_0_D	((uint32_t)3U << 21U)
+#define MOD_SEL1_SSP1_0_E	((uint32_t)4U << 21U)
+#define MOD_SEL1_SSI_A		((uint32_t)0U << 20U)
+#define MOD_SEL1_SSI_B		((uint32_t)1U << 20U)
+#define MOD_SEL1_SPEED_PULSE_IF_A	((uint32_t)0U << 19U)
+#define MOD_SEL1_SPEED_PULSE_IF_B	((uint32_t)1U << 19U)
+#define MOD_SEL1_SIMCARD_A	((uint32_t)0U << 17U)
+#define MOD_SEL1_SIMCARD_B	((uint32_t)1U << 17U)
+#define MOD_SEL1_SIMCARD_C	((uint32_t)2U << 17U)
+#define MOD_SEL1_SIMCARD_D	((uint32_t)3U << 17U)
+#define MOD_SEL1_SDHI2_A	((uint32_t)0U << 16U)
+#define MOD_SEL1_SDHI2_B	((uint32_t)1U << 16U)
+#define MOD_SEL1_SCIF4_A	((uint32_t)0U << 14U)
+#define MOD_SEL1_SCIF4_B	((uint32_t)1U << 14U)
+#define MOD_SEL1_SCIF4_C	((uint32_t)2U << 14U)
+#define MOD_SEL1_SCIF3_A	((uint32_t)0U << 13U)
+#define MOD_SEL1_SCIF3_B	((uint32_t)1U << 13U)
+#define MOD_SEL1_SCIF2_A	((uint32_t)0U << 12U)
+#define MOD_SEL1_SCIF2_B	((uint32_t)1U << 12U)
+#define MOD_SEL1_SCIF1_A	((uint32_t)0U << 11U)
+#define MOD_SEL1_SCIF1_B	((uint32_t)1U << 11U)
+#define MOD_SEL1_SCIF_A		((uint32_t)0U << 10U)
+#define MOD_SEL1_SCIF_B		((uint32_t)1U << 10U)
+#define MOD_SEL1_REMOCON_A	((uint32_t)0U << 9U)
+#define MOD_SEL1_REMOCON_B	((uint32_t)1U << 9U)
+#define MOD_SEL1_RCAN0_A	((uint32_t)0U << 6U)
+#define MOD_SEL1_RCAN0_B	((uint32_t)1U << 6U)
+#define MOD_SEL1_PWM6_A		((uint32_t)0U << 5U)
+#define MOD_SEL1_PWM6_B		((uint32_t)1U << 5U)
+#define MOD_SEL1_PWM5_A		((uint32_t)0U << 4U)
+#define MOD_SEL1_PWM5_B		((uint32_t)1U << 4U)
+#define MOD_SEL1_PWM4_A		((uint32_t)0U << 3U)
+#define MOD_SEL1_PWM4_B		((uint32_t)1U << 3U)
+#define MOD_SEL1_PWM3_A		((uint32_t)0U << 2U)
+#define MOD_SEL1_PWM3_B		((uint32_t)1U << 2U)
+#define MOD_SEL1_PWM2_A		((uint32_t)0U << 1U)
+#define MOD_SEL1_PWM2_B		((uint32_t)1U << 1U)
+#define MOD_SEL1_PWM1_A		((uint32_t)0U << 0U)
+#define MOD_SEL1_PWM1_B		((uint32_t)1U << 0U)
+#define MOD_SEL2_I2C_5_A	((uint32_t)0U << 31U)
+#define MOD_SEL2_I2C_5_B	((uint32_t)1U << 31U)
+#define MOD_SEL2_I2C_3_A	((uint32_t)0U << 30U)
+#define MOD_SEL2_I2C_3_B	((uint32_t)1U << 30U)
+#define MOD_SEL2_I2C_0_A	((uint32_t)0U << 29U)
+#define MOD_SEL2_I2C_0_B	((uint32_t)1U << 29U)
+#define MOD_SEL2_FM_A		((uint32_t)0U << 27U)
+#define MOD_SEL2_FM_B		((uint32_t)1U << 27U)
+#define MOD_SEL2_FM_C		((uint32_t)2U << 27U)
+#define MOD_SEL2_FM_D		((uint32_t)3U << 27U)
+#define MOD_SEL2_SCIF5_A	((uint32_t)0U << 26U)
+#define MOD_SEL2_SCIF5_B	((uint32_t)1U << 26U)
+#define MOD_SEL2_I2C6_A		((uint32_t)0U << 23U)
+#define MOD_SEL2_I2C6_B		((uint32_t)1U << 23U)
+#define MOD_SEL2_I2C6_C		((uint32_t)2U << 23U)
+#define MOD_SEL2_NDF_A		((uint32_t)0U << 22U)
+#define MOD_SEL2_NDF_B		((uint32_t)1U << 22U)
+#define MOD_SEL2_SSI2_A		((uint32_t)0U << 21U)
+#define MOD_SEL2_SSI2_B		((uint32_t)1U << 21U)
+#define MOD_SEL2_SSI9_A		((uint32_t)0U << 20U)
+#define MOD_SEL2_SSI9_B		((uint32_t)1U << 20U)
+#define MOD_SEL2_TIMER_TMU2_A	((uint32_t)0U << 19U)
+#define MOD_SEL2_TIMER_TMU2_B	((uint32_t)1U << 19U)
+#define MOD_SEL2_ADG_B_A	((uint32_t)0U << 18U)
+#define MOD_SEL2_ADG_B_B	((uint32_t)1U << 18U)
+#define MOD_SEL2_ADG_C_A	((uint32_t)0U << 17U)
+#define MOD_SEL2_ADG_C_B	((uint32_t)1U << 17U)
+#define MOD_SEL2_VIN4_A		((uint32_t)0U << 0U)
+#define MOD_SEL2_VIN4_B		((uint32_t)1U << 0U)
+
+static void pfc_reg_write(uint32_t addr, uint32_t data)
+{
+	mmio_write_32(PFC_PMMR, ~data);
+	mmio_write_32((uintptr_t)addr, data);
+}
+
+void pfc_init_h3_v2(void)
+{
+	uint32_t reg;
+
+	/* initialize module select */
+	pfc_reg_write(PFC_MOD_SEL0, MOD_SEL0_MSIOF3_A
+		      | MOD_SEL0_MSIOF2_A
+		      | MOD_SEL0_MSIOF1_A
+		      | MOD_SEL0_LBSC_A
+		      | MOD_SEL0_IEBUS_A
+		      | MOD_SEL0_I2C2_A
+		      | MOD_SEL0_I2C1_A
+		      | MOD_SEL0_HSCIF4_A
+		      | MOD_SEL0_HSCIF3_A
+		      | MOD_SEL0_HSCIF1_A
+		      | MOD_SEL0_FSO_A
+		      | MOD_SEL0_HSCIF2_A
+		      | MOD_SEL0_ETHERAVB_A
+		      | MOD_SEL0_DRIF3_A
+		      | MOD_SEL0_DRIF2_A
+		      | MOD_SEL0_DRIF1_A
+		      | MOD_SEL0_DRIF0_A
+		      | MOD_SEL0_CANFD0_A
+		      | MOD_SEL0_ADG_A_A);
+	pfc_reg_write(PFC_MOD_SEL1, MOD_SEL1_TSIF1_A
+		      | MOD_SEL1_TSIF0_A
+		      | MOD_SEL1_TIMER_TMU_A
+		      | MOD_SEL1_SSP1_1_A
+		      | MOD_SEL1_SSP1_0_A
+		      | MOD_SEL1_SSI_A
+		      | MOD_SEL1_SPEED_PULSE_IF_A
+		      | MOD_SEL1_SIMCARD_A
+		      | MOD_SEL1_SDHI2_A
+		      | MOD_SEL1_SCIF4_A
+		      | MOD_SEL1_SCIF3_A
+		      | MOD_SEL1_SCIF2_A
+		      | MOD_SEL1_SCIF1_A
+		      | MOD_SEL1_SCIF_A
+		      | MOD_SEL1_REMOCON_A
+		      | MOD_SEL1_RCAN0_A
+		      | MOD_SEL1_PWM6_A
+		      | MOD_SEL1_PWM5_A
+		      | MOD_SEL1_PWM4_A
+		      | MOD_SEL1_PWM3_A
+		      | MOD_SEL1_PWM2_A
+		      | MOD_SEL1_PWM1_A);
+	pfc_reg_write(PFC_MOD_SEL2, MOD_SEL2_I2C_5_A
+		      | MOD_SEL2_I2C_3_A
+		      | MOD_SEL2_I2C_0_A
+		      | MOD_SEL2_FM_A
+		      | MOD_SEL2_SCIF5_A
+		      | MOD_SEL2_I2C6_A
+		      | MOD_SEL2_NDF_A
+		      | MOD_SEL2_SSI2_A
+		      | MOD_SEL2_SSI9_A
+		      | MOD_SEL2_TIMER_TMU2_A
+		      | MOD_SEL2_ADG_B_A
+		      | MOD_SEL2_ADG_C_A
+		      | MOD_SEL2_VIN4_A);
+
+	/* initialize peripheral function select */
+	pfc_reg_write(PFC_IPSR0, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR1, IPSR_28_FUNC(6)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(3)
+		      | IPSR_8_FUNC(3)
+		      | IPSR_4_FUNC(3)
+		      | IPSR_0_FUNC(3));
+	pfc_reg_write(PFC_IPSR2, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(6)
+		      | IPSR_20_FUNC(6)
+		      | IPSR_16_FUNC(6)
+		      | IPSR_12_FUNC(6)
+		      | IPSR_8_FUNC(6)
+		      | IPSR_4_FUNC(6)
+		      | IPSR_0_FUNC(6));
+	pfc_reg_write(PFC_IPSR3, IPSR_28_FUNC(6)
+		      | IPSR_24_FUNC(6)
+		      | IPSR_20_FUNC(6)
+		      | IPSR_16_FUNC(6)
+		      | IPSR_12_FUNC(6)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR4, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(6)
+		      | IPSR_4_FUNC(6)
+		      | IPSR_0_FUNC(6));
+	pfc_reg_write(PFC_IPSR5, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(6)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR6, IPSR_28_FUNC(6)
+		      | IPSR_24_FUNC(6)
+		      | IPSR_20_FUNC(6)
+		      | IPSR_16_FUNC(6)
+		      | IPSR_12_FUNC(6)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR7, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(6)
+		      | IPSR_4_FUNC(6)
+		      | IPSR_0_FUNC(6));
+	pfc_reg_write(PFC_IPSR8, IPSR_28_FUNC(1)
+		      | IPSR_24_FUNC(1)
+		      | IPSR_20_FUNC(1)
+		      | IPSR_16_FUNC(1)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR9, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR10, IPSR_28_FUNC(1)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR11, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(4)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(1));
+	pfc_reg_write(PFC_IPSR12, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(4)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR13, IPSR_28_FUNC(8)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(3)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR14, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(3)
+		      | IPSR_0_FUNC(8));
+	pfc_reg_write(PFC_IPSR15, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR16, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR17, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(1)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR18, IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+
+	/* initialize GPIO/perihperal function select */
+	pfc_reg_write(PFC_GPSR0, GPSR0_D15
+		      | GPSR0_D14
+		      | GPSR0_D13
+		      | GPSR0_D12
+		      | GPSR0_D11
+		      | GPSR0_D10
+		      | GPSR0_D9
+		      | GPSR0_D8);
+	pfc_reg_write(PFC_GPSR1, GPSR1_CLKOUT
+		      | GPSR1_EX_WAIT0_A
+		      | GPSR1_A19
+		      | GPSR1_A18
+		      | GPSR1_A17
+		      | GPSR1_A16
+		      | GPSR1_A15
+		      | GPSR1_A14
+		      | GPSR1_A13
+		      | GPSR1_A12
+		      | GPSR1_A7
+		      | GPSR1_A6
+		      | GPSR1_A5
+		      | GPSR1_A4
+		      | GPSR1_A3
+		      | GPSR1_A2
+		      | GPSR1_A1
+		      | GPSR1_A0);
+	pfc_reg_write(PFC_GPSR2, GPSR2_AVB_AVTP_CAPTURE_A
+		      | GPSR2_AVB_AVTP_MATCH_A
+		      | GPSR2_AVB_LINK
+		      | GPSR2_AVB_PHY_INT
+		      | GPSR2_AVB_MDC
+		      | GPSR2_PWM2_A
+		      | GPSR2_PWM1_A
+		      | GPSR2_IRQ5
+		      | GPSR2_IRQ4
+		      | GPSR2_IRQ3
+		      | GPSR2_IRQ2
+		      | GPSR2_IRQ1
+		      | GPSR2_IRQ0);
+	pfc_reg_write(PFC_GPSR3, GPSR3_SD0_WP
+		      | GPSR3_SD0_CD
+		      | GPSR3_SD1_DAT3
+		      | GPSR3_SD1_DAT2
+		      | GPSR3_SD1_DAT1
+		      | GPSR3_SD1_DAT0
+		      | GPSR3_SD0_DAT3
+		      | GPSR3_SD0_DAT2
+		      | GPSR3_SD0_DAT1
+		      | GPSR3_SD0_DAT0
+		      | GPSR3_SD0_CMD
+		      | GPSR3_SD0_CLK);
+	pfc_reg_write(PFC_GPSR4, GPSR4_SD3_DAT7
+		      | GPSR4_SD3_DAT6
+		      | GPSR4_SD3_DAT3
+		      | GPSR4_SD3_DAT2
+		      | GPSR4_SD3_DAT1
+		      | GPSR4_SD3_DAT0
+		      | GPSR4_SD3_CMD
+		      | GPSR4_SD3_CLK
+		      | GPSR4_SD2_DS
+		      | GPSR4_SD2_DAT3
+		      | GPSR4_SD2_DAT2
+		      | GPSR4_SD2_DAT1
+		      | GPSR4_SD2_DAT0
+		      | GPSR4_SD2_CMD
+		      | GPSR4_SD2_CLK);
+	pfc_reg_write(PFC_GPSR5, GPSR5_MSIOF0_SS2
+		      | GPSR5_MSIOF0_SS1
+		      | GPSR5_MSIOF0_SYNC
+		      | GPSR5_HRTS0
+		      | GPSR5_HCTS0
+		      | GPSR5_HTX0
+		      | GPSR5_HRX0
+		      | GPSR5_HSCK0
+		      | GPSR5_RX2_A
+		      | GPSR5_TX2_A
+		      | GPSR5_SCK2
+		      | GPSR5_RTS1_TANS
+		      | GPSR5_CTS1
+		      | GPSR5_TX1_A
+		      | GPSR5_RX1_A
+		      | GPSR5_RTS0_TANS
+		      | GPSR5_SCK0);
+	pfc_reg_write(PFC_GPSR6, GPSR6_USB30_OVC
+		      | GPSR6_USB30_PWEN
+		      | GPSR6_USB1_OVC
+		      | GPSR6_USB1_PWEN
+		      | GPSR6_USB0_OVC
+		      | GPSR6_USB0_PWEN
+		      | GPSR6_AUDIO_CLKB_B
+		      | GPSR6_AUDIO_CLKA_A
+		      | GPSR6_SSI_SDATA8
+		      | GPSR6_SSI_SDATA7
+		      | GPSR6_SSI_WS78
+		      | GPSR6_SSI_SCK78
+		      | GPSR6_SSI_WS6
+		      | GPSR6_SSI_SCK6
+		      | GPSR6_SSI_SDATA4
+		      | GPSR6_SSI_WS4
+		      | GPSR6_SSI_SCK4
+		      | GPSR6_SSI_SDATA1_A
+		      | GPSR6_SSI_SDATA0
+		      | GPSR6_SSI_WS0129
+		      | GPSR6_SSI_SCK0129);
+	pfc_reg_write(PFC_GPSR7, GPSR7_HDMI1_CEC
+		      | GPSR7_HDMI0_CEC
+		      | GPSR7_AVS2
+		      | GPSR7_AVS1);
+
+	/* initialize POC control register */
+	pfc_reg_write(PFC_POCCTRL0, POC_SD3_DS_33V
+		      | POC_SD3_DAT7_33V
+		      | POC_SD3_DAT6_33V
+		      | POC_SD3_DAT5_33V
+		      | POC_SD3_DAT4_33V
+		      | POC_SD3_DAT3_33V
+		      | POC_SD3_DAT2_33V
+		      | POC_SD3_DAT1_33V
+		      | POC_SD3_DAT0_33V
+		      | POC_SD3_CMD_33V
+		      | POC_SD3_CLK_33V
+		      | POC_SD0_DAT3_33V
+		      | POC_SD0_DAT2_33V
+		      | POC_SD0_DAT1_33V
+		      | POC_SD0_DAT0_33V
+		      | POC_SD0_CMD_33V
+		      | POC_SD0_CLK_33V);
+
+	/* initialize DRV control register */
+	reg = mmio_read_32(PFC_DRVCTRL0);
+	reg = ((reg & DRVCTRL0_MASK) | DRVCTRL0_QSPI0_SPCLK(3)
+	       | DRVCTRL0_QSPI0_MOSI_IO0(3)
+	       | DRVCTRL0_QSPI0_MISO_IO1(3)
+	       | DRVCTRL0_QSPI0_IO2(3)
+	       | DRVCTRL0_QSPI0_IO3(3)
+	       | DRVCTRL0_QSPI0_SSL(3)
+	       | DRVCTRL0_QSPI1_SPCLK(3)
+	       | DRVCTRL0_QSPI1_MOSI_IO0(3));
+	pfc_reg_write(PFC_DRVCTRL0, reg);
+	reg = mmio_read_32(PFC_DRVCTRL1);
+	reg = ((reg & DRVCTRL1_MASK) | DRVCTRL1_QSPI1_MISO_IO1(3)
+	       | DRVCTRL1_QSPI1_IO2(3)
+	       | DRVCTRL1_QSPI1_IO3(3)
+	       | DRVCTRL1_QSPI1_SS(3)
+	       | DRVCTRL1_RPC_INT(3)
+	       | DRVCTRL1_RPC_WP(3)
+	       | DRVCTRL1_RPC_RESET(3)
+	       | DRVCTRL1_AVB_RX_CTL(7));
+	pfc_reg_write(PFC_DRVCTRL1, reg);
+	reg = mmio_read_32(PFC_DRVCTRL2);
+	reg = ((reg & DRVCTRL2_MASK) | DRVCTRL2_AVB_RXC(7)
+	       | DRVCTRL2_AVB_RD0(7)
+	       | DRVCTRL2_AVB_RD1(7)
+	       | DRVCTRL2_AVB_RD2(7)
+	       | DRVCTRL2_AVB_RD3(7)
+	       | DRVCTRL2_AVB_TX_CTL(3)
+	       | DRVCTRL2_AVB_TXC(3)
+	       | DRVCTRL2_AVB_TD0(3));
+	pfc_reg_write(PFC_DRVCTRL2, reg);
+	reg = mmio_read_32(PFC_DRVCTRL3);
+	reg = ((reg & DRVCTRL3_MASK) | DRVCTRL3_AVB_TD1(3)
+	       | DRVCTRL3_AVB_TD2(3)
+	       | DRVCTRL3_AVB_TD3(3)
+	       | DRVCTRL3_AVB_TXCREFCLK(7)
+	       | DRVCTRL3_AVB_MDIO(7)
+	       | DRVCTRL3_AVB_MDC(7)
+	       | DRVCTRL3_AVB_MAGIC(7)
+	       | DRVCTRL3_AVB_PHY_INT(7));
+	pfc_reg_write(PFC_DRVCTRL3, reg);
+	reg = mmio_read_32(PFC_DRVCTRL4);
+	reg = ((reg & DRVCTRL4_MASK) | DRVCTRL4_AVB_LINK(7)
+	       | DRVCTRL4_AVB_AVTP_MATCH(7)
+	       | DRVCTRL4_AVB_AVTP_CAPTURE(7)
+	       | DRVCTRL4_IRQ0(7)
+	       | DRVCTRL4_IRQ1(7)
+	       | DRVCTRL4_IRQ2(7)
+	       | DRVCTRL4_IRQ3(7)
+	       | DRVCTRL4_IRQ4(7));
+	pfc_reg_write(PFC_DRVCTRL4, reg);
+	reg = mmio_read_32(PFC_DRVCTRL5);
+	reg = ((reg & DRVCTRL5_MASK) | DRVCTRL5_IRQ5(7)
+	       | DRVCTRL5_PWM0(7)
+	       | DRVCTRL5_PWM1(7)
+	       | DRVCTRL5_PWM2(7)
+	       | DRVCTRL5_A0(3)
+	       | DRVCTRL5_A1(3)
+	       | DRVCTRL5_A2(3)
+	       | DRVCTRL5_A3(3));
+	pfc_reg_write(PFC_DRVCTRL5, reg);
+	reg = mmio_read_32(PFC_DRVCTRL6);
+	reg = ((reg & DRVCTRL6_MASK) | DRVCTRL6_A4(3)
+	       | DRVCTRL6_A5(3)
+	       | DRVCTRL6_A6(3)
+	       | DRVCTRL6_A7(3)
+	       | DRVCTRL6_A8(7)
+	       | DRVCTRL6_A9(7)
+	       | DRVCTRL6_A10(7)
+	       | DRVCTRL6_A11(7));
+	pfc_reg_write(PFC_DRVCTRL6, reg);
+	reg = mmio_read_32(PFC_DRVCTRL7);
+	reg = ((reg & DRVCTRL7_MASK) | DRVCTRL7_A12(3)
+	       | DRVCTRL7_A13(3)
+	       | DRVCTRL7_A14(3)
+	       | DRVCTRL7_A15(3)
+	       | DRVCTRL7_A16(3)
+	       | DRVCTRL7_A17(3)
+	       | DRVCTRL7_A18(3)
+	       | DRVCTRL7_A19(3));
+	pfc_reg_write(PFC_DRVCTRL7, reg);
+	reg = mmio_read_32(PFC_DRVCTRL8);
+	reg = ((reg & DRVCTRL8_MASK) | DRVCTRL8_CLKOUT(7)
+	       | DRVCTRL8_CS0(7)
+	       | DRVCTRL8_CS1_A2(7)
+	       | DRVCTRL8_BS(7)
+	       | DRVCTRL8_RD(7)
+	       | DRVCTRL8_RD_W(7)
+	       | DRVCTRL8_WE0(7)
+	       | DRVCTRL8_WE1(7));
+	pfc_reg_write(PFC_DRVCTRL8, reg);
+	reg = mmio_read_32(PFC_DRVCTRL9);
+	reg = ((reg & DRVCTRL9_MASK) | DRVCTRL9_EX_WAIT0(7)
+	       | DRVCTRL9_PRESETOU(7)
+	       | DRVCTRL9_D0(7)
+	       | DRVCTRL9_D1(7)
+	       | DRVCTRL9_D2(7)
+	       | DRVCTRL9_D3(7)
+	       | DRVCTRL9_D4(7)
+	       | DRVCTRL9_D5(7));
+	pfc_reg_write(PFC_DRVCTRL9, reg);
+	reg = mmio_read_32(PFC_DRVCTRL10);
+	reg = ((reg & DRVCTRL10_MASK) | DRVCTRL10_D6(7)
+	       | DRVCTRL10_D7(7)
+	       | DRVCTRL10_D8(3)
+	       | DRVCTRL10_D9(3)
+	       | DRVCTRL10_D10(3)
+	       | DRVCTRL10_D11(3)
+	       | DRVCTRL10_D12(3)
+	       | DRVCTRL10_D13(3));
+	pfc_reg_write(PFC_DRVCTRL10, reg);
+	reg = mmio_read_32(PFC_DRVCTRL11);
+	reg = ((reg & DRVCTRL11_MASK) | DRVCTRL11_D14(3)
+	       | DRVCTRL11_D15(3)
+	       | DRVCTRL11_AVS1(7)
+	       | DRVCTRL11_AVS2(7)
+	       | DRVCTRL11_HDMI0_CEC(7)
+	       | DRVCTRL11_HDMI1_CEC(7)
+	       | DRVCTRL11_DU_DOTCLKIN0(3)
+	       | DRVCTRL11_DU_DOTCLKIN1(3));
+	pfc_reg_write(PFC_DRVCTRL11, reg);
+	reg = mmio_read_32(PFC_DRVCTRL12);
+	reg = ((reg & DRVCTRL12_MASK) | DRVCTRL12_DU_DOTCLKIN2(3)
+	       | DRVCTRL12_DU_DOTCLKIN3(3)
+	       | DRVCTRL12_DU_FSCLKST(3)
+	       | DRVCTRL12_DU_TMS(3));
+	pfc_reg_write(PFC_DRVCTRL12, reg);
+	reg = mmio_read_32(PFC_DRVCTRL13);
+	reg = ((reg & DRVCTRL13_MASK) | DRVCTRL13_TDO(3)
+	       | DRVCTRL13_ASEBRK(3)
+	       | DRVCTRL13_SD0_CLK(7)
+	       | DRVCTRL13_SD0_CMD(7)
+	       | DRVCTRL13_SD0_DAT0(7)
+	       | DRVCTRL13_SD0_DAT1(7)
+	       | DRVCTRL13_SD0_DAT2(7)
+	       | DRVCTRL13_SD0_DAT3(7));
+	pfc_reg_write(PFC_DRVCTRL13, reg);
+	reg = mmio_read_32(PFC_DRVCTRL14);
+	reg = ((reg & DRVCTRL14_MASK) | DRVCTRL14_SD1_CLK(7)
+	       | DRVCTRL14_SD1_CMD(7)
+	       | DRVCTRL14_SD1_DAT0(5)
+	       | DRVCTRL14_SD1_DAT1(5)
+	       | DRVCTRL14_SD1_DAT2(5)
+	       | DRVCTRL14_SD1_DAT3(5)
+	       | DRVCTRL14_SD2_CLK(5)
+	       | DRVCTRL14_SD2_CMD(5));
+	pfc_reg_write(PFC_DRVCTRL14, reg);
+	reg = mmio_read_32(PFC_DRVCTRL15);
+	reg = ((reg & DRVCTRL15_MASK) | DRVCTRL15_SD2_DAT0(5)
+	       | DRVCTRL15_SD2_DAT1(5)
+	       | DRVCTRL15_SD2_DAT2(5)
+	       | DRVCTRL15_SD2_DAT3(5)
+	       | DRVCTRL15_SD2_DS(5)
+	       | DRVCTRL15_SD3_CLK(7)
+	       | DRVCTRL15_SD3_CMD(7)
+	       | DRVCTRL15_SD3_DAT0(7));
+	pfc_reg_write(PFC_DRVCTRL15, reg);
+	reg = mmio_read_32(PFC_DRVCTRL16);
+	reg = ((reg & DRVCTRL16_MASK) | DRVCTRL16_SD3_DAT1(7)
+	       | DRVCTRL16_SD3_DAT2(7)
+	       | DRVCTRL16_SD3_DAT3(7)
+	       | DRVCTRL16_SD3_DAT4(7)
+	       | DRVCTRL16_SD3_DAT5(7)
+	       | DRVCTRL16_SD3_DAT6(7)
+	       | DRVCTRL16_SD3_DAT7(7)
+	       | DRVCTRL16_SD3_DS(7));
+	pfc_reg_write(PFC_DRVCTRL16, reg);
+	reg = mmio_read_32(PFC_DRVCTRL17);
+	reg = ((reg & DRVCTRL17_MASK) | DRVCTRL17_SD0_CD(7)
+	       | DRVCTRL17_SD0_WP(7)
+	       | DRVCTRL17_SD1_CD(7)
+	       | DRVCTRL17_SD1_WP(7)
+	       | DRVCTRL17_SCK0(7)
+	       | DRVCTRL17_RX0(7)
+	       | DRVCTRL17_TX0(7)
+	       | DRVCTRL17_CTS0(7));
+	pfc_reg_write(PFC_DRVCTRL17, reg);
+	reg = mmio_read_32(PFC_DRVCTRL18);
+	reg = ((reg & DRVCTRL18_MASK) | DRVCTRL18_RTS0_TANS(7)
+	       | DRVCTRL18_RX1(7)
+	       | DRVCTRL18_TX1(7)
+	       | DRVCTRL18_CTS1(7)
+	       | DRVCTRL18_RTS1_TANS(7)
+	       | DRVCTRL18_SCK2(7)
+	       | DRVCTRL18_TX2(7)
+	       | DRVCTRL18_RX2(7));
+	pfc_reg_write(PFC_DRVCTRL18, reg);
+	reg = mmio_read_32(PFC_DRVCTRL19);
+	reg = ((reg & DRVCTRL19_MASK) | DRVCTRL19_HSCK0(7)
+	       | DRVCTRL19_HRX0(7)
+	       | DRVCTRL19_HTX0(7)
+	       | DRVCTRL19_HCTS0(7)
+	       | DRVCTRL19_HRTS0(7)
+	       | DRVCTRL19_MSIOF0_SCK(7)
+	       | DRVCTRL19_MSIOF0_SYNC(7)
+	       | DRVCTRL19_MSIOF0_SS1(7));
+	pfc_reg_write(PFC_DRVCTRL19, reg);
+	reg = mmio_read_32(PFC_DRVCTRL20);
+	reg = ((reg & DRVCTRL20_MASK) | DRVCTRL20_MSIOF0_TXD(7)
+	       | DRVCTRL20_MSIOF0_SS2(7)
+	       | DRVCTRL20_MSIOF0_RXD(7)
+	       | DRVCTRL20_MLB_CLK(7)
+	       | DRVCTRL20_MLB_SIG(7)
+	       | DRVCTRL20_MLB_DAT(7)
+	       | DRVCTRL20_MLB_REF(7)
+	       | DRVCTRL20_SSI_SCK0129(7));
+	pfc_reg_write(PFC_DRVCTRL20, reg);
+	reg = mmio_read_32(PFC_DRVCTRL21);
+	reg = ((reg & DRVCTRL21_MASK) | DRVCTRL21_SSI_WS0129(7)
+	       | DRVCTRL21_SSI_SDATA0(7)
+	       | DRVCTRL21_SSI_SDATA1(7)
+	       | DRVCTRL21_SSI_SDATA2(7)
+	       | DRVCTRL21_SSI_SCK34(7)
+	       | DRVCTRL21_SSI_WS34(7)
+	       | DRVCTRL21_SSI_SDATA3(7)
+	       | DRVCTRL21_SSI_SCK4(7));
+	pfc_reg_write(PFC_DRVCTRL21, reg);
+	reg = mmio_read_32(PFC_DRVCTRL22);
+	reg = ((reg & DRVCTRL22_MASK) | DRVCTRL22_SSI_WS4(7)
+	       | DRVCTRL22_SSI_SDATA4(7)
+	       | DRVCTRL22_SSI_SCK5(7)
+	       | DRVCTRL22_SSI_WS5(7)
+	       | DRVCTRL22_SSI_SDATA5(7)
+	       | DRVCTRL22_SSI_SCK6(7)
+	       | DRVCTRL22_SSI_WS6(7)
+	       | DRVCTRL22_SSI_SDATA6(7));
+	pfc_reg_write(PFC_DRVCTRL22, reg);
+	reg = mmio_read_32(PFC_DRVCTRL23);
+	reg = ((reg & DRVCTRL23_MASK) | DRVCTRL23_SSI_SCK78(7)
+	       | DRVCTRL23_SSI_WS78(7)
+	       | DRVCTRL23_SSI_SDATA7(7)
+	       | DRVCTRL23_SSI_SDATA8(7)
+	       | DRVCTRL23_SSI_SDATA9(7)
+	       | DRVCTRL23_AUDIO_CLKA(7)
+	       | DRVCTRL23_AUDIO_CLKB(7)
+	       | DRVCTRL23_USB0_PWEN(7));
+	pfc_reg_write(PFC_DRVCTRL23, reg);
+	reg = mmio_read_32(PFC_DRVCTRL24);
+	reg = ((reg & DRVCTRL24_MASK) | DRVCTRL24_USB0_OVC(7)
+	       | DRVCTRL24_USB1_PWEN(7)
+	       | DRVCTRL24_USB1_OVC(7)
+	       | DRVCTRL24_USB30_PWEN(7)
+	       | DRVCTRL24_USB30_OVC(7)
+	       | DRVCTRL24_USB31_PWEN(7)
+	       | DRVCTRL24_USB31_OVC(7));
+	pfc_reg_write(PFC_DRVCTRL24, reg);
+
+	/* initialize LSI pin pull-up/down control */
+	pfc_reg_write(PFC_PUD0, 0x00005FBFU);
+	pfc_reg_write(PFC_PUD1, 0x00300FFEU);
+	pfc_reg_write(PFC_PUD2, 0x330001E6U);
+	pfc_reg_write(PFC_PUD3, 0x000002E0U);
+	pfc_reg_write(PFC_PUD4, 0xFFFFFF00U);
+	pfc_reg_write(PFC_PUD5, 0x7F5FFF87U);
+	pfc_reg_write(PFC_PUD6, 0x00000055U);
+
+	/* initialize LSI pin pull-enable register */
+	pfc_reg_write(PFC_PUEN0, 0x00000FFFU);
+	pfc_reg_write(PFC_PUEN1, 0x00100234U);
+	pfc_reg_write(PFC_PUEN2, 0x000004C4U);
+	pfc_reg_write(PFC_PUEN3, 0x00000200U);
+	pfc_reg_write(PFC_PUEN4, 0x3E000000U);
+	pfc_reg_write(PFC_PUEN5, 0x1F000805U);
+	pfc_reg_write(PFC_PUEN6, 0x00000006U);
+
+	/* initialize positive/negative logic select */
+	mmio_write_32(GPIO_POSNEG0, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG1, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG2, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG3, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG4, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG5, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG6, 0x00000000U);
+
+	/* initialize general IO/interrupt switching */
+	mmio_write_32(GPIO_IOINTSEL0, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL1, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL2, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL3, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL4, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL5, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL6, 0x00000000U);
+
+	/* initialize general output register */
+	mmio_write_32(GPIO_OUTDT1, 0x00000000U);
+	mmio_write_32(GPIO_OUTDT2, 0x00000400U);
+	mmio_write_32(GPIO_OUTDT3, 0x0000C000U);
+	mmio_write_32(GPIO_OUTDT5, 0x00000006U);
+	mmio_write_32(GPIO_OUTDT6, 0x00003880U);
+
+	/* initialize general input/output switching */
+	mmio_write_32(GPIO_INOUTSEL0, 0x00000000U);
+	mmio_write_32(GPIO_INOUTSEL1, 0x01000A00U);
+	mmio_write_32(GPIO_INOUTSEL2, 0x00000400U);
+	mmio_write_32(GPIO_INOUTSEL3, 0x0000C000U);
+	mmio_write_32(GPIO_INOUTSEL4, 0x00000000U);
+#if (RCAR_GEN3_ULCB == 1)
+	mmio_write_32(GPIO_INOUTSEL5, 0x0000000EU);
+#else
+	mmio_write_32(GPIO_INOUTSEL5, 0x0000020EU);
+#endif
+	mmio_write_32(GPIO_INOUTSEL6, 0x00013880U);
+}
diff --git a/drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v2.h b/drivers/renesas/rcar/pfc/H3/pfc_init_h3_v2.h
similarity index 100%
rename from drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v2.h
rename to drivers/renesas/rcar/pfc/H3/pfc_init_h3_v2.h
diff --git a/drivers/renesas/rcar/pfc/M3/pfc_init_m3.c b/drivers/renesas/rcar/pfc/M3/pfc_init_m3.c
new file mode 100644
index 0000000..380899d
--- /dev/null
+++ b/drivers/renesas/rcar/pfc/M3/pfc_init_m3.c
@@ -0,0 +1,1313 @@
+/*
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>		/* for uint32_t */
+
+#include <lib/mmio.h>
+
+#include "pfc_init_m3.h"
+#include "rcar_def.h"
+#include "rcar_private.h"
+#include "../pfc_regs.h"
+
+#define GPSR0_D15		BIT(15)
+#define GPSR0_D14		BIT(14)
+#define GPSR0_D13		BIT(13)
+#define GPSR0_D12		BIT(12)
+#define GPSR0_D11		BIT(11)
+#define GPSR0_D10		BIT(10)
+#define GPSR0_D9		BIT(9)
+#define GPSR0_D8		BIT(8)
+#define GPSR0_D7		BIT(7)
+#define GPSR0_D6		BIT(6)
+#define GPSR0_D5		BIT(5)
+#define GPSR0_D4		BIT(4)
+#define GPSR0_D3		BIT(3)
+#define GPSR0_D2		BIT(2)
+#define GPSR0_D1		BIT(1)
+#define GPSR0_D0		BIT(0)
+#define GPSR1_CLKOUT		BIT(28)
+#define GPSR1_EX_WAIT0_A	BIT(27)
+#define GPSR1_WE1		BIT(26)
+#define GPSR1_WE0		BIT(25)
+#define GPSR1_RD_WR		BIT(24)
+#define GPSR1_RD		BIT(23)
+#define GPSR1_BS		BIT(22)
+#define GPSR1_CS1_A26		BIT(21)
+#define GPSR1_CS0		BIT(20)
+#define GPSR1_A19		BIT(19)
+#define GPSR1_A18		BIT(18)
+#define GPSR1_A17		BIT(17)
+#define GPSR1_A16		BIT(16)
+#define GPSR1_A15		BIT(15)
+#define GPSR1_A14		BIT(14)
+#define GPSR1_A13		BIT(13)
+#define GPSR1_A12		BIT(12)
+#define GPSR1_A11		BIT(11)
+#define GPSR1_A10		BIT(10)
+#define GPSR1_A9		BIT(9)
+#define GPSR1_A8		BIT(8)
+#define GPSR1_A7		BIT(7)
+#define GPSR1_A6		BIT(6)
+#define GPSR1_A5		BIT(5)
+#define GPSR1_A4		BIT(4)
+#define GPSR1_A3		BIT(3)
+#define GPSR1_A2		BIT(2)
+#define GPSR1_A1		BIT(1)
+#define GPSR1_A0		BIT(0)
+#define GPSR2_AVB_AVTP_CAPTURE_A	BIT(14)
+#define GPSR2_AVB_AVTP_MATCH_A	BIT(13)
+#define GPSR2_AVB_LINK		BIT(12)
+#define GPSR2_AVB_PHY_INT	BIT(11)
+#define GPSR2_AVB_MAGIC		BIT(10)
+#define GPSR2_AVB_MDC		BIT(9)
+#define GPSR2_PWM2_A		BIT(8)
+#define GPSR2_PWM1_A		BIT(7)
+#define GPSR2_PWM0		BIT(6)
+#define GPSR2_IRQ5		BIT(5)
+#define GPSR2_IRQ4		BIT(4)
+#define GPSR2_IRQ3		BIT(3)
+#define GPSR2_IRQ2		BIT(2)
+#define GPSR2_IRQ1		BIT(1)
+#define GPSR2_IRQ0		BIT(0)
+#define GPSR3_SD1_WP		BIT(15)
+#define GPSR3_SD1_CD		BIT(14)
+#define GPSR3_SD0_WP		BIT(13)
+#define GPSR3_SD0_CD		BIT(12)
+#define GPSR3_SD1_DAT3		BIT(11)
+#define GPSR3_SD1_DAT2		BIT(10)
+#define GPSR3_SD1_DAT1		BIT(9)
+#define GPSR3_SD1_DAT0		BIT(8)
+#define GPSR3_SD1_CMD		BIT(7)
+#define GPSR3_SD1_CLK		BIT(6)
+#define GPSR3_SD0_DAT3		BIT(5)
+#define GPSR3_SD0_DAT2		BIT(4)
+#define GPSR3_SD0_DAT1		BIT(3)
+#define GPSR3_SD0_DAT0		BIT(2)
+#define GPSR3_SD0_CMD		BIT(1)
+#define GPSR3_SD0_CLK		BIT(0)
+#define GPSR4_SD3_DS		BIT(17)
+#define GPSR4_SD3_DAT7		BIT(16)
+#define GPSR4_SD3_DAT6		BIT(15)
+#define GPSR4_SD3_DAT5		BIT(14)
+#define GPSR4_SD3_DAT4		BIT(13)
+#define GPSR4_SD3_DAT3		BIT(12)
+#define GPSR4_SD3_DAT2		BIT(11)
+#define GPSR4_SD3_DAT1		BIT(10)
+#define GPSR4_SD3_DAT0		BIT(9)
+#define GPSR4_SD3_CMD		BIT(8)
+#define GPSR4_SD3_CLK		BIT(7)
+#define GPSR4_SD2_DS		BIT(6)
+#define GPSR4_SD2_DAT3		BIT(5)
+#define GPSR4_SD2_DAT2		BIT(4)
+#define GPSR4_SD2_DAT1		BIT(3)
+#define GPSR4_SD2_DAT0		BIT(2)
+#define GPSR4_SD2_CMD		BIT(1)
+#define GPSR4_SD2_CLK		BIT(0)
+#define GPSR5_MLB_DAT		BIT(25)
+#define GPSR5_MLB_SIG		BIT(24)
+#define GPSR5_MLB_CLK		BIT(23)
+#define GPSR5_MSIOF0_RXD	BIT(22)
+#define GPSR5_MSIOF0_SS2	BIT(21)
+#define GPSR5_MSIOF0_TXD	BIT(20)
+#define GPSR5_MSIOF0_SS1	BIT(19)
+#define GPSR5_MSIOF0_SYNC	BIT(18)
+#define GPSR5_MSIOF0_SCK	BIT(17)
+#define GPSR5_HRTS0		BIT(16)
+#define GPSR5_HCTS0		BIT(15)
+#define GPSR5_HTX0		BIT(14)
+#define GPSR5_HRX0		BIT(13)
+#define GPSR5_HSCK0		BIT(12)
+#define GPSR5_RX2_A		BIT(11)
+#define GPSR5_TX2_A		BIT(10)
+#define GPSR5_SCK2		BIT(9)
+#define GPSR5_RTS1_TANS		BIT(8)
+#define GPSR5_CTS1		BIT(7)
+#define GPSR5_TX1_A		BIT(6)
+#define GPSR5_RX1_A		BIT(5)
+#define GPSR5_RTS0_TANS		BIT(4)
+#define GPSR5_CTS0		BIT(3)
+#define GPSR5_TX0		BIT(2)
+#define GPSR5_RX0		BIT(1)
+#define GPSR5_SCK0		BIT(0)
+#define GPSR6_USB31_OVC		BIT(31)
+#define GPSR6_USB31_PWEN	BIT(30)
+#define GPSR6_USB30_OVC		BIT(29)
+#define GPSR6_USB30_PWEN	BIT(28)
+#define GPSR6_USB1_OVC		BIT(27)
+#define GPSR6_USB1_PWEN		BIT(26)
+#define GPSR6_USB0_OVC		BIT(25)
+#define GPSR6_USB0_PWEN		BIT(24)
+#define GPSR6_AUDIO_CLKB_B	BIT(23)
+#define GPSR6_AUDIO_CLKA_A	BIT(22)
+#define GPSR6_SSI_SDATA9_A	BIT(21)
+#define GPSR6_SSI_SDATA8	BIT(20)
+#define GPSR6_SSI_SDATA7	BIT(19)
+#define GPSR6_SSI_WS78		BIT(18)
+#define GPSR6_SSI_SCK78		BIT(17)
+#define GPSR6_SSI_SDATA6	BIT(16)
+#define GPSR6_SSI_WS6		BIT(15)
+#define GPSR6_SSI_SCK6		BIT(14)
+#define GPSR6_SSI_SDATA5	BIT(13)
+#define GPSR6_SSI_WS5		BIT(12)
+#define GPSR6_SSI_SCK5		BIT(11)
+#define GPSR6_SSI_SDATA4	BIT(10)
+#define GPSR6_SSI_WS4		BIT(9)
+#define GPSR6_SSI_SCK4		BIT(8)
+#define GPSR6_SSI_SDATA3	BIT(7)
+#define GPSR6_SSI_WS34		BIT(6)
+#define GPSR6_SSI_SCK34		BIT(5)
+#define GPSR6_SSI_SDATA2_A	BIT(4)
+#define GPSR6_SSI_SDATA1_A	BIT(3)
+#define GPSR6_SSI_SDATA0	BIT(2)
+#define GPSR6_SSI_WS0129	BIT(1)
+#define GPSR6_SSI_SCK0129	BIT(0)
+#define GPSR7_HDMI1_CEC		BIT(3)
+#define GPSR7_HDMI0_CEC		BIT(2)
+#define GPSR7_AVS2		BIT(1)
+#define GPSR7_AVS1		BIT(0)
+
+#define IPSR_28_FUNC(x)		((uint32_t)(x) << 28U)
+#define IPSR_24_FUNC(x)		((uint32_t)(x) << 24U)
+#define IPSR_20_FUNC(x)		((uint32_t)(x) << 20U)
+#define IPSR_16_FUNC(x)		((uint32_t)(x) << 16U)
+#define IPSR_12_FUNC(x)		((uint32_t)(x) << 12U)
+#define IPSR_8_FUNC(x)		((uint32_t)(x) << 8U)
+#define IPSR_4_FUNC(x)		((uint32_t)(x) << 4U)
+#define IPSR_0_FUNC(x)		((uint32_t)(x) << 0U)
+
+#define POC_SD3_DS_33V		BIT(29)
+#define POC_SD3_DAT7_33V	BIT(28)
+#define POC_SD3_DAT6_33V	BIT(27)
+#define POC_SD3_DAT5_33V	BIT(26)
+#define POC_SD3_DAT4_33V	BIT(25)
+#define POC_SD3_DAT3_33V	BIT(24)
+#define POC_SD3_DAT2_33V	BIT(23)
+#define POC_SD3_DAT1_33V	BIT(22)
+#define POC_SD3_DAT0_33V	BIT(21)
+#define POC_SD3_CMD_33V		BIT(20)
+#define POC_SD3_CLK_33V		BIT(19)
+#define POC_SD2_DS_33V		BIT(18)
+#define POC_SD2_DAT3_33V	BIT(17)
+#define POC_SD2_DAT2_33V	BIT(16)
+#define POC_SD2_DAT1_33V	BIT(15)
+#define POC_SD2_DAT0_33V	BIT(14)
+#define POC_SD2_CMD_33V		BIT(13)
+#define POC_SD2_CLK_33V		BIT(12)
+#define POC_SD1_DAT3_33V	BIT(11)
+#define POC_SD1_DAT2_33V	BIT(10)
+#define POC_SD1_DAT1_33V	BIT(9)
+#define POC_SD1_DAT0_33V	BIT(8)
+#define POC_SD1_CMD_33V		BIT(7)
+#define POC_SD1_CLK_33V		BIT(6)
+#define POC_SD0_DAT3_33V	BIT(5)
+#define POC_SD0_DAT2_33V	BIT(4)
+#define POC_SD0_DAT1_33V	BIT(3)
+#define POC_SD0_DAT0_33V	BIT(2)
+#define POC_SD0_CMD_33V		BIT(1)
+#define POC_SD0_CLK_33V		BIT(0)
+
+#define DRVCTRL0_MASK		(0xCCCCCCCCU)
+#define DRVCTRL1_MASK		(0xCCCCCCC8U)
+#define DRVCTRL2_MASK		(0x88888888U)
+#define DRVCTRL3_MASK		(0x88888888U)
+#define DRVCTRL4_MASK		(0x88888888U)
+#define DRVCTRL5_MASK		(0x88888888U)
+#define DRVCTRL6_MASK		(0x88888888U)
+#define DRVCTRL7_MASK		(0x88888888U)
+#define DRVCTRL8_MASK		(0x88888888U)
+#define DRVCTRL9_MASK		(0x88888888U)
+#define DRVCTRL10_MASK		(0x88888888U)
+#define DRVCTRL11_MASK		(0x888888CCU)
+#define DRVCTRL12_MASK		(0xCCCFFFCFU)
+#define DRVCTRL13_MASK		(0xCC888888U)
+#define DRVCTRL14_MASK		(0x88888888U)
+#define DRVCTRL15_MASK		(0x88888888U)
+#define DRVCTRL16_MASK		(0x88888888U)
+#define DRVCTRL17_MASK		(0x88888888U)
+#define DRVCTRL18_MASK		(0x88888888U)
+#define DRVCTRL19_MASK		(0x88888888U)
+#define DRVCTRL20_MASK		(0x88888888U)
+#define DRVCTRL21_MASK		(0x88888888U)
+#define DRVCTRL22_MASK		(0x88888888U)
+#define DRVCTRL23_MASK		(0x88888888U)
+#define DRVCTRL24_MASK		(0x8888888FU)
+
+#define DRVCTRL0_QSPI0_SPCLK(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL0_QSPI0_MOSI_IO0(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL0_QSPI0_MISO_IO1(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL0_QSPI0_IO2(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL0_QSPI0_IO3(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL0_QSPI0_SSL(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL0_QSPI1_SPCLK(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL0_QSPI1_MOSI_IO0(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL1_QSPI1_MISO_IO1(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL1_QSPI1_IO2(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL1_QSPI1_IO3(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL1_QSPI1_SS(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL1_RPC_INT(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL1_RPC_WP(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL1_RPC_RESET(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL1_AVB_RX_CTL(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL2_AVB_RXC(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL2_AVB_RD0(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL2_AVB_RD1(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL2_AVB_RD2(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL2_AVB_RD3(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL2_AVB_TX_CTL(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL2_AVB_TXC(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL2_AVB_TD0(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL3_AVB_TD1(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL3_AVB_TD2(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL3_AVB_TD3(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL3_AVB_TXCREFCLK(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL3_AVB_MDIO(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL3_AVB_MDC(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL3_AVB_MAGIC(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL3_AVB_PHY_INT(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL4_AVB_LINK(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL4_AVB_AVTP_MATCH(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL4_AVB_AVTP_CAPTURE(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL4_IRQ0(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL4_IRQ1(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL4_IRQ2(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL4_IRQ3(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL4_IRQ4(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL5_IRQ5(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL5_PWM0(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL5_PWM1(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL5_PWM2(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL5_A0(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL5_A1(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL5_A2(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL5_A3(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL6_A4(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL6_A5(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL6_A6(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL6_A7(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL6_A8(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL6_A9(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL6_A10(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL6_A11(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL7_A12(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL7_A13(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL7_A14(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL7_A15(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL7_A16(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL7_A17(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL7_A18(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL7_A19(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL8_CLKOUT(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL8_CS0(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL8_CS1_A2(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL8_BS(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL8_RD(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL8_RD_W(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL8_WE0(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL8_WE1(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL9_EX_WAIT0(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL9_PRESETOU(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL9_D0(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL9_D1(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL9_D2(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL9_D3(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL9_D4(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL9_D5(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL10_D6(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL10_D7(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL10_D8(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL10_D9(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL10_D10(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL10_D11(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL10_D12(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL10_D13(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL11_D14(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL11_D15(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL11_AVS1(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL11_AVS2(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL11_HDMI0_CEC(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL11_HDMI1_CEC(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL11_DU_DOTCLKIN0(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL11_DU_DOTCLKIN1(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL12_DU_DOTCLKIN2(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL12_DU_DOTCLKIN3(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL12_DU_FSCLKST(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL12_DU_TMS(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL13_TDO(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL13_ASEBRK(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL13_SD0_CLK(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL13_SD0_CMD(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL13_SD0_DAT0(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL13_SD0_DAT1(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL13_SD0_DAT2(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL13_SD0_DAT3(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL14_SD1_CLK(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL14_SD1_CMD(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL14_SD1_DAT0(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL14_SD1_DAT1(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL14_SD1_DAT2(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL14_SD1_DAT3(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL14_SD2_CLK(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL14_SD2_CMD(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL15_SD2_DAT0(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL15_SD2_DAT1(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL15_SD2_DAT2(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL15_SD2_DAT3(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL15_SD2_DS(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL15_SD3_CLK(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL15_SD3_CMD(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL15_SD3_DAT0(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL16_SD3_DAT1(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL16_SD3_DAT2(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL16_SD3_DAT3(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL16_SD3_DAT4(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL16_SD3_DAT5(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL16_SD3_DAT6(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL16_SD3_DAT7(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL16_SD3_DS(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL17_SD0_CD(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL17_SD0_WP(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL17_SD1_CD(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL17_SD1_WP(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL17_SCK0(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL17_RX0(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL17_TX0(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL17_CTS0(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL18_RTS0_TANS(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL18_RX1(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL18_TX1(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL18_CTS1(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL18_RTS1_TANS(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL18_SCK2(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL18_TX2(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL18_RX2(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL19_HSCK0(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL19_HRX0(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL19_HTX0(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL19_HCTS0(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL19_HRTS0(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL19_MSIOF0_SCK(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL19_MSIOF0_SYNC(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL19_MSIOF0_SS1(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL20_MSIOF0_TXD(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL20_MSIOF0_SS2(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL20_MSIOF0_RXD(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL20_MLB_CLK(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL20_MLB_SIG(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL20_MLB_DAT(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL20_MLB_REF(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL20_SSI_SCK0129(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL21_SSI_WS0129(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL21_SSI_SDATA0(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL21_SSI_SDATA1(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL21_SSI_SDATA2(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL21_SSI_SCK34(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL21_SSI_WS34(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL21_SSI_SDATA3(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL21_SSI_SCK4(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL22_SSI_WS4(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL22_SSI_SDATA4(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL22_SSI_SCK5(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL22_SSI_WS5(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL22_SSI_SDATA5(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL22_SSI_SCK6(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL22_SSI_WS6(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL22_SSI_SDATA6(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL23_SSI_SCK78(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL23_SSI_WS78(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL23_SSI_SDATA7(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL23_SSI_SDATA8(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL23_SSI_SDATA9(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL23_AUDIO_CLKA(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL23_AUDIO_CLKB(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL23_USB0_PWEN(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL24_USB0_OVC(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL24_USB1_PWEN(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL24_USB1_OVC(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL24_USB30_PWEN(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL24_USB30_OVC(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL24_USB31_PWEN(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL24_USB31_OVC(x)	((uint32_t)(x) << 4U)
+
+#define MOD_SEL0_MSIOF3_A	((uint32_t)0U << 29U)
+#define MOD_SEL0_MSIOF3_B	((uint32_t)1U << 29U)
+#define MOD_SEL0_MSIOF3_C	((uint32_t)2U << 29U)
+#define MOD_SEL0_MSIOF3_D	((uint32_t)3U << 29U)
+#define MOD_SEL0_MSIOF3_E	((uint32_t)4U << 29U)
+#define MOD_SEL0_MSIOF2_A	((uint32_t)0U << 27U)
+#define MOD_SEL0_MSIOF2_B	((uint32_t)1U << 27U)
+#define MOD_SEL0_MSIOF2_C	((uint32_t)2U << 27U)
+#define MOD_SEL0_MSIOF2_D	((uint32_t)3U << 27U)
+#define MOD_SEL0_MSIOF1_A	((uint32_t)0U << 24U)
+#define MOD_SEL0_MSIOF1_B	((uint32_t)1U << 24U)
+#define MOD_SEL0_MSIOF1_C	((uint32_t)2U << 24U)
+#define MOD_SEL0_MSIOF1_D	((uint32_t)3U << 24U)
+#define MOD_SEL0_MSIOF1_E	((uint32_t)4U << 24U)
+#define MOD_SEL0_MSIOF1_F	((uint32_t)5U << 24U)
+#define MOD_SEL0_MSIOF1_G	((uint32_t)6U << 24U)
+#define MOD_SEL0_LBSC_A		((uint32_t)0U << 23U)
+#define MOD_SEL0_LBSC_B		((uint32_t)1U << 23U)
+#define MOD_SEL0_IEBUS_A	((uint32_t)0U << 22U)
+#define MOD_SEL0_IEBUS_B	((uint32_t)1U << 22U)
+#define MOD_SEL0_I2C2_A		((uint32_t)0U << 21U)
+#define MOD_SEL0_I2C2_B		((uint32_t)1U << 21U)
+#define MOD_SEL0_I2C1_A		((uint32_t)0U << 20U)
+#define MOD_SEL0_I2C1_B		((uint32_t)1U << 20U)
+#define MOD_SEL0_HSCIF4_A	((uint32_t)0U << 19U)
+#define MOD_SEL0_HSCIF4_B	((uint32_t)1U << 19U)
+#define MOD_SEL0_HSCIF3_A	((uint32_t)0U << 17U)
+#define MOD_SEL0_HSCIF3_B	((uint32_t)1U << 17U)
+#define MOD_SEL0_HSCIF3_C	((uint32_t)2U << 17U)
+#define MOD_SEL0_HSCIF3_D	((uint32_t)3U << 17U)
+#define MOD_SEL0_HSCIF1_A	((uint32_t)0U << 16U)
+#define MOD_SEL0_HSCIF1_B	((uint32_t)1U << 16U)
+#define MOD_SEL0_FSO_A		((uint32_t)0U << 15U)
+#define MOD_SEL0_FSO_B		((uint32_t)1U << 15U)
+#define MOD_SEL0_HSCIF2_A	((uint32_t)0U << 13U)
+#define MOD_SEL0_HSCIF2_B	((uint32_t)1U << 13U)
+#define MOD_SEL0_HSCIF2_C	((uint32_t)2U << 13U)
+#define MOD_SEL0_ETHERAVB_A	((uint32_t)0U << 12U)
+#define MOD_SEL0_ETHERAVB_B	((uint32_t)1U << 12U)
+#define MOD_SEL0_DRIF3_A	((uint32_t)0U << 11U)
+#define MOD_SEL0_DRIF3_B	((uint32_t)1U << 11U)
+#define MOD_SEL0_DRIF2_A	((uint32_t)0U << 10U)
+#define MOD_SEL0_DRIF2_B	((uint32_t)1U << 10U)
+#define MOD_SEL0_DRIF1_A	((uint32_t)0U << 8U)
+#define MOD_SEL0_DRIF1_B	((uint32_t)1U << 8U)
+#define MOD_SEL0_DRIF1_C	((uint32_t)2U << 8U)
+#define MOD_SEL0_DRIF0_A	((uint32_t)0U << 6U)
+#define MOD_SEL0_DRIF0_B	((uint32_t)1U << 6U)
+#define MOD_SEL0_DRIF0_C	((uint32_t)2U << 6U)
+#define MOD_SEL0_CANFD0_A	((uint32_t)0U << 5U)
+#define MOD_SEL0_CANFD0_B	((uint32_t)1U << 5U)
+#define MOD_SEL0_ADG_A_A	((uint32_t)0U << 3U)
+#define MOD_SEL0_ADG_A_B	((uint32_t)1U << 3U)
+#define MOD_SEL0_ADG_A_C	((uint32_t)2U << 3U)
+#define MOD_SEL1_TSIF1_A	((uint32_t)0U << 30U)
+#define MOD_SEL1_TSIF1_B	((uint32_t)1U << 30U)
+#define MOD_SEL1_TSIF1_C	((uint32_t)2U << 30U)
+#define MOD_SEL1_TSIF1_D	((uint32_t)3U << 30U)
+#define MOD_SEL1_TSIF0_A	((uint32_t)0U << 27U)
+#define MOD_SEL1_TSIF0_B	((uint32_t)1U << 27U)
+#define MOD_SEL1_TSIF0_C	((uint32_t)2U << 27U)
+#define MOD_SEL1_TSIF0_D	((uint32_t)3U << 27U)
+#define MOD_SEL1_TSIF0_E	((uint32_t)4U << 27U)
+#define MOD_SEL1_TIMER_TMU_A	((uint32_t)0U << 26U)
+#define MOD_SEL1_TIMER_TMU_B	((uint32_t)1U << 26U)
+#define MOD_SEL1_SSP1_1_A	((uint32_t)0U << 24U)
+#define MOD_SEL1_SSP1_1_B	((uint32_t)1U << 24U)
+#define MOD_SEL1_SSP1_1_C	((uint32_t)2U << 24U)
+#define MOD_SEL1_SSP1_1_D	((uint32_t)3U << 24U)
+#define MOD_SEL1_SSP1_0_A	((uint32_t)0U << 21U)
+#define MOD_SEL1_SSP1_0_B	((uint32_t)1U << 21U)
+#define MOD_SEL1_SSP1_0_C	((uint32_t)2U << 21U)
+#define MOD_SEL1_SSP1_0_D	((uint32_t)3U << 21U)
+#define MOD_SEL1_SSP1_0_E	((uint32_t)4U << 21U)
+#define MOD_SEL1_SSI_A		((uint32_t)0U << 20U)
+#define MOD_SEL1_SSI_B		((uint32_t)1U << 20U)
+#define MOD_SEL1_SPEED_PULSE_IF_A	((uint32_t)0U << 19U)
+#define MOD_SEL1_SPEED_PULSE_IF_B	((uint32_t)1U << 19U)
+#define MOD_SEL1_SIMCARD_A	((uint32_t)0U << 17U)
+#define MOD_SEL1_SIMCARD_B	((uint32_t)1U << 17U)
+#define MOD_SEL1_SIMCARD_C	((uint32_t)2U << 17U)
+#define MOD_SEL1_SIMCARD_D	((uint32_t)3U << 17U)
+#define MOD_SEL1_SDHI2_A	((uint32_t)0U << 16U)
+#define MOD_SEL1_SDHI2_B	((uint32_t)1U << 16U)
+#define MOD_SEL1_SCIF4_A	((uint32_t)0U << 14U)
+#define MOD_SEL1_SCIF4_B	((uint32_t)1U << 14U)
+#define MOD_SEL1_SCIF4_C	((uint32_t)2U << 14U)
+#define MOD_SEL1_SCIF3_A	((uint32_t)0U << 13U)
+#define MOD_SEL1_SCIF3_B	((uint32_t)1U << 13U)
+#define MOD_SEL1_SCIF2_A	((uint32_t)0U << 12U)
+#define MOD_SEL1_SCIF2_B	((uint32_t)1U << 12U)
+#define MOD_SEL1_SCIF1_A	((uint32_t)0U << 11U)
+#define MOD_SEL1_SCIF1_B	((uint32_t)1U << 11U)
+#define MOD_SEL1_SCIF_A		((uint32_t)0U << 10U)
+#define MOD_SEL1_SCIF_B		((uint32_t)1U << 10U)
+#define MOD_SEL1_REMOCON_A	((uint32_t)0U << 9U)
+#define MOD_SEL1_REMOCON_B	((uint32_t)1U << 9U)
+#define MOD_SEL1_RCAN0_A	((uint32_t)0U << 6U)
+#define MOD_SEL1_RCAN0_B	((uint32_t)1U << 6U)
+#define MOD_SEL1_PWM6_A		((uint32_t)0U << 5U)
+#define MOD_SEL1_PWM6_B		((uint32_t)1U << 5U)
+#define MOD_SEL1_PWM5_A		((uint32_t)0U << 4U)
+#define MOD_SEL1_PWM5_B		((uint32_t)1U << 4U)
+#define MOD_SEL1_PWM4_A		((uint32_t)0U << 3U)
+#define MOD_SEL1_PWM4_B		((uint32_t)1U << 3U)
+#define MOD_SEL1_PWM3_A		((uint32_t)0U << 2U)
+#define MOD_SEL1_PWM3_B		((uint32_t)1U << 2U)
+#define MOD_SEL1_PWM2_A		((uint32_t)0U << 1U)
+#define MOD_SEL1_PWM2_B		((uint32_t)1U << 1U)
+#define MOD_SEL1_PWM1_A		((uint32_t)0U << 0U)
+#define MOD_SEL1_PWM1_B		((uint32_t)1U << 0U)
+#define MOD_SEL2_I2C_5_A	((uint32_t)0U << 31U)
+#define MOD_SEL2_I2C_5_B	((uint32_t)1U << 31U)
+#define MOD_SEL2_I2C_3_A	((uint32_t)0U << 30U)
+#define MOD_SEL2_I2C_3_B	((uint32_t)1U << 30U)
+#define MOD_SEL2_I2C_0_A	((uint32_t)0U << 29U)
+#define MOD_SEL2_I2C_0_B	((uint32_t)1U << 29U)
+#define MOD_SEL2_FM_A		((uint32_t)0U << 27U)
+#define MOD_SEL2_FM_B		((uint32_t)1U << 27U)
+#define MOD_SEL2_FM_C		((uint32_t)2U << 27U)
+#define MOD_SEL2_FM_D		((uint32_t)3U << 27U)
+#define MOD_SEL2_SCIF5_A	((uint32_t)0U << 26U)
+#define MOD_SEL2_SCIF5_B	((uint32_t)1U << 26U)
+#define MOD_SEL2_I2C6_A		((uint32_t)0U << 23U)
+#define MOD_SEL2_I2C6_B		((uint32_t)1U << 23U)
+#define MOD_SEL2_I2C6_C		((uint32_t)2U << 23U)
+#define MOD_SEL2_NDF_A		((uint32_t)0U << 22U)
+#define MOD_SEL2_NDF_B		((uint32_t)1U << 22U)
+#define MOD_SEL2_SSI2_A		((uint32_t)0U << 21U)
+#define MOD_SEL2_SSI2_B		((uint32_t)1U << 21U)
+#define MOD_SEL2_SSI9_A		((uint32_t)0U << 20U)
+#define MOD_SEL2_SSI9_B		((uint32_t)1U << 20U)
+#define MOD_SEL2_TIMER_TMU2_A	((uint32_t)0U << 19U)
+#define MOD_SEL2_TIMER_TMU2_B	((uint32_t)1U << 19U)
+#define MOD_SEL2_ADG_B_A	((uint32_t)0U << 18U)
+#define MOD_SEL2_ADG_B_B	((uint32_t)1U << 18U)
+#define MOD_SEL2_ADG_C_A	((uint32_t)0U << 17U)
+#define MOD_SEL2_ADG_C_B	((uint32_t)1U << 17U)
+#define MOD_SEL2_VIN4_A		((uint32_t)0U << 0U)
+#define MOD_SEL2_VIN4_B		((uint32_t)1U << 0U)
+
+/* SCIF3 Registers for Dummy write */
+#define SCIF3_BASE		(0xE6C50000U)
+#define SCIF3_SCFCR		(SCIF3_BASE + 0x0018U)
+#define SCIF3_SCFDR		(SCIF3_BASE + 0x001CU)
+#define SCFCR_DATA		(0x0000U)
+
+/* Realtime module stop control */
+#define CPG_BASE		(0xE6150000U)
+#define CPG_SCMSTPCR0		(CPG_BASE + 0x0B20U)
+#define CPG_MSTPSR0		(CPG_BASE + 0x0030U)
+#define SCMSTPCR0_RTDMAC	(0x00200000U)
+
+/* RT-DMAC Registers */
+#define RTDMAC_CH		(0U)	/* choose 0 to 15 */
+
+#define RTDMAC_BASE		(0xFFC10000U)
+#define RTDMAC_RDMOR		(RTDMAC_BASE + 0x0060U)
+#define RTDMAC_RDMCHCLR		(RTDMAC_BASE + 0x0080U)
+#define RTDMAC_RDMSAR(x)	(RTDMAC_BASE + 0x8000U + (0x80U * (x)))
+#define RTDMAC_RDMDAR(x)	(RTDMAC_BASE + 0x8004U + (0x80U * (x)))
+#define RTDMAC_RDMTCR(x)	(RTDMAC_BASE + 0x8008U + (0x80U * (x)))
+#define RTDMAC_RDMCHCR(x)	(RTDMAC_BASE + 0x800CU + (0x80U * (x)))
+#define RTDMAC_RDMCHCRB(x)	(RTDMAC_BASE + 0x801CU + (0x80U * (x)))
+#define RTDMAC_RDMDPBASE(x)	(RTDMAC_BASE + 0x8050U + (0x80U * (x)))
+#define RTDMAC_DESC_BASE	(RTDMAC_BASE + 0xA000U)
+#define RTDMAC_DESC_RDMSAR	(RTDMAC_DESC_BASE + 0x0000U)
+#define RTDMAC_DESC_RDMDAR	(RTDMAC_DESC_BASE + 0x0004U)
+#define RTDMAC_DESC_RDMTCR	(RTDMAC_DESC_BASE + 0x0008U)
+
+#define RDMOR_DME		(0x0001U)	/* DMA Master Enable */
+#define RDMCHCR_DPM_INFINITE	(0x30000000U)	/* Infinite repeat mode */
+#define RDMCHCR_RPT_TCR		(0x02000000U)	/* enable to update TCR */
+#define RDMCHCR_TS_2		(0x00000008U)	/* Word(2byte) units transfer */
+#define RDMCHCR_RS_AUTO		(0x00000400U)	/* Auto request */
+#define RDMCHCR_DE		(0x00000001U)	/* DMA Enable */
+#define RDMCHCRB_DRST		(0x00008000U)	/* Descriptor reset */
+#define RDMCHCRB_SLM_256	(0x00000080U)	/* once in 256 clock cycle */
+#define RDMDPBASE_SEL_EXT	(0x00000001U)	/* External memory use */
+
+static void start_rtdma0_descriptor(void)
+{
+	uint32_t reg;
+
+	reg = mmio_read_32(RCAR_PRR);
+	reg &= (RCAR_PRODUCT_MASK | RCAR_CUT_MASK);
+	if (reg == (RCAR_PRODUCT_M3_CUT10)) {
+		/* Enable clock supply to RTDMAC. */
+		mstpcr_write(CPG_SCMSTPCR0, CPG_MSTPSR0, SCMSTPCR0_RTDMAC);
+
+		/* Initialize ch0, Reset Descriptor */
+		mmio_write_32(RTDMAC_RDMCHCLR, BIT(RTDMAC_CH));
+		mmio_write_32(RTDMAC_RDMCHCRB(RTDMAC_CH), RDMCHCRB_DRST);
+
+		/* Enable DMA */
+		mmio_write_16(RTDMAC_RDMOR, RDMOR_DME);
+
+		/* Set first transfer */
+		mmio_write_32(RTDMAC_RDMSAR(RTDMAC_CH), RCAR_PRR);
+		mmio_write_32(RTDMAC_RDMDAR(RTDMAC_CH), SCIF3_SCFDR);
+		mmio_write_32(RTDMAC_RDMTCR(RTDMAC_CH), 0x00000001U);
+
+		/* Set descriptor */
+		mmio_write_32(RTDMAC_DESC_RDMSAR, 0x00000000U);
+		mmio_write_32(RTDMAC_DESC_RDMDAR, 0x00000000U);
+		mmio_write_32(RTDMAC_DESC_RDMTCR, 0x00200000U);
+		mmio_write_32(RTDMAC_RDMCHCRB(RTDMAC_CH), RDMCHCRB_SLM_256);
+		mmio_write_32(RTDMAC_RDMDPBASE(RTDMAC_CH), RTDMAC_DESC_BASE
+			      | RDMDPBASE_SEL_EXT);
+
+		/* Set transfer parameter, Start transfer */
+		mmio_write_32(RTDMAC_RDMCHCR(RTDMAC_CH), RDMCHCR_DPM_INFINITE
+			      | RDMCHCR_RPT_TCR
+			      | RDMCHCR_TS_2
+			      | RDMCHCR_RS_AUTO
+			      | RDMCHCR_DE);
+	}
+}
+
+static void pfc_reg_write(uint32_t addr, uint32_t data)
+{
+	uint32_t prr;
+
+	prr = mmio_read_32(RCAR_PRR);
+	prr &= (RCAR_PRODUCT_MASK | RCAR_CUT_MASK);
+
+	mmio_write_32(PFC_PMMR, ~data);
+	if (prr == (RCAR_PRODUCT_M3_CUT10)) {
+		mmio_write_16(SCIF3_SCFCR, SCFCR_DATA);	/* Dummy write */
+	}
+	mmio_write_32((uintptr_t)addr, data);
+	if (prr == (RCAR_PRODUCT_M3_CUT10)) {
+		mmio_write_16(SCIF3_SCFCR, SCFCR_DATA);	/* Dummy write */
+	}
+}
+
+void pfc_init_m3(void)
+{
+	uint32_t reg;
+
+	/* Work around for PFC eratta */
+	start_rtdma0_descriptor();
+
+	/* initialize module select */
+	pfc_reg_write(PFC_MOD_SEL0, MOD_SEL0_MSIOF3_A
+		      | MOD_SEL0_MSIOF2_A
+		      | MOD_SEL0_MSIOF1_A
+		      | MOD_SEL0_LBSC_A
+		      | MOD_SEL0_IEBUS_A
+		      | MOD_SEL0_I2C2_A
+		      | MOD_SEL0_I2C1_A
+		      | MOD_SEL0_HSCIF4_A
+		      | MOD_SEL0_HSCIF3_A
+		      | MOD_SEL0_HSCIF1_A
+		      | MOD_SEL0_FSO_A
+		      | MOD_SEL0_HSCIF2_A
+		      | MOD_SEL0_ETHERAVB_A
+		      | MOD_SEL0_DRIF3_A
+		      | MOD_SEL0_DRIF2_A
+		      | MOD_SEL0_DRIF1_A
+		      | MOD_SEL0_DRIF0_A
+		      | MOD_SEL0_CANFD0_A
+		      | MOD_SEL0_ADG_A_A);
+	pfc_reg_write(PFC_MOD_SEL1, MOD_SEL1_TSIF1_A
+		      | MOD_SEL1_TSIF0_A
+		      | MOD_SEL1_TIMER_TMU_A
+		      | MOD_SEL1_SSP1_1_A
+		      | MOD_SEL1_SSP1_0_A
+		      | MOD_SEL1_SSI_A
+		      | MOD_SEL1_SPEED_PULSE_IF_A
+		      | MOD_SEL1_SIMCARD_A
+		      | MOD_SEL1_SDHI2_A
+		      | MOD_SEL1_SCIF4_A
+		      | MOD_SEL1_SCIF3_A
+		      | MOD_SEL1_SCIF2_A
+		      | MOD_SEL1_SCIF1_A
+		      | MOD_SEL1_SCIF_A
+		      | MOD_SEL1_REMOCON_A
+		      | MOD_SEL1_RCAN0_A
+		      | MOD_SEL1_PWM6_A
+		      | MOD_SEL1_PWM5_A
+		      | MOD_SEL1_PWM4_A
+		      | MOD_SEL1_PWM3_A
+		      | MOD_SEL1_PWM2_A
+		      | MOD_SEL1_PWM1_A);
+	pfc_reg_write(PFC_MOD_SEL2, MOD_SEL2_I2C_5_A
+		      | MOD_SEL2_I2C_3_A
+		      | MOD_SEL2_I2C_0_A
+		      | MOD_SEL2_FM_A
+		      | MOD_SEL2_SCIF5_A
+		      | MOD_SEL2_I2C6_A
+		      | MOD_SEL2_NDF_A
+		      | MOD_SEL2_SSI2_A
+		      | MOD_SEL2_SSI9_A
+		      | MOD_SEL2_TIMER_TMU2_A
+		      | MOD_SEL2_ADG_B_A
+		      | MOD_SEL2_ADG_C_A
+		      | MOD_SEL2_VIN4_A);
+
+	/* initialize peripheral function select */
+	pfc_reg_write(PFC_IPSR0, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR1, IPSR_28_FUNC(6)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(3)
+		      | IPSR_8_FUNC(3)
+		      | IPSR_4_FUNC(3)
+		      | IPSR_0_FUNC(3));
+	pfc_reg_write(PFC_IPSR2, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(6)
+		      | IPSR_20_FUNC(6)
+		      | IPSR_16_FUNC(6)
+		      | IPSR_12_FUNC(6)
+		      | IPSR_8_FUNC(6)
+		      | IPSR_4_FUNC(6)
+		      | IPSR_0_FUNC(6));
+	pfc_reg_write(PFC_IPSR3, IPSR_28_FUNC(6)
+		      | IPSR_24_FUNC(6)
+		      | IPSR_20_FUNC(6)
+		      | IPSR_16_FUNC(6)
+		      | IPSR_12_FUNC(6)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR4, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(6)
+		      | IPSR_4_FUNC(6)
+		      | IPSR_0_FUNC(6));
+	pfc_reg_write(PFC_IPSR5, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(6)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR6, IPSR_28_FUNC(6)
+		      | IPSR_24_FUNC(6)
+		      | IPSR_20_FUNC(6)
+		      | IPSR_16_FUNC(6)
+		      | IPSR_12_FUNC(6)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR7, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(6)
+		      | IPSR_4_FUNC(6)
+		      | IPSR_0_FUNC(6));
+	pfc_reg_write(PFC_IPSR8, IPSR_28_FUNC(1)
+		      | IPSR_24_FUNC(1)
+		      | IPSR_20_FUNC(1)
+		      | IPSR_16_FUNC(1)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR9, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR10, IPSR_28_FUNC(1)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR11, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(4)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(1));
+	pfc_reg_write(PFC_IPSR12, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(4)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR13, IPSR_28_FUNC(8)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(3)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR14, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(3)
+		      | IPSR_0_FUNC(8));
+	pfc_reg_write(PFC_IPSR15, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR16, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR17, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(1)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR18, IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+
+	/* initialize GPIO/perihperal function select */
+	pfc_reg_write(PFC_GPSR0, GPSR0_D15
+		      | GPSR0_D14
+		      | GPSR0_D13
+		      | GPSR0_D12
+		      | GPSR0_D11
+		      | GPSR0_D10
+		      | GPSR0_D9
+		      | GPSR0_D8);
+	pfc_reg_write(PFC_GPSR1, GPSR1_CLKOUT
+		      | GPSR1_EX_WAIT0_A
+		      | GPSR1_A19
+		      | GPSR1_A18
+		      | GPSR1_A17
+		      | GPSR1_A16
+		      | GPSR1_A15
+		      | GPSR1_A14
+		      | GPSR1_A13
+		      | GPSR1_A12
+		      | GPSR1_A7
+		      | GPSR1_A6
+		      | GPSR1_A5
+		      | GPSR1_A4
+		      | GPSR1_A3
+		      | GPSR1_A2
+		      | GPSR1_A1
+		      | GPSR1_A0);
+	pfc_reg_write(PFC_GPSR2, GPSR2_AVB_AVTP_CAPTURE_A
+		      | GPSR2_AVB_AVTP_MATCH_A
+		      | GPSR2_AVB_LINK
+		      | GPSR2_AVB_PHY_INT
+		      | GPSR2_AVB_MDC
+		      | GPSR2_PWM2_A
+		      | GPSR2_PWM1_A
+		      | GPSR2_IRQ5
+		      | GPSR2_IRQ4
+		      | GPSR2_IRQ3
+		      | GPSR2_IRQ2
+		      | GPSR2_IRQ1
+		      | GPSR2_IRQ0);
+	pfc_reg_write(PFC_GPSR3, GPSR3_SD0_WP
+		      | GPSR3_SD0_CD
+		      | GPSR3_SD1_DAT3
+		      | GPSR3_SD1_DAT2
+		      | GPSR3_SD1_DAT1
+		      | GPSR3_SD1_DAT0
+		      | GPSR3_SD0_DAT3
+		      | GPSR3_SD0_DAT2
+		      | GPSR3_SD0_DAT1
+		      | GPSR3_SD0_DAT0
+		      | GPSR3_SD0_CMD
+		      | GPSR3_SD0_CLK);
+	pfc_reg_write(PFC_GPSR4, GPSR4_SD3_DAT7
+		      | GPSR4_SD3_DAT6
+		      | GPSR4_SD3_DAT3
+		      | GPSR4_SD3_DAT2
+		      | GPSR4_SD3_DAT1
+		      | GPSR4_SD3_DAT0
+		      | GPSR4_SD3_CMD
+		      | GPSR4_SD3_CLK
+		      | GPSR4_SD2_DS
+		      | GPSR4_SD2_DAT3
+		      | GPSR4_SD2_DAT2
+		      | GPSR4_SD2_DAT1
+		      | GPSR4_SD2_DAT0
+		      | GPSR4_SD2_CMD
+		      | GPSR4_SD2_CLK);
+	pfc_reg_write(PFC_GPSR5, GPSR5_MSIOF0_SS2
+		      | GPSR5_MSIOF0_SS1
+		      | GPSR5_MSIOF0_SYNC
+		      | GPSR5_HRTS0
+		      | GPSR5_HCTS0
+		      | GPSR5_HTX0
+		      | GPSR5_HRX0
+		      | GPSR5_HSCK0
+		      | GPSR5_RX2_A
+		      | GPSR5_TX2_A
+		      | GPSR5_SCK2
+		      | GPSR5_RTS1_TANS
+		      | GPSR5_CTS1
+		      | GPSR5_TX1_A
+		      | GPSR5_RX1_A
+		      | GPSR5_RTS0_TANS
+		      | GPSR5_SCK0);
+	pfc_reg_write(PFC_GPSR6, GPSR6_USB30_OVC
+		      | GPSR6_USB30_PWEN
+		      | GPSR6_USB1_OVC
+		      | GPSR6_USB1_PWEN
+		      | GPSR6_USB0_OVC
+		      | GPSR6_USB0_PWEN
+		      | GPSR6_AUDIO_CLKB_B
+		      | GPSR6_AUDIO_CLKA_A
+		      | GPSR6_SSI_SDATA8
+		      | GPSR6_SSI_SDATA7
+		      | GPSR6_SSI_WS78
+		      | GPSR6_SSI_SCK78
+		      | GPSR6_SSI_WS6
+		      | GPSR6_SSI_SCK6
+		      | GPSR6_SSI_SDATA4
+		      | GPSR6_SSI_WS4
+		      | GPSR6_SSI_SCK4
+		      | GPSR6_SSI_SDATA1_A
+		      | GPSR6_SSI_SDATA0
+		      | GPSR6_SSI_WS0129
+		      | GPSR6_SSI_SCK0129);
+	pfc_reg_write(PFC_GPSR7, GPSR7_HDMI1_CEC
+		      | GPSR7_HDMI0_CEC
+		      | GPSR7_AVS2
+		      | GPSR7_AVS1);
+
+	/* initialize POC control register */
+	pfc_reg_write(PFC_POCCTRL0, POC_SD3_DS_33V
+		      | POC_SD3_DAT7_33V
+		      | POC_SD3_DAT6_33V
+		      | POC_SD3_DAT5_33V
+		      | POC_SD3_DAT4_33V
+		      | POC_SD3_DAT3_33V
+		      | POC_SD3_DAT2_33V
+		      | POC_SD3_DAT1_33V
+		      | POC_SD3_DAT0_33V
+		      | POC_SD3_CMD_33V
+		      | POC_SD3_CLK_33V
+		      | POC_SD0_DAT3_33V
+		      | POC_SD0_DAT2_33V
+		      | POC_SD0_DAT1_33V
+		      | POC_SD0_DAT0_33V
+		      | POC_SD0_CMD_33V
+		      | POC_SD0_CLK_33V);
+
+	/* initialize DRV control register */
+	reg = mmio_read_32(PFC_DRVCTRL0);
+	reg = ((reg & DRVCTRL0_MASK) | DRVCTRL0_QSPI0_SPCLK(3)
+	       | DRVCTRL0_QSPI0_MOSI_IO0(3)
+	       | DRVCTRL0_QSPI0_MISO_IO1(3)
+	       | DRVCTRL0_QSPI0_IO2(3)
+	       | DRVCTRL0_QSPI0_IO3(3)
+	       | DRVCTRL0_QSPI0_SSL(3)
+	       | DRVCTRL0_QSPI1_SPCLK(3)
+	       | DRVCTRL0_QSPI1_MOSI_IO0(3));
+	pfc_reg_write(PFC_DRVCTRL0, reg);
+	reg = mmio_read_32(PFC_DRVCTRL1);
+	reg = ((reg & DRVCTRL1_MASK) | DRVCTRL1_QSPI1_MISO_IO1(3)
+	       | DRVCTRL1_QSPI1_IO2(3)
+	       | DRVCTRL1_QSPI1_IO3(3)
+	       | DRVCTRL1_QSPI1_SS(3)
+	       | DRVCTRL1_RPC_INT(3)
+	       | DRVCTRL1_RPC_WP(3)
+	       | DRVCTRL1_RPC_RESET(3)
+	       | DRVCTRL1_AVB_RX_CTL(7));
+	pfc_reg_write(PFC_DRVCTRL1, reg);
+	reg = mmio_read_32(PFC_DRVCTRL2);
+	reg = ((reg & DRVCTRL2_MASK) | DRVCTRL2_AVB_RXC(7)
+	       | DRVCTRL2_AVB_RD0(7)
+	       | DRVCTRL2_AVB_RD1(7)
+	       | DRVCTRL2_AVB_RD2(7)
+	       | DRVCTRL2_AVB_RD3(7)
+	       | DRVCTRL2_AVB_TX_CTL(3)
+	       | DRVCTRL2_AVB_TXC(3)
+	       | DRVCTRL2_AVB_TD0(3));
+	pfc_reg_write(PFC_DRVCTRL2, reg);
+	reg = mmio_read_32(PFC_DRVCTRL3);
+	reg = ((reg & DRVCTRL3_MASK) | DRVCTRL3_AVB_TD1(3)
+	       | DRVCTRL3_AVB_TD2(3)
+	       | DRVCTRL3_AVB_TD3(3)
+	       | DRVCTRL3_AVB_TXCREFCLK(7)
+	       | DRVCTRL3_AVB_MDIO(7)
+	       | DRVCTRL3_AVB_MDC(7)
+	       | DRVCTRL3_AVB_MAGIC(7)
+	       | DRVCTRL3_AVB_PHY_INT(7));
+	pfc_reg_write(PFC_DRVCTRL3, reg);
+	reg = mmio_read_32(PFC_DRVCTRL4);
+	reg = ((reg & DRVCTRL4_MASK) | DRVCTRL4_AVB_LINK(7)
+	       | DRVCTRL4_AVB_AVTP_MATCH(7)
+	       | DRVCTRL4_AVB_AVTP_CAPTURE(7)
+	       | DRVCTRL4_IRQ0(7)
+	       | DRVCTRL4_IRQ1(7)
+	       | DRVCTRL4_IRQ2(7)
+	       | DRVCTRL4_IRQ3(7)
+	       | DRVCTRL4_IRQ4(7));
+	pfc_reg_write(PFC_DRVCTRL4, reg);
+	reg = mmio_read_32(PFC_DRVCTRL5);
+	reg = ((reg & DRVCTRL5_MASK) | DRVCTRL5_IRQ5(7)
+	       | DRVCTRL5_PWM0(7)
+	       | DRVCTRL5_PWM1(7)
+	       | DRVCTRL5_PWM2(7)
+	       | DRVCTRL5_A0(3)
+	       | DRVCTRL5_A1(3)
+	       | DRVCTRL5_A2(3)
+	       | DRVCTRL5_A3(3));
+	pfc_reg_write(PFC_DRVCTRL5, reg);
+	reg = mmio_read_32(PFC_DRVCTRL6);
+	reg = ((reg & DRVCTRL6_MASK) | DRVCTRL6_A4(3)
+	       | DRVCTRL6_A5(3)
+	       | DRVCTRL6_A6(3)
+	       | DRVCTRL6_A7(3)
+	       | DRVCTRL6_A8(7)
+	       | DRVCTRL6_A9(7)
+	       | DRVCTRL6_A10(7)
+	       | DRVCTRL6_A11(7));
+	pfc_reg_write(PFC_DRVCTRL6, reg);
+	reg = mmio_read_32(PFC_DRVCTRL7);
+	reg = ((reg & DRVCTRL7_MASK) | DRVCTRL7_A12(3)
+	       | DRVCTRL7_A13(3)
+	       | DRVCTRL7_A14(3)
+	       | DRVCTRL7_A15(3)
+	       | DRVCTRL7_A16(3)
+	       | DRVCTRL7_A17(3)
+	       | DRVCTRL7_A18(3)
+	       | DRVCTRL7_A19(3));
+	pfc_reg_write(PFC_DRVCTRL7, reg);
+	reg = mmio_read_32(PFC_DRVCTRL8);
+	reg = ((reg & DRVCTRL8_MASK) | DRVCTRL8_CLKOUT(7)
+	       | DRVCTRL8_CS0(7)
+	       | DRVCTRL8_CS1_A2(7)
+	       | DRVCTRL8_BS(7)
+	       | DRVCTRL8_RD(7)
+	       | DRVCTRL8_RD_W(7)
+	       | DRVCTRL8_WE0(7)
+	       | DRVCTRL8_WE1(7));
+	pfc_reg_write(PFC_DRVCTRL8, reg);
+	reg = mmio_read_32(PFC_DRVCTRL9);
+	reg = ((reg & DRVCTRL9_MASK) | DRVCTRL9_EX_WAIT0(7)
+	       | DRVCTRL9_PRESETOU(7)
+	       | DRVCTRL9_D0(7)
+	       | DRVCTRL9_D1(7)
+	       | DRVCTRL9_D2(7)
+	       | DRVCTRL9_D3(7)
+	       | DRVCTRL9_D4(7)
+	       | DRVCTRL9_D5(7));
+	pfc_reg_write(PFC_DRVCTRL9, reg);
+	reg = mmio_read_32(PFC_DRVCTRL10);
+	reg = ((reg & DRVCTRL10_MASK) | DRVCTRL10_D6(7)
+	       | DRVCTRL10_D7(7)
+	       | DRVCTRL10_D8(3)
+	       | DRVCTRL10_D9(3)
+	       | DRVCTRL10_D10(3)
+	       | DRVCTRL10_D11(3)
+	       | DRVCTRL10_D12(3)
+	       | DRVCTRL10_D13(3));
+	pfc_reg_write(PFC_DRVCTRL10, reg);
+	reg = mmio_read_32(PFC_DRVCTRL11);
+	reg = ((reg & DRVCTRL11_MASK) | DRVCTRL11_D14(3)
+	       | DRVCTRL11_D15(3)
+	       | DRVCTRL11_AVS1(7)
+	       | DRVCTRL11_AVS2(7)
+	       | DRVCTRL11_HDMI0_CEC(7)
+	       | DRVCTRL11_HDMI1_CEC(7)
+	       | DRVCTRL11_DU_DOTCLKIN0(3)
+	       | DRVCTRL11_DU_DOTCLKIN1(3));
+	pfc_reg_write(PFC_DRVCTRL11, reg);
+	reg = mmio_read_32(PFC_DRVCTRL12);
+	reg = ((reg & DRVCTRL12_MASK) | DRVCTRL12_DU_DOTCLKIN2(3)
+	       | DRVCTRL12_DU_DOTCLKIN3(3)
+	       | DRVCTRL12_DU_FSCLKST(3)
+	       | DRVCTRL12_DU_TMS(3));
+	pfc_reg_write(PFC_DRVCTRL12, reg);
+	reg = mmio_read_32(PFC_DRVCTRL13);
+	reg = ((reg & DRVCTRL13_MASK) | DRVCTRL13_TDO(3)
+	       | DRVCTRL13_ASEBRK(3)
+	       | DRVCTRL13_SD0_CLK(7)
+	       | DRVCTRL13_SD0_CMD(7)
+	       | DRVCTRL13_SD0_DAT0(7)
+	       | DRVCTRL13_SD0_DAT1(7)
+	       | DRVCTRL13_SD0_DAT2(7)
+	       | DRVCTRL13_SD0_DAT3(7));
+	pfc_reg_write(PFC_DRVCTRL13, reg);
+	reg = mmio_read_32(PFC_DRVCTRL14);
+	reg = ((reg & DRVCTRL14_MASK) | DRVCTRL14_SD1_CLK(7)
+	       | DRVCTRL14_SD1_CMD(7)
+	       | DRVCTRL14_SD1_DAT0(5)
+	       | DRVCTRL14_SD1_DAT1(5)
+	       | DRVCTRL14_SD1_DAT2(5)
+	       | DRVCTRL14_SD1_DAT3(5)
+	       | DRVCTRL14_SD2_CLK(5)
+	       | DRVCTRL14_SD2_CMD(5));
+	pfc_reg_write(PFC_DRVCTRL14, reg);
+	reg = mmio_read_32(PFC_DRVCTRL15);
+	reg = ((reg & DRVCTRL15_MASK) | DRVCTRL15_SD2_DAT0(5)
+	       | DRVCTRL15_SD2_DAT1(5)
+	       | DRVCTRL15_SD2_DAT2(5)
+	       | DRVCTRL15_SD2_DAT3(5)
+	       | DRVCTRL15_SD2_DS(5)
+	       | DRVCTRL15_SD3_CLK(7)
+	       | DRVCTRL15_SD3_CMD(7)
+	       | DRVCTRL15_SD3_DAT0(7));
+	pfc_reg_write(PFC_DRVCTRL15, reg);
+	reg = mmio_read_32(PFC_DRVCTRL16);
+	reg = ((reg & DRVCTRL16_MASK) | DRVCTRL16_SD3_DAT1(7)
+	       | DRVCTRL16_SD3_DAT2(7)
+	       | DRVCTRL16_SD3_DAT3(7)
+	       | DRVCTRL16_SD3_DAT4(7)
+	       | DRVCTRL16_SD3_DAT5(7)
+	       | DRVCTRL16_SD3_DAT6(7)
+	       | DRVCTRL16_SD3_DAT7(7)
+	       | DRVCTRL16_SD3_DS(7));
+	pfc_reg_write(PFC_DRVCTRL16, reg);
+	reg = mmio_read_32(PFC_DRVCTRL17);
+	reg = ((reg & DRVCTRL17_MASK) | DRVCTRL17_SD0_CD(7)
+	       | DRVCTRL17_SD0_WP(7)
+	       | DRVCTRL17_SD1_CD(7)
+	       | DRVCTRL17_SD1_WP(7)
+	       | DRVCTRL17_SCK0(7)
+	       | DRVCTRL17_RX0(7)
+	       | DRVCTRL17_TX0(7)
+	       | DRVCTRL17_CTS0(7));
+	pfc_reg_write(PFC_DRVCTRL17, reg);
+	reg = mmio_read_32(PFC_DRVCTRL18);
+	reg = ((reg & DRVCTRL18_MASK) | DRVCTRL18_RTS0_TANS(7)
+	       | DRVCTRL18_RX1(7)
+	       | DRVCTRL18_TX1(7)
+	       | DRVCTRL18_CTS1(7)
+	       | DRVCTRL18_RTS1_TANS(7)
+	       | DRVCTRL18_SCK2(7)
+	       | DRVCTRL18_TX2(7)
+	       | DRVCTRL18_RX2(7));
+	pfc_reg_write(PFC_DRVCTRL18, reg);
+	reg = mmio_read_32(PFC_DRVCTRL19);
+	reg = ((reg & DRVCTRL19_MASK) | DRVCTRL19_HSCK0(7)
+	       | DRVCTRL19_HRX0(7)
+	       | DRVCTRL19_HTX0(7)
+	       | DRVCTRL19_HCTS0(7)
+	       | DRVCTRL19_HRTS0(7)
+	       | DRVCTRL19_MSIOF0_SCK(7)
+	       | DRVCTRL19_MSIOF0_SYNC(7)
+	       | DRVCTRL19_MSIOF0_SS1(7));
+	pfc_reg_write(PFC_DRVCTRL19, reg);
+	reg = mmio_read_32(PFC_DRVCTRL20);
+	reg = ((reg & DRVCTRL20_MASK) | DRVCTRL20_MSIOF0_TXD(7)
+	       | DRVCTRL20_MSIOF0_SS2(7)
+	       | DRVCTRL20_MSIOF0_RXD(7)
+	       | DRVCTRL20_MLB_CLK(7)
+	       | DRVCTRL20_MLB_SIG(7)
+	       | DRVCTRL20_MLB_DAT(7)
+	       | DRVCTRL20_MLB_REF(7)
+	       | DRVCTRL20_SSI_SCK0129(7));
+	pfc_reg_write(PFC_DRVCTRL20, reg);
+	reg = mmio_read_32(PFC_DRVCTRL21);
+	reg = ((reg & DRVCTRL21_MASK) | DRVCTRL21_SSI_WS0129(7)
+	       | DRVCTRL21_SSI_SDATA0(7)
+	       | DRVCTRL21_SSI_SDATA1(7)
+	       | DRVCTRL21_SSI_SDATA2(7)
+	       | DRVCTRL21_SSI_SCK34(7)
+	       | DRVCTRL21_SSI_WS34(7)
+	       | DRVCTRL21_SSI_SDATA3(7)
+	       | DRVCTRL21_SSI_SCK4(7));
+	pfc_reg_write(PFC_DRVCTRL21, reg);
+	reg = mmio_read_32(PFC_DRVCTRL22);
+	reg = ((reg & DRVCTRL22_MASK) | DRVCTRL22_SSI_WS4(7)
+	       | DRVCTRL22_SSI_SDATA4(7)
+	       | DRVCTRL22_SSI_SCK5(7)
+	       | DRVCTRL22_SSI_WS5(7)
+	       | DRVCTRL22_SSI_SDATA5(7)
+	       | DRVCTRL22_SSI_SCK6(7)
+	       | DRVCTRL22_SSI_WS6(7)
+	       | DRVCTRL22_SSI_SDATA6(7));
+	pfc_reg_write(PFC_DRVCTRL22, reg);
+	reg = mmio_read_32(PFC_DRVCTRL23);
+	reg = ((reg & DRVCTRL23_MASK) | DRVCTRL23_SSI_SCK78(7)
+	       | DRVCTRL23_SSI_WS78(7)
+	       | DRVCTRL23_SSI_SDATA7(7)
+	       | DRVCTRL23_SSI_SDATA8(7)
+	       | DRVCTRL23_SSI_SDATA9(7)
+	       | DRVCTRL23_AUDIO_CLKA(7)
+	       | DRVCTRL23_AUDIO_CLKB(7)
+	       | DRVCTRL23_USB0_PWEN(7));
+	pfc_reg_write(PFC_DRVCTRL23, reg);
+	reg = mmio_read_32(PFC_DRVCTRL24);
+	reg = ((reg & DRVCTRL24_MASK) | DRVCTRL24_USB0_OVC(7)
+	       | DRVCTRL24_USB1_PWEN(7)
+	       | DRVCTRL24_USB1_OVC(7)
+	       | DRVCTRL24_USB30_PWEN(7)
+	       | DRVCTRL24_USB30_OVC(7)
+	       | DRVCTRL24_USB31_PWEN(7)
+	       | DRVCTRL24_USB31_OVC(7));
+	pfc_reg_write(PFC_DRVCTRL24, reg);
+
+	/* initialize LSI pin pull-up/down control */
+	pfc_reg_write(PFC_PUD0, 0x00005FBFU);
+	pfc_reg_write(PFC_PUD1, 0x00300FFEU);
+	pfc_reg_write(PFC_PUD2, 0x330001E6U);
+	pfc_reg_write(PFC_PUD3, 0x000002E0U);
+	pfc_reg_write(PFC_PUD4, 0xFFFFFF00U);
+	pfc_reg_write(PFC_PUD5, 0x7F5FFF87U);
+	pfc_reg_write(PFC_PUD6, 0x00000055U);
+
+	/* initialize LSI pin pull-enable register */
+	pfc_reg_write(PFC_PUEN0, 0x00000FFFU);
+	pfc_reg_write(PFC_PUEN1, 0x00100234U);
+	pfc_reg_write(PFC_PUEN2, 0x000004C4U);
+	pfc_reg_write(PFC_PUEN3, 0x00000200U);
+	pfc_reg_write(PFC_PUEN4, 0x3E000000U);
+	pfc_reg_write(PFC_PUEN5, 0x1F000805U);
+	pfc_reg_write(PFC_PUEN6, 0x00000006U);
+
+	/* initialize positive/negative logic select */
+	mmio_write_32(GPIO_POSNEG0, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG1, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG2, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG3, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG4, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG5, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG6, 0x00000000U);
+
+	/* initialize general IO/interrupt switching */
+	mmio_write_32(GPIO_IOINTSEL0, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL1, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL2, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL3, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL4, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL5, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL6, 0x00000000U);
+
+	/* initialize general output register */
+	mmio_write_32(GPIO_OUTDT1, 0x00000000U);
+	mmio_write_32(GPIO_OUTDT2, 0x00000400U);
+	mmio_write_32(GPIO_OUTDT3, 0x0000C000U);
+	mmio_write_32(GPIO_OUTDT5, 0x00000006U);
+	mmio_write_32(GPIO_OUTDT6, 0x00003880U);
+
+	/* initialize general input/output switching */
+	mmio_write_32(GPIO_INOUTSEL0, 0x00000000U);
+	mmio_write_32(GPIO_INOUTSEL1, 0x01000A00U);
+	mmio_write_32(GPIO_INOUTSEL2, 0x00000400U);
+	mmio_write_32(GPIO_INOUTSEL3, 0x0000C000U);
+	mmio_write_32(GPIO_INOUTSEL4, 0x00000000U);
+#if (RCAR_GEN3_ULCB == 1)
+	mmio_write_32(GPIO_INOUTSEL5, 0x0000000EU);
+#else
+	mmio_write_32(GPIO_INOUTSEL5, 0x0000020EU);
+#endif
+	mmio_write_32(GPIO_INOUTSEL6, 0x00013880U);
+}
diff --git a/drivers/staging/renesas/rcar/pfc/M3/pfc_init_m3.h b/drivers/renesas/rcar/pfc/M3/pfc_init_m3.h
similarity index 100%
rename from drivers/staging/renesas/rcar/pfc/M3/pfc_init_m3.h
rename to drivers/renesas/rcar/pfc/M3/pfc_init_m3.h
diff --git a/drivers/renesas/rcar/pfc/M3N/pfc_init_m3n.c b/drivers/renesas/rcar/pfc/M3N/pfc_init_m3n.c
new file mode 100644
index 0000000..3fac375
--- /dev/null
+++ b/drivers/renesas/rcar/pfc/M3N/pfc_init_m3n.c
@@ -0,0 +1,1220 @@
+/*
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>		/* for uint32_t */
+
+#include <lib/mmio.h>
+
+#include "pfc_init_m3n.h"
+#include "rcar_def.h"
+#include "../pfc_regs.h"
+
+#define GPSR0_D15		BIT(15)
+#define GPSR0_D14		BIT(14)
+#define GPSR0_D13		BIT(13)
+#define GPSR0_D12		BIT(12)
+#define GPSR0_D11		BIT(11)
+#define GPSR0_D10		BIT(10)
+#define GPSR0_D9		BIT(9)
+#define GPSR0_D8		BIT(8)
+#define GPSR0_D7		BIT(7)
+#define GPSR0_D6		BIT(6)
+#define GPSR0_D5		BIT(5)
+#define GPSR0_D4		BIT(4)
+#define GPSR0_D3		BIT(3)
+#define GPSR0_D2		BIT(2)
+#define GPSR0_D1		BIT(1)
+#define GPSR0_D0		BIT(0)
+#define GPSR1_CLKOUT		BIT(28)
+#define GPSR1_EX_WAIT0_A	BIT(27)
+#define GPSR1_WE1		BIT(26)
+#define GPSR1_WE0		BIT(25)
+#define GPSR1_RD_WR		BIT(24)
+#define GPSR1_RD		BIT(23)
+#define GPSR1_BS		BIT(22)
+#define GPSR1_CS1_A26		BIT(21)
+#define GPSR1_CS0		BIT(20)
+#define GPSR1_A19		BIT(19)
+#define GPSR1_A18		BIT(18)
+#define GPSR1_A17		BIT(17)
+#define GPSR1_A16		BIT(16)
+#define GPSR1_A15		BIT(15)
+#define GPSR1_A14		BIT(14)
+#define GPSR1_A13		BIT(13)
+#define GPSR1_A12		BIT(12)
+#define GPSR1_A11		BIT(11)
+#define GPSR1_A10		BIT(10)
+#define GPSR1_A9		BIT(9)
+#define GPSR1_A8		BIT(8)
+#define GPSR1_A7		BIT(7)
+#define GPSR1_A6		BIT(6)
+#define GPSR1_A5		BIT(5)
+#define GPSR1_A4		BIT(4)
+#define GPSR1_A3		BIT(3)
+#define GPSR1_A2		BIT(2)
+#define GPSR1_A1		BIT(1)
+#define GPSR1_A0		BIT(0)
+#define GPSR2_AVB_AVTP_CAPTURE_A	BIT(14)
+#define GPSR2_AVB_AVTP_MATCH_A	BIT(13)
+#define GPSR2_AVB_LINK		BIT(12)
+#define GPSR2_AVB_PHY_INT	BIT(11)
+#define GPSR2_AVB_MAGIC		BIT(10)
+#define GPSR2_AVB_MDC		BIT(9)
+#define GPSR2_PWM2_A		BIT(8)
+#define GPSR2_PWM1_A		BIT(7)
+#define GPSR2_PWM0		BIT(6)
+#define GPSR2_IRQ5		BIT(5)
+#define GPSR2_IRQ4		BIT(4)
+#define GPSR2_IRQ3		BIT(3)
+#define GPSR2_IRQ2		BIT(2)
+#define GPSR2_IRQ1		BIT(1)
+#define GPSR2_IRQ0		BIT(0)
+#define GPSR3_SD1_WP		BIT(15)
+#define GPSR3_SD1_CD		BIT(14)
+#define GPSR3_SD0_WP		BIT(13)
+#define GPSR3_SD0_CD		BIT(12)
+#define GPSR3_SD1_DAT3		BIT(11)
+#define GPSR3_SD1_DAT2		BIT(10)
+#define GPSR3_SD1_DAT1		BIT(9)
+#define GPSR3_SD1_DAT0		BIT(8)
+#define GPSR3_SD1_CMD		BIT(7)
+#define GPSR3_SD1_CLK		BIT(6)
+#define GPSR3_SD0_DAT3		BIT(5)
+#define GPSR3_SD0_DAT2		BIT(4)
+#define GPSR3_SD0_DAT1		BIT(3)
+#define GPSR3_SD0_DAT0		BIT(2)
+#define GPSR3_SD0_CMD		BIT(1)
+#define GPSR3_SD0_CLK		BIT(0)
+#define GPSR4_SD3_DS		BIT(17)
+#define GPSR4_SD3_DAT7		BIT(16)
+#define GPSR4_SD3_DAT6		BIT(15)
+#define GPSR4_SD3_DAT5		BIT(14)
+#define GPSR4_SD3_DAT4		BIT(13)
+#define GPSR4_SD3_DAT3		BIT(12)
+#define GPSR4_SD3_DAT2		BIT(11)
+#define GPSR4_SD3_DAT1		BIT(10)
+#define GPSR4_SD3_DAT0		BIT(9)
+#define GPSR4_SD3_CMD		BIT(8)
+#define GPSR4_SD3_CLK		BIT(7)
+#define GPSR4_SD2_DS		BIT(6)
+#define GPSR4_SD2_DAT3		BIT(5)
+#define GPSR4_SD2_DAT2		BIT(4)
+#define GPSR4_SD2_DAT1		BIT(3)
+#define GPSR4_SD2_DAT0		BIT(2)
+#define GPSR4_SD2_CMD		BIT(1)
+#define GPSR4_SD2_CLK		BIT(0)
+#define GPSR5_MLB_DAT		BIT(25)
+#define GPSR5_MLB_SIG		BIT(24)
+#define GPSR5_MLB_CLK		BIT(23)
+#define GPSR5_MSIOF0_RXD	BIT(22)
+#define GPSR5_MSIOF0_SS2	BIT(21)
+#define GPSR5_MSIOF0_TXD	BIT(20)
+#define GPSR5_MSIOF0_SS1	BIT(19)
+#define GPSR5_MSIOF0_SYNC	BIT(18)
+#define GPSR5_MSIOF0_SCK	BIT(17)
+#define GPSR5_HRTS0		BIT(16)
+#define GPSR5_HCTS0		BIT(15)
+#define GPSR5_HTX0		BIT(14)
+#define GPSR5_HRX0		BIT(13)
+#define GPSR5_HSCK0		BIT(12)
+#define GPSR5_RX2_A		BIT(11)
+#define GPSR5_TX2_A		BIT(10)
+#define GPSR5_SCK2		BIT(9)
+#define GPSR5_RTS1_TANS		BIT(8)
+#define GPSR5_CTS1		BIT(7)
+#define GPSR5_TX1_A		BIT(6)
+#define GPSR5_RX1_A		BIT(5)
+#define GPSR5_RTS0_TANS		BIT(4)
+#define GPSR5_CTS0		BIT(3)
+#define GPSR5_TX0		BIT(2)
+#define GPSR5_RX0		BIT(1)
+#define GPSR5_SCK0		BIT(0)
+#define GPSR6_USB31_OVC		BIT(31)
+#define GPSR6_USB31_PWEN	BIT(30)
+#define GPSR6_USB30_OVC		BIT(29)
+#define GPSR6_USB30_PWEN	BIT(28)
+#define GPSR6_USB1_OVC		BIT(27)
+#define GPSR6_USB1_PWEN		BIT(26)
+#define GPSR6_USB0_OVC		BIT(25)
+#define GPSR6_USB0_PWEN		BIT(24)
+#define GPSR6_AUDIO_CLKB_B	BIT(23)
+#define GPSR6_AUDIO_CLKA_A	BIT(22)
+#define GPSR6_SSI_SDATA9_A	BIT(21)
+#define GPSR6_SSI_SDATA8	BIT(20)
+#define GPSR6_SSI_SDATA7	BIT(19)
+#define GPSR6_SSI_WS78		BIT(18)
+#define GPSR6_SSI_SCK78		BIT(17)
+#define GPSR6_SSI_SDATA6	BIT(16)
+#define GPSR6_SSI_WS6		BIT(15)
+#define GPSR6_SSI_SCK6		BIT(14)
+#define GPSR6_SSI_SDATA5	BIT(13)
+#define GPSR6_SSI_WS5		BIT(12)
+#define GPSR6_SSI_SCK5		BIT(11)
+#define GPSR6_SSI_SDATA4	BIT(10)
+#define GPSR6_SSI_WS4		BIT(9)
+#define GPSR6_SSI_SCK4		BIT(8)
+#define GPSR6_SSI_SDATA3	BIT(7)
+#define GPSR6_SSI_WS34		BIT(6)
+#define GPSR6_SSI_SCK34		BIT(5)
+#define GPSR6_SSI_SDATA2_A	BIT(4)
+#define GPSR6_SSI_SDATA1_A	BIT(3)
+#define GPSR6_SSI_SDATA0	BIT(2)
+#define GPSR6_SSI_WS0129	BIT(1)
+#define GPSR6_SSI_SCK0129	BIT(0)
+#define GPSR7_HDMI1_CEC		BIT(3)
+#define GPSR7_HDMI0_CEC		BIT(2)
+#define GPSR7_AVS2		BIT(1)
+#define GPSR7_AVS1		BIT(0)
+
+#define IPSR_28_FUNC(x)		((uint32_t)(x) << 28U)
+#define IPSR_24_FUNC(x)		((uint32_t)(x) << 24U)
+#define IPSR_20_FUNC(x)		((uint32_t)(x) << 20U)
+#define IPSR_16_FUNC(x)		((uint32_t)(x) << 16U)
+#define IPSR_12_FUNC(x)		((uint32_t)(x) << 12U)
+#define IPSR_8_FUNC(x)		((uint32_t)(x) << 8U)
+#define IPSR_4_FUNC(x)		((uint32_t)(x) << 4U)
+#define IPSR_0_FUNC(x)		((uint32_t)(x) << 0U)
+
+#define POC_SD3_DS_33V		BIT(29)
+#define POC_SD3_DAT7_33V	BIT(28)
+#define POC_SD3_DAT6_33V	BIT(27)
+#define POC_SD3_DAT5_33V	BIT(26)
+#define POC_SD3_DAT4_33V	BIT(25)
+#define POC_SD3_DAT3_33V	BIT(24)
+#define POC_SD3_DAT2_33V	BIT(23)
+#define POC_SD3_DAT1_33V	BIT(22)
+#define POC_SD3_DAT0_33V	BIT(21)
+#define POC_SD3_CMD_33V		BIT(20)
+#define POC_SD3_CLK_33V		BIT(19)
+#define POC_SD2_DS_33V		BIT(18)
+#define POC_SD2_DAT3_33V	BIT(17)
+#define POC_SD2_DAT2_33V	BIT(16)
+#define POC_SD2_DAT1_33V	BIT(15)
+#define POC_SD2_DAT0_33V	BIT(14)
+#define POC_SD2_CMD_33V		BIT(13)
+#define POC_SD2_CLK_33V		BIT(12)
+#define POC_SD1_DAT3_33V	BIT(11)
+#define POC_SD1_DAT2_33V	BIT(10)
+#define POC_SD1_DAT1_33V	BIT(9)
+#define POC_SD1_DAT0_33V	BIT(8)
+#define POC_SD1_CMD_33V		BIT(7)
+#define POC_SD1_CLK_33V		BIT(6)
+#define POC_SD0_DAT3_33V	BIT(5)
+#define POC_SD0_DAT2_33V	BIT(4)
+#define POC_SD0_DAT1_33V	BIT(3)
+#define POC_SD0_DAT0_33V	BIT(2)
+#define POC_SD0_CMD_33V		BIT(1)
+#define POC_SD0_CLK_33V		BIT(0)
+
+#define DRVCTRL0_MASK		(0xCCCCCCCCU)
+#define DRVCTRL1_MASK		(0xCCCCCCC8U)
+#define DRVCTRL2_MASK		(0x88888888U)
+#define DRVCTRL3_MASK		(0x88888888U)
+#define DRVCTRL4_MASK		(0x88888888U)
+#define DRVCTRL5_MASK		(0x88888888U)
+#define DRVCTRL6_MASK		(0x88888888U)
+#define DRVCTRL7_MASK		(0x88888888U)
+#define DRVCTRL8_MASK		(0x88888888U)
+#define DRVCTRL9_MASK		(0x88888888U)
+#define DRVCTRL10_MASK		(0x88888888U)
+#define DRVCTRL11_MASK		(0x888888CCU)
+#define DRVCTRL12_MASK		(0xCCCFFFCFU)
+#define DRVCTRL13_MASK		(0xCC888888U)
+#define DRVCTRL14_MASK		(0x88888888U)
+#define DRVCTRL15_MASK		(0x88888888U)
+#define DRVCTRL16_MASK		(0x88888888U)
+#define DRVCTRL17_MASK		(0x88888888U)
+#define DRVCTRL18_MASK		(0x88888888U)
+#define DRVCTRL19_MASK		(0x88888888U)
+#define DRVCTRL20_MASK		(0x88888888U)
+#define DRVCTRL21_MASK		(0x88888888U)
+#define DRVCTRL22_MASK		(0x88888888U)
+#define DRVCTRL23_MASK		(0x88888888U)
+#define DRVCTRL24_MASK		(0x8888888FU)
+
+#define DRVCTRL0_QSPI0_SPCLK(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL0_QSPI0_MOSI_IO0(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL0_QSPI0_MISO_IO1(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL0_QSPI0_IO2(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL0_QSPI0_IO3(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL0_QSPI0_SSL(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL0_QSPI1_SPCLK(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL0_QSPI1_MOSI_IO0(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL1_QSPI1_MISO_IO1(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL1_QSPI1_IO2(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL1_QSPI1_IO3(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL1_QSPI1_SS(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL1_RPC_INT(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL1_RPC_WP(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL1_RPC_RESET(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL1_AVB_RX_CTL(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL2_AVB_RXC(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL2_AVB_RD0(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL2_AVB_RD1(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL2_AVB_RD2(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL2_AVB_RD3(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL2_AVB_TX_CTL(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL2_AVB_TXC(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL2_AVB_TD0(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL3_AVB_TD1(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL3_AVB_TD2(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL3_AVB_TD3(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL3_AVB_TXCREFCLK(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL3_AVB_MDIO(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL3_AVB_MDC(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL3_AVB_MAGIC(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL3_AVB_PHY_INT(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL4_AVB_LINK(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL4_AVB_AVTP_MATCH(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL4_AVB_AVTP_CAPTURE(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL4_IRQ0(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL4_IRQ1(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL4_IRQ2(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL4_IRQ3(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL4_IRQ4(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL5_IRQ5(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL5_PWM0(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL5_PWM1(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL5_PWM2(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL5_A0(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL5_A1(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL5_A2(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL5_A3(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL6_A4(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL6_A5(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL6_A6(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL6_A7(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL6_A8(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL6_A9(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL6_A10(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL6_A11(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL7_A12(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL7_A13(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL7_A14(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL7_A15(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL7_A16(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL7_A17(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL7_A18(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL7_A19(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL8_CLKOUT(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL8_CS0(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL8_CS1_A2(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL8_BS(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL8_RD(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL8_RD_W(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL8_WE0(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL8_WE1(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL9_EX_WAIT0(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL9_PRESETOU(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL9_D0(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL9_D1(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL9_D2(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL9_D3(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL9_D4(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL9_D5(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL10_D6(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL10_D7(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL10_D8(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL10_D9(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL10_D10(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL10_D11(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL10_D12(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL10_D13(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL11_D14(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL11_D15(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL11_AVS1(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL11_AVS2(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL11_HDMI0_CEC(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL11_HDMI1_CEC(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL11_DU_DOTCLKIN0(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL11_DU_DOTCLKIN1(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL12_DU_DOTCLKIN2(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL12_DU_DOTCLKIN3(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL12_DU_FSCLKST(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL12_DU_TMS(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL13_TDO(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL13_ASEBRK(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL13_SD0_CLK(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL13_SD0_CMD(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL13_SD0_DAT0(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL13_SD0_DAT1(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL13_SD0_DAT2(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL13_SD0_DAT3(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL14_SD1_CLK(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL14_SD1_CMD(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL14_SD1_DAT0(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL14_SD1_DAT1(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL14_SD1_DAT2(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL14_SD1_DAT3(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL14_SD2_CLK(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL14_SD2_CMD(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL15_SD2_DAT0(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL15_SD2_DAT1(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL15_SD2_DAT2(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL15_SD2_DAT3(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL15_SD2_DS(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL15_SD3_CLK(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL15_SD3_CMD(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL15_SD3_DAT0(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL16_SD3_DAT1(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL16_SD3_DAT2(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL16_SD3_DAT3(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL16_SD3_DAT4(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL16_SD3_DAT5(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL16_SD3_DAT6(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL16_SD3_DAT7(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL16_SD3_DS(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL17_SD0_CD(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL17_SD0_WP(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL17_SD1_CD(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL17_SD1_WP(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL17_SCK0(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL17_RX0(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL17_TX0(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL17_CTS0(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL18_RTS0_TANS(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL18_RX1(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL18_TX1(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL18_CTS1(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL18_RTS1_TANS(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL18_SCK2(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL18_TX2(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL18_RX2(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL19_HSCK0(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL19_HRX0(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL19_HTX0(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL19_HCTS0(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL19_HRTS0(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL19_MSIOF0_SCK(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL19_MSIOF0_SYNC(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL19_MSIOF0_SS1(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL20_MSIOF0_TXD(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL20_MSIOF0_SS2(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL20_MSIOF0_RXD(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL20_MLB_CLK(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL20_MLB_SIG(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL20_MLB_DAT(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL20_MLB_REF(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL20_SSI_SCK0129(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL21_SSI_WS0129(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL21_SSI_SDATA0(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL21_SSI_SDATA1(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL21_SSI_SDATA2(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL21_SSI_SCK34(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL21_SSI_WS34(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL21_SSI_SDATA3(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL21_SSI_SCK4(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL22_SSI_WS4(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL22_SSI_SDATA4(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL22_SSI_SCK5(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL22_SSI_WS5(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL22_SSI_SDATA5(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL22_SSI_SCK6(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL22_SSI_WS6(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL22_SSI_SDATA6(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL23_SSI_SCK78(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL23_SSI_WS78(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL23_SSI_SDATA7(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL23_SSI_SDATA8(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL23_SSI_SDATA9(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL23_AUDIO_CLKA(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL23_AUDIO_CLKB(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL23_USB0_PWEN(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL24_USB0_OVC(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL24_USB1_PWEN(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL24_USB1_OVC(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL24_USB30_PWEN(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL24_USB30_OVC(x)	((uint32_t)(x) << 12U)
+#define DRVCTRL24_USB31_PWEN(x)	((uint32_t)(x) << 8U)
+#define DRVCTRL24_USB31_OVC(x)	((uint32_t)(x) << 4U)
+
+#define MOD_SEL0_MSIOF3_A	((uint32_t)0U << 29U)
+#define MOD_SEL0_MSIOF3_B	((uint32_t)1U << 29U)
+#define MOD_SEL0_MSIOF3_C	((uint32_t)2U << 29U)
+#define MOD_SEL0_MSIOF3_D	((uint32_t)3U << 29U)
+#define MOD_SEL0_MSIOF3_E	((uint32_t)4U << 29U)
+#define MOD_SEL0_MSIOF2_A	((uint32_t)0U << 27U)
+#define MOD_SEL0_MSIOF2_B	((uint32_t)1U << 27U)
+#define MOD_SEL0_MSIOF2_C	((uint32_t)2U << 27U)
+#define MOD_SEL0_MSIOF2_D	((uint32_t)3U << 27U)
+#define MOD_SEL0_MSIOF1_A	((uint32_t)0U << 24U)
+#define MOD_SEL0_MSIOF1_B	((uint32_t)1U << 24U)
+#define MOD_SEL0_MSIOF1_C	((uint32_t)2U << 24U)
+#define MOD_SEL0_MSIOF1_D	((uint32_t)3U << 24U)
+#define MOD_SEL0_MSIOF1_E	((uint32_t)4U << 24U)
+#define MOD_SEL0_MSIOF1_F	((uint32_t)5U << 24U)
+#define MOD_SEL0_MSIOF1_G	((uint32_t)6U << 24U)
+#define MOD_SEL0_LBSC_A		((uint32_t)0U << 23U)
+#define MOD_SEL0_LBSC_B		((uint32_t)1U << 23U)
+#define MOD_SEL0_IEBUS_A	((uint32_t)0U << 22U)
+#define MOD_SEL0_IEBUS_B	((uint32_t)1U << 22U)
+#define MOD_SEL0_I2C2_A		((uint32_t)0U << 21U)
+#define MOD_SEL0_I2C2_B		((uint32_t)1U << 21U)
+#define MOD_SEL0_I2C1_A		((uint32_t)0U << 20U)
+#define MOD_SEL0_I2C1_B		((uint32_t)1U << 20U)
+#define MOD_SEL0_HSCIF4_A	((uint32_t)0U << 19U)
+#define MOD_SEL0_HSCIF4_B	((uint32_t)1U << 19U)
+#define MOD_SEL0_HSCIF3_A	((uint32_t)0U << 17U)
+#define MOD_SEL0_HSCIF3_B	((uint32_t)1U << 17U)
+#define MOD_SEL0_HSCIF3_C	((uint32_t)2U << 17U)
+#define MOD_SEL0_HSCIF3_D	((uint32_t)3U << 17U)
+#define MOD_SEL0_HSCIF1_A	((uint32_t)0U << 16U)
+#define MOD_SEL0_HSCIF1_B	((uint32_t)1U << 16U)
+#define MOD_SEL0_FSO_A		((uint32_t)0U << 15U)
+#define MOD_SEL0_FSO_B		((uint32_t)1U << 15U)
+#define MOD_SEL0_HSCIF2_A	((uint32_t)0U << 13U)
+#define MOD_SEL0_HSCIF2_B	((uint32_t)1U << 13U)
+#define MOD_SEL0_HSCIF2_C	((uint32_t)2U << 13U)
+#define MOD_SEL0_ETHERAVB_A	((uint32_t)0U << 12U)
+#define MOD_SEL0_ETHERAVB_B	((uint32_t)1U << 12U)
+#define MOD_SEL0_DRIF3_A	((uint32_t)0U << 11U)
+#define MOD_SEL0_DRIF3_B	((uint32_t)1U << 11U)
+#define MOD_SEL0_DRIF2_A	((uint32_t)0U << 10U)
+#define MOD_SEL0_DRIF2_B	((uint32_t)1U << 10U)
+#define MOD_SEL0_DRIF1_A	((uint32_t)0U << 8U)
+#define MOD_SEL0_DRIF1_B	((uint32_t)1U << 8U)
+#define MOD_SEL0_DRIF1_C	((uint32_t)2U << 8U)
+#define MOD_SEL0_DRIF0_A	((uint32_t)0U << 6U)
+#define MOD_SEL0_DRIF0_B	((uint32_t)1U << 6U)
+#define MOD_SEL0_DRIF0_C	((uint32_t)2U << 6U)
+#define MOD_SEL0_CANFD0_A	((uint32_t)0U << 5U)
+#define MOD_SEL0_CANFD0_B	((uint32_t)1U << 5U)
+#define MOD_SEL0_ADG_A_A	((uint32_t)0U << 3U)
+#define MOD_SEL0_ADG_A_B	((uint32_t)1U << 3U)
+#define MOD_SEL0_ADG_A_C	((uint32_t)2U << 3U)
+#define MOD_SEL1_TSIF1_A	((uint32_t)0U << 30U)
+#define MOD_SEL1_TSIF1_B	((uint32_t)1U << 30U)
+#define MOD_SEL1_TSIF1_C	((uint32_t)2U << 30U)
+#define MOD_SEL1_TSIF1_D	((uint32_t)3U << 30U)
+#define MOD_SEL1_TSIF0_A	((uint32_t)0U << 27U)
+#define MOD_SEL1_TSIF0_B	((uint32_t)1U << 27U)
+#define MOD_SEL1_TSIF0_C	((uint32_t)2U << 27U)
+#define MOD_SEL1_TSIF0_D	((uint32_t)3U << 27U)
+#define MOD_SEL1_TSIF0_E	((uint32_t)4U << 27U)
+#define MOD_SEL1_TIMER_TMU_A	((uint32_t)0U << 26U)
+#define MOD_SEL1_TIMER_TMU_B	((uint32_t)1U << 26U)
+#define MOD_SEL1_SSP1_1_A	((uint32_t)0U << 24U)
+#define MOD_SEL1_SSP1_1_B	((uint32_t)1U << 24U)
+#define MOD_SEL1_SSP1_1_C	((uint32_t)2U << 24U)
+#define MOD_SEL1_SSP1_1_D	((uint32_t)3U << 24U)
+#define MOD_SEL1_SSP1_0_A	((uint32_t)0U << 21U)
+#define MOD_SEL1_SSP1_0_B	((uint32_t)1U << 21U)
+#define MOD_SEL1_SSP1_0_C	((uint32_t)2U << 21U)
+#define MOD_SEL1_SSP1_0_D	((uint32_t)3U << 21U)
+#define MOD_SEL1_SSP1_0_E	((uint32_t)4U << 21U)
+#define MOD_SEL1_SSI_A		((uint32_t)0U << 20U)
+#define MOD_SEL1_SSI_B		((uint32_t)1U << 20U)
+#define MOD_SEL1_SPEED_PULSE_IF_A	((uint32_t)0U << 19U)
+#define MOD_SEL1_SPEED_PULSE_IF_B	((uint32_t)1U << 19U)
+#define MOD_SEL1_SIMCARD_A	((uint32_t)0U << 17U)
+#define MOD_SEL1_SIMCARD_B	((uint32_t)1U << 17U)
+#define MOD_SEL1_SIMCARD_C	((uint32_t)2U << 17U)
+#define MOD_SEL1_SIMCARD_D	((uint32_t)3U << 17U)
+#define MOD_SEL1_SDHI2_A	((uint32_t)0U << 16U)
+#define MOD_SEL1_SDHI2_B	((uint32_t)1U << 16U)
+#define MOD_SEL1_SCIF4_A	((uint32_t)0U << 14U)
+#define MOD_SEL1_SCIF4_B	((uint32_t)1U << 14U)
+#define MOD_SEL1_SCIF4_C	((uint32_t)2U << 14U)
+#define MOD_SEL1_SCIF3_A	((uint32_t)0U << 13U)
+#define MOD_SEL1_SCIF3_B	((uint32_t)1U << 13U)
+#define MOD_SEL1_SCIF2_A	((uint32_t)0U << 12U)
+#define MOD_SEL1_SCIF2_B	((uint32_t)1U << 12U)
+#define MOD_SEL1_SCIF1_A	((uint32_t)0U << 11U)
+#define MOD_SEL1_SCIF1_B	((uint32_t)1U << 11U)
+#define MOD_SEL1_SCIF_A		((uint32_t)0U << 10U)
+#define MOD_SEL1_SCIF_B		((uint32_t)1U << 10U)
+#define MOD_SEL1_REMOCON_A	((uint32_t)0U << 9U)
+#define MOD_SEL1_REMOCON_B	((uint32_t)1U << 9U)
+#define MOD_SEL1_RCAN0_A	((uint32_t)0U << 6U)
+#define MOD_SEL1_RCAN0_B	((uint32_t)1U << 6U)
+#define MOD_SEL1_PWM6_A		((uint32_t)0U << 5U)
+#define MOD_SEL1_PWM6_B		((uint32_t)1U << 5U)
+#define MOD_SEL1_PWM5_A		((uint32_t)0U << 4U)
+#define MOD_SEL1_PWM5_B		((uint32_t)1U << 4U)
+#define MOD_SEL1_PWM4_A		((uint32_t)0U << 3U)
+#define MOD_SEL1_PWM4_B		((uint32_t)1U << 3U)
+#define MOD_SEL1_PWM3_A		((uint32_t)0U << 2U)
+#define MOD_SEL1_PWM3_B		((uint32_t)1U << 2U)
+#define MOD_SEL1_PWM2_A		((uint32_t)0U << 1U)
+#define MOD_SEL1_PWM2_B		((uint32_t)1U << 1U)
+#define MOD_SEL1_PWM1_A		((uint32_t)0U << 0U)
+#define MOD_SEL1_PWM1_B		((uint32_t)1U << 0U)
+#define MOD_SEL2_I2C_5_A	((uint32_t)0U << 31U)
+#define MOD_SEL2_I2C_5_B	((uint32_t)1U << 31U)
+#define MOD_SEL2_I2C_3_A	((uint32_t)0U << 30U)
+#define MOD_SEL2_I2C_3_B	((uint32_t)1U << 30U)
+#define MOD_SEL2_I2C_0_A	((uint32_t)0U << 29U)
+#define MOD_SEL2_I2C_0_B	((uint32_t)1U << 29U)
+#define MOD_SEL2_FM_A		((uint32_t)0U << 27U)
+#define MOD_SEL2_FM_B		((uint32_t)1U << 27U)
+#define MOD_SEL2_FM_C		((uint32_t)2U << 27U)
+#define MOD_SEL2_FM_D		((uint32_t)3U << 27U)
+#define MOD_SEL2_SCIF5_A	((uint32_t)0U << 26U)
+#define MOD_SEL2_SCIF5_B	((uint32_t)1U << 26U)
+#define MOD_SEL2_I2C6_A		((uint32_t)0U << 23U)
+#define MOD_SEL2_I2C6_B		((uint32_t)1U << 23U)
+#define MOD_SEL2_I2C6_C		((uint32_t)2U << 23U)
+#define MOD_SEL2_NDF_A		((uint32_t)0U << 22U)
+#define MOD_SEL2_NDF_B		((uint32_t)1U << 22U)
+#define MOD_SEL2_SSI2_A		((uint32_t)0U << 21U)
+#define MOD_SEL2_SSI2_B		((uint32_t)1U << 21U)
+#define MOD_SEL2_SSI9_A		((uint32_t)0U << 20U)
+#define MOD_SEL2_SSI9_B		((uint32_t)1U << 20U)
+#define MOD_SEL2_TIMER_TMU2_A	((uint32_t)0U << 19U)
+#define MOD_SEL2_TIMER_TMU2_B	((uint32_t)1U << 19U)
+#define MOD_SEL2_ADG_B_A	((uint32_t)0U << 18U)
+#define MOD_SEL2_ADG_B_B	((uint32_t)1U << 18U)
+#define MOD_SEL2_ADG_C_A	((uint32_t)0U << 17U)
+#define MOD_SEL2_ADG_C_B	((uint32_t)1U << 17U)
+#define MOD_SEL2_VIN4_A		((uint32_t)0U << 0U)
+#define MOD_SEL2_VIN4_B		((uint32_t)1U << 0U)
+
+static void pfc_reg_write(uint32_t addr, uint32_t data)
+{
+	mmio_write_32(PFC_PMMR, ~data);
+	mmio_write_32((uintptr_t)addr, data);
+}
+
+void pfc_init_m3n(void)
+{
+	uint32_t reg;
+
+	/* initialize module select */
+	pfc_reg_write(PFC_MOD_SEL0, MOD_SEL0_MSIOF3_A
+		      | MOD_SEL0_MSIOF2_A
+		      | MOD_SEL0_MSIOF1_A
+		      | MOD_SEL0_LBSC_A
+		      | MOD_SEL0_IEBUS_A
+		      | MOD_SEL0_I2C2_A
+		      | MOD_SEL0_I2C1_A
+		      | MOD_SEL0_HSCIF4_A
+		      | MOD_SEL0_HSCIF3_A
+		      | MOD_SEL0_HSCIF1_A
+		      | MOD_SEL0_FSO_A
+		      | MOD_SEL0_HSCIF2_A
+		      | MOD_SEL0_ETHERAVB_A
+		      | MOD_SEL0_DRIF3_A
+		      | MOD_SEL0_DRIF2_A
+		      | MOD_SEL0_DRIF1_A
+		      | MOD_SEL0_DRIF0_A
+		      | MOD_SEL0_CANFD0_A
+		      | MOD_SEL0_ADG_A_A);
+	pfc_reg_write(PFC_MOD_SEL1, MOD_SEL1_TSIF1_A
+		      | MOD_SEL1_TSIF0_A
+		      | MOD_SEL1_TIMER_TMU_A
+		      | MOD_SEL1_SSP1_1_A
+		      | MOD_SEL1_SSP1_0_A
+		      | MOD_SEL1_SSI_A
+		      | MOD_SEL1_SPEED_PULSE_IF_A
+		      | MOD_SEL1_SIMCARD_A
+		      | MOD_SEL1_SDHI2_A
+		      | MOD_SEL1_SCIF4_A
+		      | MOD_SEL1_SCIF3_A
+		      | MOD_SEL1_SCIF2_A
+		      | MOD_SEL1_SCIF1_A
+		      | MOD_SEL1_SCIF_A
+		      | MOD_SEL1_REMOCON_A
+		      | MOD_SEL1_RCAN0_A
+		      | MOD_SEL1_PWM6_A
+		      | MOD_SEL1_PWM5_A
+		      | MOD_SEL1_PWM4_A
+		      | MOD_SEL1_PWM3_A
+		      | MOD_SEL1_PWM2_A
+		      | MOD_SEL1_PWM1_A);
+	pfc_reg_write(PFC_MOD_SEL2, MOD_SEL2_I2C_5_A
+		      | MOD_SEL2_I2C_3_A
+		      | MOD_SEL2_I2C_0_A
+		      | MOD_SEL2_FM_A
+		      | MOD_SEL2_SCIF5_A
+		      | MOD_SEL2_I2C6_A
+		      | MOD_SEL2_NDF_A
+		      | MOD_SEL2_SSI2_A
+		      | MOD_SEL2_SSI9_A
+		      | MOD_SEL2_TIMER_TMU2_A
+		      | MOD_SEL2_ADG_B_A
+		      | MOD_SEL2_ADG_C_A
+		      | MOD_SEL2_VIN4_A);
+
+	/* initialize peripheral function select */
+	pfc_reg_write(PFC_IPSR0, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR1, IPSR_28_FUNC(6)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(3)
+		      | IPSR_8_FUNC(3)
+		      | IPSR_4_FUNC(3)
+		      | IPSR_0_FUNC(3));
+	pfc_reg_write(PFC_IPSR2, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(6)
+		      | IPSR_20_FUNC(6)
+		      | IPSR_16_FUNC(6)
+		      | IPSR_12_FUNC(6)
+		      | IPSR_8_FUNC(6)
+		      | IPSR_4_FUNC(6)
+		      | IPSR_0_FUNC(6));
+	pfc_reg_write(PFC_IPSR3, IPSR_28_FUNC(6)
+		      | IPSR_24_FUNC(6)
+		      | IPSR_20_FUNC(6)
+		      | IPSR_16_FUNC(6)
+		      | IPSR_12_FUNC(6)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR4, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(6)
+		      | IPSR_4_FUNC(6)
+		      | IPSR_0_FUNC(6));
+	pfc_reg_write(PFC_IPSR5, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(6)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR6, IPSR_28_FUNC(6)
+		      | IPSR_24_FUNC(6)
+		      | IPSR_20_FUNC(6)
+		      | IPSR_16_FUNC(6)
+		      | IPSR_12_FUNC(6)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR7, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(6)
+		      | IPSR_4_FUNC(6)
+		      | IPSR_0_FUNC(6));
+	pfc_reg_write(PFC_IPSR8, IPSR_28_FUNC(1)
+		      | IPSR_24_FUNC(1)
+		      | IPSR_20_FUNC(1)
+		      | IPSR_16_FUNC(1)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR9, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR10, IPSR_28_FUNC(1)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR11, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(4)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(1));
+	pfc_reg_write(PFC_IPSR12, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(4)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR13, IPSR_28_FUNC(8)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(3)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR14, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(3)
+		      | IPSR_0_FUNC(8));
+	pfc_reg_write(PFC_IPSR15, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR16, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR17, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(1)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR18, IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+
+	/* initialize GPIO/perihperal function select */
+	pfc_reg_write(PFC_GPSR0, GPSR0_D15
+		      | GPSR0_D14
+		      | GPSR0_D13
+		      | GPSR0_D12
+		      | GPSR0_D11
+		      | GPSR0_D10
+		      | GPSR0_D9
+		      | GPSR0_D8);
+	pfc_reg_write(PFC_GPSR1, GPSR1_CLKOUT
+		      | GPSR1_EX_WAIT0_A
+		      | GPSR1_A19
+		      | GPSR1_A18
+		      | GPSR1_A17
+		      | GPSR1_A16
+		      | GPSR1_A15
+		      | GPSR1_A14
+		      | GPSR1_A13
+		      | GPSR1_A12
+		      | GPSR1_A7
+		      | GPSR1_A6
+		      | GPSR1_A5
+		      | GPSR1_A4
+		      | GPSR1_A3
+		      | GPSR1_A2
+		      | GPSR1_A1
+		      | GPSR1_A0);
+	pfc_reg_write(PFC_GPSR2, GPSR2_AVB_AVTP_CAPTURE_A
+		      | GPSR2_AVB_AVTP_MATCH_A
+		      | GPSR2_AVB_LINK
+		      | GPSR2_AVB_PHY_INT
+		      | GPSR2_AVB_MDC
+		      | GPSR2_PWM2_A
+		      | GPSR2_PWM1_A
+		      | GPSR2_IRQ5
+		      | GPSR2_IRQ4
+		      | GPSR2_IRQ3
+		      | GPSR2_IRQ2
+		      | GPSR2_IRQ1
+		      | GPSR2_IRQ0);
+	pfc_reg_write(PFC_GPSR3, GPSR3_SD0_WP
+		      | GPSR3_SD0_CD
+		      | GPSR3_SD1_DAT3
+		      | GPSR3_SD1_DAT2
+		      | GPSR3_SD1_DAT1
+		      | GPSR3_SD1_DAT0
+		      | GPSR3_SD0_DAT3
+		      | GPSR3_SD0_DAT2
+		      | GPSR3_SD0_DAT1
+		      | GPSR3_SD0_DAT0
+		      | GPSR3_SD0_CMD
+		      | GPSR3_SD0_CLK);
+	pfc_reg_write(PFC_GPSR4, GPSR4_SD3_DAT7
+		      | GPSR4_SD3_DAT6
+		      | GPSR4_SD3_DAT3
+		      | GPSR4_SD3_DAT2
+		      | GPSR4_SD3_DAT1
+		      | GPSR4_SD3_DAT0
+		      | GPSR4_SD3_CMD
+		      | GPSR4_SD3_CLK
+		      | GPSR4_SD2_DS
+		      | GPSR4_SD2_DAT3
+		      | GPSR4_SD2_DAT2
+		      | GPSR4_SD2_DAT1
+		      | GPSR4_SD2_DAT0
+		      | GPSR4_SD2_CMD
+		      | GPSR4_SD2_CLK);
+	pfc_reg_write(PFC_GPSR5, GPSR5_MSIOF0_SS2
+		      | GPSR5_MSIOF0_SS1
+		      | GPSR5_MSIOF0_SYNC
+		      | GPSR5_HRTS0
+		      | GPSR5_HCTS0
+		      | GPSR5_HTX0
+		      | GPSR5_HRX0
+		      | GPSR5_HSCK0
+		      | GPSR5_RX2_A
+		      | GPSR5_TX2_A
+		      | GPSR5_SCK2
+		      | GPSR5_RTS1_TANS
+		      | GPSR5_CTS1
+		      | GPSR5_TX1_A
+		      | GPSR5_RX1_A
+		      | GPSR5_RTS0_TANS
+		      | GPSR5_SCK0);
+	pfc_reg_write(PFC_GPSR6, GPSR6_USB30_OVC
+		      | GPSR6_USB30_PWEN
+		      | GPSR6_USB1_OVC
+		      | GPSR6_USB1_PWEN
+		      | GPSR6_USB0_OVC
+		      | GPSR6_USB0_PWEN
+		      | GPSR6_AUDIO_CLKB_B
+		      | GPSR6_AUDIO_CLKA_A
+		      | GPSR6_SSI_SDATA8
+		      | GPSR6_SSI_SDATA7
+		      | GPSR6_SSI_WS78
+		      | GPSR6_SSI_SCK78
+		      | GPSR6_SSI_WS6
+		      | GPSR6_SSI_SCK6
+		      | GPSR6_SSI_SDATA4
+		      | GPSR6_SSI_WS4
+		      | GPSR6_SSI_SCK4
+		      | GPSR6_SSI_SDATA1_A
+		      | GPSR6_SSI_SDATA0
+		      | GPSR6_SSI_WS0129
+		      | GPSR6_SSI_SCK0129);
+	pfc_reg_write(PFC_GPSR7, GPSR7_HDMI1_CEC
+		      | GPSR7_HDMI0_CEC
+		      | GPSR7_AVS2
+		      | GPSR7_AVS1);
+
+	/* initialize POC control register */
+	pfc_reg_write(PFC_POCCTRL0, POC_SD3_DS_33V
+		      | POC_SD3_DAT7_33V
+		      | POC_SD3_DAT6_33V
+		      | POC_SD3_DAT5_33V
+		      | POC_SD3_DAT4_33V
+		      | POC_SD3_DAT3_33V
+		      | POC_SD3_DAT2_33V
+		      | POC_SD3_DAT1_33V
+		      | POC_SD3_DAT0_33V
+		      | POC_SD3_CMD_33V
+		      | POC_SD3_CLK_33V
+		      | POC_SD0_DAT3_33V
+		      | POC_SD0_DAT2_33V
+		      | POC_SD0_DAT1_33V
+		      | POC_SD0_DAT0_33V
+		      | POC_SD0_CMD_33V
+		      | POC_SD0_CLK_33V);
+
+	/* initialize DRV control register */
+	reg = mmio_read_32(PFC_DRVCTRL0);
+	reg = ((reg & DRVCTRL0_MASK) | DRVCTRL0_QSPI0_SPCLK(3)
+	       | DRVCTRL0_QSPI0_MOSI_IO0(3)
+	       | DRVCTRL0_QSPI0_MISO_IO1(3)
+	       | DRVCTRL0_QSPI0_IO2(3)
+	       | DRVCTRL0_QSPI0_IO3(3)
+	       | DRVCTRL0_QSPI0_SSL(3)
+	       | DRVCTRL0_QSPI1_SPCLK(3)
+	       | DRVCTRL0_QSPI1_MOSI_IO0(3));
+	pfc_reg_write(PFC_DRVCTRL0, reg);
+	reg = mmio_read_32(PFC_DRVCTRL1);
+	reg = ((reg & DRVCTRL1_MASK) | DRVCTRL1_QSPI1_MISO_IO1(3)
+	       | DRVCTRL1_QSPI1_IO2(3)
+	       | DRVCTRL1_QSPI1_IO3(3)
+	       | DRVCTRL1_QSPI1_SS(3)
+	       | DRVCTRL1_RPC_INT(3)
+	       | DRVCTRL1_RPC_WP(3)
+	       | DRVCTRL1_RPC_RESET(3)
+	       | DRVCTRL1_AVB_RX_CTL(7));
+	pfc_reg_write(PFC_DRVCTRL1, reg);
+	reg = mmio_read_32(PFC_DRVCTRL2);
+	reg = ((reg & DRVCTRL2_MASK) | DRVCTRL2_AVB_RXC(7)
+	       | DRVCTRL2_AVB_RD0(7)
+	       | DRVCTRL2_AVB_RD1(7)
+	       | DRVCTRL2_AVB_RD2(7)
+	       | DRVCTRL2_AVB_RD3(7)
+	       | DRVCTRL2_AVB_TX_CTL(3)
+	       | DRVCTRL2_AVB_TXC(3)
+	       | DRVCTRL2_AVB_TD0(3));
+	pfc_reg_write(PFC_DRVCTRL2, reg);
+	reg = mmio_read_32(PFC_DRVCTRL3);
+	reg = ((reg & DRVCTRL3_MASK) | DRVCTRL3_AVB_TD1(3)
+	       | DRVCTRL3_AVB_TD2(3)
+	       | DRVCTRL3_AVB_TD3(3)
+	       | DRVCTRL3_AVB_TXCREFCLK(7)
+	       | DRVCTRL3_AVB_MDIO(7)
+	       | DRVCTRL3_AVB_MDC(7)
+	       | DRVCTRL3_AVB_MAGIC(7)
+	       | DRVCTRL3_AVB_PHY_INT(7));
+	pfc_reg_write(PFC_DRVCTRL3, reg);
+	reg = mmio_read_32(PFC_DRVCTRL4);
+	reg = ((reg & DRVCTRL4_MASK) | DRVCTRL4_AVB_LINK(7)
+	       | DRVCTRL4_AVB_AVTP_MATCH(7)
+	       | DRVCTRL4_AVB_AVTP_CAPTURE(7)
+	       | DRVCTRL4_IRQ0(7)
+	       | DRVCTRL4_IRQ1(7)
+	       | DRVCTRL4_IRQ2(7)
+	       | DRVCTRL4_IRQ3(7)
+	       | DRVCTRL4_IRQ4(7));
+	pfc_reg_write(PFC_DRVCTRL4, reg);
+	reg = mmio_read_32(PFC_DRVCTRL5);
+	reg = ((reg & DRVCTRL5_MASK) | DRVCTRL5_IRQ5(7)
+	       | DRVCTRL5_PWM0(7)
+	       | DRVCTRL5_PWM1(7)
+	       | DRVCTRL5_PWM2(7)
+	       | DRVCTRL5_A0(3)
+	       | DRVCTRL5_A1(3)
+	       | DRVCTRL5_A2(3)
+	       | DRVCTRL5_A3(3));
+	pfc_reg_write(PFC_DRVCTRL5, reg);
+	reg = mmio_read_32(PFC_DRVCTRL6);
+	reg = ((reg & DRVCTRL6_MASK) | DRVCTRL6_A4(3)
+	       | DRVCTRL6_A5(3)
+	       | DRVCTRL6_A6(3)
+	       | DRVCTRL6_A7(3)
+	       | DRVCTRL6_A8(7)
+	       | DRVCTRL6_A9(7)
+	       | DRVCTRL6_A10(7)
+	       | DRVCTRL6_A11(7));
+	pfc_reg_write(PFC_DRVCTRL6, reg);
+	reg = mmio_read_32(PFC_DRVCTRL7);
+	reg = ((reg & DRVCTRL7_MASK) | DRVCTRL7_A12(3)
+	       | DRVCTRL7_A13(3)
+	       | DRVCTRL7_A14(3)
+	       | DRVCTRL7_A15(3)
+	       | DRVCTRL7_A16(3)
+	       | DRVCTRL7_A17(3)
+	       | DRVCTRL7_A18(3)
+	       | DRVCTRL7_A19(3));
+	pfc_reg_write(PFC_DRVCTRL7, reg);
+	reg = mmio_read_32(PFC_DRVCTRL8);
+	reg = ((reg & DRVCTRL8_MASK) | DRVCTRL8_CLKOUT(7)
+	       | DRVCTRL8_CS0(7)
+	       | DRVCTRL8_CS1_A2(7)
+	       | DRVCTRL8_BS(7)
+	       | DRVCTRL8_RD(7)
+	       | DRVCTRL8_RD_W(7)
+	       | DRVCTRL8_WE0(7)
+	       | DRVCTRL8_WE1(7));
+	pfc_reg_write(PFC_DRVCTRL8, reg);
+	reg = mmio_read_32(PFC_DRVCTRL9);
+	reg = ((reg & DRVCTRL9_MASK) | DRVCTRL9_EX_WAIT0(7)
+	       | DRVCTRL9_PRESETOU(7)
+	       | DRVCTRL9_D0(7)
+	       | DRVCTRL9_D1(7)
+	       | DRVCTRL9_D2(7)
+	       | DRVCTRL9_D3(7)
+	       | DRVCTRL9_D4(7)
+	       | DRVCTRL9_D5(7));
+	pfc_reg_write(PFC_DRVCTRL9, reg);
+	reg = mmio_read_32(PFC_DRVCTRL10);
+	reg = ((reg & DRVCTRL10_MASK) | DRVCTRL10_D6(7)
+	       | DRVCTRL10_D7(7)
+	       | DRVCTRL10_D8(3)
+	       | DRVCTRL10_D9(3)
+	       | DRVCTRL10_D10(3)
+	       | DRVCTRL10_D11(3)
+	       | DRVCTRL10_D12(3)
+	       | DRVCTRL10_D13(3));
+	pfc_reg_write(PFC_DRVCTRL10, reg);
+	reg = mmio_read_32(PFC_DRVCTRL11);
+	reg = ((reg & DRVCTRL11_MASK) | DRVCTRL11_D14(3)
+	       | DRVCTRL11_D15(3)
+	       | DRVCTRL11_AVS1(7)
+	       | DRVCTRL11_AVS2(7)
+	       | DRVCTRL11_HDMI0_CEC(7)
+	       | DRVCTRL11_HDMI1_CEC(7)
+	       | DRVCTRL11_DU_DOTCLKIN0(3)
+	       | DRVCTRL11_DU_DOTCLKIN1(3));
+	pfc_reg_write(PFC_DRVCTRL11, reg);
+	reg = mmio_read_32(PFC_DRVCTRL12);
+	reg = ((reg & DRVCTRL12_MASK) | DRVCTRL12_DU_DOTCLKIN2(3)
+	       | DRVCTRL12_DU_DOTCLKIN3(3)
+	       | DRVCTRL12_DU_FSCLKST(3)
+	       | DRVCTRL12_DU_TMS(3));
+	pfc_reg_write(PFC_DRVCTRL12, reg);
+	reg = mmio_read_32(PFC_DRVCTRL13);
+	reg = ((reg & DRVCTRL13_MASK) | DRVCTRL13_TDO(3)
+	       | DRVCTRL13_ASEBRK(3)
+	       | DRVCTRL13_SD0_CLK(7)
+	       | DRVCTRL13_SD0_CMD(7)
+	       | DRVCTRL13_SD0_DAT0(7)
+	       | DRVCTRL13_SD0_DAT1(7)
+	       | DRVCTRL13_SD0_DAT2(7)
+	       | DRVCTRL13_SD0_DAT3(7));
+	pfc_reg_write(PFC_DRVCTRL13, reg);
+	reg = mmio_read_32(PFC_DRVCTRL14);
+	reg = ((reg & DRVCTRL14_MASK) | DRVCTRL14_SD1_CLK(7)
+	       | DRVCTRL14_SD1_CMD(7)
+	       | DRVCTRL14_SD1_DAT0(5)
+	       | DRVCTRL14_SD1_DAT1(5)
+	       | DRVCTRL14_SD1_DAT2(5)
+	       | DRVCTRL14_SD1_DAT3(5)
+	       | DRVCTRL14_SD2_CLK(5)
+	       | DRVCTRL14_SD2_CMD(5));
+	pfc_reg_write(PFC_DRVCTRL14, reg);
+	reg = mmio_read_32(PFC_DRVCTRL15);
+	reg = ((reg & DRVCTRL15_MASK) | DRVCTRL15_SD2_DAT0(5)
+	       | DRVCTRL15_SD2_DAT1(5)
+	       | DRVCTRL15_SD2_DAT2(5)
+	       | DRVCTRL15_SD2_DAT3(5)
+	       | DRVCTRL15_SD2_DS(5)
+	       | DRVCTRL15_SD3_CLK(7)
+	       | DRVCTRL15_SD3_CMD(7)
+	       | DRVCTRL15_SD3_DAT0(7));
+	pfc_reg_write(PFC_DRVCTRL15, reg);
+	reg = mmio_read_32(PFC_DRVCTRL16);
+	reg = ((reg & DRVCTRL16_MASK) | DRVCTRL16_SD3_DAT1(7)
+	       | DRVCTRL16_SD3_DAT2(7)
+	       | DRVCTRL16_SD3_DAT3(7)
+	       | DRVCTRL16_SD3_DAT4(7)
+	       | DRVCTRL16_SD3_DAT5(7)
+	       | DRVCTRL16_SD3_DAT6(7)
+	       | DRVCTRL16_SD3_DAT7(7)
+	       | DRVCTRL16_SD3_DS(7));
+	pfc_reg_write(PFC_DRVCTRL16, reg);
+	reg = mmio_read_32(PFC_DRVCTRL17);
+	reg = ((reg & DRVCTRL17_MASK) | DRVCTRL17_SD0_CD(7)
+	       | DRVCTRL17_SD0_WP(7)
+	       | DRVCTRL17_SD1_CD(7)
+	       | DRVCTRL17_SD1_WP(7)
+	       | DRVCTRL17_SCK0(7)
+	       | DRVCTRL17_RX0(7)
+	       | DRVCTRL17_TX0(7)
+	       | DRVCTRL17_CTS0(7));
+	pfc_reg_write(PFC_DRVCTRL17, reg);
+	reg = mmio_read_32(PFC_DRVCTRL18);
+	reg = ((reg & DRVCTRL18_MASK) | DRVCTRL18_RTS0_TANS(7)
+	       | DRVCTRL18_RX1(7)
+	       | DRVCTRL18_TX1(7)
+	       | DRVCTRL18_CTS1(7)
+	       | DRVCTRL18_RTS1_TANS(7)
+	       | DRVCTRL18_SCK2(7)
+	       | DRVCTRL18_TX2(7)
+	       | DRVCTRL18_RX2(7));
+	pfc_reg_write(PFC_DRVCTRL18, reg);
+	reg = mmio_read_32(PFC_DRVCTRL19);
+	reg = ((reg & DRVCTRL19_MASK) | DRVCTRL19_HSCK0(7)
+	       | DRVCTRL19_HRX0(7)
+	       | DRVCTRL19_HTX0(7)
+	       | DRVCTRL19_HCTS0(7)
+	       | DRVCTRL19_HRTS0(7)
+	       | DRVCTRL19_MSIOF0_SCK(7)
+	       | DRVCTRL19_MSIOF0_SYNC(7)
+	       | DRVCTRL19_MSIOF0_SS1(7));
+	pfc_reg_write(PFC_DRVCTRL19, reg);
+	reg = mmio_read_32(PFC_DRVCTRL20);
+	reg = ((reg & DRVCTRL20_MASK) | DRVCTRL20_MSIOF0_TXD(7)
+	       | DRVCTRL20_MSIOF0_SS2(7)
+	       | DRVCTRL20_MSIOF0_RXD(7)
+	       | DRVCTRL20_MLB_CLK(7)
+	       | DRVCTRL20_MLB_SIG(7)
+	       | DRVCTRL20_MLB_DAT(7)
+	       | DRVCTRL20_MLB_REF(7)
+	       | DRVCTRL20_SSI_SCK0129(7));
+	pfc_reg_write(PFC_DRVCTRL20, reg);
+	reg = mmio_read_32(PFC_DRVCTRL21);
+	reg = ((reg & DRVCTRL21_MASK) | DRVCTRL21_SSI_WS0129(7)
+	       | DRVCTRL21_SSI_SDATA0(7)
+	       | DRVCTRL21_SSI_SDATA1(7)
+	       | DRVCTRL21_SSI_SDATA2(7)
+	       | DRVCTRL21_SSI_SCK34(7)
+	       | DRVCTRL21_SSI_WS34(7)
+	       | DRVCTRL21_SSI_SDATA3(7)
+	       | DRVCTRL21_SSI_SCK4(7));
+	pfc_reg_write(PFC_DRVCTRL21, reg);
+	reg = mmio_read_32(PFC_DRVCTRL22);
+	reg = ((reg & DRVCTRL22_MASK) | DRVCTRL22_SSI_WS4(7)
+	       | DRVCTRL22_SSI_SDATA4(7)
+	       | DRVCTRL22_SSI_SCK5(7)
+	       | DRVCTRL22_SSI_WS5(7)
+	       | DRVCTRL22_SSI_SDATA5(7)
+	       | DRVCTRL22_SSI_SCK6(7)
+	       | DRVCTRL22_SSI_WS6(7)
+	       | DRVCTRL22_SSI_SDATA6(7));
+	pfc_reg_write(PFC_DRVCTRL22, reg);
+	reg = mmio_read_32(PFC_DRVCTRL23);
+	reg = ((reg & DRVCTRL23_MASK) | DRVCTRL23_SSI_SCK78(7)
+	       | DRVCTRL23_SSI_WS78(7)
+	       | DRVCTRL23_SSI_SDATA7(7)
+	       | DRVCTRL23_SSI_SDATA8(7)
+	       | DRVCTRL23_SSI_SDATA9(7)
+	       | DRVCTRL23_AUDIO_CLKA(7)
+	       | DRVCTRL23_AUDIO_CLKB(7)
+	       | DRVCTRL23_USB0_PWEN(7));
+	pfc_reg_write(PFC_DRVCTRL23, reg);
+	reg = mmio_read_32(PFC_DRVCTRL24);
+	reg = ((reg & DRVCTRL24_MASK) | DRVCTRL24_USB0_OVC(7)
+	       | DRVCTRL24_USB1_PWEN(7)
+	       | DRVCTRL24_USB1_OVC(7)
+	       | DRVCTRL24_USB30_PWEN(7)
+	       | DRVCTRL24_USB30_OVC(7)
+	       | DRVCTRL24_USB31_PWEN(7)
+	       | DRVCTRL24_USB31_OVC(7));
+	pfc_reg_write(PFC_DRVCTRL24, reg);
+
+	/* initialize LSI pin pull-up/down control */
+	pfc_reg_write(PFC_PUD0, 0x00005FBFU);
+	pfc_reg_write(PFC_PUD1, 0x00300FFEU);
+	pfc_reg_write(PFC_PUD2, 0x330001E6U);
+	pfc_reg_write(PFC_PUD3, 0x000002E0U);
+	pfc_reg_write(PFC_PUD4, 0xFFFFFF00U);
+	pfc_reg_write(PFC_PUD5, 0x7F5FFF87U);
+	pfc_reg_write(PFC_PUD6, 0x00000055U);
+
+	/* initialize LSI pin pull-enable register */
+	pfc_reg_write(PFC_PUEN0, 0x00000FFFU);
+	pfc_reg_write(PFC_PUEN1, 0x00100234U);
+	pfc_reg_write(PFC_PUEN2, 0x000004C4U);
+	pfc_reg_write(PFC_PUEN3, 0x00000200U);
+	pfc_reg_write(PFC_PUEN4, 0x3E000000U);
+	pfc_reg_write(PFC_PUEN5, 0x1F000805U);
+	pfc_reg_write(PFC_PUEN6, 0x00000006U);
+
+	/* initialize positive/negative logic select */
+	mmio_write_32(GPIO_POSNEG0, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG1, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG2, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG3, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG4, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG5, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG6, 0x00000000U);
+
+	/* initialize general IO/interrupt switching */
+	mmio_write_32(GPIO_IOINTSEL0, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL1, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL2, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL3, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL4, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL5, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL6, 0x00000000U);
+
+	/* initialize general output register */
+	mmio_write_32(GPIO_OUTDT1, 0x00000000U);
+	mmio_write_32(GPIO_OUTDT2, 0x00000400U);
+	mmio_write_32(GPIO_OUTDT3, 0x0000C000U);
+	mmio_write_32(GPIO_OUTDT5, 0x00000006U);
+	mmio_write_32(GPIO_OUTDT6, 0x00003880U);
+
+	/* initialize general input/output switching */
+	mmio_write_32(GPIO_INOUTSEL0, 0x00000000U);
+	mmio_write_32(GPIO_INOUTSEL1, 0x01000A00U);
+	mmio_write_32(GPIO_INOUTSEL2, 0x00000400U);
+	mmio_write_32(GPIO_INOUTSEL3, 0x0000C000U);
+	mmio_write_32(GPIO_INOUTSEL4, 0x00000000U);
+#if (RCAR_GEN3_ULCB == 1)
+	mmio_write_32(GPIO_INOUTSEL5, 0x0000000EU);
+#else
+	mmio_write_32(GPIO_INOUTSEL5, 0x0000020EU);
+#endif
+	mmio_write_32(GPIO_INOUTSEL6, 0x00013880U);
+}
diff --git a/drivers/staging/renesas/rcar/pfc/M3N/pfc_init_m3n.h b/drivers/renesas/rcar/pfc/M3N/pfc_init_m3n.h
similarity index 100%
rename from drivers/staging/renesas/rcar/pfc/M3N/pfc_init_m3n.h
rename to drivers/renesas/rcar/pfc/M3N/pfc_init_m3n.h
diff --git a/drivers/renesas/rcar/pfc/V3M/pfc_init_v3m.c b/drivers/renesas/rcar/pfc/V3M/pfc_init_v3m.c
new file mode 100644
index 0000000..51d6f42
--- /dev/null
+++ b/drivers/renesas/rcar/pfc/V3M/pfc_init_v3m.c
@@ -0,0 +1,906 @@
+/*
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>		/* for uint32_t */
+#include <lib/mmio.h>
+#include "pfc_init_v3m.h"
+#include "include/rcar_def.h"
+#include "rcar_private.h"
+#include "../pfc_regs.h"
+
+/* Pin functon bit */
+#define GPSR0_DU_EXODDF_DU_ODDF_DISP_CDE	BIT(21)
+#define GPSR0_DU_EXVSYNC_DU_VSYNC		BIT(20)
+#define GPSR0_DU_EXHSYNC_DU_HSYNC		BIT(19)
+#define GPSR0_DU_DOTCLKOUT			BIT(18)
+#define GPSR0_DU_DB7				BIT(17)
+#define GPSR0_DU_DB6				BIT(16)
+#define GPSR0_DU_DB5				BIT(15)
+#define GPSR0_DU_DB4				BIT(14)
+#define GPSR0_DU_DB3				BIT(13)
+#define GPSR0_DU_DB2				BIT(12)
+#define GPSR0_DU_DG7				BIT(11)
+#define GPSR0_DU_DG6				BIT(10)
+#define GPSR0_DU_DG5				BIT(9)
+#define GPSR0_DU_DG4				BIT(8)
+#define GPSR0_DU_DG3				BIT(7)
+#define GPSR0_DU_DG2				BIT(6)
+#define GPSR0_DU_DR7				BIT(5)
+#define GPSR0_DU_DR6				BIT(4)
+#define GPSR0_DU_DR5				BIT(3)
+#define GPSR0_DU_DR4				BIT(2)
+#define GPSR0_DU_DR3				BIT(1)
+#define GPSR0_DU_DR2				BIT(0)
+
+#define GPSR1_DIGRF_CLKOUT			BIT(27)
+#define GPSR1_DIGRF_CLKIN			BIT(26)
+#define GPSR1_CANFD_CLK				BIT(25)
+#define GPSR1_CANFD1_RX				BIT(24)
+#define GPSR1_CANFD1_TX				BIT(23)
+#define GPSR1_CANFD0_RX				BIT(22)
+#define GPSR1_CANFD0_TX				BIT(21)
+#define GPSR1_AVB0_AVTP_CAPTURE			BIT(20)
+#define GPSR1_AVB0_AVTP_MATCH			BIT(19)
+#define GPSR1_AVB0_LINK				BIT(18)
+#define GPSR1_AVB0_PHY_INT			BIT(17)
+#define GPSR1_AVB0_MAGIC			BIT(16)
+#define GPSR1_AVB0_MDC				BIT(15)
+#define GPSR1_AVB0_MDIO				BIT(14)
+#define GPSR1_AVB0_TXCREFCLK			BIT(13)
+#define GPSR1_AVB0_TD3				BIT(12)
+#define GPSR1_AVB0_TD2				BIT(11)
+#define GPSR1_AVB0_TD1				BIT(10)
+#define GPSR1_AVB0_TD0				BIT(9)
+#define GPSR1_AVB0_TXC				BIT(8)
+#define GPSR1_AVB0_TX_CTL			BIT(7)
+#define GPSR1_AVB0_RD3				BIT(6)
+#define GPSR1_AVB0_RD2				BIT(5)
+#define GPSR1_AVB0_RD1				BIT(4)
+#define GPSR1_AVB0_RD0				BIT(3)
+#define GPSR1_AVB0_RXC				BIT(2)
+#define GPSR1_AVB0_RX_CTL			BIT(1)
+#define GPSR1_IRQ0				BIT(0)
+
+#define GPSR2_VI0_FIELD				BIT(16)
+#define GPSR2_VI0_DATA11			BIT(15)
+#define GPSR2_VI0_DATA10			BIT(14)
+#define GPSR2_VI0_DATA9				BIT(13)
+#define GPSR2_VI0_DATA8				BIT(12)
+#define GPSR2_VI0_DATA7				BIT(11)
+#define GPSR2_VI0_DATA6				BIT(10)
+#define GPSR2_VI0_DATA5				BIT(9)
+#define GPSR2_VI0_DATA4				BIT(8)
+#define GPSR2_VI0_DATA3				BIT(7)
+#define GPSR2_VI0_DATA2				BIT(6)
+#define GPSR2_VI0_DATA1				BIT(5)
+#define GPSR2_VI0_DATA0				BIT(4)
+#define GPSR2_VI0_VSYNC_N			BIT(3)
+#define GPSR2_VI0_HSYNC_N			BIT(2)
+#define GPSR2_VI0_CLKENB			BIT(1)
+#define GPSR2_VI0_CLK				BIT(0)
+
+#define GPSR3_VI1_FIELD				BIT(16)
+#define GPSR3_VI1_DATA11			BIT(15)
+#define GPSR3_VI1_DATA10			BIT(14)
+#define GPSR3_VI1_DATA9				BIT(13)
+#define GPSR3_VI1_DATA8				BIT(12)
+#define GPSR3_VI1_DATA7				BIT(11)
+#define GPSR3_VI1_DATA6				BIT(10)
+#define GPSR3_VI1_DATA5				BIT(9)
+#define GPSR3_VI1_DATA4				BIT(8)
+#define GPSR3_VI1_DATA3				BIT(7)
+#define GPSR3_VI1_DATA2				BIT(6)
+#define GPSR3_VI1_DATA1				BIT(5)
+#define GPSR3_VI1_DATA0				BIT(4)
+#define GPSR3_VI1_VSYNC_N			BIT(3)
+#define GPSR3_VI1_HSYNC_N			BIT(2)
+#define GPSR3_VI1_CLKENB			BIT(1)
+#define GPSR3_VI1_CLK				BIT(0)
+
+#define GPSR4_SDA2				BIT(5)
+#define GPSR4_SCL2				BIT(4)
+#define GPSR4_SDA1				BIT(3)
+#define GPSR4_SCL1				BIT(2)
+#define GPSR4_SDA0				BIT(1)
+#define GPSR4_SCL0				BIT(0)
+
+#define GPSR5_RPC_INT_N				BIT(14)
+#define GPSR5_RPC_WP_N				BIT(13)
+#define GPSR5_RPC_RESET_N			BIT(12)
+#define GPSR5_QSPI1_SSL				BIT(11)
+#define GPSR5_QSPI1_IO3				BIT(10)
+#define GPSR5_QSPI1_IO2				BIT(9)
+#define GPSR5_QSPI1_MISO_IO1			BIT(8)
+#define GPSR5_QSPI1_MOSI_IO0			BIT(7)
+#define GPSR5_QSPI1_SPCLK			BIT(6)
+#define GPSR5_QSPI0_SSL				BIT(5)
+#define GPSR5_QSPI0_IO3				BIT(4)
+#define GPSR5_QSPI0_IO2				BIT(3)
+#define GPSR5_QSPI0_MISO_IO1			BIT(2)
+#define GPSR5_QSPI0_MOSI_IO0			BIT(1)
+#define GPSR5_QSPI0_SPCLK			BIT(0)
+
+#define IPSR_28_FUNC(x)				((uint32_t)(x) << 28U)
+#define IPSR_24_FUNC(x)				((uint32_t)(x) << 24U)
+#define IPSR_20_FUNC(x)				((uint32_t)(x) << 20U)
+#define IPSR_16_FUNC(x)				((uint32_t)(x) << 16U)
+#define IPSR_12_FUNC(x)				((uint32_t)(x) << 12U)
+#define IPSR_8_FUNC(x)				((uint32_t)(x) << 8U)
+#define IPSR_4_FUNC(x)				((uint32_t)(x) << 4U)
+#define IPSR_0_FUNC(x)				((uint32_t)(x) << 0U)
+
+#define IOCTRL30_POC_VI0_DATA5			BIT(31)
+#define IOCTRL30_POC_VI0_DATA4			BIT(30)
+#define IOCTRL30_POC_VI0_DATA3			BIT(29)
+#define IOCTRL30_POC_VI0_DATA2			BIT(28)
+#define IOCTRL30_POC_VI0_DATA1			BIT(27)
+#define IOCTRL30_POC_VI0_DATA0			BIT(26)
+#define IOCTRL30_POC_VI0_VSYNC_N		BIT(25)
+#define IOCTRL30_POC_VI0_HSYNC_N		BIT(24)
+#define IOCTRL30_POC_VI0_CLKENB			BIT(23)
+#define IOCTRL30_POC_VI0_CLK			BIT(22)
+#define IOCTRL30_POC_DU_EXODDF_DU_ODDF_DISP_CDE	BIT(21)
+#define IOCTRL30_POC_DU_EXVSYNC_DU_VSYNC	BIT(20)
+#define IOCTRL30_POC_DU_EXHSYNC_DU_HSYNC	BIT(19)
+#define IOCTRL30_POC_DU_DOTCLKOUT		BIT(18)
+#define IOCTRL30_POC_DU_DB7			BIT(17)
+#define IOCTRL30_POC_DU_DB6			BIT(16)
+#define IOCTRL30_POC_DU_DB5			BIT(15)
+#define IOCTRL30_POC_DU_DB4			BIT(14)
+#define IOCTRL30_POC_DU_DB3			BIT(13)
+#define IOCTRL30_POC_DU_DB2			BIT(12)
+#define IOCTRL30_POC_DU_DG7			BIT(11)
+#define IOCTRL30_POC_DU_DG6			BIT(10)
+#define IOCTRL30_POC_DU_DG5			BIT(9)
+#define IOCTRL30_POC_DU_DG4			BIT(8)
+#define IOCTRL30_POC_DU_DG3			BIT(7)
+#define IOCTRL30_POC_DU_DG2			BIT(6)
+#define IOCTRL30_POC_DU_DR7			BIT(5)
+#define IOCTRL30_POC_DU_DR6			BIT(4)
+#define IOCTRL30_POC_DU_DR5			BIT(3)
+#define IOCTRL30_POC_DU_DR4			BIT(2)
+#define IOCTRL30_POC_DU_DR3			BIT(1)
+#define IOCTRL30_POC_DU_DR2			BIT(0)
+
+#define IOCTRL31_POC_DUMMY_31			BIT(31)
+#define IOCTRL31_POC_DUMMY_30			BIT(30)
+#define IOCTRL31_POC_DUMMY_29			BIT(29)
+#define IOCTRL31_POC_DUMMY_28			BIT(28)
+#define IOCTRL31_POC_DUMMY_27			BIT(27)
+#define IOCTRL31_POC_DUMMY_26			BIT(26)
+#define IOCTRL31_POC_DUMMY_25			BIT(25)
+#define IOCTRL31_POC_DUMMY_24			BIT(24)
+#define IOCTRL31_POC_VI1_FIELD			BIT(23)
+#define IOCTRL31_POC_VI1_DATA11			BIT(22)
+#define IOCTRL31_POC_VI1_DATA10			BIT(21)
+#define IOCTRL31_POC_VI1_DATA9			BIT(20)
+#define IOCTRL31_POC_VI1_DATA8			BIT(19)
+#define IOCTRL31_POC_VI1_DATA7			BIT(18)
+#define IOCTRL31_POC_VI1_DATA6			BIT(17)
+#define IOCTRL31_POC_VI1_DATA5			BIT(16)
+#define IOCTRL31_POC_VI1_DATA4			BIT(15)
+#define IOCTRL31_POC_VI1_DATA3			BIT(14)
+#define IOCTRL31_POC_VI1_DATA2			BIT(13)
+#define IOCTRL31_POC_VI1_DATA1			BIT(12)
+#define IOCTRL31_POC_VI1_DATA0			BIT(11)
+#define IOCTRL31_POC_VI1_VSYNC_N		BIT(10)
+#define IOCTRL31_POC_VI1_HSYNC_N		BIT(9)
+#define IOCTRL31_POC_VI1_CLKENB			BIT(8)
+#define IOCTRL31_POC_VI1_CLK			BIT(7)
+#define IOCTRL31_POC_VI0_FIELD			BIT(6)
+#define IOCTRL31_POC_VI0_DATA11			BIT(5)
+#define IOCTRL31_POC_VI0_DATA10			BIT(4)
+#define IOCTRL31_POC_VI0_DATA9			BIT(3)
+#define IOCTRL31_POC_VI0_DATA8			BIT(2)
+#define IOCTRL31_POC_VI0_DATA7			BIT(1)
+#define IOCTRL31_POC_VI0_DATA6			BIT(0)
+#define IOCTRL32_POC2_VREF			BIT(0)
+#define IOCTRL40_SD0TDSEL1			BIT(1)
+#define IOCTRL40_SD0TDSEL0			BIT(0)
+
+#define PUEN0_PUEN_VI0_CLK			BIT(31)
+#define PUEN0_PUEN_TDI				BIT(30)
+#define PUEN0_PUEN_TMS				BIT(29)
+#define PUEN0_PUEN_TCK				BIT(28)
+#define PUEN0_PUEN_TRST_N			BIT(27)
+#define PUEN0_PUEN_IRQ0				BIT(26)
+#define PUEN0_PUEN_FSCLKST_N			BIT(25)
+#define PUEN0_PUEN_EXTALR			BIT(24)
+#define PUEN0_PUEN_PRESETOUT_N			BIT(23)
+#define PUEN0_PUEN_DU_DOTCLKIN			BIT(22)
+#define PUEN0_PUEN_DU_EXODDF_DU_ODDF_DISP_CDE	BIT(21)
+#define PUEN0_PUEN_DU_EXVSYNC_DU_VSYNC		BIT(20)
+#define PUEN0_PUEN_DU_EXHSYNC_DU_HSYNC		BIT(19)
+#define PUEN0_PUEN_DU_DOTCLKOUT			BIT(18)
+#define PUEN0_PUEN_DU_DB7			BIT(17)
+#define PUEN0_PUEN_DU_DB6			BIT(16)
+#define PUEN0_PUEN_DU_DB5			BIT(15)
+#define PUEN0_PUEN_DU_DB4			BIT(14)
+#define PUEN0_PUEN_DU_DB3			BIT(13)
+#define PUEN0_PUEN_DU_DB2			BIT(12)
+#define PUEN0_PUEN_DU_DG7			BIT(11)
+#define PUEN0_PUEN_DU_DG6			BIT(10)
+#define PUEN0_PUEN_DU_DG5			BIT(9)
+#define PUEN0_PUEN_DU_DG4			BIT(8)
+#define PUEN0_PUEN_DU_DG3			BIT(7)
+#define PUEN0_PUEN_DU_DG2			BIT(6)
+#define PUEN0_PUEN_DU_DR7			BIT(5)
+#define PUEN0_PUEN_DU_DR6			BIT(4)
+#define PUEN0_PUEN_DU_DR5			BIT(3)
+#define PUEN0_PUEN_DU_DR4			BIT(2)
+#define PUEN0_PUEN_DU_DR3			BIT(1)
+#define PUEN0_PUEN_DU_DR2			BIT(0)
+
+#define PUEN1_PUEN_VI1_DATA11			BIT(31)
+#define PUEN1_PUEN_VI1_DATA10			BIT(30)
+#define PUEN1_PUEN_VI1_DATA9			BIT(29)
+#define PUEN1_PUEN_VI1_DATA8			BIT(28)
+#define PUEN1_PUEN_VI1_DATA7			BIT(27)
+#define PUEN1_PUEN_VI1_DATA6			BIT(26)
+#define PUEN1_PUEN_VI1_DATA5			BIT(25)
+#define PUEN1_PUEN_VI1_DATA4			BIT(24)
+#define PUEN1_PUEN_VI1_DATA3			BIT(23)
+#define PUEN1_PUEN_VI1_DATA2			BIT(22)
+#define PUEN1_PUEN_VI1_DATA1			BIT(21)
+#define PUEN1_PUEN_VI1_DATA0			BIT(20)
+#define PUEN1_PUEN_VI1_VSYNC_N			BIT(19)
+#define PUEN1_PUEN_VI1_HSYNC_N			BIT(18)
+#define PUEN1_PUEN_VI1_CLKENB			BIT(17)
+#define PUEN1_PUEN_VI1_CLK			BIT(16)
+#define PUEN1_PUEN_VI0_FIELD			BIT(15)
+#define PUEN1_PUEN_VI0_DATA11			BIT(14)
+#define PUEN1_PUEN_VI0_DATA10			BIT(13)
+#define PUEN1_PUEN_VI0_DATA9			BIT(12)
+#define PUEN1_PUEN_VI0_DATA8			BIT(11)
+#define PUEN1_PUEN_VI0_DATA7			BIT(10)
+#define PUEN1_PUEN_VI0_DATA6			BIT(9)
+#define PUEN1_PUEN_VI0_DATA5			BIT(8)
+#define PUEN1_PUEN_VI0_DATA4			BIT(7)
+#define PUEN1_PUEN_VI0_DATA3			BIT(6)
+#define PUEN1_PUEN_VI0_DATA2			BIT(5)
+#define PUEN1_PUEN_VI0_DATA1			BIT(4)
+#define PUEN1_PUEN_VI0_DATA0			BIT(3)
+#define PUEN1_PUEN_VI0_VSYNC_N			BIT(2)
+#define PUEN1_PUEN_VI0_HSYNC_N			BIT(1)
+#define PUEN1_PUEN_VI0_CLKENB			BIT(0)
+
+#define PUEN2_PUEN_CANFD_CLK			BIT(31)
+#define PUEN2_PUEN_CANFD1_RX			BIT(30)
+#define PUEN2_PUEN_CANFD1_TX			BIT(29)
+#define PUEN2_PUEN_CANFD0_RX			BIT(28)
+#define PUEN2_PUEN_CANFD0_TX			BIT(27)
+#define PUEN2_PUEN_AVB0_AVTP_CAPTURE		BIT(26)
+#define PUEN2_PUEN_AVB0_AVTP_MATCH		BIT(25)
+#define PUEN2_PUEN_AVB0_LINK			BIT(24)
+#define PUEN2_PUEN_AVB0_PHY_INT			BIT(23)
+#define PUEN2_PUEN_AVB0_MAGIC			BIT(22)
+#define PUEN2_PUEN_AVB0_MDC			BIT(21)
+#define PUEN2_PUEN_AVB0_MDIO			BIT(20)
+#define PUEN2_PUEN_AVB0_TXCREFCLK		BIT(19)
+#define PUEN2_PUEN_AVB0_TD3			BIT(18)
+#define PUEN2_PUEN_AVB0_TD2			BIT(17)
+#define PUEN2_PUEN_AVB0_TD1			BIT(16)
+#define PUEN2_PUEN_AVB0_TD0			BIT(15)
+#define PUEN2_PUEN_AVB0_TXC			BIT(14)
+#define PUEN2_PUEN_AVB0_TX_CTL			BIT(13)
+#define PUEN2_PUEN_AVB0_RD3			BIT(12)
+#define PUEN2_PUEN_AVB0_RD2			BIT(11)
+#define PUEN2_PUEN_AVB0_RD1			BIT(10)
+#define PUEN2_PUEN_AVB0_RD0			BIT(9)
+#define PUEN2_PUEN_AVB0_RXC			BIT(8)
+#define PUEN2_PUEN_AVB0_RX_CTL			BIT(7)
+#define PUEN2_PUEN_SDA2				BIT(6)
+#define PUEN2_PUEN_SCL2				BIT(5)
+#define PUEN2_PUEN_SDA1				BIT(4)
+#define PUEN2_PUEN_SCL1				BIT(3)
+#define PUEN2_PUEN_SDA0				BIT(2)
+#define PUEN2_PUEN_SCL0				BIT(1)
+#define PUEN2_PUEN_VI1_FIELD			BIT(0)
+
+#define PUEN3_PUEN_DIGRF_CLKOUT			BIT(16)
+#define PUEN3_PUEN_DIGRF_CLKIN			BIT(15)
+#define PUEN3_PUEN_RPC_INT_N			BIT(14)
+#define PUEN3_PUEN_RPC_WP_N			BIT(13)
+#define PUEN3_PUEN_RPC_RESET_N			BIT(12)
+#define PUEN3_PUEN_QSPI1_SSL			BIT(11)
+#define PUEN3_PUEN_QSPI1_IO3			BIT(10)
+#define PUEN3_PUEN_QSPI1_IO2			BIT(9)
+#define PUEN3_PUEN_QSPI1_MISO_IO1		BIT(8)
+#define PUEN3_PUEN_QSPI1_MOSI_IO0		BIT(7)
+#define PUEN3_PUEN_QSPI1_SPCLK			BIT(6)
+#define PUEN3_PUEN_QSPI0_SSL			BIT(5)
+#define PUEN3_PUEN_QSPI0_IO3			BIT(4)
+#define PUEN3_PUEN_QSPI0_IO2			BIT(3)
+#define PUEN3_PUEN_QSPI0_MISO_IO1		BIT(2)
+#define PUEN3_PUEN_QSPI0_MOSI_IO0		BIT(1)
+#define PUEN3_PUEN_QSPI0_SPCLK			BIT(0)
+
+#define PUD0_PUD_VI0_CLK			BIT(31)
+#define PUD0_PUD_IRQ0				BIT(26)
+#define PUD0_PUD_FSCLKST_N			BIT(25)
+#define PUD0_PUD_PRESETOUT_N			BIT(23)
+#define PUD0_PUD_DU_EXODDF_DU_ODDF_DISP_CDE	BIT(21)
+#define PUD0_PUD_DU_EXVSYNC_DU_VSYNC		BIT(20)
+#define PUD0_PUD_DU_EXHSYNC_DU_HSYNC		BIT(19)
+#define PUD0_PUD_DU_DOTCLKOUT			BIT(18)
+#define PUD0_PUD_DU_DB7				BIT(17)
+#define PUD0_PUD_DU_DB6				BIT(16)
+#define PUD0_PUD_DU_DB5				BIT(15)
+#define PUD0_PUD_DU_DB4				BIT(14)
+#define PUD0_PUD_DU_DB3				BIT(13)
+#define PUD0_PUD_DU_DB2				BIT(12)
+#define PUD0_PUD_DU_DG7				BIT(11)
+#define PUD0_PUD_DU_DG6				BIT(10)
+#define PUD0_PUD_DU_DG5				BIT(9)
+#define PUD0_PUD_DU_DG4				BIT(8)
+#define PUD0_PUD_DU_DG3				BIT(7)
+#define PUD0_PUD_DU_DG2				BIT(6)
+#define PUD0_PUD_DU_DR7				BIT(5)
+#define PUD0_PUD_DU_DR6				BIT(4)
+#define PUD0_PUD_DU_DR5				BIT(3)
+#define PUD0_PUD_DU_DR4				BIT(2)
+#define PUD0_PUD_DU_DR3				BIT(1)
+#define PUD0_PUD_DU_DR2				BIT(0)
+
+#define PUD1_PUD_VI1_DATA11			BIT(31)
+#define PUD1_PUD_VI1_DATA10			BIT(30)
+#define PUD1_PUD_VI1_DATA9			BIT(29)
+#define PUD1_PUD_VI1_DATA8			BIT(28)
+#define PUD1_PUD_VI1_DATA7			BIT(27)
+#define PUD1_PUD_VI1_DATA6			BIT(26)
+#define PUD1_PUD_VI1_DATA5			BIT(25)
+#define PUD1_PUD_VI1_DATA4			BIT(24)
+#define PUD1_PUD_VI1_DATA3			BIT(23)
+#define PUD1_PUD_VI1_DATA2			BIT(22)
+#define PUD1_PUD_VI1_DATA1			BIT(21)
+#define PUD1_PUD_VI1_DATA0			BIT(20)
+#define PUD1_PUD_VI1_VSYNC_N			BIT(19)
+#define PUD1_PUD_VI1_HSYNC_N			BIT(18)
+#define PUD1_PUD_VI1_CLKENB			BIT(17)
+#define PUD1_PUD_VI1_CLK			BIT(16)
+#define PUD1_PUD_VI0_FIELD			BIT(15)
+#define PUD1_PUD_VI0_DATA11			BIT(14)
+#define PUD1_PUD_VI0_DATA10			BIT(13)
+#define PUD1_PUD_VI0_DATA9			BIT(12)
+#define PUD1_PUD_VI0_DATA8			BIT(11)
+#define PUD1_PUD_VI0_DATA7			BIT(10)
+#define PUD1_PUD_VI0_DATA6			BIT(9)
+#define PUD1_PUD_VI0_DATA5			BIT(8)
+#define PUD1_PUD_VI0_DATA4			BIT(7)
+#define PUD1_PUD_VI0_DATA3			BIT(6)
+#define PUD1_PUD_VI0_DATA2			BIT(5)
+#define PUD1_PUD_VI0_DATA1			BIT(4)
+#define PUD1_PUD_VI0_DATA0			BIT(3)
+#define PUD1_PUD_VI0_VSYNC_N			BIT(2)
+#define PUD1_PUD_VI0_HSYNC_N			BIT(1)
+#define PUD1_PUD_VI0_CLKENB			BIT(0)
+
+#define PUD2_PUD_CANFD_CLK			BIT(31)
+#define PUD2_PUD_CANFD1_RX			BIT(30)
+#define PUD2_PUD_CANFD1_TX			BIT(29)
+#define PUD2_PUD_CANFD0_RX			BIT(28)
+#define PUD2_PUD_CANFD0_TX			BIT(27)
+#define PUD2_PUD_AVB0_AVTP_CAPTURE		BIT(26)
+#define PUD2_PUD_AVB0_AVTP_MATCH		BIT(25)
+#define PUD2_PUD_AVB0_LINK			BIT(24)
+#define PUD2_PUD_AVB0_PHY_INT			BIT(23)
+#define PUD2_PUD_AVB0_MAGIC			BIT(22)
+#define PUD2_PUD_AVB0_MDC			BIT(21)
+#define PUD2_PUD_AVB0_MDIO			BIT(20)
+#define PUD2_PUD_AVB0_TXCREFCLK			BIT(19)
+#define PUD2_PUD_AVB0_TD3			BIT(18)
+#define PUD2_PUD_AVB0_TD2			BIT(17)
+#define PUD2_PUD_AVB0_TD1			BIT(16)
+#define PUD2_PUD_AVB0_TD0			BIT(15)
+#define PUD2_PUD_AVB0_TXC			BIT(14)
+#define PUD2_PUD_AVB0_TX_CTL			BIT(13)
+#define PUD2_PUD_AVB0_RD3			BIT(12)
+#define PUD2_PUD_AVB0_RD2			BIT(11)
+#define PUD2_PUD_AVB0_RD1			BIT(10)
+#define PUD2_PUD_AVB0_RD0			BIT(9)
+#define PUD2_PUD_AVB0_RXC			BIT(8)
+#define PUD2_PUD_AVB0_RX_CTL			BIT(7)
+#define PUD2_PUD_SDA2				BIT(6)
+#define PUD2_PUD_SCL2				BIT(5)
+#define PUD2_PUD_SDA1				BIT(4)
+#define PUD2_PUD_SCL1				BIT(3)
+#define PUD2_PUD_SDA0				BIT(2)
+#define PUD2_PUD_SCL0				BIT(1)
+#define PUD2_PUD_VI1_FIELD			BIT(0)
+
+#define PUD3_PUD_DIGRF_CLKOUT			BIT(16)
+#define PUD3_PUD_DIGRF_CLKIN			BIT(15)
+#define PUD3_PUD_RPC_INT_N			BIT(14)
+#define PUD3_PUD_RPC_WP_N			BIT(13)
+#define PUD3_PUD_RPC_RESET_N			BIT(12)
+#define PUD3_PUD_QSPI1_SSL			BIT(11)
+#define PUD3_PUD_QSPI1_IO3			BIT(10)
+#define PUD3_PUD_QSPI1_IO2			BIT(9)
+#define PUD3_PUD_QSPI1_MISO_IO1			BIT(8)
+#define PUD3_PUD_QSPI1_MOSI_IO0			BIT(7)
+#define PUD3_PUD_QSPI1_SPCLK			BIT(6)
+#define PUD3_PUD_QSPI0_SSL			BIT(5)
+#define PUD3_PUD_QSPI0_IO3			BIT(4)
+#define PUD3_PUD_QSPI0_IO2			BIT(3)
+#define PUD3_PUD_QSPI0_MISO_IO1			BIT(2)
+#define PUD3_PUD_QSPI0_MOSI_IO0			BIT(1)
+#define PUD3_PUD_QSPI0_SPCLK			BIT(0)
+
+#define MOD_SEL0_sel_hscif0			BIT(10)
+#define MOD_SEL0_sel_scif1			BIT(9)
+#define MOD_SEL0_sel_canfd0			BIT(8)
+#define MOD_SEL0_sel_pwm4			BIT(7)
+#define MOD_SEL0_sel_pwm3			BIT(6)
+#define MOD_SEL0_sel_pwm2			BIT(5)
+#define MOD_SEL0_sel_pwm1			BIT(4)
+#define MOD_SEL0_sel_pwm0			BIT(3)
+#define MOD_SEL0_sel_rfso			BIT(2)
+#define MOD_SEL0_sel_rsp			BIT(1)
+#define MOD_SEL0_sel_tmu			BIT(0)
+
+/* SCIF3 Registers for Dummy write */
+#define SCIF3_BASE		(0xE6C50000U)
+#define SCIF3_SCFCR		(SCIF3_BASE + 0x0018U)
+#define SCIF3_SCFDR		(SCIF3_BASE + 0x001CU)
+#define SCFCR_DATA		(0x0000U)
+
+/* Realtime module stop control */
+#define CPG_BASE		(0xE6150000U)
+#define CPG_MSTPSR0		(CPG_BASE + 0x0030U)
+#define CPG_RMSTPCR0		(CPG_BASE + 0x0110U)
+#define RMSTPCR0_RTDMAC		(0x00200000U)
+
+/* RT-DMAC Registers */
+#define RTDMAC_CH		(0U)		/* choose 0 to 15 */
+
+#define RTDMAC_BASE		(0xFFC10000U)
+#define RTDMAC_RDMOR		(RTDMAC_BASE + 0x0060U)
+#define RTDMAC_RDMCHCLR		(RTDMAC_BASE + 0x0080U)
+#define RTDMAC_RDMSAR(x)	(RTDMAC_BASE + 0x8000U + (0x80U * (x)))
+#define RTDMAC_RDMDAR(x)	(RTDMAC_BASE + 0x8004U + (0x80U * (x)))
+#define RTDMAC_RDMTCR(x)	(RTDMAC_BASE + 0x8008U + (0x80U * (x)))
+#define RTDMAC_RDMCHCR(x)	(RTDMAC_BASE + 0x800CU + (0x80U * (x)))
+#define RTDMAC_RDMCHCRB(x)	(RTDMAC_BASE + 0x801CU + (0x80U * (x)))
+#define RTDMAC_RDMDPBASE(x)	(RTDMAC_BASE + 0x8050U + (0x80U * (x)))
+#define RTDMAC_DESC_BASE	(RTDMAC_BASE + 0xA000U)
+#define RTDMAC_DESC_RDMSAR	(RTDMAC_DESC_BASE + 0x0000U)
+#define RTDMAC_DESC_RDMDAR	(RTDMAC_DESC_BASE + 0x0004U)
+#define RTDMAC_DESC_RDMTCR	(RTDMAC_DESC_BASE + 0x0008U)
+
+#define RDMOR_DME		(0x0001U)	/* DMA Master Enable */
+#define RDMCHCR_DPM_INFINITE	(0x30000000U)	/* Infinite repeat mode */
+#define RDMCHCR_RPT_TCR		(0x02000000U)	/* enable to update TCR */
+#define RDMCHCR_TS_2		(0x00000008U)	/* Word(2byte) units transfer */
+#define RDMCHCR_RS_AUTO		(0x00000400U)	/* Auto request */
+#define RDMCHCR_DE		(0x00000001U)	/* DMA Enable */
+#define RDMCHCRB_DRST		(0x00008000U)	/* Descriptor reset */
+#define RDMCHCRB_SLM_256	(0x00000080U)	/* once in 256 clock cycle */
+#define RDMDPBASE_SEL_EXT	(0x00000001U)	/* External memory use */
+
+static void pfc_reg_write(uint32_t addr, uint32_t data)
+{
+	mmio_write_32(PFC_PMMR, ~data);
+	mmio_write_32((uintptr_t)addr, data);
+}
+
+static void start_rtdma0_descriptor(void)
+{
+	uint32_t reg;
+
+	/* Module stop clear */
+	while ((mmio_read_32(CPG_MSTPSR0) & RMSTPCR0_RTDMAC) != 0U) {
+		reg = mmio_read_32(CPG_RMSTPCR0);
+		reg &= ~RMSTPCR0_RTDMAC;
+		cpg_write(CPG_RMSTPCR0, reg);
+	}
+
+	/* Initialize ch0, Reset Descriptor */
+	mmio_write_32(RTDMAC_RDMCHCLR, BIT(RTDMAC_CH));
+	mmio_write_32(RTDMAC_RDMCHCRB(RTDMAC_CH), RDMCHCRB_DRST);
+
+	/* Enable DMA */
+	mmio_write_16(RTDMAC_RDMOR, RDMOR_DME);
+
+	/* Set first transfer */
+	mmio_write_32(RTDMAC_RDMSAR(RTDMAC_CH), RCAR_PRR);
+	mmio_write_32(RTDMAC_RDMDAR(RTDMAC_CH), SCIF3_SCFDR);
+	mmio_write_32(RTDMAC_RDMTCR(RTDMAC_CH), 0x00000001U);
+
+	/* Set descriptor */
+	mmio_write_32(RTDMAC_DESC_RDMSAR, 0x00000000U);
+	mmio_write_32(RTDMAC_DESC_RDMDAR, 0x00000000U);
+	mmio_write_32(RTDMAC_DESC_RDMTCR, 0x00200000U);
+	mmio_write_32(RTDMAC_RDMCHCRB(RTDMAC_CH), RDMCHCRB_SLM_256);
+	mmio_write_32(RTDMAC_RDMDPBASE(RTDMAC_CH), RTDMAC_DESC_BASE
+						 | RDMDPBASE_SEL_EXT);
+
+	/* Set transfer parameter, Start transfer */
+	mmio_write_32(RTDMAC_RDMCHCR(RTDMAC_CH), RDMCHCR_DPM_INFINITE
+					       | RDMCHCR_RPT_TCR
+					       | RDMCHCR_TS_2
+					       | RDMCHCR_RS_AUTO
+					       | RDMCHCR_DE);
+}
+
+void pfc_init_v3m(void)
+{
+	/* Work around for PFC eratta */
+	start_rtdma0_descriptor();
+
+	// pin function
+	// md[4:1]!=0000
+	/* initialize GPIO/perihperal function select */
+
+	pfc_reg_write(PFC_GPSR0, 0x00000000);
+
+	pfc_reg_write(PFC_GPSR1, GPSR1_CANFD_CLK);
+
+	pfc_reg_write(PFC_GPSR2, 0x00000000);
+
+	pfc_reg_write(PFC_GPSR3, 0x00000000);
+
+	pfc_reg_write(PFC_GPSR4, GPSR4_SDA2
+				   | GPSR4_SCL2);
+
+	pfc_reg_write(PFC_GPSR5, GPSR5_QSPI1_SSL
+				   | GPSR5_QSPI1_IO3
+				   | GPSR5_QSPI1_IO2
+				   | GPSR5_QSPI1_MISO_IO1
+				   | GPSR5_QSPI1_MOSI_IO0
+				   | GPSR5_QSPI1_SPCLK
+				   | GPSR5_QSPI0_SSL
+				   | GPSR5_QSPI0_IO3
+				   | GPSR5_QSPI0_IO2
+				   | GPSR5_QSPI0_MISO_IO1
+				   | GPSR5_QSPI0_MOSI_IO0
+				   | GPSR5_QSPI0_SPCLK);
+
+	/* initialize peripheral function select */
+	pfc_reg_write(PFC_IPSR0, IPSR_28_FUNC(0)
+				   | IPSR_24_FUNC(0)
+				   | IPSR_20_FUNC(0)
+				   | IPSR_16_FUNC(0)
+				   | IPSR_12_FUNC(0)
+				   | IPSR_8_FUNC(0)
+				   | IPSR_4_FUNC(0)
+				   | IPSR_0_FUNC(0));
+
+	pfc_reg_write(PFC_IPSR1, IPSR_28_FUNC(0)
+				   | IPSR_24_FUNC(0)
+				   | IPSR_20_FUNC(0)
+				   | IPSR_16_FUNC(0)
+				   | IPSR_12_FUNC(0)
+				   | IPSR_8_FUNC(0)
+				   | IPSR_4_FUNC(0)
+				   | IPSR_0_FUNC(0));
+
+	pfc_reg_write(PFC_IPSR2, IPSR_28_FUNC(0)
+				   | IPSR_24_FUNC(0)
+				   | IPSR_20_FUNC(0)
+				   | IPSR_16_FUNC(0)
+				   | IPSR_12_FUNC(0)
+				   | IPSR_8_FUNC(0)
+				   | IPSR_4_FUNC(0)
+				   | IPSR_0_FUNC(0));
+
+	pfc_reg_write(PFC_IPSR3, IPSR_28_FUNC(0)
+				   | IPSR_24_FUNC(0)
+				   | IPSR_20_FUNC(0)
+				   | IPSR_16_FUNC(0)
+				   | IPSR_12_FUNC(0)
+				   | IPSR_8_FUNC(0)
+				   | IPSR_4_FUNC(0)
+				   | IPSR_0_FUNC(0));
+
+	pfc_reg_write(PFC_IPSR4, IPSR_28_FUNC(0)
+				   | IPSR_24_FUNC(0)
+				   | IPSR_20_FUNC(0)
+				   | IPSR_16_FUNC(0)
+				   | IPSR_12_FUNC(0)
+				   | IPSR_8_FUNC(0)
+				   | IPSR_4_FUNC(0)
+				   | IPSR_0_FUNC(0));
+
+	pfc_reg_write(PFC_IPSR5, IPSR_28_FUNC(0)
+				   | IPSR_24_FUNC(0)
+				   | IPSR_20_FUNC(0)
+				   | IPSR_16_FUNC(0)
+				   | IPSR_12_FUNC(0)
+				   | IPSR_8_FUNC(0)
+				   | IPSR_4_FUNC(0)
+				   | IPSR_0_FUNC(0));
+
+	pfc_reg_write(PFC_IPSR6, IPSR_28_FUNC(0)
+				   | IPSR_24_FUNC(0)
+				   | IPSR_20_FUNC(0)
+				   | IPSR_16_FUNC(0)
+				   | IPSR_12_FUNC(0)
+				   | IPSR_8_FUNC(0)
+				   | IPSR_4_FUNC(0)
+				   | IPSR_0_FUNC(0));
+
+	pfc_reg_write(PFC_IPSR7, IPSR_28_FUNC(0)
+				   | IPSR_24_FUNC(4)
+				   | IPSR_20_FUNC(4)
+				   | IPSR_16_FUNC(4)
+				   | IPSR_12_FUNC(4)
+				   | IPSR_8_FUNC(0)
+				   | IPSR_4_FUNC(0)
+				   | IPSR_0_FUNC(0));
+
+	pfc_reg_write(PFC_IPSR8, IPSR_28_FUNC(0)
+				   | IPSR_24_FUNC(0)
+				   | IPSR_20_FUNC(0)
+				   | IPSR_16_FUNC(4)
+				   | IPSR_12_FUNC(0)
+				   | IPSR_8_FUNC(0)
+				   | IPSR_4_FUNC(0)
+				   | IPSR_0_FUNC(0));
+
+	/* initialize POC Control */
+
+	pfc_reg_write(PFC_POCCTRL0, IOCTRL30_POC_VI0_DATA5
+				   | IOCTRL30_POC_VI0_DATA4
+				   | IOCTRL30_POC_VI0_DATA3
+				   | IOCTRL30_POC_VI0_DATA2
+				   | IOCTRL30_POC_VI0_DATA1
+				   | IOCTRL30_POC_VI0_DATA0
+				   | IOCTRL30_POC_VI0_VSYNC_N
+				   | IOCTRL30_POC_VI0_HSYNC_N
+				   | IOCTRL30_POC_VI0_CLKENB
+				   | IOCTRL30_POC_VI0_CLK
+				   | IOCTRL30_POC_DU_EXODDF_DU_ODDF_DISP_CDE
+				   | IOCTRL30_POC_DU_EXVSYNC_DU_VSYNC
+				   | IOCTRL30_POC_DU_EXHSYNC_DU_HSYNC
+				   | IOCTRL30_POC_DU_DOTCLKOUT
+				   | IOCTRL30_POC_DU_DB7
+				   | IOCTRL30_POC_DU_DB6
+				   | IOCTRL30_POC_DU_DB5
+				   | IOCTRL30_POC_DU_DB4
+				   | IOCTRL30_POC_DU_DB3
+				   | IOCTRL30_POC_DU_DB2
+				   | IOCTRL30_POC_DU_DG7
+				   | IOCTRL30_POC_DU_DG6
+				   | IOCTRL30_POC_DU_DG5
+				   | IOCTRL30_POC_DU_DG4
+				   | IOCTRL30_POC_DU_DG3
+				   | IOCTRL30_POC_DU_DG2
+				   | IOCTRL30_POC_DU_DR7
+				   | IOCTRL30_POC_DU_DR6
+				   | IOCTRL30_POC_DU_DR5
+				   | IOCTRL30_POC_DU_DR4
+				   | IOCTRL30_POC_DU_DR3
+				   | IOCTRL30_POC_DU_DR2);
+
+	pfc_reg_write(PFC_IOCTRL31, IOCTRL31_POC_DUMMY_31
+				   | IOCTRL31_POC_DUMMY_30
+				   | IOCTRL31_POC_DUMMY_29
+				   | IOCTRL31_POC_DUMMY_28
+				   | IOCTRL31_POC_DUMMY_27
+				   | IOCTRL31_POC_DUMMY_26
+				   | IOCTRL31_POC_DUMMY_25
+				   | IOCTRL31_POC_DUMMY_24
+				   | IOCTRL31_POC_VI1_FIELD
+				   | IOCTRL31_POC_VI1_DATA11
+				   | IOCTRL31_POC_VI1_DATA10
+				   | IOCTRL31_POC_VI1_DATA9
+				   | IOCTRL31_POC_VI1_DATA8
+				   | IOCTRL31_POC_VI1_DATA7
+				   | IOCTRL31_POC_VI1_DATA6
+				   | IOCTRL31_POC_VI1_DATA5
+				   | IOCTRL31_POC_VI1_DATA4
+				   | IOCTRL31_POC_VI1_DATA3
+				   | IOCTRL31_POC_VI1_DATA2
+				   | IOCTRL31_POC_VI1_DATA1
+				   | IOCTRL31_POC_VI1_DATA0
+				   | IOCTRL31_POC_VI1_VSYNC_N
+				   | IOCTRL31_POC_VI1_HSYNC_N
+				   | IOCTRL31_POC_VI1_CLKENB
+				   | IOCTRL31_POC_VI1_CLK
+				   | IOCTRL31_POC_VI0_FIELD
+				   | IOCTRL31_POC_VI0_DATA11
+				   | IOCTRL31_POC_VI0_DATA10
+				   | IOCTRL31_POC_VI0_DATA9
+				   | IOCTRL31_POC_VI0_DATA8
+				   | IOCTRL31_POC_VI0_DATA7
+				   | IOCTRL31_POC_VI0_DATA6);
+
+	pfc_reg_write(PFC_POCCTRL1, 0x00000000);
+
+	pfc_reg_write(PFC_TDSELCTRL0, 0x00000000);
+
+	/* initialize Pull enable */
+	pfc_reg_write(PFC_PUEN0, PUEN0_PUEN_VI0_CLK
+				   | PUEN0_PUEN_TDI
+				   | PUEN0_PUEN_TMS
+				   | PUEN0_PUEN_TCK
+				   | PUEN0_PUEN_TRST_N
+				   | PUEN0_PUEN_IRQ0
+				   | PUEN0_PUEN_FSCLKST_N
+				   | PUEN0_PUEN_DU_EXHSYNC_DU_HSYNC
+				   | PUEN0_PUEN_DU_DOTCLKOUT
+				   | PUEN0_PUEN_DU_DB7
+				   | PUEN0_PUEN_DU_DB6
+				   | PUEN0_PUEN_DU_DB5
+				   | PUEN0_PUEN_DU_DB4
+				   | PUEN0_PUEN_DU_DB3
+				   | PUEN0_PUEN_DU_DB2
+				   | PUEN0_PUEN_DU_DG7
+				   | PUEN0_PUEN_DU_DG6
+				   | PUEN0_PUEN_DU_DG5
+				   | PUEN0_PUEN_DU_DG4
+				   | PUEN0_PUEN_DU_DG3
+				   | PUEN0_PUEN_DU_DG2
+				   | PUEN0_PUEN_DU_DR7
+				   | PUEN0_PUEN_DU_DR6
+				   | PUEN0_PUEN_DU_DR5
+				   | PUEN0_PUEN_DU_DR4
+				   | PUEN0_PUEN_DU_DR3
+				   | PUEN0_PUEN_DU_DR2);
+
+	pfc_reg_write(PFC_PUEN1, PUEN1_PUEN_VI1_DATA11
+				   | PUEN1_PUEN_VI1_DATA10
+				   | PUEN1_PUEN_VI1_DATA9
+				   | PUEN1_PUEN_VI1_DATA8
+				   | PUEN1_PUEN_VI1_DATA7
+				   | PUEN1_PUEN_VI1_DATA6
+				   | PUEN1_PUEN_VI1_DATA5
+				   | PUEN1_PUEN_VI1_DATA4
+				   | PUEN1_PUEN_VI1_DATA3
+				   | PUEN1_PUEN_VI1_DATA2
+				   | PUEN1_PUEN_VI1_DATA1
+				   | PUEN1_PUEN_VI1_DATA0
+				   | PUEN1_PUEN_VI1_VSYNC_N
+				   | PUEN1_PUEN_VI1_HSYNC_N
+				   | PUEN1_PUEN_VI1_CLKENB
+				   | PUEN1_PUEN_VI1_CLK
+				   | PUEN1_PUEN_VI0_DATA11
+				   | PUEN1_PUEN_VI0_DATA10
+				   | PUEN1_PUEN_VI0_DATA9
+				   | PUEN1_PUEN_VI0_DATA8
+				   | PUEN1_PUEN_VI0_DATA7
+				   | PUEN1_PUEN_VI0_DATA6
+				   | PUEN1_PUEN_VI0_DATA5
+				   | PUEN1_PUEN_VI0_DATA4
+				   | PUEN1_PUEN_VI0_DATA3
+				   | PUEN1_PUEN_VI0_DATA2
+				   | PUEN1_PUEN_VI0_DATA1);
+
+	pfc_reg_write(PFC_PUEN2, PUEN2_PUEN_CANFD_CLK
+				   | PUEN2_PUEN_CANFD1_RX
+				   | PUEN2_PUEN_CANFD1_TX
+				   | PUEN2_PUEN_CANFD0_RX
+				   | PUEN2_PUEN_CANFD0_TX
+				   | PUEN2_PUEN_AVB0_AVTP_CAPTURE
+				   | PUEN2_PUEN_AVB0_AVTP_MATCH
+				   | PUEN2_PUEN_AVB0_LINK
+				   | PUEN2_PUEN_AVB0_PHY_INT
+				   | PUEN2_PUEN_AVB0_MAGIC
+				   | PUEN2_PUEN_AVB0_TXCREFCLK
+				   | PUEN2_PUEN_AVB0_TD3
+				   | PUEN2_PUEN_AVB0_TD2
+				   | PUEN2_PUEN_AVB0_TD1
+				   | PUEN2_PUEN_AVB0_TD0
+				   | PUEN2_PUEN_AVB0_TXC
+				   | PUEN2_PUEN_AVB0_TX_CTL
+				   | PUEN2_PUEN_AVB0_RD3
+				   | PUEN2_PUEN_AVB0_RD2
+				   | PUEN2_PUEN_AVB0_RD1
+				   | PUEN2_PUEN_AVB0_RD0
+				   | PUEN2_PUEN_AVB0_RXC
+				   | PUEN2_PUEN_AVB0_RX_CTL
+				   | PUEN2_PUEN_VI1_FIELD);
+
+	pfc_reg_write(PFC_PUEN3, PUEN3_PUEN_DIGRF_CLKOUT
+				   | PUEN3_PUEN_DIGRF_CLKIN);
+
+	/* initialize PUD Control */
+	pfc_reg_write(PFC_PUD0, PUD0_PUD_VI0_CLK
+				   | PUD0_PUD_IRQ0
+				   | PUD0_PUD_FSCLKST_N
+				   | PUD0_PUD_DU_EXODDF_DU_ODDF_DISP_CDE
+				   | PUD0_PUD_DU_EXVSYNC_DU_VSYNC
+				   | PUD0_PUD_DU_EXHSYNC_DU_HSYNC
+				   | PUD0_PUD_DU_DOTCLKOUT
+				   | PUD0_PUD_DU_DB7
+				   | PUD0_PUD_DU_DB6
+				   | PUD0_PUD_DU_DB5
+				   | PUD0_PUD_DU_DB4
+				   | PUD0_PUD_DU_DB3
+				   | PUD0_PUD_DU_DB2
+				   | PUD0_PUD_DU_DG7
+				   | PUD0_PUD_DU_DG6
+				   | PUD0_PUD_DU_DG5
+				   | PUD0_PUD_DU_DG4
+				   | PUD0_PUD_DU_DG3
+				   | PUD0_PUD_DU_DG2
+				   | PUD0_PUD_DU_DR7
+				   | PUD0_PUD_DU_DR6
+				   | PUD0_PUD_DU_DR5
+				   | PUD0_PUD_DU_DR4
+				   | PUD0_PUD_DU_DR3
+				   | PUD0_PUD_DU_DR2);
+
+	pfc_reg_write(PFC_PUD1, PUD1_PUD_VI1_DATA11
+				   | PUD1_PUD_VI1_DATA10
+				   | PUD1_PUD_VI1_DATA9
+				   | PUD1_PUD_VI1_DATA8
+				   | PUD1_PUD_VI1_DATA7
+				   | PUD1_PUD_VI1_DATA6
+				   | PUD1_PUD_VI1_DATA5
+				   | PUD1_PUD_VI1_DATA4
+				   | PUD1_PUD_VI1_DATA3
+				   | PUD1_PUD_VI1_DATA2
+				   | PUD1_PUD_VI1_DATA1
+				   | PUD1_PUD_VI1_DATA0
+				   | PUD1_PUD_VI1_VSYNC_N
+				   | PUD1_PUD_VI1_HSYNC_N
+				   | PUD1_PUD_VI1_CLKENB
+				   | PUD1_PUD_VI1_CLK
+				   | PUD1_PUD_VI0_DATA11
+				   | PUD1_PUD_VI0_DATA10
+				   | PUD1_PUD_VI0_DATA9
+				   | PUD1_PUD_VI0_DATA8
+				   | PUD1_PUD_VI0_DATA7
+				   | PUD1_PUD_VI0_DATA6
+				   | PUD1_PUD_VI0_DATA5
+				   | PUD1_PUD_VI0_DATA4
+				   | PUD1_PUD_VI0_DATA3
+				   | PUD1_PUD_VI0_DATA2
+				   | PUD1_PUD_VI0_DATA1
+				   | PUD1_PUD_VI0_DATA0
+				   | PUD1_PUD_VI0_VSYNC_N
+				   | PUD1_PUD_VI0_HSYNC_N
+				   | PUD1_PUD_VI0_CLKENB);
+
+	pfc_reg_write(PFC_PUD2, PUD2_PUD_CANFD_CLK
+				   | PUD2_PUD_CANFD1_RX
+				   | PUD2_PUD_CANFD1_TX
+				   | PUD2_PUD_CANFD0_RX
+				   | PUD2_PUD_CANFD0_TX
+				   | PUD2_PUD_AVB0_AVTP_CAPTURE
+				   | PUD2_PUD_VI1_FIELD);
+
+	pfc_reg_write(PFC_PUD3, PUD3_PUD_DIGRF_CLKOUT
+				   | PUD3_PUD_DIGRF_CLKIN);
+
+	/* initialize Module Select */
+	pfc_reg_write(PFC_MOD_SEL0, 0x00000000);
+
+	// gpio
+	/* initialize positive/negative logic select */
+	mmio_write_32(GPIO_POSNEG0, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG1, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG2, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG3, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG4, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG5, 0x00000000U);
+
+	/* initialize general IO/interrupt switching */
+	mmio_write_32(GPIO_IOINTSEL0, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL1, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL2, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL3, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL4, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL5, 0x00000000U);
+
+	/* initialize general output register */
+	mmio_write_32(GPIO_OUTDT0, 0x00000000U);
+	mmio_write_32(GPIO_OUTDT1, 0x00000000U);
+	mmio_write_32(GPIO_OUTDT2, 0x00000000U);
+	mmio_write_32(GPIO_OUTDT3, 0x00000000U);
+	mmio_write_32(GPIO_OUTDT4, 0x00000000U);
+	mmio_write_32(GPIO_OUTDT5, 0x00000000U);
+
+	/* initialize general input/output switching */
+	mmio_write_32(GPIO_INOUTSEL0, 0x00000000U);
+	mmio_write_32(GPIO_INOUTSEL1, 0x00000000U);
+	mmio_write_32(GPIO_INOUTSEL2, 0x00000000U);
+	mmio_write_32(GPIO_INOUTSEL3, 0x00000000U);
+	mmio_write_32(GPIO_INOUTSEL4, 0x00000000U);
+	mmio_write_32(GPIO_INOUTSEL5, 0x00000000U);
+}
diff --git a/drivers/staging/renesas/rcar/pfc/V3M/pfc_init_v3m.h b/drivers/renesas/rcar/pfc/V3M/pfc_init_v3m.h
similarity index 67%
rename from drivers/staging/renesas/rcar/pfc/V3M/pfc_init_v3m.h
rename to drivers/renesas/rcar/pfc/V3M/pfc_init_v3m.h
index eded87c..7bab92f 100644
--- a/drivers/staging/renesas/rcar/pfc/V3M/pfc_init_v3m.h
+++ b/drivers/renesas/rcar/pfc/V3M/pfc_init_v3m.h
@@ -5,9 +5,9 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef PFC_INIT_V3M_H__
-#define PFC_INIT_V3M_H__
+#ifndef PFC_INIT_V3M_H
+#define PFC_INIT_V3M_H
 
 void pfc_init_v3m(void);
 
-#endif	/* PFC_INIT_V3M_H__ */
+#endif	/* PFC_INIT_V3M_H */
diff --git a/drivers/renesas/rcar/pfc/pfc.mk b/drivers/renesas/rcar/pfc/pfc.mk
new file mode 100644
index 0000000..f1dd92c
--- /dev/null
+++ b/drivers/renesas/rcar/pfc/pfc.mk
@@ -0,0 +1,69 @@
+#
+# Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+ifeq (${RCAR_LSI},${RCAR_AUTO})
+    BL2_SOURCES += drivers/renesas/rcar/pfc/H3/pfc_init_h3_v1.c
+    BL2_SOURCES += drivers/renesas/rcar/pfc/H3/pfc_init_h3_v2.c
+    BL2_SOURCES += drivers/renesas/rcar/pfc/M3/pfc_init_m3.c
+    BL2_SOURCES += drivers/renesas/rcar/pfc/M3N/pfc_init_m3n.c
+    BL2_SOURCES += drivers/renesas/rcar/pfc/V3M/pfc_init_v3m.c
+
+else ifdef RCAR_LSI_CUT_COMPAT
+  ifeq (${RCAR_LSI},${RCAR_H3})
+    BL2_SOURCES += drivers/renesas/rcar/pfc/H3/pfc_init_h3_v1.c
+    BL2_SOURCES += drivers/renesas/rcar/pfc/H3/pfc_init_h3_v2.c
+  endif
+  ifeq (${RCAR_LSI},${RCAR_H3N})
+    BL2_SOURCES += drivers/renesas/rcar/pfc/H3/pfc_init_h3_v1.c
+    BL2_SOURCES += drivers/renesas/rcar/pfc/H3/pfc_init_h3_v2.c
+  endif
+  ifeq (${RCAR_LSI},${RCAR_M3})
+    BL2_SOURCES += drivers/renesas/rcar/pfc/M3/pfc_init_m3.c
+  endif
+  ifeq (${RCAR_LSI},${RCAR_M3N})
+    BL2_SOURCES += drivers/renesas/rcar/pfc/M3N/pfc_init_m3n.c
+  endif
+  ifeq (${RCAR_LSI},${RCAR_V3M})
+    BL2_SOURCES += drivers/renesas/rcar/pfc/V3M/pfc_init_v3m.c
+  endif
+  ifeq (${RCAR_LSI},${RCAR_E3})
+    BL2_SOURCES += drivers/renesas/rcar/pfc/E3/pfc_init_e3.c
+  endif
+  ifeq (${RCAR_LSI},${RCAR_D3})
+    BL2_SOURCES += drivers/renesas/rcar/pfc/D3/pfc_init_d3.c
+  endif
+else
+  ifeq (${RCAR_LSI},${RCAR_H3})
+    ifeq (${LSI_CUT},10)
+      BL2_SOURCES += drivers/renesas/rcar/pfc/H3/pfc_init_h3_v1.c
+    else ifeq (${LSI_CUT},11)
+      BL2_SOURCES += drivers/renesas/rcar/pfc/H3/pfc_init_h3_v1.c
+    else
+#     LSI_CUT 20 or later
+      BL2_SOURCES += drivers/renesas/rcar/pfc/H3/pfc_init_h3_v2.c
+    endif
+  endif
+  ifeq (${RCAR_LSI},${RCAR_H3N})
+    BL2_SOURCES += drivers/renesas/rcar/pfc/H3/pfc_init_h3_v2.c
+  endif
+  ifeq (${RCAR_LSI},${RCAR_M3})
+    BL2_SOURCES += drivers/renesas/rcar/pfc/M3/pfc_init_m3.c
+  endif
+  ifeq (${RCAR_LSI},${RCAR_M3N})
+    BL2_SOURCES += drivers/renesas/rcar/pfc/M3N/pfc_init_m3n.c
+  endif
+  ifeq (${RCAR_LSI},${RCAR_V3M})
+    BL2_SOURCES += drivers/renesas/rcar/pfc/V3M/pfc_init_v3m.c
+  endif
+  ifeq (${RCAR_LSI},${RCAR_E3})
+    BL2_SOURCES += drivers/renesas/rcar/pfc/E3/pfc_init_e3.c
+  endif
+  ifeq (${RCAR_LSI},${RCAR_D3})
+    BL2_SOURCES += drivers/renesas/rcar/pfc/D3/pfc_init_d3.c
+  endif
+endif
+
+BL2_SOURCES += drivers/renesas/rcar/pfc/pfc_init.c
diff --git a/drivers/staging/renesas/rcar/pfc/pfc_init.c b/drivers/renesas/rcar/pfc/pfc_init.c
similarity index 93%
rename from drivers/staging/renesas/rcar/pfc/pfc_init.c
rename to drivers/renesas/rcar/pfc/pfc_init.c
index 3cf32d4..e9455af 100644
--- a/drivers/staging/renesas/rcar/pfc/pfc_init.c
+++ b/drivers/renesas/rcar/pfc/pfc_init.c
@@ -51,16 +51,19 @@
 #define PRR_PRODUCT_11		(0x01U)
 #define PRR_PRODUCT_20		(0x10U)
 
-#define PRR_PRODUCT_ERR(reg)	do{\
-				ERROR("LSI Product ID(PRR=0x%x) PFC "\
-				"initialize not supported.\n",reg);\
-				panic();\
-				}while(0)
-#define PRR_CUT_ERR(reg)	do{\
-				ERROR("LSI Cut ID(PRR=0x%x) PFC "\
-				"initialize not supported.\n",reg);\
-				panic();\
-				}while(0)
+#define PRR_PRODUCT_ERR(reg)				\
+	do {						\
+		ERROR("LSI Product ID(PRR=0x%x) PFC initialize not supported.\n", \
+			reg);				\
+		panic();				\
+	} while (0)
+
+#define PRR_CUT_ERR(reg)				\
+	do {						\
+		ERROR("LSI Cut ID(PRR=0x%x) PFC initialize not supported.\n", \
+			reg);				\
+		panic();\
+	} while (0)
 
 void rcar_pfc_init(void)
 {
diff --git a/drivers/renesas/rcar/pfc/pfc_regs.h b/drivers/renesas/rcar/pfc/pfc_regs.h
new file mode 100644
index 0000000..b0b4e6f
--- /dev/null
+++ b/drivers/renesas/rcar/pfc/pfc_regs.h
@@ -0,0 +1,231 @@
+/*
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef PFC_REGS_H
+#define PFC_REGS_H
+
+/* GPIO base address */
+#define GPIO_BASE		(0xE6050000U)
+
+/* GPIO registers */
+#define GPIO_IOINTSEL0		(GPIO_BASE + 0x0000U)
+#define GPIO_INOUTSEL0		(GPIO_BASE + 0x0004U)
+#define GPIO_OUTDT0		(GPIO_BASE + 0x0008U)
+#define GPIO_INDT0		(GPIO_BASE + 0x000CU)
+#define GPIO_INTDT0		(GPIO_BASE + 0x0010U)
+#define GPIO_INTCLR0		(GPIO_BASE + 0x0014U)
+#define GPIO_INTMSK0		(GPIO_BASE + 0x0018U)
+#define GPIO_MSKCLR0		(GPIO_BASE + 0x001CU)
+#define GPIO_POSNEG0		(GPIO_BASE + 0x0020U)
+#define GPIO_EDGLEVEL0		(GPIO_BASE + 0x0024U)
+#define GPIO_FILONOFF0		(GPIO_BASE + 0x0028U)
+#define GPIO_INTMSKS0		(GPIO_BASE + 0x0038U)
+#define GPIO_MSKCLRS0		(GPIO_BASE + 0x003CU)
+#define GPIO_OUTDTSEL0		(GPIO_BASE + 0x0040U)
+#define GPIO_OUTDTH0		(GPIO_BASE + 0x0044U)
+#define GPIO_OUTDTL0		(GPIO_BASE + 0x0048U)
+#define GPIO_BOTHEDGE0		(GPIO_BASE + 0x004CU)
+#define GPIO_IOINTSEL1		(GPIO_BASE + 0x1000U)
+#define GPIO_INOUTSEL1		(GPIO_BASE + 0x1004U)
+#define GPIO_OUTDT1		(GPIO_BASE + 0x1008U)
+#define GPIO_INDT1		(GPIO_BASE + 0x100CU)
+#define GPIO_INTDT1		(GPIO_BASE + 0x1010U)
+#define GPIO_INTCLR1		(GPIO_BASE + 0x1014U)
+#define GPIO_INTMSK1		(GPIO_BASE + 0x1018U)
+#define GPIO_MSKCLR1		(GPIO_BASE + 0x101CU)
+#define GPIO_POSNEG1		(GPIO_BASE + 0x1020U)
+#define GPIO_EDGLEVEL1		(GPIO_BASE + 0x1024U)
+#define GPIO_FILONOFF1		(GPIO_BASE + 0x1028U)
+#define GPIO_INTMSKS1		(GPIO_BASE + 0x1038U)
+#define GPIO_MSKCLRS1		(GPIO_BASE + 0x103CU)
+#define GPIO_OUTDTSEL1		(GPIO_BASE + 0x1040U)
+#define GPIO_OUTDTH1		(GPIO_BASE + 0x1044U)
+#define GPIO_OUTDTL1		(GPIO_BASE + 0x1048U)
+#define GPIO_BOTHEDGE1		(GPIO_BASE + 0x104CU)
+#define GPIO_IOINTSEL2		(GPIO_BASE + 0x2000U)
+#define GPIO_INOUTSEL2		(GPIO_BASE + 0x2004U)
+#define GPIO_OUTDT2		(GPIO_BASE + 0x2008U)
+#define GPIO_INDT2		(GPIO_BASE + 0x200CU)
+#define GPIO_INTDT2		(GPIO_BASE + 0x2010U)
+#define GPIO_INTCLR2		(GPIO_BASE + 0x2014U)
+#define GPIO_INTMSK2		(GPIO_BASE + 0x2018U)
+#define GPIO_MSKCLR2		(GPIO_BASE + 0x201CU)
+#define GPIO_POSNEG2		(GPIO_BASE + 0x2020U)
+#define GPIO_EDGLEVEL2		(GPIO_BASE + 0x2024U)
+#define GPIO_FILONOFF2		(GPIO_BASE + 0x2028U)
+#define GPIO_INTMSKS2		(GPIO_BASE + 0x2038U)
+#define GPIO_MSKCLRS2		(GPIO_BASE + 0x203CU)
+#define GPIO_OUTDTSEL2		(GPIO_BASE + 0x2040U)
+#define GPIO_OUTDTH2		(GPIO_BASE + 0x2044U)
+#define GPIO_OUTDTL2		(GPIO_BASE + 0x2048U)
+#define GPIO_BOTHEDGE2		(GPIO_BASE + 0x204CU)
+#define GPIO_IOINTSEL3		(GPIO_BASE + 0x3000U)
+#define GPIO_INOUTSEL3		(GPIO_BASE + 0x3004U)
+#define GPIO_OUTDT3		(GPIO_BASE + 0x3008U)
+#define GPIO_INDT3		(GPIO_BASE + 0x300CU)
+#define GPIO_INTDT3		(GPIO_BASE + 0x3010U)
+#define GPIO_INTCLR3		(GPIO_BASE + 0x3014U)
+#define GPIO_INTMSK3		(GPIO_BASE + 0x3018U)
+#define GPIO_MSKCLR3		(GPIO_BASE + 0x301CU)
+#define GPIO_POSNEG3		(GPIO_BASE + 0x3020U)
+#define GPIO_EDGLEVEL3		(GPIO_BASE + 0x3024U)
+#define GPIO_FILONOFF3		(GPIO_BASE + 0x3028U)
+#define GPIO_INTMSKS3		(GPIO_BASE + 0x3038U)
+#define GPIO_MSKCLRS3		(GPIO_BASE + 0x303CU)
+#define GPIO_OUTDTSEL3		(GPIO_BASE + 0x3040U)
+#define GPIO_OUTDTH3		(GPIO_BASE + 0x3044U)
+#define GPIO_OUTDTL3		(GPIO_BASE + 0x3048U)
+#define GPIO_BOTHEDGE3		(GPIO_BASE + 0x304CU)
+#define GPIO_IOINTSEL4		(GPIO_BASE + 0x4000U)
+#define GPIO_INOUTSEL4		(GPIO_BASE + 0x4004U)
+#define GPIO_OUTDT4		(GPIO_BASE + 0x4008U)
+#define GPIO_INDT4		(GPIO_BASE + 0x400CU)
+#define GPIO_INTDT4		(GPIO_BASE + 0x4010U)
+#define GPIO_INTCLR4		(GPIO_BASE + 0x4014U)
+#define GPIO_INTMSK4		(GPIO_BASE + 0x4018U)
+#define GPIO_MSKCLR4		(GPIO_BASE + 0x401CU)
+#define GPIO_POSNEG4		(GPIO_BASE + 0x4020U)
+#define GPIO_EDGLEVEL4		(GPIO_BASE + 0x4024U)
+#define GPIO_FILONOFF4		(GPIO_BASE + 0x4028U)
+#define GPIO_INTMSKS4		(GPIO_BASE + 0x4038U)
+#define GPIO_MSKCLRS4		(GPIO_BASE + 0x403CU)
+#define GPIO_OUTDTSEL4		(GPIO_BASE + 0x4040U)
+#define GPIO_OUTDTH4		(GPIO_BASE + 0x4044U)
+#define GPIO_OUTDTL4		(GPIO_BASE + 0x4048U)
+#define GPIO_BOTHEDGE4		(GPIO_BASE + 0x404CU)
+#define GPIO_IOINTSEL5		(GPIO_BASE + 0x5000U)
+#define GPIO_INOUTSEL5		(GPIO_BASE + 0x5004U)
+#define GPIO_OUTDT5		(GPIO_BASE + 0x5008U)
+#define GPIO_INDT5		(GPIO_BASE + 0x500CU)
+#define GPIO_INTDT5		(GPIO_BASE + 0x5010U)
+#define GPIO_INTCLR5		(GPIO_BASE + 0x5014U)
+#define GPIO_INTMSK5		(GPIO_BASE + 0x5018U)
+#define GPIO_MSKCLR5		(GPIO_BASE + 0x501CU)
+#define GPIO_POSNEG5		(GPIO_BASE + 0x5020U)
+#define GPIO_EDGLEVEL5		(GPIO_BASE + 0x5024U)
+#define GPIO_FILONOFF5		(GPIO_BASE + 0x5028U)
+#define GPIO_INTMSKS5		(GPIO_BASE + 0x5038U)
+#define GPIO_MSKCLRS5		(GPIO_BASE + 0x503CU)
+#define GPIO_OUTDTSEL5		(GPIO_BASE + 0x5040U)
+#define GPIO_OUTDTH5		(GPIO_BASE + 0x5044U)
+#define GPIO_OUTDTL5		(GPIO_BASE + 0x5048U)
+#define GPIO_BOTHEDGE5		(GPIO_BASE + 0x504CU)
+#define GPIO_IOINTSEL6		(GPIO_BASE + 0x5400U)
+#define GPIO_INOUTSEL6		(GPIO_BASE + 0x5404U)
+#define GPIO_OUTDT6		(GPIO_BASE + 0x5408U)
+#define GPIO_INDT6		(GPIO_BASE + 0x540CU)
+#define GPIO_INTDT6		(GPIO_BASE + 0x5410U)
+#define GPIO_INTCLR6		(GPIO_BASE + 0x5414U)
+#define GPIO_INTMSK6		(GPIO_BASE + 0x5418U)
+#define GPIO_MSKCLR6		(GPIO_BASE + 0x541CU)
+#define GPIO_POSNEG6		(GPIO_BASE + 0x5420U)
+#define GPIO_EDGLEVEL6		(GPIO_BASE + 0x5424U)
+#define GPIO_FILONOFF6		(GPIO_BASE + 0x5428U)
+#define GPIO_INTMSKS6		(GPIO_BASE + 0x5438U)
+#define GPIO_MSKCLRS6		(GPIO_BASE + 0x543CU)
+#define GPIO_OUTDTSEL6		(GPIO_BASE + 0x5440U)
+#define GPIO_OUTDTH6		(GPIO_BASE + 0x5444U)
+#define GPIO_OUTDTL6		(GPIO_BASE + 0x5448U)
+#define GPIO_BOTHEDGE6		(GPIO_BASE + 0x544CU)
+#define GPIO_IOINTSEL7		(GPIO_BASE + 0x5800U)
+#define GPIO_INOUTSEL7		(GPIO_BASE + 0x5804U)
+#define GPIO_OUTDT7		(GPIO_BASE + 0x5808U)
+#define GPIO_INDT7		(GPIO_BASE + 0x580CU)
+#define GPIO_INTDT7		(GPIO_BASE + 0x5810U)
+#define GPIO_INTCLR7		(GPIO_BASE + 0x5814U)
+#define GPIO_INTMSK7		(GPIO_BASE + 0x5818U)
+#define GPIO_MSKCLR7		(GPIO_BASE + 0x581CU)
+#define GPIO_POSNEG7		(GPIO_BASE + 0x5820U)
+#define GPIO_EDGLEVEL7		(GPIO_BASE + 0x5824U)
+#define GPIO_FILONOFF7		(GPIO_BASE + 0x5828U)
+#define GPIO_INTMSKS7		(GPIO_BASE + 0x5838U)
+#define GPIO_MSKCLRS7		(GPIO_BASE + 0x583CU)
+#define GPIO_OUTDTSEL7		(GPIO_BASE + 0x5840U)
+#define GPIO_OUTDTH7		(GPIO_BASE + 0x5844U)
+#define GPIO_OUTDTL7		(GPIO_BASE + 0x5848U)
+#define GPIO_BOTHEDGE7		(GPIO_BASE + 0x584CU)
+
+/* Pin functon base address */
+#define PFC_BASE		(0xE6060000U)
+
+/* Pin functon registers */
+#define PFC_PMMR		(PFC_BASE + 0x0000U)
+#define PFC_GPSR0		(PFC_BASE + 0x0100U)
+#define PFC_GPSR1		(PFC_BASE + 0x0104U)
+#define PFC_GPSR2		(PFC_BASE + 0x0108U)
+#define PFC_GPSR3		(PFC_BASE + 0x010CU)
+#define PFC_GPSR4		(PFC_BASE + 0x0110U)
+#define PFC_GPSR5		(PFC_BASE + 0x0114U)
+#define PFC_GPSR6		(PFC_BASE + 0x0118U)
+#define PFC_GPSR7		(PFC_BASE + 0x011CU)
+#define PFC_IPSR0		(PFC_BASE + 0x0200U)
+#define PFC_IPSR1		(PFC_BASE + 0x0204U)
+#define PFC_IPSR2		(PFC_BASE + 0x0208U)
+#define PFC_IPSR3		(PFC_BASE + 0x020CU)
+#define PFC_IPSR4		(PFC_BASE + 0x0210U)
+#define PFC_IPSR5		(PFC_BASE + 0x0214U)
+#define PFC_IPSR6		(PFC_BASE + 0x0218U)
+#define PFC_IPSR7		(PFC_BASE + 0x021CU)
+#define PFC_IPSR8		(PFC_BASE + 0x0220U)
+#define PFC_IPSR9		(PFC_BASE + 0x0224U)
+#define PFC_IPSR10		(PFC_BASE + 0x0228U)
+#define PFC_IPSR11		(PFC_BASE + 0x022CU)
+#define PFC_IPSR12		(PFC_BASE + 0x0230U)
+#define PFC_IPSR13		(PFC_BASE + 0x0234U)
+#define PFC_IPSR14		(PFC_BASE + 0x0238U)
+#define PFC_IPSR15		(PFC_BASE + 0x023CU)
+#define PFC_IPSR16		(PFC_BASE + 0x0240U)
+#define PFC_IPSR17		(PFC_BASE + 0x0244U)
+#define PFC_IPSR18		(PFC_BASE + 0x0248U)
+#define PFC_DRVCTRL0		(PFC_BASE + 0x0300U)
+#define PFC_DRVCTRL1		(PFC_BASE + 0x0304U)
+#define PFC_DRVCTRL2		(PFC_BASE + 0x0308U)
+#define PFC_DRVCTRL3		(PFC_BASE + 0x030CU)
+#define PFC_DRVCTRL4		(PFC_BASE + 0x0310U)
+#define PFC_DRVCTRL5		(PFC_BASE + 0x0314U)
+#define PFC_DRVCTRL6		(PFC_BASE + 0x0318U)
+#define PFC_DRVCTRL7		(PFC_BASE + 0x031CU)
+#define PFC_DRVCTRL8		(PFC_BASE + 0x0320U)
+#define PFC_DRVCTRL9		(PFC_BASE + 0x0324U)
+#define PFC_DRVCTRL10		(PFC_BASE + 0x0328U)
+#define PFC_DRVCTRL11		(PFC_BASE + 0x032CU)
+#define PFC_DRVCTRL12		(PFC_BASE + 0x0330U)
+#define PFC_DRVCTRL13		(PFC_BASE + 0x0334U)
+#define PFC_DRVCTRL14		(PFC_BASE + 0x0338U)
+#define PFC_DRVCTRL15		(PFC_BASE + 0x033CU)
+#define PFC_DRVCTRL16		(PFC_BASE + 0x0340U)
+#define PFC_DRVCTRL17		(PFC_BASE + 0x0344U)
+#define PFC_DRVCTRL18		(PFC_BASE + 0x0348U)
+#define PFC_DRVCTRL19		(PFC_BASE + 0x034CU)
+#define PFC_DRVCTRL20		(PFC_BASE + 0x0350U)
+#define PFC_DRVCTRL21		(PFC_BASE + 0x0354U)
+#define PFC_DRVCTRL22		(PFC_BASE + 0x0358U)
+#define PFC_DRVCTRL23		(PFC_BASE + 0x035CU)
+#define PFC_DRVCTRL24		(PFC_BASE + 0x0360U)
+#define PFC_POCCTRL0		(PFC_BASE + 0x0380U)
+#define PFC_IOCTRL31		(PFC_BASE + 0x0384U)
+#define PFC_POCCTRL1		(PFC_BASE + 0x0388U)
+#define PFC_TDSELCTRL0		(PFC_BASE + 0x03C0U)
+#define PFC_IOCTRL		(PFC_BASE + 0x03E0U)
+#define PFC_TSREG		(PFC_BASE + 0x03E4U)
+#define PFC_PUEN0		(PFC_BASE + 0x0400U)
+#define PFC_PUEN1		(PFC_BASE + 0x0404U)
+#define PFC_PUEN2		(PFC_BASE + 0x0408U)
+#define PFC_PUEN3		(PFC_BASE + 0x040CU)
+#define PFC_PUEN4		(PFC_BASE + 0x0410U)
+#define PFC_PUEN5		(PFC_BASE + 0x0414U)
+#define PFC_PUEN6		(PFC_BASE + 0x0418U)
+#define PFC_PUD0		(PFC_BASE + 0x0440U)
+#define PFC_PUD1		(PFC_BASE + 0x0444U)
+#define PFC_PUD2		(PFC_BASE + 0x0448U)
+#define PFC_PUD3		(PFC_BASE + 0x044CU)
+#define PFC_PUD4		(PFC_BASE + 0x0450U)
+#define PFC_PUD5		(PFC_BASE + 0x0454U)
+#define PFC_PUD6		(PFC_BASE + 0x0458U)
+#define PFC_MOD_SEL0		(PFC_BASE + 0x0500U)
+#define PFC_MOD_SEL1		(PFC_BASE + 0x0504U)
+#define PFC_MOD_SEL2		(PFC_BASE + 0x0508U)
+
+#endif /* PFC_REGS_H */
diff --git a/drivers/staging/renesas/rcar/pfc/D3/pfc_init_d3.c b/drivers/staging/renesas/rcar/pfc/D3/pfc_init_d3.c
deleted file mode 100644
index 1f20d19..0000000
--- a/drivers/staging/renesas/rcar/pfc/D3/pfc_init_d3.c
+++ /dev/null
@@ -1,943 +0,0 @@
-/*
- * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <stdint.h>
-#include <lib/mmio.h>
-#include "pfc_init_d3.h"
-#include "rcar_def.h"
-
-
-/* GPIO base address */
-#define	GPIO_BASE		(0xE6050000U)
-
-/* GPIO registers */
-#define	GPIO_IOINTSEL0		(GPIO_BASE + 0x0000U)
-#define	GPIO_INOUTSEL0		(GPIO_BASE + 0x0004U)
-#define	GPIO_OUTDT0		(GPIO_BASE + 0x0008U)
-#define	GPIO_INDT0		(GPIO_BASE + 0x000CU)
-#define	GPIO_INTDT0		(GPIO_BASE + 0x0010U)
-#define	GPIO_INTCLR0		(GPIO_BASE + 0x0014U)
-#define	GPIO_INTMSK0		(GPIO_BASE + 0x0018U)
-#define	GPIO_MSKCLR0		(GPIO_BASE + 0x001CU)
-#define	GPIO_POSNEG0		(GPIO_BASE + 0x0020U)
-#define	GPIO_EDGLEVEL0		(GPIO_BASE + 0x0024U)
-#define	GPIO_FILONOFF0		(GPIO_BASE + 0x0028U)
-#define	GPIO_INTMSKS0		(GPIO_BASE + 0x0038U)
-#define	GPIO_MSKCLRS0		(GPIO_BASE + 0x003CU)
-#define	GPIO_OUTDTSEL0		(GPIO_BASE + 0x0040U)
-#define	GPIO_OUTDTH0		(GPIO_BASE + 0x0044U)
-#define	GPIO_OUTDTL0		(GPIO_BASE + 0x0048U)
-#define	GPIO_BOTHEDGE0		(GPIO_BASE + 0x004CU)
-#define	GPIO_IOINTSEL1		(GPIO_BASE + 0x1000U)
-#define	GPIO_INOUTSEL1		(GPIO_BASE + 0x1004U)
-#define	GPIO_OUTDT1		(GPIO_BASE + 0x1008U)
-#define	GPIO_INDT1		(GPIO_BASE + 0x100CU)
-#define	GPIO_INTDT1		(GPIO_BASE + 0x1010U)
-#define	GPIO_INTCLR1		(GPIO_BASE + 0x1014U)
-#define	GPIO_INTMSK1		(GPIO_BASE + 0x1018U)
-#define	GPIO_MSKCLR1		(GPIO_BASE + 0x101CU)
-#define	GPIO_POSNEG1		(GPIO_BASE + 0x1020U)
-#define	GPIO_EDGLEVEL1		(GPIO_BASE + 0x1024U)
-#define	GPIO_FILONOFF1		(GPIO_BASE + 0x1028U)
-#define	GPIO_INTMSKS1		(GPIO_BASE + 0x1038U)
-#define	GPIO_MSKCLRS1		(GPIO_BASE + 0x103CU)
-#define	GPIO_OUTDTSEL1		(GPIO_BASE + 0x1040U)
-#define	GPIO_OUTDTH1		(GPIO_BASE + 0x1044U)
-#define	GPIO_OUTDTL1		(GPIO_BASE + 0x1048U)
-#define	GPIO_BOTHEDGE1		(GPIO_BASE + 0x104CU)
-#define	GPIO_IOINTSEL2		(GPIO_BASE + 0x2000U)
-#define	GPIO_INOUTSEL2		(GPIO_BASE + 0x2004U)
-#define	GPIO_OUTDT2		(GPIO_BASE + 0x2008U)
-#define	GPIO_INDT2		(GPIO_BASE + 0x200CU)
-#define	GPIO_INTDT2		(GPIO_BASE + 0x2010U)
-#define	GPIO_INTCLR2		(GPIO_BASE + 0x2014U)
-#define	GPIO_INTMSK2		(GPIO_BASE + 0x2018U)
-#define	GPIO_MSKCLR2		(GPIO_BASE + 0x201CU)
-#define	GPIO_POSNEG2		(GPIO_BASE + 0x2020U)
-#define	GPIO_EDGLEVEL2		(GPIO_BASE + 0x2024U)
-#define	GPIO_FILONOFF2		(GPIO_BASE + 0x2028U)
-#define	GPIO_INTMSKS2		(GPIO_BASE + 0x2038U)
-#define	GPIO_MSKCLRS2		(GPIO_BASE + 0x203CU)
-#define	GPIO_OUTDTSEL2		(GPIO_BASE + 0x2040U)
-#define	GPIO_OUTDTH2		(GPIO_BASE + 0x2044U)
-#define	GPIO_OUTDTL2		(GPIO_BASE + 0x2048U)
-#define	GPIO_BOTHEDGE2		(GPIO_BASE + 0x204CU)
-#define	GPIO_IOINTSEL3		(GPIO_BASE + 0x3000U)
-#define	GPIO_INOUTSEL3		(GPIO_BASE + 0x3004U)
-#define	GPIO_OUTDT3		(GPIO_BASE + 0x3008U)
-#define	GPIO_INDT3		(GPIO_BASE + 0x300CU)
-#define	GPIO_INTDT3		(GPIO_BASE + 0x3010U)
-#define	GPIO_INTCLR3		(GPIO_BASE + 0x3014U)
-#define	GPIO_INTMSK3		(GPIO_BASE + 0x3018U)
-#define	GPIO_MSKCLR3		(GPIO_BASE + 0x301CU)
-#define	GPIO_POSNEG3		(GPIO_BASE + 0x3020U)
-#define	GPIO_EDGLEVEL3		(GPIO_BASE + 0x3024U)
-#define	GPIO_FILONOFF3		(GPIO_BASE + 0x3028U)
-#define	GPIO_INTMSKS3		(GPIO_BASE + 0x3038U)
-#define	GPIO_MSKCLRS3		(GPIO_BASE + 0x303CU)
-#define	GPIO_OUTDTSEL3		(GPIO_BASE + 0x3040U)
-#define	GPIO_OUTDTH3		(GPIO_BASE + 0x3044U)
-#define	GPIO_OUTDTL3		(GPIO_BASE + 0x3048U)
-#define	GPIO_BOTHEDGE3		(GPIO_BASE + 0x304CU)
-#define	GPIO_IOINTSEL4		(GPIO_BASE + 0x4000U)
-#define	GPIO_INOUTSEL4		(GPIO_BASE + 0x4004U)
-#define	GPIO_OUTDT4		(GPIO_BASE + 0x4008U)
-#define	GPIO_INDT4		(GPIO_BASE + 0x400CU)
-#define	GPIO_INTDT4		(GPIO_BASE + 0x4010U)
-#define	GPIO_INTCLR4		(GPIO_BASE + 0x4014U)
-#define	GPIO_INTMSK4		(GPIO_BASE + 0x4018U)
-#define	GPIO_MSKCLR4		(GPIO_BASE + 0x401CU)
-#define	GPIO_POSNEG4		(GPIO_BASE + 0x4020U)
-#define	GPIO_EDGLEVEL4		(GPIO_BASE + 0x4024U)
-#define	GPIO_FILONOFF4		(GPIO_BASE + 0x4028U)
-#define	GPIO_INTMSKS4		(GPIO_BASE + 0x4038U)
-#define	GPIO_MSKCLRS4		(GPIO_BASE + 0x403CU)
-#define	GPIO_OUTDTSEL4		(GPIO_BASE + 0x4040U)
-#define	GPIO_OUTDTH4		(GPIO_BASE + 0x4044U)
-#define	GPIO_OUTDTL4		(GPIO_BASE + 0x4048U)
-#define	GPIO_BOTHEDGE4		(GPIO_BASE + 0x404CU)
-#define	GPIO_IOINTSEL5		(GPIO_BASE + 0x5000U)
-#define	GPIO_INOUTSEL5		(GPIO_BASE + 0x5004U)
-#define	GPIO_OUTDT5		(GPIO_BASE + 0x5008U)
-#define	GPIO_INDT5		(GPIO_BASE + 0x500CU)
-#define	GPIO_INTDT5		(GPIO_BASE + 0x5010U)
-#define	GPIO_INTCLR5		(GPIO_BASE + 0x5014U)
-#define	GPIO_INTMSK5		(GPIO_BASE + 0x5018U)
-#define	GPIO_MSKCLR5		(GPIO_BASE + 0x501CU)
-#define	GPIO_POSNEG5		(GPIO_BASE + 0x5020U)
-#define	GPIO_EDGLEVEL5		(GPIO_BASE + 0x5024U)
-#define	GPIO_FILONOFF5		(GPIO_BASE + 0x5028U)
-#define	GPIO_INTMSKS5		(GPIO_BASE + 0x5038U)
-#define	GPIO_MSKCLRS5		(GPIO_BASE + 0x503CU)
-#define	GPIO_OUTDTSEL5		(GPIO_BASE + 0x5040U)
-#define	GPIO_OUTDTH5		(GPIO_BASE + 0x5044U)
-#define	GPIO_OUTDTL5		(GPIO_BASE + 0x5048U)
-#define	GPIO_BOTHEDGE5		(GPIO_BASE + 0x504CU)
-#define	GPIO_IOINTSEL6		(GPIO_BASE + 0x5400U)
-#define	GPIO_INOUTSEL6		(GPIO_BASE + 0x5404U)
-#define	GPIO_OUTDT6		(GPIO_BASE + 0x5408U)
-#define	GPIO_INDT6		(GPIO_BASE + 0x540CU)
-#define	GPIO_INTDT6		(GPIO_BASE + 0x5410U)
-#define	GPIO_INTCLR6		(GPIO_BASE + 0x5414U)
-#define	GPIO_INTMSK6		(GPIO_BASE + 0x5418U)
-#define	GPIO_MSKCLR6		(GPIO_BASE + 0x541CU)
-#define	GPIO_POSNEG6		(GPIO_BASE + 0x5420U)
-#define	GPIO_EDGLEVEL6		(GPIO_BASE + 0x5424U)
-#define	GPIO_FILONOFF6		(GPIO_BASE + 0x5428U)
-#define	GPIO_INTMSKS6		(GPIO_BASE + 0x5438U)
-#define	GPIO_MSKCLRS6		(GPIO_BASE + 0x543CU)
-#define	GPIO_OUTDTSEL6		(GPIO_BASE + 0x5440U)
-#define	GPIO_OUTDTH6		(GPIO_BASE + 0x5444U)
-#define	GPIO_OUTDTL6		(GPIO_BASE + 0x5448U)
-#define	GPIO_BOTHEDGE6		(GPIO_BASE + 0x544CU)
-#define	GPIO_IOINTSEL7		(GPIO_BASE + 0x5800U)
-#define	GPIO_INOUTSEL7		(GPIO_BASE + 0x5804U)
-#define	GPIO_OUTDT7		(GPIO_BASE + 0x5808U)
-#define	GPIO_INDT7		(GPIO_BASE + 0x580CU)
-#define	GPIO_INTDT7		(GPIO_BASE + 0x5810U)
-#define	GPIO_INTCLR7		(GPIO_BASE + 0x5814U)
-#define	GPIO_INTMSK7		(GPIO_BASE + 0x5818U)
-#define	GPIO_MSKCLR7		(GPIO_BASE + 0x581CU)
-#define	GPIO_POSNEG7		(GPIO_BASE + 0x5820U)
-#define	GPIO_EDGLEVEL7		(GPIO_BASE + 0x5824U)
-#define	GPIO_FILONOFF7		(GPIO_BASE + 0x5828U)
-#define	GPIO_INTMSKS7		(GPIO_BASE + 0x5838U)
-#define	GPIO_MSKCLRS7		(GPIO_BASE + 0x583CU)
-#define	GPIO_OUTDTSEL7		(GPIO_BASE + 0x5840U)
-#define	GPIO_OUTDTH7		(GPIO_BASE + 0x5844U)
-#define	GPIO_OUTDTL7		(GPIO_BASE + 0x5848U)
-#define	GPIO_BOTHEDGE7		(GPIO_BASE + 0x584CU)
-
-
-/* Pin functon base address */
-#define	PFC_BASE		(0xE6060000U)
-
-/* Pin functon registers */
-#define	PFC_PMMR		(PFC_BASE + 0x0000U)
-#define PFC_GPSR0		(PFC_BASE + 0x0100U)
-#define PFC_GPSR1		(PFC_BASE + 0x0104U)
-#define PFC_GPSR2		(PFC_BASE + 0x0108U)
-#define PFC_GPSR3		(PFC_BASE + 0x010CU)
-#define PFC_GPSR4		(PFC_BASE + 0x0110U)
-#define	PFC_GPSR5		(PFC_BASE + 0x0114U)
-#define	PFC_GPSR6		(PFC_BASE + 0x0118U)
-#define	PFC_GPSR7		(PFC_BASE + 0x011CU)
-#define	PFC_IPSR0		(PFC_BASE + 0x0200U)
-#define	PFC_IPSR1		(PFC_BASE + 0x0204U)
-#define	PFC_IPSR2		(PFC_BASE + 0x0208U)
-#define	PFC_IPSR3		(PFC_BASE + 0x020CU)
-#define	PFC_IPSR4		(PFC_BASE + 0x0210U)
-#define	PFC_IPSR5		(PFC_BASE + 0x0214U)
-#define	PFC_IPSR6		(PFC_BASE + 0x0218U)
-#define	PFC_IPSR7		(PFC_BASE + 0x021CU)
-#define	PFC_IPSR8		(PFC_BASE + 0x0220U)
-#define	PFC_IPSR9		(PFC_BASE + 0x0224U)
-#define	PFC_IPSR10		(PFC_BASE + 0x0228U)
-#define	PFC_IPSR11		(PFC_BASE + 0x022CU)
-#define	PFC_IPSR12		(PFC_BASE + 0x0230U)
-#define	PFC_IPSR13		(PFC_BASE + 0x0234U)
-#define	PFC_IPSR14		(PFC_BASE + 0x0238U)
-#define	PFC_IPSR15		(PFC_BASE + 0x023CU)
-#define	PFC_IPSR16		(PFC_BASE + 0x0240U)
-#define	PFC_IPSR17		(PFC_BASE + 0x0244U)
-#define	PFC_IPSR18		(PFC_BASE + 0x0248U)
-#define PFC_DRVCTRL0		(PFC_BASE + 0x0300U)
-#define PFC_DRVCTRL1		(PFC_BASE + 0x0304U)
-#define PFC_DRVCTRL2		(PFC_BASE + 0x0308U)
-#define PFC_DRVCTRL3		(PFC_BASE + 0x030CU)
-#define PFC_DRVCTRL4		(PFC_BASE + 0x0310U)
-#define PFC_DRVCTRL5		(PFC_BASE + 0x0314U)
-#define PFC_DRVCTRL6		(PFC_BASE + 0x0318U)
-#define PFC_DRVCTRL7		(PFC_BASE + 0x031CU)
-#define PFC_DRVCTRL8		(PFC_BASE + 0x0320U)
-#define PFC_DRVCTRL9		(PFC_BASE + 0x0324U)
-#define PFC_DRVCTRL10		(PFC_BASE + 0x0328U)
-#define PFC_DRVCTRL11		(PFC_BASE + 0x032CU)
-#define PFC_DRVCTRL12		(PFC_BASE + 0x0330U)
-#define PFC_DRVCTRL13		(PFC_BASE + 0x0334U)
-#define PFC_DRVCTRL14		(PFC_BASE + 0x0338U)
-#define PFC_DRVCTRL15		(PFC_BASE + 0x033CU)
-#define PFC_DRVCTRL16		(PFC_BASE + 0x0340U)
-#define PFC_DRVCTRL17		(PFC_BASE + 0x0344U)
-#define PFC_DRVCTRL18		(PFC_BASE + 0x0348U)
-#define PFC_DRVCTRL19		(PFC_BASE + 0x034CU)
-#define PFC_DRVCTRL20		(PFC_BASE + 0x0350U)
-#define PFC_DRVCTRL21		(PFC_BASE + 0x0354U)
-#define PFC_DRVCTRL22		(PFC_BASE + 0x0358U)
-#define PFC_DRVCTRL23		(PFC_BASE + 0x035CU)
-#define PFC_DRVCTRL24		(PFC_BASE + 0x0360U)
-#define PFC_POCCTRL0		(PFC_BASE + 0x0380U)
-#define PFC_POCCTRL1		(PFC_BASE + 0x0388U)
-#define	PFC_TDSELCTRL0		(PFC_BASE + 0x03C0U)
-#define	PFC_IOCTRL		(PFC_BASE + 0x03E0U)
-#define	PFC_TSREG		(PFC_BASE + 0x03E4U)
-#define	PFC_PUEN0		(PFC_BASE + 0x0400U)
-#define	PFC_PUEN1		(PFC_BASE + 0x0404U)
-#define	PFC_PUEN2		(PFC_BASE + 0x0408U)
-#define	PFC_PUEN3		(PFC_BASE + 0x040CU)
-#define	PFC_PUEN4		(PFC_BASE + 0x0410U)
-#define	PFC_PUEN5		(PFC_BASE + 0x0414U)
-#define	PFC_PUEN6		(PFC_BASE + 0x0418U)
-#define	PFC_PUD0		(PFC_BASE + 0x0440U)
-#define	PFC_PUD1		(PFC_BASE + 0x0444U)
-#define	PFC_PUD2		(PFC_BASE + 0x0448U)
-#define	PFC_PUD3		(PFC_BASE + 0x044CU)
-#define	PFC_PUD4		(PFC_BASE + 0x0450U)
-#define	PFC_PUD5		(PFC_BASE + 0x0454U)
-#define	PFC_PUD6		(PFC_BASE + 0x0458U)
-#define	PFC_MOD_SEL0		(PFC_BASE + 0x0500U)
-#define	PFC_MOD_SEL1		(PFC_BASE + 0x0504U)
-#define	PFC_MOD_SEL2		(PFC_BASE + 0x0508U)
-
-#define	GPSR0_D15		((uint32_t)1U << 15U)
-#define	GPSR0_D14		((uint32_t)1U << 14U)
-#define	GPSR0_D13		((uint32_t)1U << 13U)
-#define	GPSR0_D12		((uint32_t)1U << 12U)
-#define	GPSR0_D11		((uint32_t)1U << 11U)
-#define	GPSR0_D10		((uint32_t)1U << 10U)
-#define	GPSR0_D9		((uint32_t)1U << 9U)
-#define	GPSR0_D8		((uint32_t)1U << 8U)
-#define	GPSR0_D7		((uint32_t)1U << 7U)
-#define	GPSR0_D6		((uint32_t)1U << 6U)
-#define	GPSR0_D5		((uint32_t)1U << 5U)
-#define	GPSR0_D4		((uint32_t)1U << 4U)
-#define	GPSR0_D3		((uint32_t)1U << 3U)
-#define	GPSR0_D2		((uint32_t)1U << 2U)
-#define	GPSR0_D1		((uint32_t)1U << 1U)
-#define	GPSR0_D0		((uint32_t)1U << 0U)
-#define	GPSR1_CLKOUT		((uint32_t)1U << 28U)
-#define	GPSR1_EX_WAIT0_A	((uint32_t)1U << 27U)
-#define	GPSR1_WE1		((uint32_t)1U << 26U)
-#define	GPSR1_WE0		((uint32_t)1U << 25U)
-#define	GPSR1_RD_WR		((uint32_t)1U << 24U)
-#define	GPSR1_RD		((uint32_t)1U << 23U)
-#define	GPSR1_BS		((uint32_t)1U << 22U)
-#define	GPSR1_CS1_A26		((uint32_t)1U << 21U)
-#define	GPSR1_CS0		((uint32_t)1U << 20U)
-#define	GPSR1_A19		((uint32_t)1U << 19U)
-#define	GPSR1_A18		((uint32_t)1U << 18U)
-#define	GPSR1_A17		((uint32_t)1U << 17U)
-#define	GPSR1_A16		((uint32_t)1U << 16U)
-#define	GPSR1_A15		((uint32_t)1U << 15U)
-#define	GPSR1_A14		((uint32_t)1U << 14U)
-#define	GPSR1_A13		((uint32_t)1U << 13U)
-#define	GPSR1_A12		((uint32_t)1U << 12U)
-#define	GPSR1_A11		((uint32_t)1U << 11U)
-#define	GPSR1_A10		((uint32_t)1U << 10U)
-#define	GPSR1_A9		((uint32_t)1U << 9U)
-#define	GPSR1_A8		((uint32_t)1U << 8U)
-#define	GPSR1_A7		((uint32_t)1U << 7U)
-#define	GPSR1_A6		((uint32_t)1U << 6U)
-#define	GPSR1_A5		((uint32_t)1U << 5U)
-#define	GPSR1_A4		((uint32_t)1U << 4U)
-#define	GPSR1_A3		((uint32_t)1U << 3U)
-#define	GPSR1_A2		((uint32_t)1U << 2U)
-#define	GPSR1_A1		((uint32_t)1U << 1U)
-#define	GPSR1_A0		((uint32_t)1U << 0U)
-#define	GPSR2_AVB_AVTP_CAPTURE_A	((uint32_t)1U << 14U)
-#define	GPSR2_AVB_AVTP_MATCH_A	((uint32_t)1U << 13U)
-#define	GPSR2_AVB_LINK		((uint32_t)1U << 12U)
-#define	GPSR2_AVB_PHY_INT	((uint32_t)1U << 11U)
-#define	GPSR2_AVB_MAGIC		((uint32_t)1U << 10U)
-#define	GPSR2_AVB_MDC		((uint32_t)1U << 9U)
-#define	GPSR2_PWM2_A		((uint32_t)1U << 8U)
-#define	GPSR2_PWM1_A		((uint32_t)1U << 7U)
-#define	GPSR2_PWM0		((uint32_t)1U << 6U)
-#define	GPSR2_IRQ5		((uint32_t)1U << 5U)
-#define	GPSR2_IRQ4		((uint32_t)1U << 4U)
-#define	GPSR2_IRQ3		((uint32_t)1U << 3U)
-#define	GPSR2_IRQ2		((uint32_t)1U << 2U)
-#define	GPSR2_IRQ1		((uint32_t)1U << 1U)
-#define	GPSR2_IRQ0		((uint32_t)1U << 0U)
-#define	GPSR3_SD1_WP		((uint32_t)1U << 15U)
-#define	GPSR3_SD1_CD		((uint32_t)1U << 14U)
-#define	GPSR3_SD0_WP		((uint32_t)1U << 13U)
-#define	GPSR3_SD0_CD		((uint32_t)1U << 12U)
-#define	GPSR3_SD1_DAT3		((uint32_t)1U << 11U)
-#define	GPSR3_SD1_DAT2		((uint32_t)1U << 10U)
-#define	GPSR3_SD1_DAT1		((uint32_t)1U << 9U)
-#define	GPSR3_SD1_DAT0		((uint32_t)1U << 8U)
-#define	GPSR3_SD1_CMD		((uint32_t)1U << 7U)
-#define	GPSR3_SD1_CLK		((uint32_t)1U << 6U)
-#define	GPSR3_SD0_DAT3		((uint32_t)1U << 5U)
-#define	GPSR3_SD0_DAT2		((uint32_t)1U << 4U)
-#define	GPSR3_SD0_DAT1		((uint32_t)1U << 3U)
-#define	GPSR3_SD0_DAT0		((uint32_t)1U << 2U)
-#define	GPSR3_SD0_CMD		((uint32_t)1U << 1U)
-#define	GPSR3_SD0_CLK		((uint32_t)1U << 0U)
-#define	GPSR4_SD3_DS		((uint32_t)1U << 17U)
-#define	GPSR4_SD3_DAT7		((uint32_t)1U << 16U)
-#define	GPSR4_SD3_DAT6		((uint32_t)1U << 15U)
-#define	GPSR4_SD3_DAT5		((uint32_t)1U << 14U)
-#define	GPSR4_SD3_DAT4		((uint32_t)1U << 13U)
-#define	GPSR4_SD3_DAT3		((uint32_t)1U << 12U)
-#define	GPSR4_SD3_DAT2		((uint32_t)1U << 11U)
-#define	GPSR4_SD3_DAT1		((uint32_t)1U << 10U)
-#define	GPSR4_SD3_DAT0		((uint32_t)1U << 9U)
-#define	GPSR4_SD3_CMD		((uint32_t)1U << 8U)
-#define	GPSR4_SD3_CLK		((uint32_t)1U << 7U)
-#define	GPSR4_SD2_DS		((uint32_t)1U << 6U)
-#define	GPSR4_SD2_DAT3		((uint32_t)1U << 5U)
-#define	GPSR4_SD2_DAT2		((uint32_t)1U << 4U)
-#define	GPSR4_SD2_DAT1		((uint32_t)1U << 3U)
-#define	GPSR4_SD2_DAT0		((uint32_t)1U << 2U)
-#define	GPSR4_SD2_CMD		((uint32_t)1U << 1U)
-#define	GPSR4_SD2_CLK		((uint32_t)1U << 0U)
-#define	GPSR5_MLB_DAT		((uint32_t)1U << 25U)
-#define	GPSR5_MLB_SIG		((uint32_t)1U << 24U)
-#define	GPSR5_MLB_CLK		((uint32_t)1U << 23U)
-#define	GPSR5_MSIOF0_RXD	((uint32_t)1U << 22U)
-#define	GPSR5_MSIOF0_SS2	((uint32_t)1U << 21U)
-#define	GPSR5_MSIOF0_TXD	((uint32_t)1U << 20U)
-#define	GPSR5_MSIOF0_SS1	((uint32_t)1U << 19U)
-#define	GPSR5_MSIOF0_SYNC	((uint32_t)1U << 18U)
-#define	GPSR5_MSIOF0_SCK	((uint32_t)1U << 17U)
-#define	GPSR5_HRTS0		((uint32_t)1U << 16U)
-#define	GPSR5_HCTS0		((uint32_t)1U << 15U)
-#define	GPSR5_HTX0		((uint32_t)1U << 14U)
-#define	GPSR5_HRX0		((uint32_t)1U << 13U)
-#define	GPSR5_HSCK0		((uint32_t)1U << 12U)
-#define	GPSR5_RX2_A		((uint32_t)1U << 11U)
-#define	GPSR5_TX2_A		((uint32_t)1U << 10U)
-#define	GPSR5_SCK2		((uint32_t)1U << 9U)
-#define	GPSR5_RTS1_TANS		((uint32_t)1U << 8U)
-#define	GPSR5_CTS1		((uint32_t)1U << 7U)
-#define	GPSR5_TX1_A		((uint32_t)1U << 6U)
-#define	GPSR5_RX1_A		((uint32_t)1U << 5U)
-#define	GPSR5_RTS0_TANS		((uint32_t)1U << 4U)
-#define	GPSR5_CTS0		((uint32_t)1U << 3U)
-#define	GPSR5_TX0		((uint32_t)1U << 2U)
-#define	GPSR5_RX0		((uint32_t)1U << 1U)
-#define	GPSR5_SCK0		((uint32_t)1U << 0U)
-#define	GPSR6_USB31_OVC		((uint32_t)1U << 31U)
-#define	GPSR6_USB31_PWEN	((uint32_t)1U << 30U)
-#define	GPSR6_USB30_OVC		((uint32_t)1U << 29U)
-#define	GPSR6_USB30_PWEN	((uint32_t)1U << 28U)
-#define	GPSR6_USB1_OVC		((uint32_t)1U << 27U)
-#define	GPSR6_USB1_PWEN		((uint32_t)1U << 26U)
-#define	GPSR6_USB0_OVC		((uint32_t)1U << 25U)
-#define	GPSR6_USB0_PWEN		((uint32_t)1U << 24U)
-#define	GPSR6_AUDIO_CLKB_B	((uint32_t)1U << 23U)
-#define	GPSR6_AUDIO_CLKA_A	((uint32_t)1U << 22U)
-#define	GPSR6_SSI_SDATA9_A	((uint32_t)1U << 21U)
-#define	GPSR6_SSI_SDATA8	((uint32_t)1U << 20U)
-#define	GPSR6_SSI_SDATA7	((uint32_t)1U << 19U)
-#define	GPSR6_SSI_WS78		((uint32_t)1U << 18U)
-#define	GPSR6_SSI_SCK78		((uint32_t)1U << 17U)
-#define	GPSR6_SSI_SDATA6	((uint32_t)1U << 16U)
-#define	GPSR6_SSI_WS6		((uint32_t)1U << 15U)
-#define	GPSR6_SSI_SCK6		((uint32_t)1U << 14U)
-#define	GPSR6_SSI_SDATA5	((uint32_t)1U << 13U)
-#define	GPSR6_SSI_WS5		((uint32_t)1U << 12U)
-#define	GPSR6_SSI_SCK5		((uint32_t)1U << 11U)
-#define	GPSR6_SSI_SDATA4	((uint32_t)1U << 10U)
-#define	GPSR6_SSI_WS4		((uint32_t)1U << 9U)
-#define	GPSR6_SSI_SCK4		((uint32_t)1U << 8U)
-#define	GPSR6_SSI_SDATA3	((uint32_t)1U << 7U)
-#define	GPSR6_SSI_WS34		((uint32_t)1U << 6U)
-#define	GPSR6_SSI_SCK34		((uint32_t)1U << 5U)
-#define	GPSR6_SSI_SDATA2_A	((uint32_t)1U << 4U)
-#define	GPSR6_SSI_SDATA1_A	((uint32_t)1U << 3U)
-#define	GPSR6_SSI_SDATA0	((uint32_t)1U << 2U)
-#define	GPSR6_SSI_WS0129	((uint32_t)1U << 1U)
-#define	GPSR6_SSI_SCK0129	((uint32_t)1U << 0U)
-#define	GPSR7_HDMI1_CEC		((uint32_t)1U << 3U)
-#define	GPSR7_HDMI0_CEC		((uint32_t)1U << 2U)
-#define	GPSR7_AVS2		((uint32_t)1U << 1U)
-#define	GPSR7_AVS1		((uint32_t)1U << 0U)
-
-#define	IPSR_28_FUNC(x)		((uint32_t)(x) << 28U)
-#define	IPSR_24_FUNC(x)		((uint32_t)(x) << 24U)
-#define	IPSR_20_FUNC(x)		((uint32_t)(x) << 20U)
-#define	IPSR_16_FUNC(x)		((uint32_t)(x) << 16U)
-#define	IPSR_12_FUNC(x)		((uint32_t)(x) << 12U)
-#define	IPSR_8_FUNC(x)		((uint32_t)(x) << 8U)
-#define	IPSR_4_FUNC(x)		((uint32_t)(x) << 4U)
-#define	IPSR_0_FUNC(x)		((uint32_t)(x) << 0U)
-
-#define	POC_SD3_DS_33V		((uint32_t)1U << 29U)
-#define	POC_SD3_DAT7_33V	((uint32_t)1U << 28U)
-#define	POC_SD3_DAT6_33V	((uint32_t)1U << 27U)
-#define	POC_SD3_DAT5_33V	((uint32_t)1U << 26U)
-#define	POC_SD3_DAT4_33V	((uint32_t)1U << 25U)
-#define	POC_SD3_DAT3_33V	((uint32_t)1U << 24U)
-#define	POC_SD3_DAT2_33V	((uint32_t)1U << 23U)
-#define	POC_SD3_DAT1_33V	((uint32_t)1U << 22U)
-#define	POC_SD3_DAT0_33V	((uint32_t)1U << 21U)
-#define	POC_SD3_CMD_33V		((uint32_t)1U << 20U)
-#define	POC_SD3_CLK_33V		((uint32_t)1U << 19U)
-#define	POC_SD2_DS_33V		((uint32_t)1U << 18U)
-#define	POC_SD2_DAT3_33V	((uint32_t)1U << 17U)
-#define	POC_SD2_DAT2_33V	((uint32_t)1U << 16U)
-#define	POC_SD2_DAT1_33V	((uint32_t)1U << 15U)
-#define	POC_SD2_DAT0_33V	((uint32_t)1U << 14U)
-#define	POC_SD2_CMD_33V		((uint32_t)1U << 13U)
-#define	POC_SD2_CLK_33V		((uint32_t)1U << 12U)
-#define	POC_SD1_DAT3_33V	((uint32_t)1U << 11U)
-#define	POC_SD1_DAT2_33V	((uint32_t)1U << 10U)
-#define	POC_SD1_DAT1_33V	((uint32_t)1U << 9U)
-#define	POC_SD1_DAT0_33V	((uint32_t)1U << 8U)
-#define	POC_SD1_CMD_33V		((uint32_t)1U << 7U)
-#define	POC_SD1_CLK_33V		((uint32_t)1U << 6U)
-#define	POC_SD0_DAT3_33V	((uint32_t)1U << 5U)
-#define	POC_SD0_DAT2_33V	((uint32_t)1U << 4U)
-#define	POC_SD0_DAT1_33V	((uint32_t)1U << 3U)
-#define	POC_SD0_DAT0_33V	((uint32_t)1U << 2U)
-#define	POC_SD0_CMD_33V		((uint32_t)1U << 1U)
-#define	POC_SD0_CLK_33V		((uint32_t)1U << 0U)
-
-#define	DRVCTRL0_MASK		(0xCCCCCCCCU)
-#define	DRVCTRL1_MASK		(0xCCCCCCC8U)
-#define	DRVCTRL2_MASK		(0x88888888U)
-#define	DRVCTRL3_MASK		(0x88888888U)
-#define	DRVCTRL4_MASK		(0x88888888U)
-#define	DRVCTRL5_MASK		(0x88888888U)
-#define	DRVCTRL6_MASK		(0x88888888U)
-#define	DRVCTRL7_MASK		(0x88888888U)
-#define	DRVCTRL8_MASK		(0x88888888U)
-#define	DRVCTRL9_MASK		(0x88888888U)
-#define	DRVCTRL10_MASK		(0x88888888U)
-#define	DRVCTRL11_MASK		(0x888888CCU)
-#define	DRVCTRL12_MASK		(0xCCCFFFCFU)
-#define	DRVCTRL13_MASK		(0xCC888888U)
-#define	DRVCTRL14_MASK		(0x88888888U)
-#define	DRVCTRL15_MASK		(0x88888888U)
-#define	DRVCTRL16_MASK		(0x88888888U)
-#define	DRVCTRL17_MASK		(0x88888888U)
-#define	DRVCTRL18_MASK		(0x88888888U)
-#define	DRVCTRL19_MASK		(0x88888888U)
-#define	DRVCTRL20_MASK		(0x88888888U)
-#define	DRVCTRL21_MASK		(0x88888888U)
-#define	DRVCTRL22_MASK		(0x88888888U)
-#define	DRVCTRL23_MASK		(0x88888888U)
-#define	DRVCTRL24_MASK		(0x8888888FU)
-
-#define	DRVCTRL0_QSPI0_SPCLK(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL0_QSPI0_MOSI_IO0(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL0_QSPI0_MISO_IO1(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL0_QSPI0_IO2(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL0_QSPI0_IO3(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL0_QSPI0_SSL(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL0_QSPI1_SPCLK(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL0_QSPI1_MOSI_IO0(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL1_QSPI1_MISO_IO1(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL1_QSPI1_IO2(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL1_QSPI1_IO3(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL1_QSPI1_SS(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL1_RPC_INT(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL1_RPC_WP(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL1_RPC_RESET(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL1_AVB_RX_CTL(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL2_AVB_RXC(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL2_AVB_RD0(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL2_AVB_RD1(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL2_AVB_RD2(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL2_AVB_RD3(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL2_AVB_TX_CTL(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL2_AVB_TXC(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL2_AVB_TD0(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL3_AVB_TD1(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL3_AVB_TD2(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL3_AVB_TD3(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL3_AVB_TXCREFCLK(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL3_AVB_MDIO(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL3_AVB_MDC(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL3_AVB_MAGIC(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL3_AVB_PHY_INT(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL4_AVB_LINK(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL4_AVB_AVTP_MATCH(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL4_AVB_AVTP_CAPTURE(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL4_IRQ0(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL4_IRQ1(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL4_IRQ2(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL4_IRQ3(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL4_IRQ4(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL5_IRQ5(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL5_PWM0(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL5_PWM1(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL5_PWM2(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL5_A0(x)		((uint32_t)(x) << 12U)
-#define	DRVCTRL5_A1(x)		((uint32_t)(x) << 8U)
-#define	DRVCTRL5_A2(x)		((uint32_t)(x) << 4U)
-#define	DRVCTRL5_A3(x)		((uint32_t)(x) << 0U)
-#define	DRVCTRL6_A4(x)		((uint32_t)(x) << 28U)
-#define	DRVCTRL6_A5(x)		((uint32_t)(x) << 24U)
-#define	DRVCTRL6_A6(x)		((uint32_t)(x) << 20U)
-#define	DRVCTRL6_A7(x)		((uint32_t)(x) << 16U)
-#define	DRVCTRL6_A8(x)		((uint32_t)(x) << 12U)
-#define	DRVCTRL6_A9(x)		((uint32_t)(x) << 8U)
-#define	DRVCTRL6_A10(x)		((uint32_t)(x) << 4U)
-#define	DRVCTRL6_A11(x)		((uint32_t)(x) << 0U)
-#define	DRVCTRL7_A12(x)		((uint32_t)(x) << 28U)
-#define	DRVCTRL7_A13(x)		((uint32_t)(x) << 24U)
-#define	DRVCTRL7_A14(x)		((uint32_t)(x) << 20U)
-#define	DRVCTRL7_A15(x)		((uint32_t)(x) << 16U)
-#define	DRVCTRL7_A16(x)		((uint32_t)(x) << 12U)
-#define	DRVCTRL7_A17(x)		((uint32_t)(x) << 8U)
-#define	DRVCTRL7_A18(x)		((uint32_t)(x) << 4U)
-#define	DRVCTRL7_A19(x)		((uint32_t)(x) << 0U)
-#define	DRVCTRL8_CLKOUT(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL8_CS0(x)		((uint32_t)(x) << 24U)
-#define	DRVCTRL8_CS1_A2(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL8_BS(x)		((uint32_t)(x) << 16U)
-#define	DRVCTRL8_RD(x)		((uint32_t)(x) << 12U)
-#define	DRVCTRL8_RD_W(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL8_WE0(x)		((uint32_t)(x) << 4U)
-#define	DRVCTRL8_WE1(x)		((uint32_t)(x) << 0U)
-#define	DRVCTRL9_EX_WAIT0(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL9_PRESETOU(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL9_D0(x)		((uint32_t)(x) << 20U)
-#define	DRVCTRL9_D1(x)		((uint32_t)(x) << 16U)
-#define	DRVCTRL9_D2(x)		((uint32_t)(x) << 12U)
-#define	DRVCTRL9_D3(x)		((uint32_t)(x) << 8U)
-#define	DRVCTRL9_D4(x)		((uint32_t)(x) << 4U)
-#define	DRVCTRL9_D5(x)		((uint32_t)(x) << 0U)
-#define	DRVCTRL10_D6(x)		((uint32_t)(x) << 28U)
-#define	DRVCTRL10_D7(x)		((uint32_t)(x) << 24U)
-#define	DRVCTRL10_D8(x)		((uint32_t)(x) << 20U)
-#define	DRVCTRL10_D9(x)		((uint32_t)(x) << 16U)
-#define	DRVCTRL10_D10(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL10_D11(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL10_D12(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL10_D13(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL11_D14(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL11_D15(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL11_AVS1(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL11_AVS2(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL11_HDMI0_CEC(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL11_HDMI1_CEC(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL11_DU_DOTCLKIN0(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL11_DU_DOTCLKIN1(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL12_DU_DOTCLKIN2(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL12_DU_DOTCLKIN3(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL12_DU_FSCLKST(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL12_DU_TMS(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL13_TDO(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL13_ASEBRK(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL13_SD0_CLK(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL13_SD0_CMD(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL13_SD0_DAT0(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL13_SD0_DAT1(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL13_SD0_DAT2(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL13_SD0_DAT3(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL14_SD1_CLK(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL14_SD1_CMD(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL14_SD1_DAT0(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL14_SD1_DAT1(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL14_SD1_DAT2(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL14_SD1_DAT3(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL14_SD2_CLK(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL14_SD2_CMD(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL15_SD2_DAT0(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL15_SD2_DAT1(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL15_SD2_DAT2(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL15_SD2_DAT3(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL15_SD2_DS(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL15_SD3_CLK(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL15_SD3_CMD(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL15_SD3_DAT0(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL16_SD3_DAT1(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL16_SD3_DAT2(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL16_SD3_DAT3(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL16_SD3_DAT4(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL16_SD3_DAT5(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL16_SD3_DAT6(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL16_SD3_DAT7(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL16_SD3_DS(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL17_SD0_CD(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL17_SD0_WP(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL17_SD1_CD(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL17_SD1_WP(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL17_SCK0(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL17_RX0(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL17_TX0(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL17_CTS0(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL18_RTS0_TANS(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL18_RX1(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL18_TX1(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL18_CTS1(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL18_RTS1_TANS(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL18_SCK2(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL18_TX2(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL18_RX2(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL19_HSCK0(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL19_HRX0(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL19_HTX0(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL19_HCTS0(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL19_HRTS0(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL19_MSIOF0_SCK(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL19_MSIOF0_SYNC(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL19_MSIOF0_SS1(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL20_MSIOF0_TXD(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL20_MSIOF0_SS2(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL20_MSIOF0_RXD(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL20_MLB_CLK(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL20_MLB_SIG(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL20_MLB_DAT(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL20_MLB_REF(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL20_SSI_SCK0129(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL21_SSI_WS0129(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL21_SSI_SDATA0(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL21_SSI_SDATA1(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL21_SSI_SDATA2(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL21_SSI_SCK34(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL21_SSI_WS34(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL21_SSI_SDATA3(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL21_SSI_SCK4(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL22_SSI_WS4(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL22_SSI_SDATA4(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL22_SSI_SCK5(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL22_SSI_WS5(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL22_SSI_SDATA5(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL22_SSI_SCK6(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL22_SSI_WS6(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL22_SSI_SDATA6(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL23_SSI_SCK78(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL23_SSI_WS78(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL23_SSI_SDATA7(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL23_SSI_SDATA8(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL23_SSI_SDATA9(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL23_AUDIO_CLKA(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL23_AUDIO_CLKB(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL23_USB0_PWEN(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL24_USB0_OVC(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL24_USB1_PWEN(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL24_USB1_OVC(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL24_USB30_PWEN(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL24_USB30_OVC(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL24_USB31_PWEN(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL24_USB31_OVC(x)	((uint32_t)(x) << 4U)
-
-#define	MOD_SEL0_MSIOF3_A	((uint32_t)0U << 29U)
-#define	MOD_SEL0_MSIOF3_B	((uint32_t)1U << 29U)
-#define	MOD_SEL0_MSIOF3_C	((uint32_t)2U << 29U)
-#define	MOD_SEL0_MSIOF3_D	((uint32_t)3U << 29U)
-#define	MOD_SEL0_MSIOF3_E	((uint32_t)4U << 29U)
-#define	MOD_SEL0_MSIOF2_A	((uint32_t)0U << 27U)
-#define	MOD_SEL0_MSIOF2_B	((uint32_t)1U << 27U)
-#define	MOD_SEL0_MSIOF2_C	((uint32_t)2U << 27U)
-#define	MOD_SEL0_MSIOF2_D	((uint32_t)3U << 27U)
-#define	MOD_SEL0_MSIOF1_A	((uint32_t)0U << 24U)
-#define	MOD_SEL0_MSIOF1_B	((uint32_t)1U << 24U)
-#define	MOD_SEL0_MSIOF1_C	((uint32_t)2U << 24U)
-#define	MOD_SEL0_MSIOF1_D	((uint32_t)3U << 24U)
-#define	MOD_SEL0_MSIOF1_E	((uint32_t)4U << 24U)
-#define	MOD_SEL0_MSIOF1_F	((uint32_t)5U << 24U)
-#define	MOD_SEL0_MSIOF1_G	((uint32_t)6U << 24U)
-#define	MOD_SEL0_LBSC_A		((uint32_t)0U << 23U)
-#define	MOD_SEL0_LBSC_B		((uint32_t)1U << 23U)
-#define	MOD_SEL0_IEBUS_A	((uint32_t)0U << 22U)
-#define	MOD_SEL0_IEBUS_B	((uint32_t)1U << 22U)
-#define	MOD_SEL0_I2C2_A		((uint32_t)0U << 21U)
-#define	MOD_SEL0_I2C2_B		((uint32_t)1U << 21U)
-#define	MOD_SEL0_I2C1_A		((uint32_t)0U << 20U)
-#define	MOD_SEL0_I2C1_B		((uint32_t)1U << 20U)
-#define	MOD_SEL0_HSCIF4_A	((uint32_t)0U << 19U)
-#define	MOD_SEL0_HSCIF4_B	((uint32_t)1U << 19U)
-#define	MOD_SEL0_HSCIF3_A	((uint32_t)0U << 17U)
-#define	MOD_SEL0_HSCIF3_B	((uint32_t)1U << 17U)
-#define	MOD_SEL0_HSCIF3_C	((uint32_t)2U << 17U)
-#define	MOD_SEL0_HSCIF3_D	((uint32_t)3U << 17U)
-#define	MOD_SEL0_HSCIF1_A	((uint32_t)0U << 16U)
-#define	MOD_SEL0_HSCIF1_B	((uint32_t)1U << 16U)
-#define	MOD_SEL0_FSO_A		((uint32_t)0U << 15U)
-#define	MOD_SEL0_FSO_B		((uint32_t)1U << 15U)
-#define	MOD_SEL0_HSCIF2_A	((uint32_t)0U << 13U)
-#define	MOD_SEL0_HSCIF2_B	((uint32_t)1U << 13U)
-#define	MOD_SEL0_HSCIF2_C	((uint32_t)2U << 13U)
-#define	MOD_SEL0_ETHERAVB_A	((uint32_t)0U << 12U)
-#define	MOD_SEL0_ETHERAVB_B	((uint32_t)1U << 12U)
-#define	MOD_SEL0_DRIF3_A	((uint32_t)0U << 11U)
-#define	MOD_SEL0_DRIF3_B	((uint32_t)1U << 11U)
-#define	MOD_SEL0_DRIF2_A	((uint32_t)0U << 10U)
-#define	MOD_SEL0_DRIF2_B	((uint32_t)1U << 10U)
-#define	MOD_SEL0_DRIF1_A	((uint32_t)0U << 8U)
-#define	MOD_SEL0_DRIF1_B	((uint32_t)1U << 8U)
-#define	MOD_SEL0_DRIF1_C	((uint32_t)2U << 8U)
-#define	MOD_SEL0_DRIF0_A	((uint32_t)0U << 6U)
-#define	MOD_SEL0_DRIF0_B	((uint32_t)1U << 6U)
-#define	MOD_SEL0_DRIF0_C	((uint32_t)2U << 6U)
-#define	MOD_SEL0_CANFD0_A	((uint32_t)0U << 5U)
-#define	MOD_SEL0_CANFD0_B	((uint32_t)1U << 5U)
-#define	MOD_SEL0_ADG_A_A	((uint32_t)0U << 3U)
-#define	MOD_SEL0_ADG_A_B	((uint32_t)1U << 3U)
-#define	MOD_SEL0_ADG_A_C	((uint32_t)2U << 3U)
-#define	MOD_SEL1_TSIF1_A	((uint32_t)0U << 30U)
-#define	MOD_SEL1_TSIF1_B	((uint32_t)1U << 30U)
-#define	MOD_SEL1_TSIF1_C	((uint32_t)2U << 30U)
-#define	MOD_SEL1_TSIF1_D	((uint32_t)3U << 30U)
-#define	MOD_SEL1_TSIF0_A	((uint32_t)0U << 27U)
-#define	MOD_SEL1_TSIF0_B	((uint32_t)1U << 27U)
-#define	MOD_SEL1_TSIF0_C	((uint32_t)2U << 27U)
-#define	MOD_SEL1_TSIF0_D	((uint32_t)3U << 27U)
-#define	MOD_SEL1_TSIF0_E	((uint32_t)4U << 27U)
-#define	MOD_SEL1_TIMER_TMU_A	((uint32_t)0U << 26U)
-#define	MOD_SEL1_TIMER_TMU_B	((uint32_t)1U << 26U)
-#define	MOD_SEL1_SSP1_1_A	((uint32_t)0U << 24U)
-#define	MOD_SEL1_SSP1_1_B	((uint32_t)1U << 24U)
-#define	MOD_SEL1_SSP1_1_C	((uint32_t)2U << 24U)
-#define	MOD_SEL1_SSP1_1_D	((uint32_t)3U << 24U)
-#define	MOD_SEL1_SSP1_0_A	((uint32_t)0U << 21U)
-#define	MOD_SEL1_SSP1_0_B	((uint32_t)1U << 21U)
-#define	MOD_SEL1_SSP1_0_C	((uint32_t)2U << 21U)
-#define	MOD_SEL1_SSP1_0_D	((uint32_t)3U << 21U)
-#define	MOD_SEL1_SSP1_0_E	((uint32_t)4U << 21U)
-#define	MOD_SEL1_SSI_A		((uint32_t)0U << 20U)
-#define	MOD_SEL1_SSI_B		((uint32_t)1U << 20U)
-#define	MOD_SEL1_SPEED_PULSE_IF_A	((uint32_t)0U << 19U)
-#define	MOD_SEL1_SPEED_PULSE_IF_B	((uint32_t)1U << 19U)
-#define	MOD_SEL1_SIMCARD_A	((uint32_t)0U << 17U)
-#define	MOD_SEL1_SIMCARD_B	((uint32_t)1U << 17U)
-#define	MOD_SEL1_SIMCARD_C	((uint32_t)2U << 17U)
-#define	MOD_SEL1_SIMCARD_D	((uint32_t)3U << 17U)
-#define	MOD_SEL1_SDHI2_A	((uint32_t)0U << 16U)
-#define	MOD_SEL1_SDHI2_B	((uint32_t)1U << 16U)
-#define	MOD_SEL1_SCIF4_A	((uint32_t)0U << 14U)
-#define	MOD_SEL1_SCIF4_B	((uint32_t)1U << 14U)
-#define	MOD_SEL1_SCIF4_C	((uint32_t)2U << 14U)
-#define	MOD_SEL1_SCIF3_A	((uint32_t)0U << 13U)
-#define	MOD_SEL1_SCIF3_B	((uint32_t)1U << 13U)
-#define	MOD_SEL1_SCIF2_A	((uint32_t)0U << 12U)
-#define	MOD_SEL1_SCIF2_B	((uint32_t)1U << 12U)
-#define	MOD_SEL1_SCIF1_A	((uint32_t)0U << 11U)
-#define	MOD_SEL1_SCIF1_B	((uint32_t)1U << 11U)
-#define	MOD_SEL1_SCIF_A		((uint32_t)0U << 10U)
-#define	MOD_SEL1_SCIF_B		((uint32_t)1U << 10U)
-#define	MOD_SEL1_REMOCON_A	((uint32_t)0U << 9U)
-#define	MOD_SEL1_REMOCON_B	((uint32_t)1U << 9U)
-#define	MOD_SEL1_RCAN0_A	((uint32_t)0U << 6U)
-#define	MOD_SEL1_RCAN0_B	((uint32_t)1U << 6U)
-#define	MOD_SEL1_PWM6_A		((uint32_t)0U << 5U)
-#define	MOD_SEL1_PWM6_B		((uint32_t)1U << 5U)
-#define	MOD_SEL1_PWM5_A		((uint32_t)0U << 4U)
-#define	MOD_SEL1_PWM5_B		((uint32_t)1U << 4U)
-#define	MOD_SEL1_PWM4_A		((uint32_t)0U << 3U)
-#define	MOD_SEL1_PWM4_B		((uint32_t)1U << 3U)
-#define	MOD_SEL1_PWM3_A		((uint32_t)0U << 2U)
-#define	MOD_SEL1_PWM3_B		((uint32_t)1U << 2U)
-#define	MOD_SEL1_PWM2_A		((uint32_t)0U << 1U)
-#define	MOD_SEL1_PWM2_B		((uint32_t)1U << 1U)
-#define	MOD_SEL1_PWM1_A		((uint32_t)0U << 0U)
-#define	MOD_SEL1_PWM1_B		((uint32_t)1U << 0U)
-#define	MOD_SEL2_I2C_5_A	((uint32_t)0U << 31U)
-#define	MOD_SEL2_I2C_5_B	((uint32_t)1U << 31U)
-#define	MOD_SEL2_I2C_3_A	((uint32_t)0U << 30U)
-#define	MOD_SEL2_I2C_3_B	((uint32_t)1U << 30U)
-#define	MOD_SEL2_I2C_0_A	((uint32_t)0U << 29U)
-#define	MOD_SEL2_I2C_0_B	((uint32_t)1U << 29U)
-#define	MOD_SEL2_FM_A		((uint32_t)0U << 27U)
-#define	MOD_SEL2_FM_B		((uint32_t)1U << 27U)
-#define	MOD_SEL2_FM_C		((uint32_t)2U << 27U)
-#define	MOD_SEL2_FM_D		((uint32_t)3U << 27U)
-#define	MOD_SEL2_SCIF5_A	((uint32_t)0U << 26U)
-#define	MOD_SEL2_SCIF5_B	((uint32_t)1U << 26U)
-#define	MOD_SEL2_I2C6_A		((uint32_t)0U << 23U)
-#define	MOD_SEL2_I2C6_B		((uint32_t)1U << 23U)
-#define	MOD_SEL2_I2C6_C		((uint32_t)2U << 23U)
-#define	MOD_SEL2_NDF_A		((uint32_t)0U << 22U)
-#define	MOD_SEL2_NDF_B		((uint32_t)1U << 22U)
-#define	MOD_SEL2_SSI2_A		((uint32_t)0U << 21U)
-#define	MOD_SEL2_SSI2_B		((uint32_t)1U << 21U)
-#define	MOD_SEL2_SSI9_A		((uint32_t)0U << 20U)
-#define	MOD_SEL2_SSI9_B		((uint32_t)1U << 20U)
-#define	MOD_SEL2_TIMER_TMU2_A	((uint32_t)0U << 19U)
-#define	MOD_SEL2_TIMER_TMU2_B	((uint32_t)1U << 19U)
-#define	MOD_SEL2_ADG_B_A	((uint32_t)0U << 18U)
-#define	MOD_SEL2_ADG_B_B	((uint32_t)1U << 18U)
-#define	MOD_SEL2_ADG_C_A	((uint32_t)0U << 17U)
-#define	MOD_SEL2_ADG_C_B	((uint32_t)1U << 17U)
-#define	MOD_SEL2_VIN4_A		((uint32_t)0U << 0U)
-#define	MOD_SEL2_VIN4_B		((uint32_t)1U << 0U)
-
-
-/* SCIF3 Registers for Dummy write */
-#define SCIF3_BASE		(0xE6C50000U)
-#define SCIF3_SCFCR		(SCIF3_BASE + 0x0018U)
-#define SCIF3_SCFDR		(SCIF3_BASE + 0x001CU)
-#define SCFCR_DATA		(0x0000U)
-
-/* Realtime module stop control */
-#define	CPG_BASE		(0xE6150000U)
-#define CPG_MSTPSR0		(CPG_BASE + 0x0030U)
-#define CPG_RMSTPCR0		(CPG_BASE + 0x0110U)
-#define RMSTPCR0_RTDMAC		(0x00200000U)
-
-/* RT-DMAC Registers */
-#define RTDMAC_CH		(0U)		/* choose 0 to 15 */
-
-#define RTDMAC_BASE		(0xFFC10000U)
-#define RTDMAC_RDMOR		(RTDMAC_BASE + 0x0060U)
-#define RTDMAC_RDMCHCLR		(RTDMAC_BASE + 0x0080U)
-#define RTDMAC_RDMSAR(x)	(RTDMAC_BASE + 0x8000U + (0x80U * (x)))
-#define RTDMAC_RDMDAR(x)	(RTDMAC_BASE + 0x8004U + (0x80U * (x)))
-#define RTDMAC_RDMTCR(x)	(RTDMAC_BASE + 0x8008U + (0x80U * (x)))
-#define RTDMAC_RDMCHCR(x)	(RTDMAC_BASE + 0x800CU + (0x80U * (x)))
-#define RTDMAC_RDMCHCRB(x)	(RTDMAC_BASE + 0x801CU + (0x80U * (x)))
-#define RTDMAC_RDMDPBASE(x)	(RTDMAC_BASE + 0x8050U + (0x80U * (x)))
-#define RTDMAC_DESC_BASE	(RTDMAC_BASE + 0xA000U)
-#define RTDMAC_DESC_RDMSAR	(RTDMAC_DESC_BASE + 0x0000U)
-#define RTDMAC_DESC_RDMDAR	(RTDMAC_DESC_BASE + 0x0004U)
-#define RTDMAC_DESC_RDMTCR	(RTDMAC_DESC_BASE + 0x0008U)
-
-#define RDMOR_DME		(0x0001U)	/* DMA Master Enable */
-#define RDMCHCR_DPM_INFINITE	(0x30000000U)	/* Infinite repeat mode */
-#define RDMCHCR_RPT_TCR		(0x02000000U)	/* enable to update TCR */
-#define RDMCHCR_TS_2		(0x00000008U)	/* Word(2byte) units transfer */
-#define RDMCHCR_RS_AUTO		(0x00000400U)	/* Auto request */
-#define RDMCHCR_DE		(0x00000001U)	/* DMA Enable */
-#define RDMCHCRB_DRST		(0x00008000U)	/* Descriptor reset */
-#define RDMCHCRB_SLM_256	(0x00000080U)	/* once in 256 clock cycle */
-#define RDMDPBASE_SEL_EXT	(0x00000001U)	/* External memory use */
-
-
-static void pfc_reg_write(uint32_t addr, uint32_t data);
-
-static void pfc_reg_write(uint32_t addr, uint32_t data)
-{
-	uint32_t prr;
-
-	prr = mmio_read_32(RCAR_PRR);
-	prr &= (RCAR_PRODUCT_MASK | RCAR_CUT_MASK);
-
-	mmio_write_32(PFC_PMMR, ~data);
-	if (prr == (RCAR_PRODUCT_M3_CUT10)) {
-		mmio_write_16(SCIF3_SCFCR, SCFCR_DATA);	/* Dummy write */
-	}
-	mmio_write_32((uintptr_t)addr, data);
-	if (prr == (RCAR_PRODUCT_M3_CUT10)) {
-		mmio_write_16(SCIF3_SCFCR, SCFCR_DATA);	/* Dummy write */
-	}
-}
-
-
-void pfc_init_d3(void)
-{
-	/* initialize module select */
-	pfc_reg_write(PFC_MOD_SEL0, 0x00000000U);
-	pfc_reg_write(PFC_MOD_SEL1, 0x00000000U);
-
-	/* initialize peripheral function select */
-	pfc_reg_write(PFC_IPSR0,  0x00000001U);
-	pfc_reg_write(PFC_IPSR1,  0x00000000U);
-	pfc_reg_write(PFC_IPSR2,  0x00000000U);
-	pfc_reg_write(PFC_IPSR3,  0x00000000U);
-	pfc_reg_write(PFC_IPSR4,  0x00002000U);
-	pfc_reg_write(PFC_IPSR5,  0x00000000U);
-	pfc_reg_write(PFC_IPSR6,  0x00000000U);
-	pfc_reg_write(PFC_IPSR7,  0x00000000U);
-	pfc_reg_write(PFC_IPSR8,  0x11003301U);
-	pfc_reg_write(PFC_IPSR9,  0x11111111U);
-	pfc_reg_write(PFC_IPSR10, 0x00020000U);
-	pfc_reg_write(PFC_IPSR11, 0x40001110U);
-	pfc_reg_write(PFC_IPSR12, 0x00000000U);
-	pfc_reg_write(PFC_IPSR13, 0x00000000U);
-
-	/* initialize GPIO/perihperal function select */
-	pfc_reg_write(PFC_GPSR0, 0x0000001FU);
-	pfc_reg_write(PFC_GPSR1, 0x3FFFFFFFU);
-	pfc_reg_write(PFC_GPSR2, 0xFFFFFFFFU);
-	pfc_reg_write(PFC_GPSR3, 0x000003FFU);
-	pfc_reg_write(PFC_GPSR4, 0xFC7F0F7EU);
-	pfc_reg_write(PFC_GPSR5, 0x001BFFFBU);
-	pfc_reg_write(PFC_GPSR6, 0x00003FFFU);
-
-	/* initialize POC control register */
-	pfc_reg_write(PFC_POCCTRL0,   0xC00FFFFFU);
-	pfc_reg_write(PFC_POCCTRL1,   0XFFFFFFFEU);
-	pfc_reg_write(PFC_TDSELCTRL0, 0x00000000U);
-
-	/* initialize LSI pin pull-up/down control */
-	pfc_reg_write(PFC_PUD0, 0x0047C1A2U);
-	pfc_reg_write(PFC_PUD1, 0x4E13ABFFU);
-	pfc_reg_write(PFC_PUD2, 0xFFFFFFFFU);
-	pfc_reg_write(PFC_PUD3, 0xFF0FFFFFU);
-	pfc_reg_write(PFC_PUD4, 0xE0000000U);
-	pfc_reg_write(PFC_PUD5, 0x60000000U);
-
-	/* initialize LSI pin pull-enable register */
-	pfc_reg_write(PFC_PUEN0, 0x00000000U);
-	pfc_reg_write(PFC_PUEN1, 0x00000000U);
-	pfc_reg_write(PFC_PUEN2, 0x00000000U);
-	pfc_reg_write(PFC_PUEN3, 0x000F008CU);
-	pfc_reg_write(PFC_PUEN4, 0x00000000U);
-	pfc_reg_write(PFC_PUEN5, 0x00000000U);
-
-	/* initialize positive/negative logic select */
-	mmio_write_32(GPIO_POSNEG0, 0x00000000U);
-	mmio_write_32(GPIO_POSNEG1, 0x00000000U);
-	mmio_write_32(GPIO_POSNEG2, 0x00000000U);
-	mmio_write_32(GPIO_POSNEG3, 0x00000000U);
-	mmio_write_32(GPIO_POSNEG4, 0x00000000U);
-	mmio_write_32(GPIO_POSNEG5, 0x00000000U);
-	mmio_write_32(GPIO_POSNEG6, 0x00000000U);
-
-	/* initialize general IO/interrupt switching */
-	mmio_write_32(GPIO_IOINTSEL0, 0x00000000U);
-	mmio_write_32(GPIO_IOINTSEL1, 0x00000000U);
-	mmio_write_32(GPIO_IOINTSEL2, 0x00000000U);
-	mmio_write_32(GPIO_IOINTSEL3, 0x00000000U);
-	mmio_write_32(GPIO_IOINTSEL4, 0x00000000U);
-	mmio_write_32(GPIO_IOINTSEL5, 0x00000000U);
-	mmio_write_32(GPIO_IOINTSEL6, 0x00000000U);
-
-	/* initialize general output register */
-	mmio_write_32(GPIO_OUTDT0, 0x00000000U);
-	mmio_write_32(GPIO_OUTDT1, 0x00000000U);
-	mmio_write_32(GPIO_OUTDT2, 0x00000400U);
-	mmio_write_32(GPIO_OUTDT3, 0x00000000U);
-	mmio_write_32(GPIO_OUTDT4, 0x00000000U);
-	mmio_write_32(GPIO_OUTDT5, 0x00000006U);
-	mmio_write_32(GPIO_OUTDT6, 0x00003880U);
-
-	/* initialize general input/output switching */
-	mmio_write_32(GPIO_INOUTSEL0, 0x00000000U);
-	mmio_write_32(GPIO_INOUTSEL1, 0x00000000U);
-	mmio_write_32(GPIO_INOUTSEL2, 0x00000000U);
-	mmio_write_32(GPIO_INOUTSEL3, 0x00000000U);
-	mmio_write_32(GPIO_INOUTSEL4, 0x00802000U);
-	mmio_write_32(GPIO_INOUTSEL5, 0x00000000U);
-	mmio_write_32(GPIO_INOUTSEL6, 0x00000000U);
-}
diff --git a/drivers/staging/renesas/rcar/pfc/E3/pfc_init_e3.c b/drivers/staging/renesas/rcar/pfc/E3/pfc_init_e3.c
deleted file mode 100644
index 1fc13de..0000000
--- a/drivers/staging/renesas/rcar/pfc/E3/pfc_init_e3.c
+++ /dev/null
@@ -1,823 +0,0 @@
-/*
- * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <stdint.h>		/* for uint32_t */
-
-#include <lib/mmio.h>
-
-#include "pfc_init_e3.h"
-#include "rcar_def.h"
-
-/* GPIO base address */
-#define	GPIO_BASE		(0xE6050000U)
-
-/* GPIO registers */
-#define	GPIO_IOINTSEL0		(GPIO_BASE + 0x0000U)
-#define	GPIO_INOUTSEL0		(GPIO_BASE + 0x0004U)
-#define	GPIO_OUTDT0		(GPIO_BASE + 0x0008U)
-#define	GPIO_INDT0		(GPIO_BASE + 0x000CU)
-#define	GPIO_INTDT0		(GPIO_BASE + 0x0010U)
-#define	GPIO_INTCLR0		(GPIO_BASE + 0x0014U)
-#define	GPIO_INTMSK0		(GPIO_BASE + 0x0018U)
-#define	GPIO_MSKCLR0		(GPIO_BASE + 0x001CU)
-#define	GPIO_POSNEG0		(GPIO_BASE + 0x0020U)
-#define	GPIO_EDGLEVEL0		(GPIO_BASE + 0x0024U)
-#define	GPIO_FILONOFF0		(GPIO_BASE + 0x0028U)
-#define	GPIO_INTMSKS0		(GPIO_BASE + 0x0038U)
-#define	GPIO_MSKCLRS0		(GPIO_BASE + 0x003CU)
-#define	GPIO_OUTDTSEL0		(GPIO_BASE + 0x0040U)
-#define	GPIO_OUTDTH0		(GPIO_BASE + 0x0044U)
-#define	GPIO_OUTDTL0		(GPIO_BASE + 0x0048U)
-#define	GPIO_BOTHEDGE0		(GPIO_BASE + 0x004CU)
-#define	GPIO_IOINTSEL1		(GPIO_BASE + 0x1000U)
-#define	GPIO_INOUTSEL1		(GPIO_BASE + 0x1004U)
-#define	GPIO_OUTDT1		(GPIO_BASE + 0x1008U)
-#define	GPIO_INDT1		(GPIO_BASE + 0x100CU)
-#define	GPIO_INTDT1		(GPIO_BASE + 0x1010U)
-#define	GPIO_INTCLR1		(GPIO_BASE + 0x1014U)
-#define	GPIO_INTMSK1		(GPIO_BASE + 0x1018U)
-#define	GPIO_MSKCLR1		(GPIO_BASE + 0x101CU)
-#define	GPIO_POSNEG1		(GPIO_BASE + 0x1020U)
-#define	GPIO_EDGLEVEL1		(GPIO_BASE + 0x1024U)
-#define	GPIO_FILONOFF1		(GPIO_BASE + 0x1028U)
-#define	GPIO_INTMSKS1		(GPIO_BASE + 0x1038U)
-#define	GPIO_MSKCLRS1		(GPIO_BASE + 0x103CU)
-#define	GPIO_OUTDTSEL1		(GPIO_BASE + 0x1040U)
-#define	GPIO_OUTDTH1		(GPIO_BASE + 0x1044U)
-#define	GPIO_OUTDTL1		(GPIO_BASE + 0x1048U)
-#define	GPIO_BOTHEDGE1		(GPIO_BASE + 0x104CU)
-#define	GPIO_IOINTSEL2		(GPIO_BASE + 0x2000U)
-#define	GPIO_INOUTSEL2		(GPIO_BASE + 0x2004U)
-#define	GPIO_OUTDT2		(GPIO_BASE + 0x2008U)
-#define	GPIO_INDT2		(GPIO_BASE + 0x200CU)
-#define	GPIO_INTDT2		(GPIO_BASE + 0x2010U)
-#define	GPIO_INTCLR2		(GPIO_BASE + 0x2014U)
-#define	GPIO_INTMSK2		(GPIO_BASE + 0x2018U)
-#define	GPIO_MSKCLR2		(GPIO_BASE + 0x201CU)
-#define	GPIO_POSNEG2		(GPIO_BASE + 0x2020U)
-#define	GPIO_EDGLEVEL2		(GPIO_BASE + 0x2024U)
-#define	GPIO_FILONOFF2		(GPIO_BASE + 0x2028U)
-#define	GPIO_INTMSKS2		(GPIO_BASE + 0x2038U)
-#define	GPIO_MSKCLRS2		(GPIO_BASE + 0x203CU)
-#define	GPIO_OUTDTSEL2		(GPIO_BASE + 0x2040U)
-#define	GPIO_OUTDTH2		(GPIO_BASE + 0x2044U)
-#define	GPIO_OUTDTL2		(GPIO_BASE + 0x2048U)
-#define	GPIO_BOTHEDGE2		(GPIO_BASE + 0x204CU)
-#define	GPIO_IOINTSEL3		(GPIO_BASE + 0x3000U)
-#define	GPIO_INOUTSEL3		(GPIO_BASE + 0x3004U)
-#define	GPIO_OUTDT3		(GPIO_BASE + 0x3008U)
-#define	GPIO_INDT3		(GPIO_BASE + 0x300CU)
-#define	GPIO_INTDT3		(GPIO_BASE + 0x3010U)
-#define	GPIO_INTCLR3		(GPIO_BASE + 0x3014U)
-#define	GPIO_INTMSK3		(GPIO_BASE + 0x3018U)
-#define	GPIO_MSKCLR3		(GPIO_BASE + 0x301CU)
-#define	GPIO_POSNEG3		(GPIO_BASE + 0x3020U)
-#define	GPIO_EDGLEVEL3		(GPIO_BASE + 0x3024U)
-#define	GPIO_FILONOFF3		(GPIO_BASE + 0x3028U)
-#define	GPIO_INTMSKS3		(GPIO_BASE + 0x3038U)
-#define	GPIO_MSKCLRS3		(GPIO_BASE + 0x303CU)
-#define	GPIO_OUTDTSEL3		(GPIO_BASE + 0x3040U)
-#define	GPIO_OUTDTH3		(GPIO_BASE + 0x3044U)
-#define	GPIO_OUTDTL3		(GPIO_BASE + 0x3048U)
-#define	GPIO_BOTHEDGE3		(GPIO_BASE + 0x304CU)
-#define	GPIO_IOINTSEL4		(GPIO_BASE + 0x4000U)
-#define	GPIO_INOUTSEL4		(GPIO_BASE + 0x4004U)
-#define	GPIO_OUTDT4		(GPIO_BASE + 0x4008U)
-#define	GPIO_INDT4		(GPIO_BASE + 0x400CU)
-#define	GPIO_INTDT4		(GPIO_BASE + 0x4010U)
-#define	GPIO_INTCLR4		(GPIO_BASE + 0x4014U)
-#define	GPIO_INTMSK4		(GPIO_BASE + 0x4018U)
-#define	GPIO_MSKCLR4		(GPIO_BASE + 0x401CU)
-#define	GPIO_POSNEG4		(GPIO_BASE + 0x4020U)
-#define	GPIO_EDGLEVEL4		(GPIO_BASE + 0x4024U)
-#define	GPIO_FILONOFF4		(GPIO_BASE + 0x4028U)
-#define	GPIO_INTMSKS4		(GPIO_BASE + 0x4038U)
-#define	GPIO_MSKCLRS4		(GPIO_BASE + 0x403CU)
-#define	GPIO_OUTDTSEL4		(GPIO_BASE + 0x4040U)
-#define	GPIO_OUTDTH4		(GPIO_BASE + 0x4044U)
-#define	GPIO_OUTDTL4		(GPIO_BASE + 0x4048U)
-#define	GPIO_BOTHEDGE4		(GPIO_BASE + 0x404CU)
-#define	GPIO_IOINTSEL5		(GPIO_BASE + 0x5000U)
-#define	GPIO_INOUTSEL5		(GPIO_BASE + 0x5004U)
-#define	GPIO_OUTDT5		(GPIO_BASE + 0x5008U)
-#define	GPIO_INDT5		(GPIO_BASE + 0x500CU)
-#define	GPIO_INTDT5		(GPIO_BASE + 0x5010U)
-#define	GPIO_INTCLR5		(GPIO_BASE + 0x5014U)
-#define	GPIO_INTMSK5		(GPIO_BASE + 0x5018U)
-#define	GPIO_MSKCLR5		(GPIO_BASE + 0x501CU)
-#define	GPIO_POSNEG5		(GPIO_BASE + 0x5020U)
-#define	GPIO_EDGLEVEL5		(GPIO_BASE + 0x5024U)
-#define	GPIO_FILONOFF5		(GPIO_BASE + 0x5028U)
-#define	GPIO_INTMSKS5		(GPIO_BASE + 0x5038U)
-#define	GPIO_MSKCLRS5		(GPIO_BASE + 0x503CU)
-#define	GPIO_OUTDTSEL5		(GPIO_BASE + 0x5040U)
-#define	GPIO_OUTDTH5		(GPIO_BASE + 0x5044U)
-#define	GPIO_OUTDTL5		(GPIO_BASE + 0x5048U)
-#define	GPIO_BOTHEDGE5		(GPIO_BASE + 0x504CU)
-#define	GPIO_IOINTSEL6		(GPIO_BASE + 0x5400U)
-#define	GPIO_INOUTSEL6		(GPIO_BASE + 0x5404U)
-#define	GPIO_OUTDT6		(GPIO_BASE + 0x5408U)
-#define	GPIO_INDT6		(GPIO_BASE + 0x540CU)
-#define	GPIO_INTDT6		(GPIO_BASE + 0x5410U)
-#define	GPIO_INTCLR6		(GPIO_BASE + 0x5414U)
-#define	GPIO_INTMSK6		(GPIO_BASE + 0x5418U)
-#define	GPIO_MSKCLR6		(GPIO_BASE + 0x541CU)
-#define	GPIO_POSNEG6		(GPIO_BASE + 0x5420U)
-#define	GPIO_EDGLEVEL6		(GPIO_BASE + 0x5424U)
-#define	GPIO_FILONOFF6		(GPIO_BASE + 0x5428U)
-#define	GPIO_INTMSKS6		(GPIO_BASE + 0x5438U)
-#define	GPIO_MSKCLRS6		(GPIO_BASE + 0x543CU)
-#define	GPIO_OUTDTSEL6		(GPIO_BASE + 0x5440U)
-#define	GPIO_OUTDTH6		(GPIO_BASE + 0x5444U)
-#define	GPIO_OUTDTL6		(GPIO_BASE + 0x5448U)
-#define	GPIO_BOTHEDGE6		(GPIO_BASE + 0x544CU)
-
-/* Pin functon base address */
-#define	PFC_BASE		(0xE6060000U)
-
-/* Pin functon registers */
-#define	PFC_PMMR		(PFC_BASE + 0x0000U)
-#define PFC_GPSR0		(PFC_BASE + 0x0100U)
-#define PFC_GPSR1		(PFC_BASE + 0x0104U)
-#define PFC_GPSR2		(PFC_BASE + 0x0108U)
-#define PFC_GPSR3		(PFC_BASE + 0x010CU)
-#define PFC_GPSR4		(PFC_BASE + 0x0110U)
-#define	PFC_GPSR5		(PFC_BASE + 0x0114U)
-#define	PFC_GPSR6		(PFC_BASE + 0x0118U)
-#define	PFC_IPSR0		(PFC_BASE + 0x0200U)
-#define	PFC_IPSR1		(PFC_BASE + 0x0204U)
-#define	PFC_IPSR2		(PFC_BASE + 0x0208U)
-#define	PFC_IPSR3		(PFC_BASE + 0x020CU)
-#define	PFC_IPSR4		(PFC_BASE + 0x0210U)
-#define	PFC_IPSR5		(PFC_BASE + 0x0214U)
-#define	PFC_IPSR6		(PFC_BASE + 0x0218U)
-#define	PFC_IPSR7		(PFC_BASE + 0x021CU)
-#define	PFC_IPSR8		(PFC_BASE + 0x0220U)
-#define	PFC_IPSR9		(PFC_BASE + 0x0224U)
-#define	PFC_IPSR10		(PFC_BASE + 0x0228U)
-#define	PFC_IPSR11		(PFC_BASE + 0x022CU)
-#define	PFC_IPSR12		(PFC_BASE + 0x0230U)
-#define	PFC_IPSR13		(PFC_BASE + 0x0234U)
-#define	PFC_IPSR14		(PFC_BASE + 0x0238U)
-#define	PFC_IPSR15		(PFC_BASE + 0x023CU)
-#define PFC_IOCTRL30		(PFC_BASE + 0x0380U)
-#define PFC_IOCTRL32		(PFC_BASE + 0x0388U)
-#define PFC_IOCTRL40		(PFC_BASE + 0x03C0U)
-#define	PFC_PUEN0		(PFC_BASE + 0x0400U)
-#define	PFC_PUEN1		(PFC_BASE + 0x0404U)
-#define	PFC_PUEN2		(PFC_BASE + 0x0408U)
-#define	PFC_PUEN3		(PFC_BASE + 0x040CU)
-#define	PFC_PUEN4		(PFC_BASE + 0x0410U)
-#define	PFC_PUEN5		(PFC_BASE + 0x0414U)
-#define	PFC_PUD0		(PFC_BASE + 0x0440U)
-#define	PFC_PUD1		(PFC_BASE + 0x0444U)
-#define	PFC_PUD2		(PFC_BASE + 0x0448U)
-#define	PFC_PUD3		(PFC_BASE + 0x044CU)
-#define	PFC_PUD4		(PFC_BASE + 0x0450U)
-#define	PFC_PUD5		(PFC_BASE + 0x0454U)
-#define	PFC_MOD_SEL0		(PFC_BASE + 0x0500U)
-#define	PFC_MOD_SEL1		(PFC_BASE + 0x0504U)
-
-#define GPSR0_SDA4		((uint32_t)1U << 17U)
-#define GPSR0_SCL4		((uint32_t)1U << 16U)
-#define	GPSR0_D15		((uint32_t)1U << 15U)
-#define	GPSR0_D14		((uint32_t)1U << 14U)
-#define	GPSR0_D13		((uint32_t)1U << 13U)
-#define	GPSR0_D12		((uint32_t)1U << 12U)
-#define	GPSR0_D11		((uint32_t)1U << 11U)
-#define	GPSR0_D10		((uint32_t)1U << 10U)
-#define	GPSR0_D9		((uint32_t)1U << 9U)
-#define	GPSR0_D8		((uint32_t)1U << 8U)
-#define	GPSR0_D7		((uint32_t)1U << 7U)
-#define	GPSR0_D6		((uint32_t)1U << 6U)
-#define	GPSR0_D5		((uint32_t)1U << 5U)
-#define	GPSR0_D4		((uint32_t)1U << 4U)
-#define	GPSR0_D3		((uint32_t)1U << 3U)
-#define	GPSR0_D2		((uint32_t)1U << 2U)
-#define	GPSR0_D1		((uint32_t)1U << 1U)
-#define	GPSR0_D0		((uint32_t)1U << 0U)
-#define	GPSR1_WE0		((uint32_t)1U << 22U)
-#define	GPSR1_CS0		((uint32_t)1U << 21U)
-#define	GPSR1_CLKOUT		((uint32_t)1U << 20U)
-#define	GPSR1_A19		((uint32_t)1U << 19U)
-#define	GPSR1_A18		((uint32_t)1U << 18U)
-#define	GPSR1_A17		((uint32_t)1U << 17U)
-#define	GPSR1_A16		((uint32_t)1U << 16U)
-#define	GPSR1_A15		((uint32_t)1U << 15U)
-#define	GPSR1_A14		((uint32_t)1U << 14U)
-#define	GPSR1_A13		((uint32_t)1U << 13U)
-#define	GPSR1_A12		((uint32_t)1U << 12U)
-#define	GPSR1_A11		((uint32_t)1U << 11U)
-#define	GPSR1_A10		((uint32_t)1U << 10U)
-#define	GPSR1_A9		((uint32_t)1U << 9U)
-#define	GPSR1_A8		((uint32_t)1U << 8U)
-#define	GPSR1_A7		((uint32_t)1U << 7U)
-#define	GPSR1_A6		((uint32_t)1U << 6U)
-#define	GPSR1_A5		((uint32_t)1U << 5U)
-#define	GPSR1_A4		((uint32_t)1U << 4U)
-#define	GPSR1_A3		((uint32_t)1U << 3U)
-#define	GPSR1_A2		((uint32_t)1U << 2U)
-#define	GPSR1_A1		((uint32_t)1U << 1U)
-#define	GPSR1_A0		((uint32_t)1U << 0U)
-#define	GPSR2_BIT27_REVERCED 	((uint32_t)1U << 27U)
-#define	GPSR2_BIT26_REVERCED 	((uint32_t)1U << 26U)
-#define	GPSR2_EX_WAIT0		((uint32_t)1U << 25U)
-#define	GPSR2_RD_WR		((uint32_t)1U << 24U)
-#define	GPSR2_RD		((uint32_t)1U << 23U)
-#define	GPSR2_BS		((uint32_t)1U << 22U)
-#define	GPSR2_AVB_PHY_INT	((uint32_t)1U << 21U)
-#define GPSR2_AVB_TXCREFCLK	((uint32_t)1U << 20U)
-#define	GPSR2_AVB_RD3		((uint32_t)1U << 19U)
-#define	GPSR2_AVB_RD2		((uint32_t)1U << 18U)
-#define	GPSR2_AVB_RD1		((uint32_t)1U << 17U)
-#define	GPSR2_AVB_RD0		((uint32_t)1U << 16U)
-#define	GPSR2_AVB_RXC		((uint32_t)1U << 15U)
-#define	GPSR2_AVB_RX_CTL	((uint32_t)1U << 14U)
-#define GPSR2_RPC_RESET		((uint32_t)1U << 13U)
-#define GPSR2_RPC_RPC_INT	((uint32_t)1U << 12U)
-#define GPSR2_QSPI1_SSL		((uint32_t)1U << 11U)
-#define GPSR2_QSPI1_IO3		((uint32_t)1U << 10U)
-#define GPSR2_QSPI1_IO2		((uint32_t)1U << 9U)
-#define GPSR2_QSPI1_MISO_IO1	((uint32_t)1U << 8U)
-#define GPSR2_QSPI1_MOSI_IO0	((uint32_t)1U << 7U)
-#define GPSR2_QSPI1_SPCLK	((uint32_t)1U << 6U)
-#define GPSR2_QSPI0_SSL		((uint32_t)1U << 5U)
-#define GPSR2_QSPI0_IO3		((uint32_t)1U << 4U)
-#define GPSR2_QSPI0_IO2		((uint32_t)1U << 3U)
-#define GPSR2_QSPI0_MISO_IO1	((uint32_t)1U << 2U)
-#define GPSR2_QSPI0_MOSI_IO0	((uint32_t)1U << 1U)
-#define GPSR2_QSPI0_SPCLK	((uint32_t)1U << 0U)
-#define	GPSR3_SD1_WP		((uint32_t)1U << 15U)
-#define	GPSR3_SD1_CD		((uint32_t)1U << 14U)
-#define	GPSR3_SD0_WP		((uint32_t)1U << 13U)
-#define	GPSR3_SD0_CD		((uint32_t)1U << 12U)
-#define	GPSR3_SD1_DAT3		((uint32_t)1U << 11U)
-#define	GPSR3_SD1_DAT2		((uint32_t)1U << 10U)
-#define	GPSR3_SD1_DAT1		((uint32_t)1U << 9U)
-#define	GPSR3_SD1_DAT0		((uint32_t)1U << 8U)
-#define	GPSR3_SD1_CMD		((uint32_t)1U << 7U)
-#define	GPSR3_SD1_CLK		((uint32_t)1U << 6U)
-#define	GPSR3_SD0_DAT3		((uint32_t)1U << 5U)
-#define	GPSR3_SD0_DAT2		((uint32_t)1U << 4U)
-#define	GPSR3_SD0_DAT1		((uint32_t)1U << 3U)
-#define	GPSR3_SD0_DAT0		((uint32_t)1U << 2U)
-#define	GPSR3_SD0_CMD		((uint32_t)1U << 1U)
-#define	GPSR3_SD0_CLK		((uint32_t)1U << 0U)
-#define	GPSR4_SD3_DS		((uint32_t)1U << 10U)
-#define	GPSR4_SD3_DAT7		((uint32_t)1U << 9U)
-#define	GPSR4_SD3_DAT6		((uint32_t)1U << 8U)
-#define	GPSR4_SD3_DAT5		((uint32_t)1U << 7U)
-#define	GPSR4_SD3_DAT4		((uint32_t)1U << 6U)
-#define	GPSR4_SD3_DAT3		((uint32_t)1U << 5U)
-#define	GPSR4_SD3_DAT2		((uint32_t)1U << 4U)
-#define	GPSR4_SD3_DAT1		((uint32_t)1U << 3U)
-#define	GPSR4_SD3_DAT0		((uint32_t)1U << 2U)
-#define	GPSR4_SD3_CMD		((uint32_t)1U << 1U)
-#define	GPSR4_SD3_CLK		((uint32_t)1U << 0U)
-#define	GPSR5_MLB_DAT		((uint32_t)1U << 19U)
-#define	GPSR5_MLB_SIG		((uint32_t)1U << 18U)
-#define	GPSR5_MLB_CLK		((uint32_t)1U << 17U)
-#define	GPSR5_SSI_SDATA9	((uint32_t)1U << 16U)
-#define	GPSR5_MSIOF0_SS2	((uint32_t)1U << 15U)
-#define	GPSR5_MSIOF0_SS1	((uint32_t)1U << 14U)
-#define	GPSR5_MSIOF0_SYNC	((uint32_t)1U << 13U)
-#define	GPSR5_MSIOF0_TXD	((uint32_t)1U << 12U)
-#define	GPSR5_MSIOF0_RXD	((uint32_t)1U << 11U)
-#define	GPSR5_MSIOF0_SCK	((uint32_t)1U << 10U)
-#define	GPSR5_RX2_A		((uint32_t)1U << 9U)
-#define	GPSR5_TX2_A		((uint32_t)1U << 8U)
-#define	GPSR5_SCK2_A		((uint32_t)1U << 7U)
-#define	GPSR5_TX1		((uint32_t)1U << 6U)
-#define	GPSR5_RX1		((uint32_t)1U << 5U)
-#define	GPSR5_RTS0_TANS_A	((uint32_t)1U << 4U)
-#define	GPSR5_CTS0_A		((uint32_t)1U << 3U)
-#define	GPSR5_TX0_A		((uint32_t)1U << 2U)
-#define	GPSR5_RX0_A		((uint32_t)1U << 1U)
-#define	GPSR5_SCK0_A		((uint32_t)1U << 0U)
-#define	GPSR6_USB30_PWEN	((uint32_t)1U << 17U)
-#define	GPSR6_SSI_SDATA6	((uint32_t)1U << 16U)
-#define	GPSR6_SSI_WS6		((uint32_t)1U << 15U)
-#define	GPSR6_SSI_SCK6		((uint32_t)1U << 14U)
-#define	GPSR6_SSI_SDATA5	((uint32_t)1U << 13U)
-#define	GPSR6_SSI_WS5		((uint32_t)1U << 12U)
-#define	GPSR6_SSI_SCK5		((uint32_t)1U << 11U)
-#define	GPSR6_SSI_SDATA4	((uint32_t)1U << 10U)
-#define	GPSR6_USB30_OVC		((uint32_t)1U << 9U)
-#define	GPSR6_AUDIO_CLKA	((uint32_t)1U << 8U)
-#define	GPSR6_SSI_SDATA3	((uint32_t)1U << 7U)
-#define	GPSR6_SSI_WS349		((uint32_t)1U << 6U)
-#define	GPSR6_SSI_SCK349	((uint32_t)1U << 5U)
-#define	GPSR6_SSI_SDATA2	((uint32_t)1U << 4U)
-#define	GPSR6_SSI_SDATA1	((uint32_t)1U << 3U)
-#define	GPSR6_SSI_SDATA0	((uint32_t)1U << 2U)
-#define	GPSR6_SSI_WS01239	((uint32_t)1U << 1U)
-#define	GPSR6_SSI_SCK01239	((uint32_t)1U << 0U)
-
-#define	IPSR_28_FUNC(x)		((uint32_t)(x) << 28U)
-#define	IPSR_24_FUNC(x)		((uint32_t)(x) << 24U)
-#define	IPSR_20_FUNC(x)		((uint32_t)(x) << 20U)
-#define	IPSR_16_FUNC(x)		((uint32_t)(x) << 16U)
-#define	IPSR_12_FUNC(x)		((uint32_t)(x) << 12U)
-#define	IPSR_8_FUNC(x)		((uint32_t)(x) << 8U)
-#define	IPSR_4_FUNC(x)		((uint32_t)(x) << 4U)
-#define	IPSR_0_FUNC(x)		((uint32_t)(x) << 0U)
-
-#define IOCTRL30_MASK		(0x0007F000U)
-#define	POC_SD3_DS_33V		((uint32_t)1U << 29U)
-#define	POC_SD3_DAT7_33V	((uint32_t)1U << 28U)
-#define	POC_SD3_DAT6_33V	((uint32_t)1U << 27U)
-#define	POC_SD3_DAT5_33V	((uint32_t)1U << 26U)
-#define	POC_SD3_DAT4_33V	((uint32_t)1U << 25U)
-#define	POC_SD3_DAT3_33V	((uint32_t)1U << 24U)
-#define	POC_SD3_DAT2_33V	((uint32_t)1U << 23U)
-#define	POC_SD3_DAT1_33V	((uint32_t)1U << 22U)
-#define	POC_SD3_DAT0_33V	((uint32_t)1U << 21U)
-#define	POC_SD3_CMD_33V		((uint32_t)1U << 20U)
-#define	POC_SD3_CLK_33V		((uint32_t)1U << 19U)
-#define	POC_SD1_DAT3_33V	((uint32_t)1U << 11U)
-#define	POC_SD1_DAT2_33V	((uint32_t)1U << 10U)
-#define	POC_SD1_DAT1_33V	((uint32_t)1U << 9U)
-#define	POC_SD1_DAT0_33V	((uint32_t)1U << 8U)
-#define	POC_SD1_CMD_33V		((uint32_t)1U << 7U)
-#define	POC_SD1_CLK_33V		((uint32_t)1U << 6U)
-#define	POC_SD0_DAT3_33V	((uint32_t)1U << 5U)
-#define	POC_SD0_DAT2_33V	((uint32_t)1U << 4U)
-#define	POC_SD0_DAT1_33V	((uint32_t)1U << 3U)
-#define	POC_SD0_DAT0_33V	((uint32_t)1U << 2U)
-#define	POC_SD0_CMD_33V		((uint32_t)1U << 1U)
-#define	POC_SD0_CLK_33V		((uint32_t)1U << 0U)
-
-#define IOCTRL32_MASK		(0xFFFFFFFEU)
-#define POC2_VREF_33V		((uint32_t)1U << 0U)
-
-#define	MOD_SEL0_ADGB_A		((uint32_t)0U << 29U)
-#define	MOD_SEL0_ADGB_B		((uint32_t)1U << 29U)
-#define	MOD_SEL0_ADGB_C		((uint32_t)2U << 29U)
-#define	MOD_SEL0_DRIF0_A	((uint32_t)0U << 28U)
-#define	MOD_SEL0_DRIF0_B	((uint32_t)1U << 28U)
-#define	MOD_SEL0_FM_A		((uint32_t)0U << 26U)
-#define	MOD_SEL0_FM_B		((uint32_t)1U << 26U)
-#define	MOD_SEL0_FM_C		((uint32_t)2U << 26U)
-#define	MOD_SEL0_FSO_A		((uint32_t)0U << 25U)
-#define	MOD_SEL0_FSO_B		((uint32_t)1U << 25U)
-#define	MOD_SEL0_HSCIF0_A	((uint32_t)0U << 24U)
-#define	MOD_SEL0_HSCIF0_B	((uint32_t)1U << 24U)
-#define	MOD_SEL0_HSCIF1_A	((uint32_t)0U << 23U)
-#define	MOD_SEL0_HSCIF1_B	((uint32_t)1U << 23U)
-#define	MOD_SEL0_HSCIF2_A	((uint32_t)0U << 22U)
-#define	MOD_SEL0_HSCIF2_B	((uint32_t)1U << 22U)
-#define	MOD_SEL0_I2C1_A		((uint32_t)0U << 20U)
-#define	MOD_SEL0_I2C1_B		((uint32_t)1U << 20U)
-#define	MOD_SEL0_I2C1_C		((uint32_t)2U << 20U)
-#define	MOD_SEL0_I2C1_D		((uint32_t)3U << 20U)
-#define	MOD_SEL0_I2C2_A		((uint32_t)0U << 17U)
-#define	MOD_SEL0_I2C2_B		((uint32_t)1U << 17U)
-#define	MOD_SEL0_I2C2_C		((uint32_t)2U << 17U)
-#define	MOD_SEL0_I2C2_D		((uint32_t)3U << 17U)
-#define	MOD_SEL0_I2C2_E		((uint32_t)4U << 17U)
-#define	MOD_SEL0_NDFC_A		((uint32_t)0U << 16U)
-#define	MOD_SEL0_NDFC_B		((uint32_t)1U << 16U)
-#define	MOD_SEL0_PWM0_A		((uint32_t)0U << 15U)
-#define	MOD_SEL0_PWM0_B		((uint32_t)1U << 15U)
-#define	MOD_SEL0_PWM1_A		((uint32_t)0U << 14U)
-#define	MOD_SEL0_PWM1_B		((uint32_t)1U << 14U)
-#define	MOD_SEL0_PWM2_A		((uint32_t)0U << 12U)
-#define	MOD_SEL0_PWM2_B		((uint32_t)1U << 12U)
-#define	MOD_SEL0_PWM2_C		((uint32_t)2U << 12U)
-#define	MOD_SEL0_PWM3_A		((uint32_t)0U << 10U)
-#define	MOD_SEL0_PWM3_B		((uint32_t)1U << 10U)
-#define	MOD_SEL0_PWM3_C		((uint32_t)2U << 10U)
-#define	MOD_SEL0_PWM4_A		((uint32_t)0U << 9U)
-#define	MOD_SEL0_PWM4_B		((uint32_t)1U << 9U)
-#define	MOD_SEL0_PWM5_A		((uint32_t)0U << 8U)
-#define	MOD_SEL0_PWM5_B		((uint32_t)1U << 8U)
-#define	MOD_SEL0_PWM6_A		((uint32_t)0U << 7U)
-#define	MOD_SEL0_PWM6_B		((uint32_t)1U << 7U)
-#define	MOD_SEL0_REMOCON_A	((uint32_t)0U << 5U)
-#define	MOD_SEL0_REMOCON_B	((uint32_t)1U << 5U)
-#define	MOD_SEL0_REMOCON_C	((uint32_t)2U << 5U)
-#define	MOD_SEL0_SCIF_A		((uint32_t)0U << 4U)
-#define	MOD_SEL0_SCIF_B		((uint32_t)1U << 4U)
-#define	MOD_SEL0_SCIF0_A	((uint32_t)0U << 3U)
-#define	MOD_SEL0_SCIF0_B	((uint32_t)1U << 3U)
-#define	MOD_SEL0_SCIF2_A	((uint32_t)0U << 2U)
-#define	MOD_SEL0_SCIF2_B	((uint32_t)1U << 2U)
-#define	MOD_SEL0_SPEED_PULSE_IF_A	((uint32_t)0U << 0U)
-#define	MOD_SEL0_SPEED_PULSE_IF_B	((uint32_t)1U << 0U)
-#define	MOD_SEL0_SPEED_PULSE_IF_C	((uint32_t)2U << 0U)
-#define	MOD_SEL1_SIMCARD_A	((uint32_t)0U << 31U)
-#define	MOD_SEL1_SIMCARD_B	((uint32_t)1U << 31U)
-#define	MOD_SEL1_SSI2_A		((uint32_t)0U << 30U)
-#define	MOD_SEL1_SSI2_B		((uint32_t)1U << 30U)
-#define	MOD_SEL1_TIMER_TMU_A	((uint32_t)0U << 29U)
-#define	MOD_SEL1_TIMER_TMU_B	((uint32_t)1U << 29U)
-#define MOD_SEL1_USB20_CH0_A	((uint32_t)0U << 28U)
-#define MOD_SEL1_USB20_CH0_B	((uint32_t)1U << 28U)
-#define	MOD_SEL1_DRIF2_A	((uint32_t)0U << 26U)
-#define	MOD_SEL1_DRIF2_B	((uint32_t)1U << 26U)
-#define	MOD_SEL1_DRIF3_A	((uint32_t)0U << 25U)
-#define	MOD_SEL1_DRIF3_B	((uint32_t)1U << 25U)
-#define	MOD_SEL1_HSCIF3_A	((uint32_t)0U << 22U)
-#define	MOD_SEL1_HSCIF3_B	((uint32_t)1U << 22U)
-#define	MOD_SEL1_HSCIF3_C	((uint32_t)2U << 22U)
-#define	MOD_SEL1_HSCIF3_D	((uint32_t)3U << 22U)
-#define	MOD_SEL1_HSCIF3_E	((uint32_t)4U << 22U)
-#define	MOD_SEL1_HSCIF4_A	((uint32_t)0U << 19U)
-#define	MOD_SEL1_HSCIF4_B	((uint32_t)1U << 19U)
-#define	MOD_SEL1_HSCIF4_C	((uint32_t)2U << 19U)
-#define	MOD_SEL1_HSCIF4_D	((uint32_t)3U << 19U)
-#define	MOD_SEL1_HSCIF4_E	((uint32_t)4U << 19U)
-#define	MOD_SEL1_I2C6_A		((uint32_t)0U << 18U)
-#define	MOD_SEL1_I2C6_B		((uint32_t)1U << 18U)
-#define	MOD_SEL1_I2C7_A		((uint32_t)0U << 17U)
-#define	MOD_SEL1_I2C7_B		((uint32_t)1U << 17U)
-#define	MOD_SEL1_MSIOF2_A	((uint32_t)0U << 16U)
-#define	MOD_SEL1_MSIOF2_B	((uint32_t)1U << 16U)
-#define	MOD_SEL1_MSIOF3_A	((uint32_t)0U << 15U)
-#define	MOD_SEL1_MSIOF3_B	((uint32_t)1U << 15U)
-#define	MOD_SEL1_SCIF3_A	((uint32_t)0U << 13U)
-#define	MOD_SEL1_SCIF3_B	((uint32_t)1U << 13U)
-#define	MOD_SEL1_SCIF3_C	((uint32_t)2U << 13U)
-#define	MOD_SEL1_SCIF4_A	((uint32_t)0U << 11U)
-#define	MOD_SEL1_SCIF4_B	((uint32_t)1U << 11U)
-#define	MOD_SEL1_SCIF4_C	((uint32_t)2U << 11U)
-#define	MOD_SEL1_SCIF5_A	((uint32_t)0U << 9U)
-#define	MOD_SEL1_SCIF5_B	((uint32_t)1U << 9U)
-#define	MOD_SEL1_SCIF5_C	((uint32_t)2U << 9U)
-#define	MOD_SEL1_VIN4_A		((uint32_t)0U << 8U)
-#define	MOD_SEL1_VIN4_B		((uint32_t)1U << 8U)
-#define	MOD_SEL1_VIN5_A		((uint32_t)0U << 7U)
-#define	MOD_SEL1_VIN5_B		((uint32_t)1U << 7U)
-#define	MOD_SEL1_ADGC_A		((uint32_t)0U << 5U)
-#define	MOD_SEL1_ADGC_B		((uint32_t)1U << 5U)
-#define	MOD_SEL1_ADGC_C		((uint32_t)2U << 5U)
-#define	MOD_SEL1_SSI9_A		((uint32_t)0U << 4U)
-#define	MOD_SEL1_SSI9_B		((uint32_t)1U << 4U)
-
-static void pfc_reg_write(uint32_t addr, uint32_t data);
-
-static void pfc_reg_write(uint32_t addr, uint32_t data)
-{
-	mmio_write_32(PFC_PMMR, ~data);
-	mmio_write_32((uintptr_t) addr, data);
-}
-
-void pfc_init_e3(void)
-{
-	uint32_t reg;
-
-	/* initialize module select */
-	pfc_reg_write(PFC_MOD_SEL0, MOD_SEL0_ADGB_A
-		      | MOD_SEL0_DRIF0_A
-		      | MOD_SEL0_FM_A
-		      | MOD_SEL0_FSO_A
-		      | MOD_SEL0_HSCIF0_A
-		      | MOD_SEL0_HSCIF1_A
-		      | MOD_SEL0_HSCIF2_A
-		      | MOD_SEL0_I2C1_A
-		      | MOD_SEL0_I2C2_A
-		      | MOD_SEL0_NDFC_A
-		      | MOD_SEL0_PWM0_A
-		      | MOD_SEL0_PWM1_A
-		      | MOD_SEL0_PWM2_A
-		      | MOD_SEL0_PWM3_A
-		      | MOD_SEL0_PWM4_A
-		      | MOD_SEL0_PWM5_A
-		      | MOD_SEL0_PWM6_A
-		      | MOD_SEL0_REMOCON_A
-		      | MOD_SEL0_SCIF_A
-		      | MOD_SEL0_SCIF0_A
-		      | MOD_SEL0_SCIF2_A
-		      | MOD_SEL0_SPEED_PULSE_IF_A);
-	pfc_reg_write(PFC_MOD_SEL1, MOD_SEL1_SIMCARD_A
-		      | MOD_SEL1_SSI2_A
-		      | MOD_SEL1_TIMER_TMU_A
-		      | MOD_SEL1_USB20_CH0_B
-		      | MOD_SEL1_DRIF2_A
-		      | MOD_SEL1_DRIF3_A
-		      | MOD_SEL1_HSCIF3_A
-		      | MOD_SEL1_HSCIF4_A
-		      | MOD_SEL1_I2C6_A
-		      | MOD_SEL1_I2C7_A
-		      | MOD_SEL1_MSIOF2_A
-		      | MOD_SEL1_MSIOF3_A
-		      | MOD_SEL1_SCIF3_A
-		      | MOD_SEL1_SCIF4_A
-		      | MOD_SEL1_SCIF5_A
-		      | MOD_SEL1_VIN4_A
-		      | MOD_SEL1_VIN5_A
-		      | MOD_SEL1_ADGC_A
-		      | MOD_SEL1_SSI9_A);
-
-	/* initialize peripheral function select */
-	pfc_reg_write(PFC_IPSR0, IPSR_28_FUNC(0)	/* QSPI1_MISO/IO1 */
-		      | IPSR_24_FUNC(0)	/* QSPI1_MOSI/IO0 */
-		      | IPSR_20_FUNC(0)	/* QSPI1_SPCLK */
-		      | IPSR_16_FUNC(0)	/* QSPI0_IO3 */
-		      | IPSR_12_FUNC(0)	/* QSPI0_IO2 */
-		      | IPSR_8_FUNC(0)	/* QSPI0_MISO/IO1 */
-		      | IPSR_4_FUNC(0)	/* QSPI0_MOSI/IO0 */
-		      | IPSR_0_FUNC(0));	/* QSPI0_SPCLK */
-	pfc_reg_write(PFC_IPSR1, IPSR_28_FUNC(0)	/* AVB_RD2 */
-		      | IPSR_24_FUNC(0)	/* AVB_RD1 */
-		      | IPSR_20_FUNC(0)	/* AVB_RD0 */
-		      | IPSR_16_FUNC(0)	/* RPC_RESET# */
-		      | IPSR_12_FUNC(0)	/* RPC_INT# */
-		      | IPSR_8_FUNC(0)	/* QSPI1_SSL */
-		      | IPSR_4_FUNC(0)	/* QSPI1_IO3 */
-		      | IPSR_0_FUNC(0));	/* QSPI1_IO2 */
-	pfc_reg_write(PFC_IPSR2, IPSR_28_FUNC(1)	/* IRQ0 */
-		      | IPSR_24_FUNC(0)
-		      | IPSR_20_FUNC(0)
-		      | IPSR_16_FUNC(2)	/* AVB_LINK */
-		      | IPSR_12_FUNC(0)
-		      | IPSR_8_FUNC(0)	/* AVB_MDC */
-		      | IPSR_4_FUNC(0)	/* AVB_MDIO */
-		      | IPSR_0_FUNC(0));	/* AVB_TXCREFCLK */
-	pfc_reg_write(PFC_IPSR3, IPSR_28_FUNC(5)	/* DU_HSYNC */
-		      | IPSR_24_FUNC(0)
-		      | IPSR_20_FUNC(0)
-		      | IPSR_16_FUNC(0)
-		      | IPSR_12_FUNC(5)	/* DU_DG4 */
-		      | IPSR_8_FUNC(5)	/* DU_DOTCLKOUT0 */
-		      | IPSR_4_FUNC(5)	/* DU_DISP */
-		      | IPSR_0_FUNC(1));	/* IRQ1 */
-	pfc_reg_write(PFC_IPSR4, IPSR_28_FUNC(5)	/* DU_DB5 */
-		      | IPSR_24_FUNC(5)	/* DU_DB4 */
-		      | IPSR_20_FUNC(5)	/* DU_DB3 */
-		      | IPSR_16_FUNC(5)	/* DU_DB2 */
-		      | IPSR_12_FUNC(5)	/* DU_DG6 */
-		      | IPSR_8_FUNC(5)	/* DU_VSYNC */
-		      | IPSR_4_FUNC(5)	/* DU_DG5 */
-		      | IPSR_0_FUNC(5));	/* DU_DG7 */
-	pfc_reg_write(PFC_IPSR5, IPSR_28_FUNC(5)	/* DU_DR3 */
-		      | IPSR_24_FUNC(5)	/* DU_DB7 */
-		      | IPSR_20_FUNC(5)	/* DU_DR2 */
-		      | IPSR_16_FUNC(5)	/* DU_DR1 */
-		      | IPSR_12_FUNC(5)	/* DU_DR0 */
-		      | IPSR_8_FUNC(5)	/* DU_DB1 */
-		      | IPSR_4_FUNC(5)	/* DU_DB0 */
-		      | IPSR_0_FUNC(5));	/* DU_DB6 */
-	pfc_reg_write(PFC_IPSR6, IPSR_28_FUNC(5)	/* DU_DG1 */
-		      | IPSR_24_FUNC(5)	/* DU_DG0 */
-		      | IPSR_20_FUNC(5)	/* DU_DR7 */
-		      | IPSR_16_FUNC(2)	/* IRQ5 */
-		      | IPSR_12_FUNC(5)	/* DU_DR6 */
-		      | IPSR_8_FUNC(5)	/* DU_DR5 */
-		      | IPSR_4_FUNC(0)
-		      | IPSR_0_FUNC(5));	/* DU_DR4 */
-	pfc_reg_write(PFC_IPSR7, IPSR_28_FUNC(0)	/* SD0_CLK */
-		      | IPSR_24_FUNC(0)
-		      | IPSR_20_FUNC(5)	/* DU_DOTCLKIN0 */
-		      | IPSR_16_FUNC(5)	/* DU_DG3 */
-		      | IPSR_12_FUNC(0)
-		      | IPSR_8_FUNC(0)
-		      | IPSR_4_FUNC(0)
-		      | IPSR_0_FUNC(5));	/* DU_DG2 */
-	pfc_reg_write(PFC_IPSR8, IPSR_28_FUNC(0)	/* SD1_DAT0 */
-		      | IPSR_24_FUNC(0)	/* SD1_CMD */
-		      | IPSR_20_FUNC(0)	/* SD1_CLK */
-		      | IPSR_16_FUNC(0)	/* SD0_DAT3 */
-		      | IPSR_12_FUNC(0)	/* SD0_DAT2 */
-		      | IPSR_8_FUNC(0)	/* SD0_DAT1 */
-		      | IPSR_4_FUNC(0)	/* SD0_DAT0 */
-		      | IPSR_0_FUNC(0));	/* SD0_CMD */
-	pfc_reg_write(PFC_IPSR9, IPSR_28_FUNC(0)	/* SD3_DAT2 */
-		      | IPSR_24_FUNC(0)	/* SD3_DAT1 */
-		      | IPSR_20_FUNC(0)	/* SD3_DAT0 */
-		      | IPSR_16_FUNC(0)	/* SD3_CMD */
-		      | IPSR_12_FUNC(0)	/* SD3_CLK */
-		      | IPSR_8_FUNC(0)	/* SD1_DAT3 */
-		      | IPSR_4_FUNC(0)	/* SD1_DAT2 */
-		      | IPSR_0_FUNC(0));	/* SD1_DAT1 */
-	pfc_reg_write(PFC_IPSR10, IPSR_28_FUNC(0)	/* SD0_WP */
-		      | IPSR_24_FUNC(0)	/* SD0_CD */
-		      | IPSR_20_FUNC(0)	/* SD3_DS */
-		      | IPSR_16_FUNC(0)	/* SD3_DAT7 */
-		      | IPSR_12_FUNC(0)	/* SD3_DAT6 */
-		      | IPSR_8_FUNC(0)	/* SD3_DAT5 */
-		      | IPSR_4_FUNC(0)	/* SD3_DAT4 */
-		      | IPSR_0_FUNC(0));	/* SD3_DAT3 */
-	pfc_reg_write(PFC_IPSR11, IPSR_28_FUNC(0)
-		      | IPSR_24_FUNC(0)
-		      | IPSR_20_FUNC(2)	/* AUDIO_CLKOUT1_A */
-		      | IPSR_16_FUNC(2)	/* AUDIO_CLKOUT_A */
-		      | IPSR_12_FUNC(0)
-		      | IPSR_8_FUNC(0)
-		      | IPSR_4_FUNC(0)	/* SD1_WP */
-		      | IPSR_0_FUNC(0));	/* SD1_CD */
-	pfc_reg_write(PFC_IPSR12, IPSR_28_FUNC(0)
-		      | IPSR_24_FUNC(0)
-		      | IPSR_20_FUNC(0)
-		      | IPSR_16_FUNC(0)
-		      | IPSR_12_FUNC(0)	/* RX2_A */
-		      | IPSR_8_FUNC(0)	/* TX2_A */
-		      | IPSR_4_FUNC(2)	/* AUDIO_CLKB_A */
-		      | IPSR_0_FUNC(0));
-	pfc_reg_write(PFC_IPSR13, IPSR_28_FUNC(0)
-		      | IPSR_24_FUNC(0)
-		      | IPSR_20_FUNC(0)
-		      | IPSR_16_FUNC(0)
-		      | IPSR_12_FUNC(0)
-		      | IPSR_8_FUNC(2)	/* AUDIO_CLKC_A */
-		      | IPSR_4_FUNC(1)	/* HTX2_A */
-		      | IPSR_0_FUNC(1));	/* HRX2_A */
-	pfc_reg_write(PFC_IPSR14, IPSR_28_FUNC(3)	/* USB0_PWEN_B */
-		      | IPSR_24_FUNC(0)	/* SSI_SDATA4 */
-		      | IPSR_20_FUNC(0)	/* SSI_SDATA3 */
-		      | IPSR_16_FUNC(0)	/* SSI_WS349 */
-		      | IPSR_12_FUNC(0)	/* SSI_SCK349 */
-		      | IPSR_8_FUNC(0)
-		      | IPSR_4_FUNC(0)	/* SSI_SDATA1 */
-		      | IPSR_0_FUNC(0));	/* SSI_SDATA0 */
-	pfc_reg_write(PFC_IPSR15, IPSR_28_FUNC(0)	/* USB30_OVC */
-		      | IPSR_24_FUNC(0)	/* USB30_PWEN */
-		      | IPSR_20_FUNC(0)	/* AUDIO_CLKA */
-		      | IPSR_16_FUNC(1)	/* HRTS2#_A */
-		      | IPSR_12_FUNC(1)	/* HCTS2#_A */
-		      | IPSR_8_FUNC(0)
-		      | IPSR_4_FUNC(0)
-		      | IPSR_0_FUNC(3));	/* USB0_OVC_B */
-
-	/* initialize GPIO/perihperal function select */
-	pfc_reg_write(PFC_GPSR0, GPSR0_SCL4
-		      | GPSR0_D15
-		      | GPSR0_D11
-		      | GPSR0_D10
-		      | GPSR0_D9
-		      | GPSR0_D8
-		      | GPSR0_D7
-		      | GPSR0_D6
-		      | GPSR0_D5
-		      | GPSR0_D3
-		      | GPSR0_D2
-		      | GPSR0_D1
-		      | GPSR0_D0);
-	pfc_reg_write(PFC_GPSR1, GPSR1_WE0
-		      | GPSR1_CS0
-		      | GPSR1_A19
-		      | GPSR1_A18
-		      | GPSR1_A17
-		      | GPSR1_A16
-		      | GPSR1_A15
-		      | GPSR1_A14
-		      | GPSR1_A13
-		      | GPSR1_A12
-		      | GPSR1_A11
-		      | GPSR1_A10
-		      | GPSR1_A9
-		      | GPSR1_A8
-		      | GPSR1_A4
-		      | GPSR1_A3
-		      | GPSR1_A2
-		      | GPSR1_A1
-		      | GPSR1_A0);
-	pfc_reg_write(PFC_GPSR2, GPSR2_BIT27_REVERCED
-		      | GPSR2_BIT26_REVERCED
-		      | GPSR2_RD
-		      | GPSR2_AVB_PHY_INT
-		      | GPSR2_AVB_TXCREFCLK
-		      | GPSR2_AVB_RD3
-		      | GPSR2_AVB_RD2
-		      | GPSR2_AVB_RD1
-		      | GPSR2_AVB_RD0
-		      | GPSR2_AVB_RXC
-		      | GPSR2_AVB_RX_CTL
-		      | GPSR2_RPC_RESET
-		      | GPSR2_RPC_RPC_INT
-		      | GPSR2_QSPI1_SSL
-		      | GPSR2_QSPI1_IO3
-		      | GPSR2_QSPI1_IO2
-		      | GPSR2_QSPI1_MISO_IO1
-		      | GPSR2_QSPI1_MOSI_IO0
-		      | GPSR2_QSPI1_SPCLK
-		      | GPSR2_QSPI0_SSL
-		      | GPSR2_QSPI0_IO3
-		      | GPSR2_QSPI0_IO2
-		      | GPSR2_QSPI0_MISO_IO1
-		      | GPSR2_QSPI0_MOSI_IO0
-		      | GPSR2_QSPI0_SPCLK);
-	pfc_reg_write(PFC_GPSR3, GPSR3_SD1_WP
-		      | GPSR3_SD1_CD
-		      | GPSR3_SD0_WP
-		      | GPSR3_SD0_CD
-		      | GPSR3_SD1_DAT3
-		      | GPSR3_SD1_DAT2
-		      | GPSR3_SD1_DAT1
-		      | GPSR3_SD1_DAT0
-		      | GPSR3_SD1_CMD
-		      | GPSR3_SD1_CLK
-		      | GPSR3_SD0_DAT3
-		      | GPSR3_SD0_DAT2
-		      | GPSR3_SD0_DAT1
-		      | GPSR3_SD0_DAT0
-		      | GPSR3_SD0_CMD
-		      | GPSR3_SD0_CLK);
-	pfc_reg_write(PFC_GPSR4, GPSR4_SD3_DS
-		      | GPSR4_SD3_DAT7
-		      | GPSR4_SD3_DAT6
-		      | GPSR4_SD3_DAT5
-		      | GPSR4_SD3_DAT4
-		      | GPSR4_SD3_DAT3
-		      | GPSR4_SD3_DAT2
-		      | GPSR4_SD3_DAT1
-		      | GPSR4_SD3_DAT0
-		      | GPSR4_SD3_CMD
-		      | GPSR4_SD3_CLK);
-	pfc_reg_write(PFC_GPSR5, GPSR5_SSI_SDATA9
-		      | GPSR5_MSIOF0_SS2
-		      | GPSR5_MSIOF0_SS1
-		      | GPSR5_RX2_A
-		      | GPSR5_TX2_A
-		      | GPSR5_SCK2_A
-		      | GPSR5_RTS0_TANS_A
-		      | GPSR5_CTS0_A);
-	pfc_reg_write(PFC_GPSR6, GPSR6_USB30_PWEN
-		      | GPSR6_SSI_SDATA6
-		      | GPSR6_SSI_WS6
-		      | GPSR6_SSI_WS5
-		      | GPSR6_SSI_SCK5
-		      | GPSR6_SSI_SDATA4
-		      | GPSR6_USB30_OVC
-		      | GPSR6_AUDIO_CLKA
-		      | GPSR6_SSI_SDATA3
-		      | GPSR6_SSI_WS349
-		      | GPSR6_SSI_SCK349
-		      | GPSR6_SSI_SDATA1
-		      | GPSR6_SSI_SDATA0
-		      | GPSR6_SSI_WS01239
-		      | GPSR6_SSI_SCK01239);
-
-	/* initialize POC control */
-	reg = mmio_read_32(PFC_IOCTRL30);
-	reg = ((reg & IOCTRL30_MASK) | POC_SD1_DAT3_33V
-	       | POC_SD1_DAT2_33V
-	       | POC_SD1_DAT1_33V
-	       | POC_SD1_DAT0_33V
-	       | POC_SD1_CMD_33V
-	       | POC_SD1_CLK_33V
-	       | POC_SD0_DAT3_33V
-	       | POC_SD0_DAT2_33V
-	       | POC_SD0_DAT1_33V
-	       | POC_SD0_DAT0_33V
-	       | POC_SD0_CMD_33V
-	       | POC_SD0_CLK_33V);
-	pfc_reg_write(PFC_IOCTRL30, reg);
-	reg = mmio_read_32(PFC_IOCTRL32);
-	reg = (reg & IOCTRL32_MASK);
-	pfc_reg_write(PFC_IOCTRL32, reg);
-
-	/* initialize LSI pin pull-up/down control */
-	pfc_reg_write(PFC_PUD0, 0xFDF80000U);
-	pfc_reg_write(PFC_PUD1, 0xCE298464U);
-	pfc_reg_write(PFC_PUD2, 0xA4C380F4U);
-	pfc_reg_write(PFC_PUD3, 0x0000079FU);
-	pfc_reg_write(PFC_PUD4, 0xFFF0FFFFU);
-	pfc_reg_write(PFC_PUD5, 0x40000000U);
-
-	/* initialize LSI pin pull-enable register */
-	pfc_reg_write(PFC_PUEN0, 0xFFF00000U);
-	pfc_reg_write(PFC_PUEN1, 0x00000000U);
-	pfc_reg_write(PFC_PUEN2, 0x00000004U);
-	pfc_reg_write(PFC_PUEN3, 0x00000000U);
-	pfc_reg_write(PFC_PUEN4, 0x07800010U);
-	pfc_reg_write(PFC_PUEN5, 0x00000000U);
-
-	/* initialize positive/negative logic select */
-	mmio_write_32(GPIO_POSNEG0, 0x00000000U);
-	mmio_write_32(GPIO_POSNEG1, 0x00000000U);
-	mmio_write_32(GPIO_POSNEG2, 0x00000000U);
-	mmio_write_32(GPIO_POSNEG3, 0x00000000U);
-	mmio_write_32(GPIO_POSNEG4, 0x00000000U);
-	mmio_write_32(GPIO_POSNEG5, 0x00000000U);
-	mmio_write_32(GPIO_POSNEG6, 0x00000000U);
-
-	/* initialize general IO/interrupt switching */
-	mmio_write_32(GPIO_IOINTSEL0, 0x00020000U);
-	mmio_write_32(GPIO_IOINTSEL1, 0x00000000U);
-	mmio_write_32(GPIO_IOINTSEL2, 0x00000000U);
-	mmio_write_32(GPIO_IOINTSEL3, 0x00000000U);
-	mmio_write_32(GPIO_IOINTSEL4, 0x00000000U);
-	mmio_write_32(GPIO_IOINTSEL5, 0x00000000U);
-	mmio_write_32(GPIO_IOINTSEL6, 0x00000000U);
-
-	/* initialize general output register */
-	mmio_write_32(GPIO_OUTDT0, 0x00000010U);
-	mmio_write_32(GPIO_OUTDT1, 0x00100000U);
-	mmio_write_32(GPIO_OUTDT2, 0x00000000U);
-	mmio_write_32(GPIO_OUTDT3, 0x00008000U);
-	mmio_write_32(GPIO_OUTDT5, 0x00060000U);
-	mmio_write_32(GPIO_OUTDT6, 0x00000000U);
-
-	/* initialize general input/output switching */
-	mmio_write_32(GPIO_INOUTSEL0, 0x00000010U);
-	mmio_write_32(GPIO_INOUTSEL1, 0x00100020U);
-	mmio_write_32(GPIO_INOUTSEL2, 0x03000000U);
-	mmio_write_32(GPIO_INOUTSEL3, 0x00008000U);
-	mmio_write_32(GPIO_INOUTSEL4, 0x00000000U);
-	mmio_write_32(GPIO_INOUTSEL5, 0x00060000U);
-	mmio_write_32(GPIO_INOUTSEL6, 0x00004000U);
-}
diff --git a/drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v1.c b/drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v1.c
deleted file mode 100644
index e33005f..0000000
--- a/drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v1.c
+++ /dev/null
@@ -1,1405 +0,0 @@
-/*
- * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <stdint.h>
-
-#include <lib/mmio.h>
-
-/* GPIO base address */
-#define	GPIO_BASE		(0xE6050000U)
-
-/* GPIO registers */
-#define	GPIO_IOINTSEL0		(GPIO_BASE + 0x0000U)
-#define	GPIO_INOUTSEL0		(GPIO_BASE + 0x0004U)
-#define	GPIO_OUTDT0		(GPIO_BASE + 0x0008U)
-#define	GPIO_INDT0		(GPIO_BASE + 0x000CU)
-#define	GPIO_INTDT0		(GPIO_BASE + 0x0010U)
-#define	GPIO_INTCLR0		(GPIO_BASE + 0x0014U)
-#define	GPIO_INTMSK0		(GPIO_BASE + 0x0018U)
-#define	GPIO_MSKCLR0		(GPIO_BASE + 0x001CU)
-#define	GPIO_POSNEG0		(GPIO_BASE + 0x0020U)
-#define	GPIO_EDGLEVEL0		(GPIO_BASE + 0x0024U)
-#define	GPIO_FILONOFF0		(GPIO_BASE + 0x0028U)
-#define	GPIO_INTMSKS0		(GPIO_BASE + 0x0038U)
-#define	GPIO_MSKCLRS0		(GPIO_BASE + 0x003CU)
-#define	GPIO_OUTDTSEL0		(GPIO_BASE + 0x0040U)
-#define	GPIO_OUTDTH0		(GPIO_BASE + 0x0044U)
-#define	GPIO_OUTDTL0		(GPIO_BASE + 0x0048U)
-#define	GPIO_BOTHEDGE0		(GPIO_BASE + 0x004CU)
-#define	GPIO_IOINTSEL1		(GPIO_BASE + 0x1000U)
-#define	GPIO_INOUTSEL1		(GPIO_BASE + 0x1004U)
-#define	GPIO_OUTDT1		(GPIO_BASE + 0x1008U)
-#define	GPIO_INDT1		(GPIO_BASE + 0x100CU)
-#define	GPIO_INTDT1		(GPIO_BASE + 0x1010U)
-#define	GPIO_INTCLR1		(GPIO_BASE + 0x1014U)
-#define	GPIO_INTMSK1		(GPIO_BASE + 0x1018U)
-#define	GPIO_MSKCLR1		(GPIO_BASE + 0x101CU)
-#define	GPIO_POSNEG1		(GPIO_BASE + 0x1020U)
-#define	GPIO_EDGLEVEL1		(GPIO_BASE + 0x1024U)
-#define	GPIO_FILONOFF1		(GPIO_BASE + 0x1028U)
-#define	GPIO_INTMSKS1		(GPIO_BASE + 0x1038U)
-#define	GPIO_MSKCLRS1		(GPIO_BASE + 0x103CU)
-#define	GPIO_OUTDTSEL1		(GPIO_BASE + 0x1040U)
-#define	GPIO_OUTDTH1		(GPIO_BASE + 0x1044U)
-#define	GPIO_OUTDTL1		(GPIO_BASE + 0x1048U)
-#define	GPIO_BOTHEDGE1		(GPIO_BASE + 0x104CU)
-#define	GPIO_IOINTSEL2		(GPIO_BASE + 0x2000U)
-#define	GPIO_INOUTSEL2		(GPIO_BASE + 0x2004U)
-#define	GPIO_OUTDT2		(GPIO_BASE + 0x2008U)
-#define	GPIO_INDT2		(GPIO_BASE + 0x200CU)
-#define	GPIO_INTDT2		(GPIO_BASE + 0x2010U)
-#define	GPIO_INTCLR2		(GPIO_BASE + 0x2014U)
-#define	GPIO_INTMSK2		(GPIO_BASE + 0x2018U)
-#define	GPIO_MSKCLR2		(GPIO_BASE + 0x201CU)
-#define	GPIO_POSNEG2		(GPIO_BASE + 0x2020U)
-#define	GPIO_EDGLEVEL2		(GPIO_BASE + 0x2024U)
-#define	GPIO_FILONOFF2		(GPIO_BASE + 0x2028U)
-#define	GPIO_INTMSKS2		(GPIO_BASE + 0x2038U)
-#define	GPIO_MSKCLRS2		(GPIO_BASE + 0x203CU)
-#define	GPIO_OUTDTSEL2		(GPIO_BASE + 0x2040U)
-#define	GPIO_OUTDTH2		(GPIO_BASE + 0x2044U)
-#define	GPIO_OUTDTL2		(GPIO_BASE + 0x2048U)
-#define	GPIO_BOTHEDGE2		(GPIO_BASE + 0x204CU)
-#define	GPIO_IOINTSEL3		(GPIO_BASE + 0x3000U)
-#define	GPIO_INOUTSEL3		(GPIO_BASE + 0x3004U)
-#define	GPIO_OUTDT3		(GPIO_BASE + 0x3008U)
-#define	GPIO_INDT3		(GPIO_BASE + 0x300CU)
-#define	GPIO_INTDT3		(GPIO_BASE + 0x3010U)
-#define	GPIO_INTCLR3		(GPIO_BASE + 0x3014U)
-#define	GPIO_INTMSK3		(GPIO_BASE + 0x3018U)
-#define	GPIO_MSKCLR3		(GPIO_BASE + 0x301CU)
-#define	GPIO_POSNEG3		(GPIO_BASE + 0x3020U)
-#define	GPIO_EDGLEVEL3		(GPIO_BASE + 0x3024U)
-#define	GPIO_FILONOFF3		(GPIO_BASE + 0x3028U)
-#define	GPIO_INTMSKS3		(GPIO_BASE + 0x3038U)
-#define	GPIO_MSKCLRS3		(GPIO_BASE + 0x303CU)
-#define	GPIO_OUTDTSEL3		(GPIO_BASE + 0x3040U)
-#define	GPIO_OUTDTH3		(GPIO_BASE + 0x3044U)
-#define	GPIO_OUTDTL3		(GPIO_BASE + 0x3048U)
-#define	GPIO_BOTHEDGE3		(GPIO_BASE + 0x304CU)
-#define	GPIO_IOINTSEL4		(GPIO_BASE + 0x4000U)
-#define	GPIO_INOUTSEL4		(GPIO_BASE + 0x4004U)
-#define	GPIO_OUTDT4		(GPIO_BASE + 0x4008U)
-#define	GPIO_INDT4		(GPIO_BASE + 0x400CU)
-#define	GPIO_INTDT4		(GPIO_BASE + 0x4010U)
-#define	GPIO_INTCLR4		(GPIO_BASE + 0x4014U)
-#define	GPIO_INTMSK4		(GPIO_BASE + 0x4018U)
-#define	GPIO_MSKCLR4		(GPIO_BASE + 0x401CU)
-#define	GPIO_POSNEG4		(GPIO_BASE + 0x4020U)
-#define	GPIO_EDGLEVEL4		(GPIO_BASE + 0x4024U)
-#define	GPIO_FILONOFF4		(GPIO_BASE + 0x4028U)
-#define	GPIO_INTMSKS4		(GPIO_BASE + 0x4038U)
-#define	GPIO_MSKCLRS4		(GPIO_BASE + 0x403CU)
-#define	GPIO_OUTDTSEL4		(GPIO_BASE + 0x4040U)
-#define	GPIO_OUTDTH4		(GPIO_BASE + 0x4044U)
-#define	GPIO_OUTDTL4		(GPIO_BASE + 0x4048U)
-#define	GPIO_BOTHEDGE4		(GPIO_BASE + 0x404CU)
-#define	GPIO_IOINTSEL5		(GPIO_BASE + 0x5000U)
-#define	GPIO_INOUTSEL5		(GPIO_BASE + 0x5004U)
-#define	GPIO_OUTDT5		(GPIO_BASE + 0x5008U)
-#define	GPIO_INDT5		(GPIO_BASE + 0x500CU)
-#define	GPIO_INTDT5		(GPIO_BASE + 0x5010U)
-#define	GPIO_INTCLR5		(GPIO_BASE + 0x5014U)
-#define	GPIO_INTMSK5		(GPIO_BASE + 0x5018U)
-#define	GPIO_MSKCLR5		(GPIO_BASE + 0x501CU)
-#define	GPIO_POSNEG5		(GPIO_BASE + 0x5020U)
-#define	GPIO_EDGLEVEL5		(GPIO_BASE + 0x5024U)
-#define	GPIO_FILONOFF5		(GPIO_BASE + 0x5028U)
-#define	GPIO_INTMSKS5		(GPIO_BASE + 0x5038U)
-#define	GPIO_MSKCLRS5		(GPIO_BASE + 0x503CU)
-#define	GPIO_OUTDTSEL5		(GPIO_BASE + 0x5040U)
-#define	GPIO_OUTDTH5		(GPIO_BASE + 0x5044U)
-#define	GPIO_OUTDTL5		(GPIO_BASE + 0x5048U)
-#define	GPIO_BOTHEDGE5		(GPIO_BASE + 0x504CU)
-#define	GPIO_IOINTSEL6		(GPIO_BASE + 0x5400U)
-#define	GPIO_INOUTSEL6		(GPIO_BASE + 0x5404U)
-#define	GPIO_OUTDT6		(GPIO_BASE + 0x5408U)
-#define	GPIO_INDT6		(GPIO_BASE + 0x540CU)
-#define	GPIO_INTDT6		(GPIO_BASE + 0x5410U)
-#define	GPIO_INTCLR6		(GPIO_BASE + 0x5414U)
-#define	GPIO_INTMSK6		(GPIO_BASE + 0x5418U)
-#define	GPIO_MSKCLR6		(GPIO_BASE + 0x541CU)
-#define	GPIO_POSNEG6		(GPIO_BASE + 0x5420U)
-#define	GPIO_EDGLEVEL6		(GPIO_BASE + 0x5424U)
-#define	GPIO_FILONOFF6		(GPIO_BASE + 0x5428U)
-#define	GPIO_INTMSKS6		(GPIO_BASE + 0x5438U)
-#define	GPIO_MSKCLRS6		(GPIO_BASE + 0x543CU)
-#define	GPIO_OUTDTSEL6		(GPIO_BASE + 0x5440U)
-#define	GPIO_OUTDTH6		(GPIO_BASE + 0x5444U)
-#define	GPIO_OUTDTL6		(GPIO_BASE + 0x5448U)
-#define	GPIO_BOTHEDGE6		(GPIO_BASE + 0x544CU)
-#define	GPIO_IOINTSEL7		(GPIO_BASE + 0x5800U)
-#define	GPIO_INOUTSEL7		(GPIO_BASE + 0x5804U)
-#define	GPIO_OUTDT7		(GPIO_BASE + 0x5808U)
-#define	GPIO_INDT7		(GPIO_BASE + 0x580CU)
-#define	GPIO_INTDT7		(GPIO_BASE + 0x5810U)
-#define	GPIO_INTCLR7		(GPIO_BASE + 0x5814U)
-#define	GPIO_INTMSK7		(GPIO_BASE + 0x5818U)
-#define	GPIO_MSKCLR7		(GPIO_BASE + 0x581CU)
-#define	GPIO_POSNEG7		(GPIO_BASE + 0x5820U)
-#define	GPIO_EDGLEVEL7		(GPIO_BASE + 0x5824U)
-#define	GPIO_FILONOFF7		(GPIO_BASE + 0x5828U)
-#define	GPIO_INTMSKS7		(GPIO_BASE + 0x5838U)
-#define	GPIO_MSKCLRS7		(GPIO_BASE + 0x583CU)
-#define	GPIO_OUTDTSEL7		(GPIO_BASE + 0x5840U)
-#define	GPIO_OUTDTH7		(GPIO_BASE + 0x5844U)
-#define	GPIO_OUTDTL7		(GPIO_BASE + 0x5848U)
-#define	GPIO_BOTHEDGE7		(GPIO_BASE + 0x584CU)
-
-/* Pin functon base address */
-#define	PFC_BASE		(0xE6060000U)
-
-/* Pin functon registers */
-#define	PFC_PMMR		(PFC_BASE + 0x0000U)
-#define PFC_GPSR0		(PFC_BASE + 0x0100U)
-#define PFC_GPSR1		(PFC_BASE + 0x0104U)
-#define PFC_GPSR2		(PFC_BASE + 0x0108U)
-#define PFC_GPSR3		(PFC_BASE + 0x010CU)
-#define PFC_GPSR4		(PFC_BASE + 0x0110U)
-#define	PFC_GPSR5		(PFC_BASE + 0x0114U)
-#define	PFC_GPSR6		(PFC_BASE + 0x0118U)
-#define	PFC_GPSR7		(PFC_BASE + 0x011CU)
-#define	PFC_IPSR0		(PFC_BASE + 0x0200U)
-#define	PFC_IPSR1		(PFC_BASE + 0x0204U)
-#define	PFC_IPSR2		(PFC_BASE + 0x0208U)
-#define	PFC_IPSR3		(PFC_BASE + 0x020CU)
-#define	PFC_IPSR4		(PFC_BASE + 0x0210U)
-#define	PFC_IPSR5		(PFC_BASE + 0x0214U)
-#define	PFC_IPSR6		(PFC_BASE + 0x0218U)
-#define	PFC_IPSR7		(PFC_BASE + 0x021CU)
-#define	PFC_IPSR8		(PFC_BASE + 0x0220U)
-#define	PFC_IPSR9		(PFC_BASE + 0x0224U)
-#define	PFC_IPSR10		(PFC_BASE + 0x0228U)
-#define	PFC_IPSR11		(PFC_BASE + 0x022CU)
-#define	PFC_IPSR12		(PFC_BASE + 0x0230U)
-#define	PFC_IPSR13		(PFC_BASE + 0x0234U)
-#define	PFC_IPSR14		(PFC_BASE + 0x0238U)
-#define	PFC_IPSR15		(PFC_BASE + 0x023CU)
-#define	PFC_IPSR16		(PFC_BASE + 0x0240U)
-#define	PFC_IPSR17		(PFC_BASE + 0x0244U)
-#define PFC_DRVCTRL0		(PFC_BASE + 0x0300U)
-#define PFC_DRVCTRL1		(PFC_BASE + 0x0304U)
-#define PFC_DRVCTRL2		(PFC_BASE + 0x0308U)
-#define PFC_DRVCTRL3		(PFC_BASE + 0x030CU)
-#define PFC_DRVCTRL4		(PFC_BASE + 0x0310U)
-#define PFC_DRVCTRL5		(PFC_BASE + 0x0314U)
-#define PFC_DRVCTRL6		(PFC_BASE + 0x0318U)
-#define PFC_DRVCTRL7		(PFC_BASE + 0x031CU)
-#define PFC_DRVCTRL8		(PFC_BASE + 0x0320U)
-#define PFC_DRVCTRL9		(PFC_BASE + 0x0324U)
-#define PFC_DRVCTRL10		(PFC_BASE + 0x0328U)
-#define PFC_DRVCTRL11		(PFC_BASE + 0x032CU)
-#define PFC_DRVCTRL12		(PFC_BASE + 0x0330U)
-#define PFC_DRVCTRL13		(PFC_BASE + 0x0334U)
-#define PFC_DRVCTRL14		(PFC_BASE + 0x0338U)
-#define PFC_DRVCTRL15		(PFC_BASE + 0x033CU)
-#define PFC_DRVCTRL16		(PFC_BASE + 0x0340U)
-#define PFC_DRVCTRL17		(PFC_BASE + 0x0344U)
-#define PFC_DRVCTRL18		(PFC_BASE + 0x0348U)
-#define PFC_DRVCTRL19		(PFC_BASE + 0x034CU)
-#define PFC_DRVCTRL20		(PFC_BASE + 0x0350U)
-#define PFC_DRVCTRL21		(PFC_BASE + 0x0354U)
-#define PFC_DRVCTRL22		(PFC_BASE + 0x0358U)
-#define PFC_DRVCTRL23		(PFC_BASE + 0x035CU)
-#define PFC_DRVCTRL24		(PFC_BASE + 0x0360U)
-#define PFC_POCCTRL0		(PFC_BASE + 0x0380U)
-#define	PFC_TDSELCTRL0		(PFC_BASE + 0x03C0U)
-#define	PFC_IOCTRL		(PFC_BASE + 0x03E0U)
-#define	PFC_TSREG		(PFC_BASE + 0x03E4U)
-#define	PFC_PUEN0		(PFC_BASE + 0x0400U)
-#define	PFC_PUEN1		(PFC_BASE + 0x0404U)
-#define	PFC_PUEN2		(PFC_BASE + 0x0408U)
-#define	PFC_PUEN3		(PFC_BASE + 0x040CU)
-#define	PFC_PUEN4		(PFC_BASE + 0x0410U)
-#define	PFC_PUEN5		(PFC_BASE + 0x0414U)
-#define	PFC_PUEN6		(PFC_BASE + 0x0418U)
-#define	PFC_PUD0		(PFC_BASE + 0x0440U)
-#define	PFC_PUD1		(PFC_BASE + 0x0444U)
-#define	PFC_PUD2		(PFC_BASE + 0x0448U)
-#define	PFC_PUD3		(PFC_BASE + 0x044CU)
-#define	PFC_PUD4		(PFC_BASE + 0x0450U)
-#define	PFC_PUD5		(PFC_BASE + 0x0454U)
-#define	PFC_PUD6		(PFC_BASE + 0x0458U)
-#define	PFC_MOD_SEL0		(PFC_BASE + 0x0500U)
-#define	PFC_MOD_SEL1		(PFC_BASE + 0x0504U)
-#define	PFC_MOD_SEL2		(PFC_BASE + 0x0508U)
-
-#define	GPSR0_D15		((uint32_t)1U << 15U)
-#define	GPSR0_D14		((uint32_t)1U << 14U)
-#define	GPSR0_D13		((uint32_t)1U << 13U)
-#define	GPSR0_D12		((uint32_t)1U << 12U)
-#define	GPSR0_D11		((uint32_t)1U << 11U)
-#define	GPSR0_D10		((uint32_t)1U << 10U)
-#define	GPSR0_D9		((uint32_t)1U << 9U)
-#define	GPSR0_D8		((uint32_t)1U << 8U)
-#define	GPSR0_D7		((uint32_t)1U << 7U)
-#define	GPSR0_D6		((uint32_t)1U << 6U)
-#define	GPSR0_D5		((uint32_t)1U << 5U)
-#define	GPSR0_D4		((uint32_t)1U << 4U)
-#define	GPSR0_D3		((uint32_t)1U << 3U)
-#define	GPSR0_D2		((uint32_t)1U << 2U)
-#define	GPSR0_D1		((uint32_t)1U << 1U)
-#define	GPSR0_D0		((uint32_t)1U << 0U)
-#define	GPSR1_EX_WAIT0_A	((uint32_t)1U << 27U)
-#define	GPSR1_WE1		((uint32_t)1U << 26U)
-#define	GPSR1_WE0		((uint32_t)1U << 25U)
-#define	GPSR1_RD_WR		((uint32_t)1U << 24U)
-#define	GPSR1_RD		((uint32_t)1U << 23U)
-#define	GPSR1_BS		((uint32_t)1U << 22U)
-#define	GPSR1_CS1_A26		((uint32_t)1U << 21U)
-#define	GPSR1_CS0		((uint32_t)1U << 20U)
-#define	GPSR1_A19		((uint32_t)1U << 19U)
-#define	GPSR1_A18		((uint32_t)1U << 18U)
-#define	GPSR1_A17		((uint32_t)1U << 17U)
-#define	GPSR1_A16		((uint32_t)1U << 16U)
-#define	GPSR1_A15		((uint32_t)1U << 15U)
-#define	GPSR1_A14		((uint32_t)1U << 14U)
-#define	GPSR1_A13		((uint32_t)1U << 13U)
-#define	GPSR1_A12		((uint32_t)1U << 12U)
-#define	GPSR1_A11		((uint32_t)1U << 11U)
-#define	GPSR1_A10		((uint32_t)1U << 10U)
-#define	GPSR1_A9		((uint32_t)1U << 9U)
-#define	GPSR1_A8		((uint32_t)1U << 8U)
-#define	GPSR1_A7		((uint32_t)1U << 7U)
-#define	GPSR1_A6		((uint32_t)1U << 6U)
-#define	GPSR1_A5		((uint32_t)1U << 5U)
-#define	GPSR1_A4		((uint32_t)1U << 4U)
-#define	GPSR1_A3		((uint32_t)1U << 3U)
-#define	GPSR1_A2		((uint32_t)1U << 2U)
-#define	GPSR1_A1		((uint32_t)1U << 1U)
-#define	GPSR1_A0		((uint32_t)1U << 0U)
-#define	GPSR2_AVB_AVTP_CAPTURE_A	((uint32_t)1U << 14U)
-#define	GPSR2_AVB_AVTP_MATCH_A	((uint32_t)1U << 13U)
-#define	GPSR2_AVB_LINK		((uint32_t)1U << 12U)
-#define	GPSR2_AVB_PHY_INT	((uint32_t)1U << 11U)
-#define	GPSR2_AVB_MAGIC		((uint32_t)1U << 10U)
-#define	GPSR2_AVB_MDC		((uint32_t)1U << 9U)
-#define	GPSR2_PWM2_A		((uint32_t)1U << 8U)
-#define	GPSR2_PWM1_A		((uint32_t)1U << 7U)
-#define	GPSR2_PWM0		((uint32_t)1U << 6U)
-#define	GPSR2_IRQ5		((uint32_t)1U << 5U)
-#define	GPSR2_IRQ4		((uint32_t)1U << 4U)
-#define	GPSR2_IRQ3		((uint32_t)1U << 3U)
-#define	GPSR2_IRQ2		((uint32_t)1U << 2U)
-#define	GPSR2_IRQ1		((uint32_t)1U << 1U)
-#define	GPSR2_IRQ0		((uint32_t)1U << 0U)
-#define	GPSR3_SD1_WP		((uint32_t)1U << 15U)
-#define	GPSR3_SD1_CD		((uint32_t)1U << 14U)
-#define	GPSR3_SD0_WP		((uint32_t)1U << 13U)
-#define	GPSR3_SD0_CD		((uint32_t)1U << 12U)
-#define	GPSR3_SD1_DAT3		((uint32_t)1U << 11U)
-#define	GPSR3_SD1_DAT2		((uint32_t)1U << 10U)
-#define	GPSR3_SD1_DAT1		((uint32_t)1U << 9U)
-#define	GPSR3_SD1_DAT0		((uint32_t)1U << 8U)
-#define	GPSR3_SD1_CMD		((uint32_t)1U << 7U)
-#define	GPSR3_SD1_CLK		((uint32_t)1U << 6U)
-#define	GPSR3_SD0_DAT3		((uint32_t)1U << 5U)
-#define	GPSR3_SD0_DAT2		((uint32_t)1U << 4U)
-#define	GPSR3_SD0_DAT1		((uint32_t)1U << 3U)
-#define	GPSR3_SD0_DAT0		((uint32_t)1U << 2U)
-#define	GPSR3_SD0_CMD		((uint32_t)1U << 1U)
-#define	GPSR3_SD0_CLK		((uint32_t)1U << 0U)
-#define	GPSR4_SD3_DS		((uint32_t)1U << 17U)
-#define	GPSR4_SD3_DAT7		((uint32_t)1U << 16U)
-#define	GPSR4_SD3_DAT6		((uint32_t)1U << 15U)
-#define	GPSR4_SD3_DAT5		((uint32_t)1U << 14U)
-#define	GPSR4_SD3_DAT4		((uint32_t)1U << 13U)
-#define	GPSR4_SD3_DAT3		((uint32_t)1U << 12U)
-#define	GPSR4_SD3_DAT2		((uint32_t)1U << 11U)
-#define	GPSR4_SD3_DAT1		((uint32_t)1U << 10U)
-#define	GPSR4_SD3_DAT0		((uint32_t)1U << 9U)
-#define	GPSR4_SD3_CMD		((uint32_t)1U << 8U)
-#define	GPSR4_SD3_CLK		((uint32_t)1U << 7U)
-#define	GPSR4_SD2_DS		((uint32_t)1U << 6U)
-#define	GPSR4_SD2_DAT3		((uint32_t)1U << 5U)
-#define	GPSR4_SD2_DAT2		((uint32_t)1U << 4U)
-#define	GPSR4_SD2_DAT1		((uint32_t)1U << 3U)
-#define	GPSR4_SD2_DAT0		((uint32_t)1U << 2U)
-#define	GPSR4_SD2_CMD		((uint32_t)1U << 1U)
-#define	GPSR4_SD2_CLK		((uint32_t)1U << 0U)
-#define	GPSR5_MLB_DAT		((uint32_t)1U << 25U)
-#define	GPSR5_MLB_SIG		((uint32_t)1U << 24U)
-#define	GPSR5_MLB_CLK		((uint32_t)1U << 23U)
-#define	GPSR5_MSIOF0_RXD	((uint32_t)1U << 22U)
-#define	GPSR5_MSIOF0_SS2	((uint32_t)1U << 21U)
-#define	GPSR5_MSIOF0_TXD	((uint32_t)1U << 20U)
-#define	GPSR5_MSIOF0_SS1	((uint32_t)1U << 19U)
-#define	GPSR5_MSIOF0_SYNC	((uint32_t)1U << 18U)
-#define	GPSR5_MSIOF0_SCK	((uint32_t)1U << 17U)
-#define	GPSR5_HRTS0		((uint32_t)1U << 16U)
-#define	GPSR5_HCTS0		((uint32_t)1U << 15U)
-#define	GPSR5_HTX0		((uint32_t)1U << 14U)
-#define	GPSR5_HRX0		((uint32_t)1U << 13U)
-#define	GPSR5_HSCK0		((uint32_t)1U << 12U)
-#define	GPSR5_RX2_A		((uint32_t)1U << 11U)
-#define	GPSR5_TX2_A		((uint32_t)1U << 10U)
-#define	GPSR5_SCK2		((uint32_t)1U << 9U)
-#define	GPSR5_RTS1_TANS		((uint32_t)1U << 8U)
-#define	GPSR5_CTS1		((uint32_t)1U << 7U)
-#define	GPSR5_TX1_A		((uint32_t)1U << 6U)
-#define	GPSR5_RX1_A		((uint32_t)1U << 5U)
-#define	GPSR5_RTS0_TANS		((uint32_t)1U << 4U)
-#define	GPSR5_CTS0		((uint32_t)1U << 3U)
-#define	GPSR5_TX0		((uint32_t)1U << 2U)
-#define	GPSR5_RX0		((uint32_t)1U << 1U)
-#define	GPSR5_SCK0		((uint32_t)1U << 0U)
-#define	GPSR6_USB31_OVC		((uint32_t)1U << 31U)
-#define	GPSR6_USB31_PWEN	((uint32_t)1U << 30U)
-#define	GPSR6_USB30_OVC		((uint32_t)1U << 29U)
-#define	GPSR6_USB30_PWEN	((uint32_t)1U << 28U)
-#define	GPSR6_USB1_OVC		((uint32_t)1U << 27U)
-#define	GPSR6_USB1_PWEN		((uint32_t)1U << 26U)
-#define	GPSR6_USB0_OVC		((uint32_t)1U << 25U)
-#define	GPSR6_USB0_PWEN		((uint32_t)1U << 24U)
-#define	GPSR6_AUDIO_CLKB_B	((uint32_t)1U << 23U)
-#define	GPSR6_AUDIO_CLKA_A	((uint32_t)1U << 22U)
-#define	GPSR6_SSI_SDATA9_A	((uint32_t)1U << 21U)
-#define	GPSR6_SSI_SDATA8	((uint32_t)1U << 20U)
-#define	GPSR6_SSI_SDATA7	((uint32_t)1U << 19U)
-#define	GPSR6_SSI_WS78		((uint32_t)1U << 18U)
-#define	GPSR6_SSI_SCK78		((uint32_t)1U << 17U)
-#define	GPSR6_SSI_SDATA6	((uint32_t)1U << 16U)
-#define	GPSR6_SSI_WS6		((uint32_t)1U << 15U)
-#define	GPSR6_SSI_SCK6		((uint32_t)1U << 14U)
-#define	GPSR6_SSI_SDATA5	((uint32_t)1U << 13U)
-#define	GPSR6_SSI_WS5		((uint32_t)1U << 12U)
-#define	GPSR6_SSI_SCK5		((uint32_t)1U << 11U)
-#define	GPSR6_SSI_SDATA4	((uint32_t)1U << 10U)
-#define	GPSR6_SSI_WS4		((uint32_t)1U << 9U)
-#define	GPSR6_SSI_SCK4		((uint32_t)1U << 8U)
-#define	GPSR6_SSI_SDATA3	((uint32_t)1U << 7U)
-#define	GPSR6_SSI_WS34		((uint32_t)1U << 6U)
-#define	GPSR6_SSI_SCK34		((uint32_t)1U << 5U)
-#define	GPSR6_SSI_SDATA2_A	((uint32_t)1U << 4U)
-#define	GPSR6_SSI_SDATA1_A	((uint32_t)1U << 3U)
-#define	GPSR6_SSI_SDATA0	((uint32_t)1U << 2U)
-#define	GPSR6_SSI_WS0129	((uint32_t)1U << 1U)
-#define	GPSR6_SSI_SCK0129	((uint32_t)1U << 0U)
-#define	GPSR7_HDMI1_CEC		((uint32_t)1U << 3U)
-#define	GPSR7_HDMI0_CEC		((uint32_t)1U << 2U)
-#define	GPSR7_AVS2		((uint32_t)1U << 1U)
-#define	GPSR7_AVS1		((uint32_t)1U << 0U)
-
-#define	IPSR_28_FUNC(x)		((uint32_t)(x) << 28U)
-#define	IPSR_24_FUNC(x)		((uint32_t)(x) << 24U)
-#define	IPSR_20_FUNC(x)		((uint32_t)(x) << 20U)
-#define	IPSR_16_FUNC(x)		((uint32_t)(x) << 16U)
-#define	IPSR_12_FUNC(x)		((uint32_t)(x) << 12U)
-#define	IPSR_8_FUNC(x)		((uint32_t)(x) << 8U)
-#define	IPSR_4_FUNC(x)		((uint32_t)(x) << 4U)
-#define	IPSR_0_FUNC(x)		((uint32_t)(x) << 0U)
-
-#define	POC_SD3_DS_33V		((uint32_t)1U << 29U)
-#define	POC_SD3_DAT7_33V	((uint32_t)1U << 28U)
-#define	POC_SD3_DAT6_33V	((uint32_t)1U << 27U)
-#define	POC_SD3_DAT5_33V	((uint32_t)1U << 26U)
-#define	POC_SD3_DAT4_33V	((uint32_t)1U << 25U)
-#define	POC_SD3_DAT3_33V	((uint32_t)1U << 24U)
-#define	POC_SD3_DAT2_33V	((uint32_t)1U << 23U)
-#define	POC_SD3_DAT1_33V	((uint32_t)1U << 22U)
-#define	POC_SD3_DAT0_33V	((uint32_t)1U << 21U)
-#define	POC_SD3_CMD_33V		((uint32_t)1U << 20U)
-#define	POC_SD3_CLK_33V		((uint32_t)1U << 19U)
-#define	POC_SD2_DS_33V		((uint32_t)1U << 18U)
-#define	POC_SD2_DAT3_33V	((uint32_t)1U << 17U)
-#define	POC_SD2_DAT2_33V	((uint32_t)1U << 16U)
-#define	POC_SD2_DAT1_33V	((uint32_t)1U << 15U)
-#define	POC_SD2_DAT0_33V	((uint32_t)1U << 14U)
-#define	POC_SD2_CMD_33V		((uint32_t)1U << 13U)
-#define	POC_SD2_CLK_33V		((uint32_t)1U << 12U)
-#define	POC_SD1_DAT3_33V	((uint32_t)1U << 11U)
-#define	POC_SD1_DAT2_33V	((uint32_t)1U << 10U)
-#define	POC_SD1_DAT1_33V	((uint32_t)1U << 9U)
-#define	POC_SD1_DAT0_33V	((uint32_t)1U << 8U)
-#define	POC_SD1_CMD_33V		((uint32_t)1U << 7U)
-#define	POC_SD1_CLK_33V		((uint32_t)1U << 6U)
-#define	POC_SD0_DAT3_33V	((uint32_t)1U << 5U)
-#define	POC_SD0_DAT2_33V	((uint32_t)1U << 4U)
-#define	POC_SD0_DAT1_33V	((uint32_t)1U << 3U)
-#define	POC_SD0_DAT0_33V	((uint32_t)1U << 2U)
-#define	POC_SD0_CMD_33V		((uint32_t)1U << 1U)
-#define	POC_SD0_CLK_33V		((uint32_t)1U << 0U)
-
-#define	DRVCTRL0_MASK		(0xCCCCCCCCU)
-#define	DRVCTRL1_MASK		(0xCCCCCCC8U)
-#define	DRVCTRL2_MASK		(0x88888888U)
-#define	DRVCTRL3_MASK		(0x88888888U)
-#define	DRVCTRL4_MASK		(0x88888888U)
-#define	DRVCTRL5_MASK		(0x88888888U)
-#define	DRVCTRL6_MASK		(0x88888888U)
-#define	DRVCTRL7_MASK		(0x88888888U)
-#define	DRVCTRL8_MASK		(0x88888888U)
-#define	DRVCTRL9_MASK		(0x88888888U)
-#define	DRVCTRL10_MASK		(0x88888888U)
-#define	DRVCTRL11_MASK		(0x888888CCU)
-#define	DRVCTRL12_MASK		(0xCCCFFFCFU)
-#define	DRVCTRL13_MASK		(0xCC888888U)
-#define	DRVCTRL14_MASK		(0x88888888U)
-#define	DRVCTRL15_MASK		(0x88888888U)
-#define	DRVCTRL16_MASK		(0x88888888U)
-#define	DRVCTRL17_MASK		(0x88888888U)
-#define	DRVCTRL18_MASK		(0x88888888U)
-#define	DRVCTRL19_MASK		(0x88888888U)
-#define	DRVCTRL20_MASK		(0x88888888U)
-#define	DRVCTRL21_MASK		(0x88888888U)
-#define	DRVCTRL22_MASK		(0x88888888U)
-#define	DRVCTRL23_MASK		(0x88888888U)
-#define	DRVCTRL24_MASK		(0x8888888FU)
-
-#define	DRVCTRL0_QSPI0_SPCLK(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL0_QSPI0_MOSI_IO0(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL0_QSPI0_MISO_IO1(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL0_QSPI0_IO2(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL0_QSPI0_IO3(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL0_QSPI0_SSL(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL0_QSPI1_SPCLK(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL0_QSPI1_MOSI_IO0(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL1_QSPI1_MISO_IO1(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL1_QSPI1_IO2(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL1_QSPI1_IO3(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL1_QSPI1_SS(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL1_RPC_INT(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL1_RPC_WP(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL1_RPC_RESET(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL1_AVB_RX_CTL(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL2_AVB_RXC(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL2_AVB_RD0(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL2_AVB_RD1(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL2_AVB_RD2(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL2_AVB_RD3(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL2_AVB_TX_CTL(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL2_AVB_TXC(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL2_AVB_TD0(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL3_AVB_TD1(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL3_AVB_TD2(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL3_AVB_TD3(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL3_AVB_TXCREFCLK(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL3_AVB_MDIO(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL3_AVB_MDC(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL3_AVB_MAGIC(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL3_AVB_PHY_INT(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL4_AVB_LINK(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL4_AVB_AVTP_MATCH(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL4_AVB_AVTP_CAPTURE(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL4_IRQ0(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL4_IRQ1(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL4_IRQ2(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL4_IRQ3(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL4_IRQ4(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL5_IRQ5(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL5_PWM0(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL5_PWM1(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL5_PWM2(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL5_A0(x)		((uint32_t)(x) << 12U)
-#define	DRVCTRL5_A1(x)		((uint32_t)(x) << 8U)
-#define	DRVCTRL5_A2(x)		((uint32_t)(x) << 4U)
-#define	DRVCTRL5_A3(x)		((uint32_t)(x) << 0U)
-#define	DRVCTRL6_A4(x)		((uint32_t)(x) << 28U)
-#define	DRVCTRL6_A5(x)		((uint32_t)(x) << 24U)
-#define	DRVCTRL6_A6(x)		((uint32_t)(x) << 20U)
-#define	DRVCTRL6_A7(x)		((uint32_t)(x) << 16U)
-#define	DRVCTRL6_A8(x)		((uint32_t)(x) << 12U)
-#define	DRVCTRL6_A9(x)		((uint32_t)(x) << 8U)
-#define	DRVCTRL6_A10(x)		((uint32_t)(x) << 4U)
-#define	DRVCTRL6_A11(x)		((uint32_t)(x) << 0U)
-#define	DRVCTRL7_A12(x)		((uint32_t)(x) << 28U)
-#define	DRVCTRL7_A13(x)		((uint32_t)(x) << 24U)
-#define	DRVCTRL7_A14(x)		((uint32_t)(x) << 20U)
-#define	DRVCTRL7_A15(x)		((uint32_t)(x) << 16U)
-#define	DRVCTRL7_A16(x)		((uint32_t)(x) << 12U)
-#define	DRVCTRL7_A17(x)		((uint32_t)(x) << 8U)
-#define	DRVCTRL7_A18(x)		((uint32_t)(x) << 4U)
-#define	DRVCTRL7_A19(x)		((uint32_t)(x) << 0U)
-#define	DRVCTRL8_CLKOUT(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL8_CS0(x)		((uint32_t)(x) << 24U)
-#define	DRVCTRL8_CS1_A2(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL8_BS(x)		((uint32_t)(x) << 16U)
-#define	DRVCTRL8_RD(x)		((uint32_t)(x) << 12U)
-#define	DRVCTRL8_RD_W(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL8_WE0(x)		((uint32_t)(x) << 4U)
-#define	DRVCTRL8_WE1(x)		((uint32_t)(x) << 0U)
-#define	DRVCTRL9_EX_WAIT0(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL9_PRESETOU(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL9_D0(x)		((uint32_t)(x) << 20U)
-#define	DRVCTRL9_D1(x)		((uint32_t)(x) << 16U)
-#define	DRVCTRL9_D2(x)		((uint32_t)(x) << 12U)
-#define	DRVCTRL9_D3(x)		((uint32_t)(x) << 8U)
-#define	DRVCTRL9_D4(x)		((uint32_t)(x) << 4U)
-#define	DRVCTRL9_D5(x)		((uint32_t)(x) << 0U)
-#define	DRVCTRL10_D6(x)		((uint32_t)(x) << 28U)
-#define	DRVCTRL10_D7(x)		((uint32_t)(x) << 24U)
-#define	DRVCTRL10_D8(x)		((uint32_t)(x) << 20U)
-#define	DRVCTRL10_D9(x)		((uint32_t)(x) << 16U)
-#define	DRVCTRL10_D10(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL10_D11(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL10_D12(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL10_D13(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL11_D14(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL11_D15(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL11_AVS1(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL11_AVS2(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL11_HDMI0_CEC(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL11_HDMI1_CEC(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL11_DU_DOTCLKIN0(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL11_DU_DOTCLKIN1(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL12_DU_DOTCLKIN2(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL12_DU_DOTCLKIN3(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL12_DU_FSCLKST(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL12_DU_TMS(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL13_TDO(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL13_ASEBRK(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL13_SD0_CLK(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL13_SD0_CMD(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL13_SD0_DAT0(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL13_SD0_DAT1(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL13_SD0_DAT2(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL13_SD0_DAT3(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL14_SD1_CLK(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL14_SD1_CMD(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL14_SD1_DAT0(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL14_SD1_DAT1(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL14_SD1_DAT2(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL14_SD1_DAT3(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL14_SD2_CLK(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL14_SD2_CMD(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL15_SD2_DAT0(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL15_SD2_DAT1(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL15_SD2_DAT2(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL15_SD2_DAT3(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL15_SD2_DS(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL15_SD3_CLK(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL15_SD3_CMD(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL15_SD3_DAT0(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL16_SD3_DAT1(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL16_SD3_DAT2(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL16_SD3_DAT3(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL16_SD3_DAT4(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL16_SD3_DAT5(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL16_SD3_DAT6(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL16_SD3_DAT7(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL16_SD3_DS(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL17_SD0_CD(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL17_SD0_WP(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL17_SD1_CD(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL17_SD1_WP(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL17_SCK0(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL17_RX0(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL17_TX0(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL17_CTS0(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL18_RTS0_TANS(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL18_RX1(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL18_TX1(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL18_CTS1(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL18_RTS1_TANS(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL18_SCK2(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL18_TX2(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL18_RX2(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL19_HSCK0(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL19_HRX0(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL19_HTX0(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL19_HCTS0(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL19_HRTS0(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL19_MSIOF0_SCK(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL19_MSIOF0_SYNC(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL19_MSIOF0_SS1(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL20_MSIOF0_TXD(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL20_MSIOF0_SS2(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL20_MSIOF0_RXD(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL20_MLB_CLK(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL20_MLB_SIG(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL20_MLB_DAT(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL20_MLB_REF(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL20_SSI_SCK0129(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL21_SSI_WS0129(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL21_SSI_SDATA0(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL21_SSI_SDATA1(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL21_SSI_SDATA2(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL21_SSI_SCK34(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL21_SSI_WS34(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL21_SSI_SDATA3(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL21_SSI_SCK4(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL22_SSI_WS4(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL22_SSI_SDATA4(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL22_SSI_SCK5(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL22_SSI_WS5(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL22_SSI_SDATA5(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL22_SSI_SCK6(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL22_SSI_WS6(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL22_SSI_SDATA6(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL23_SSI_SCK78(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL23_SSI_WS78(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL23_SSI_SDATA7(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL23_SSI_SDATA8(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL23_SSI_SDATA9(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL23_AUDIO_CLKA(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL23_AUDIO_CLKB(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL23_USB0_PWEN(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL24_USB0_OVC(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL24_USB1_PWEN(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL24_USB1_OVC(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL24_USB30_PWEN(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL24_USB30_OVC(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL24_USB31_PWEN(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL24_USB31_OVC(x)	((uint32_t)(x) << 4U)
-
-#define	MOD_SEL0_MSIOF3_A	((uint32_t)0U << 29U)
-#define	MOD_SEL0_MSIOF3_B	((uint32_t)1U << 29U)
-#define	MOD_SEL0_MSIOF3_C	((uint32_t)2U << 29U)
-#define	MOD_SEL0_MSIOF3_D	((uint32_t)3U << 29U)
-#define	MOD_SEL0_MSIOF2_A	((uint32_t)0U << 27U)
-#define	MOD_SEL0_MSIOF2_B	((uint32_t)1U << 27U)
-#define	MOD_SEL0_MSIOF2_C	((uint32_t)2U << 27U)
-#define	MOD_SEL0_MSIOF2_D	((uint32_t)3U << 27U)
-#define	MOD_SEL0_MSIOF1_A	((uint32_t)0U << 24U)
-#define	MOD_SEL0_MSIOF1_B	((uint32_t)1U << 24U)
-#define	MOD_SEL0_MSIOF1_C	((uint32_t)2U << 24U)
-#define	MOD_SEL0_MSIOF1_D	((uint32_t)3U << 24U)
-#define	MOD_SEL0_MSIOF1_E	((uint32_t)4U << 24U)
-#define	MOD_SEL0_MSIOF1_F	((uint32_t)5U << 24U)
-#define	MOD_SEL0_MSIOF1_G	((uint32_t)6U << 24U)
-#define	MOD_SEL0_LBSC_A		((uint32_t)0U << 23U)
-#define	MOD_SEL0_LBSC_B		((uint32_t)1U << 23U)
-#define	MOD_SEL0_IEBUS_A	((uint32_t)0U << 22U)
-#define	MOD_SEL0_IEBUS_B	((uint32_t)1U << 22U)
-#define	MOD_SEL0_I2C6_A		((uint32_t)0U << 20U)
-#define	MOD_SEL0_I2C6_B		((uint32_t)1U << 20U)
-#define	MOD_SEL0_I2C6_C		((uint32_t)2U << 20U)
-#define	MOD_SEL0_I2C2_A		((uint32_t)0U << 19U)
-#define	MOD_SEL0_I2C2_B		((uint32_t)1U << 19U)
-#define	MOD_SEL0_I2C1_A		((uint32_t)0U << 18U)
-#define	MOD_SEL0_I2C1_B		((uint32_t)1U << 18U)
-#define	MOD_SEL0_HSCIF4_A	((uint32_t)0U << 17U)
-#define	MOD_SEL0_HSCIF4_B	((uint32_t)1U << 17U)
-#define	MOD_SEL0_HSCIF3_A	((uint32_t)0U << 15U)
-#define	MOD_SEL0_HSCIF3_B	((uint32_t)1U << 15U)
-#define	MOD_SEL0_HSCIF3_C	((uint32_t)2U << 15U)
-#define	MOD_SEL0_HSCIF3_D	((uint32_t)3U << 15U)
-#define	MOD_SEL0_HSCIF2_A	((uint32_t)0U << 14U)
-#define	MOD_SEL0_HSCIF2_B	((uint32_t)1U << 14U)
-#define	MOD_SEL0_HSCIF1_A	((uint32_t)0U << 13U)
-#define	MOD_SEL0_HSCIF1_B	((uint32_t)1U << 13U)
-#define	MOD_SEL0_FSO_A		((uint32_t)0U << 12U)
-#define	MOD_SEL0_FSO_B		((uint32_t)1U << 12U)
-#define	MOD_SEL0_FM_A		((uint32_t)0U << 11U)
-#define	MOD_SEL0_FM_B		((uint32_t)1U << 11U)
-#define	MOD_SEL0_ETHERAVB_A	((uint32_t)0U << 10U)
-#define	MOD_SEL0_ETHERAVB_B	((uint32_t)1U << 10U)
-#define	MOD_SEL0_DRIF3_A	((uint32_t)0U << 9U)
-#define	MOD_SEL0_DRIF3_B	((uint32_t)1U << 9U)
-#define	MOD_SEL0_DRIF2_A	((uint32_t)0U << 8U)
-#define	MOD_SEL0_DRIF2_B	((uint32_t)1U << 8U)
-#define	MOD_SEL0_DRIF1_A	((uint32_t)0U << 6U)
-#define	MOD_SEL0_DRIF1_B	((uint32_t)1U << 6U)
-#define	MOD_SEL0_DRIF1_C	((uint32_t)2U << 6U)
-#define	MOD_SEL0_DRIF0_A	((uint32_t)0U << 4U)
-#define	MOD_SEL0_DRIF0_B	((uint32_t)1U << 4U)
-#define	MOD_SEL0_DRIF0_C	((uint32_t)2U << 4U)
-#define	MOD_SEL0_CANFD0_A	((uint32_t)0U << 3U)
-#define	MOD_SEL0_CANFD0_B	((uint32_t)1U << 3U)
-#define	MOD_SEL0_ADG_A		((uint32_t)0U << 1U)
-#define	MOD_SEL0_ADG_B		((uint32_t)1U << 1U)
-#define	MOD_SEL0_ADG_C		((uint32_t)2U << 1U)
-#define	MOD_SEL0_ADG_D		((uint32_t)3U << 1U)
-#define	MOD_SEL0_5LINE_A	((uint32_t)0U << 0U)
-#define	MOD_SEL0_5LINE_B	((uint32_t)1U << 0U)
-#define	MOD_SEL1_TSIF1_A	((uint32_t)0U << 30U)
-#define	MOD_SEL1_TSIF1_B	((uint32_t)1U << 30U)
-#define	MOD_SEL1_TSIF1_C	((uint32_t)2U << 30U)
-#define	MOD_SEL1_TSIF1_D	((uint32_t)3U << 30U)
-#define	MOD_SEL1_TSIF0_A	((uint32_t)0U << 27U)
-#define	MOD_SEL1_TSIF0_B	((uint32_t)1U << 27U)
-#define	MOD_SEL1_TSIF0_C	((uint32_t)2U << 27U)
-#define	MOD_SEL1_TSIF0_D	((uint32_t)3U << 27U)
-#define	MOD_SEL1_TSIF0_E	((uint32_t)4U << 27U)
-#define	MOD_SEL1_TIMER_TMU_A	((uint32_t)0U << 26U)
-#define	MOD_SEL1_TIMER_TMU_B	((uint32_t)1U << 26U)
-#define	MOD_SEL1_SSP1_1_A	((uint32_t)0U << 24U)
-#define	MOD_SEL1_SSP1_1_B	((uint32_t)1U << 24U)
-#define	MOD_SEL1_SSP1_1_C	((uint32_t)2U << 24U)
-#define	MOD_SEL1_SSP1_1_D	((uint32_t)3U << 24U)
-#define	MOD_SEL1_SSP1_0_A	((uint32_t)0U << 21U)
-#define	MOD_SEL1_SSP1_0_B	((uint32_t)1U << 21U)
-#define	MOD_SEL1_SSP1_0_C	((uint32_t)2U << 21U)
-#define	MOD_SEL1_SSP1_0_D	((uint32_t)3U << 21U)
-#define	MOD_SEL1_SSP1_0_E	((uint32_t)4U << 21U)
-#define	MOD_SEL1_SSI_A		((uint32_t)0U << 20U)
-#define	MOD_SEL1_SSI_B		((uint32_t)1U << 20U)
-#define	MOD_SEL1_SPEED_PULSE_IF_A	((uint32_t)0U << 19U)
-#define	MOD_SEL1_SPEED_PULSE_IF_B	((uint32_t)1U << 19U)
-#define	MOD_SEL1_SIMCARD_A	((uint32_t)0U << 17U)
-#define	MOD_SEL1_SIMCARD_B	((uint32_t)1U << 17U)
-#define	MOD_SEL1_SIMCARD_C	((uint32_t)2U << 17U)
-#define	MOD_SEL1_SIMCARD_D	((uint32_t)3U << 17U)
-#define	MOD_SEL1_SDHI2_A	((uint32_t)0U << 16U)
-#define	MOD_SEL1_SDHI2_B	((uint32_t)1U << 16U)
-#define	MOD_SEL1_SCIF4_A	((uint32_t)0U << 14U)
-#define	MOD_SEL1_SCIF4_B	((uint32_t)1U << 14U)
-#define	MOD_SEL1_SCIF4_C	((uint32_t)2U << 14U)
-#define	MOD_SEL1_SCIF3_A	((uint32_t)0U << 13U)
-#define	MOD_SEL1_SCIF3_B	((uint32_t)1U << 13U)
-#define	MOD_SEL1_SCIF2_A	((uint32_t)0U << 12U)
-#define	MOD_SEL1_SCIF2_B	((uint32_t)1U << 12U)
-#define	MOD_SEL1_SCIF1_A	((uint32_t)0U << 11U)
-#define	MOD_SEL1_SCIF1_B	((uint32_t)1U << 11U)
-#define	MOD_SEL1_SCIF_A		((uint32_t)0U << 10U)
-#define	MOD_SEL1_SCIF_B		((uint32_t)1U << 10U)
-#define	MOD_SEL1_REMOCON_A	((uint32_t)0U << 9U)
-#define	MOD_SEL1_REMOCON_B	((uint32_t)1U << 9U)
-#define	MOD_SEL1_RCAN0_A	((uint32_t)0U << 6U)
-#define	MOD_SEL1_RCAN0_B	((uint32_t)1U << 6U)
-#define	MOD_SEL1_PWM6_A		((uint32_t)0U << 5U)
-#define	MOD_SEL1_PWM6_B		((uint32_t)1U << 5U)
-#define	MOD_SEL1_PWM5_A		((uint32_t)0U << 4U)
-#define	MOD_SEL1_PWM5_B		((uint32_t)1U << 4U)
-#define	MOD_SEL1_PWM4_A		((uint32_t)0U << 3U)
-#define	MOD_SEL1_PWM4_B		((uint32_t)1U << 3U)
-#define	MOD_SEL1_PWM3_A		((uint32_t)0U << 2U)
-#define	MOD_SEL1_PWM3_B		((uint32_t)1U << 2U)
-#define	MOD_SEL1_PWM2_A		((uint32_t)0U << 1U)
-#define	MOD_SEL1_PWM2_B		((uint32_t)1U << 1U)
-#define	MOD_SEL1_PWM1_A		((uint32_t)0U << 0U)
-#define	MOD_SEL1_PWM1_B		((uint32_t)1U << 0U)
-#define	MOD_SEL2_I2C_5_A	((uint32_t)0U << 31U)
-#define	MOD_SEL2_I2C_5_B	((uint32_t)1U << 31U)
-#define	MOD_SEL2_I2C_3_A	((uint32_t)0U << 30U)
-#define	MOD_SEL2_I2C_3_B	((uint32_t)1U << 30U)
-#define	MOD_SEL2_I2C_0_A	((uint32_t)0U << 29U)
-#define	MOD_SEL2_I2C_0_B	((uint32_t)1U << 29U)
-#define	MOD_SEL2_VIN4_A		((uint32_t)0U << 0U)
-#define	MOD_SEL2_VIN4_B		((uint32_t)1U << 0U)
-
-static void pfc_reg_write(uint32_t addr, uint32_t data);
-
-static void pfc_reg_write(uint32_t addr, uint32_t data)
-{
-	mmio_write_32(PFC_PMMR, ~data);
-	mmio_write_32((uintptr_t) addr, data);
-}
-
-void pfc_init_h3_v1(void)
-{
-	uint32_t reg;
-
-	/* initialize module select */
-	pfc_reg_write(PFC_MOD_SEL0, MOD_SEL0_MSIOF3_A
-		      | MOD_SEL0_MSIOF2_A
-		      | MOD_SEL0_MSIOF1_A
-		      | MOD_SEL0_LBSC_A
-		      | MOD_SEL0_IEBUS_A
-		      | MOD_SEL0_I2C6_A
-		      | MOD_SEL0_I2C2_A
-		      | MOD_SEL0_I2C1_A
-		      | MOD_SEL0_HSCIF4_A
-		      | MOD_SEL0_HSCIF3_A
-		      | MOD_SEL0_HSCIF2_A
-		      | MOD_SEL0_HSCIF1_A
-		      | MOD_SEL0_FM_A
-		      | MOD_SEL0_ETHERAVB_A
-		      | MOD_SEL0_DRIF3_A
-		      | MOD_SEL0_DRIF2_A
-		      | MOD_SEL0_DRIF1_A
-		      | MOD_SEL0_DRIF0_A
-		      | MOD_SEL0_CANFD0_A
-		      | MOD_SEL0_ADG_A
-		      | MOD_SEL0_5LINE_A);
-	pfc_reg_write(PFC_MOD_SEL1, MOD_SEL1_TSIF1_A
-		      | MOD_SEL1_TSIF0_A
-		      | MOD_SEL1_TIMER_TMU_A
-		      | MOD_SEL1_SSP1_1_A
-		      | MOD_SEL1_SSP1_0_A
-		      | MOD_SEL1_SSI_A
-		      | MOD_SEL1_SPEED_PULSE_IF_A
-		      | MOD_SEL1_SIMCARD_A
-		      | MOD_SEL1_SDHI2_A
-		      | MOD_SEL1_SCIF4_A
-		      | MOD_SEL1_SCIF3_A
-		      | MOD_SEL1_SCIF2_A
-		      | MOD_SEL1_SCIF1_A
-		      | MOD_SEL1_SCIF_A
-		      | MOD_SEL1_REMOCON_A
-		      | MOD_SEL1_RCAN0_A
-		      | MOD_SEL1_PWM6_A
-		      | MOD_SEL1_PWM5_A
-		      | MOD_SEL1_PWM4_A
-		      | MOD_SEL1_PWM3_A
-		      | MOD_SEL1_PWM2_A
-		      | MOD_SEL1_PWM1_A);
-	pfc_reg_write(PFC_MOD_SEL2, MOD_SEL2_I2C_5_A
-		      | MOD_SEL2_I2C_3_A
-		      | MOD_SEL2_I2C_0_A
-		      | MOD_SEL2_VIN4_A);
-
-	/* initialize peripheral function select */
-	pfc_reg_write(PFC_IPSR0, IPSR_28_FUNC(0)
-		      | IPSR_24_FUNC(0)
-		      | IPSR_20_FUNC(0)
-		      | IPSR_16_FUNC(0)
-		      | IPSR_12_FUNC(0)
-		      | IPSR_8_FUNC(0)
-		      | IPSR_4_FUNC(0)
-		      | IPSR_0_FUNC(0));
-	pfc_reg_write(PFC_IPSR1, IPSR_28_FUNC(6)
-		      | IPSR_24_FUNC(0)
-		      | IPSR_20_FUNC(0)
-		      | IPSR_16_FUNC(0)
-		      | IPSR_12_FUNC(3)
-		      | IPSR_8_FUNC(3)
-		      | IPSR_4_FUNC(3)
-		      | IPSR_0_FUNC(3));
-	pfc_reg_write(PFC_IPSR2, IPSR_28_FUNC(0)
-		      | IPSR_24_FUNC(6)
-		      | IPSR_20_FUNC(6)
-		      | IPSR_16_FUNC(6)
-		      | IPSR_12_FUNC(6)
-		      | IPSR_8_FUNC(6)
-		      | IPSR_4_FUNC(6)
-		      | IPSR_0_FUNC(6));
-	pfc_reg_write(PFC_IPSR3, IPSR_28_FUNC(6)
-		      | IPSR_24_FUNC(6)
-		      | IPSR_20_FUNC(6)
-		      | IPSR_16_FUNC(6)
-		      | IPSR_12_FUNC(6)
-		      | IPSR_8_FUNC(0)
-		      | IPSR_4_FUNC(0)
-		      | IPSR_0_FUNC(0));
-	pfc_reg_write(PFC_IPSR4, IPSR_28_FUNC(0)
-		      | IPSR_24_FUNC(0)
-		      | IPSR_20_FUNC(0)
-		      | IPSR_16_FUNC(0)
-		      | IPSR_12_FUNC(0)
-		      | IPSR_8_FUNC(6)
-		      | IPSR_4_FUNC(6)
-		      | IPSR_0_FUNC(6));
-	pfc_reg_write(PFC_IPSR5, IPSR_28_FUNC(0)
-		      | IPSR_24_FUNC(0)
-		      | IPSR_20_FUNC(0)
-		      | IPSR_16_FUNC(0)
-		      | IPSR_12_FUNC(0)
-		      | IPSR_8_FUNC(6)
-		      | IPSR_4_FUNC(0)
-		      | IPSR_0_FUNC(0));
-	pfc_reg_write(PFC_IPSR6, IPSR_28_FUNC(6)
-		      | IPSR_24_FUNC(6)
-		      | IPSR_20_FUNC(6)
-		      | IPSR_16_FUNC(6)
-		      | IPSR_12_FUNC(6)
-		      | IPSR_8_FUNC(0)
-		      | IPSR_4_FUNC(0)
-		      | IPSR_0_FUNC(0));
-	pfc_reg_write(PFC_IPSR7, IPSR_28_FUNC(0)
-		      | IPSR_24_FUNC(0)
-		      | IPSR_20_FUNC(0)
-		      | IPSR_16_FUNC(0)
-		      | IPSR_12_FUNC(0)
-		      | IPSR_8_FUNC(6)
-		      | IPSR_4_FUNC(6)
-		      | IPSR_0_FUNC(6));
-	pfc_reg_write(PFC_IPSR8, IPSR_28_FUNC(1)
-		      | IPSR_24_FUNC(1)
-		      | IPSR_20_FUNC(1)
-		      | IPSR_16_FUNC(1)
-		      | IPSR_12_FUNC(0)
-		      | IPSR_8_FUNC(0)
-		      | IPSR_4_FUNC(0)
-		      | IPSR_0_FUNC(0));
-	pfc_reg_write(PFC_IPSR9, IPSR_28_FUNC(0)
-		      | IPSR_24_FUNC(0)
-		      | IPSR_20_FUNC(0)
-		      | IPSR_16_FUNC(0)
-		      | IPSR_12_FUNC(0)
-		      | IPSR_8_FUNC(0)
-		      | IPSR_4_FUNC(0)
-		      | IPSR_0_FUNC(0));
-	pfc_reg_write(PFC_IPSR10, IPSR_28_FUNC(0)
-		      | IPSR_24_FUNC(4)
-		      | IPSR_20_FUNC(0)
-		      | IPSR_16_FUNC(0)
-		      | IPSR_12_FUNC(0)
-		      | IPSR_8_FUNC(0)
-		      | IPSR_4_FUNC(1)
-		      | IPSR_0_FUNC(1));
-	pfc_reg_write(PFC_IPSR11, IPSR_28_FUNC(0)
-		      | IPSR_24_FUNC(0)
-		      | IPSR_20_FUNC(0)
-		      | IPSR_16_FUNC(0)
-		      | IPSR_12_FUNC(0)
-		      | IPSR_8_FUNC(4)
-		      | IPSR_4_FUNC(0)
-		      | IPSR_0_FUNC(0));
-	pfc_reg_write(PFC_IPSR12, IPSR_28_FUNC(8)
-		      | IPSR_24_FUNC(0)
-		      | IPSR_20_FUNC(0)
-		      | IPSR_16_FUNC(0)
-		      | IPSR_12_FUNC(0)
-		      | IPSR_8_FUNC(3)
-		      | IPSR_4_FUNC(0)
-		      | IPSR_0_FUNC(0));
-	pfc_reg_write(PFC_IPSR13, IPSR_28_FUNC(0)
-		      | IPSR_24_FUNC(0)
-		      | IPSR_20_FUNC(0)
-		      | IPSR_16_FUNC(0)
-		      | IPSR_12_FUNC(0)
-		      | IPSR_8_FUNC(0)
-		      | IPSR_4_FUNC(3)
-		      | IPSR_0_FUNC(8));
-	pfc_reg_write(PFC_IPSR14, IPSR_28_FUNC(0)
-		      | IPSR_24_FUNC(0)
-		      | IPSR_20_FUNC(0)
-		      | IPSR_16_FUNC(0)
-		      | IPSR_12_FUNC(0)
-		      | IPSR_8_FUNC(0)
-		      | IPSR_4_FUNC(0)
-		      | IPSR_0_FUNC(0));
-	pfc_reg_write(PFC_IPSR15, IPSR_28_FUNC(0)
-		      | IPSR_24_FUNC(0)
-		      | IPSR_20_FUNC(0)
-		      | IPSR_16_FUNC(0)
-		      | IPSR_12_FUNC(0)
-		      | IPSR_8_FUNC(0)
-		      | IPSR_4_FUNC(1)
-		      | IPSR_0_FUNC(1));
-	pfc_reg_write(PFC_IPSR16, IPSR_28_FUNC(0)
-		      | IPSR_24_FUNC(0)
-		      | IPSR_20_FUNC(0)
-		      | IPSR_16_FUNC(0)
-		      | IPSR_12_FUNC(0)
-		      | IPSR_8_FUNC(0)
-		      | IPSR_4_FUNC(1)
-		      | IPSR_0_FUNC(0));
-	pfc_reg_write(PFC_IPSR17, IPSR_4_FUNC(0)
-		      | IPSR_0_FUNC(0));
-
-	/* initialize GPIO/perihperal function select */
-	pfc_reg_write(PFC_GPSR0, GPSR0_D15
-		      | GPSR0_D14
-		      | GPSR0_D13
-		      | GPSR0_D12
-		      | GPSR0_D11
-		      | GPSR0_D10
-		      | GPSR0_D9
-		      | GPSR0_D8);
-	pfc_reg_write(PFC_GPSR1, GPSR1_EX_WAIT0_A
-		      | GPSR1_A19
-		      | GPSR1_A18
-		      | GPSR1_A17
-		      | GPSR1_A16
-		      | GPSR1_A15
-		      | GPSR1_A14
-		      | GPSR1_A13
-		      | GPSR1_A12
-		      | GPSR1_A7
-		      | GPSR1_A6
-		      | GPSR1_A5
-		      | GPSR1_A4
-		      | GPSR1_A3
-		      | GPSR1_A2
-		      | GPSR1_A1
-		      | GPSR1_A0);
-	pfc_reg_write(PFC_GPSR2, GPSR2_AVB_AVTP_CAPTURE_A
-		      | GPSR2_AVB_AVTP_MATCH_A
-		      | GPSR2_AVB_LINK
-		      | GPSR2_AVB_PHY_INT
-		      | GPSR2_AVB_MDC
-		      | GPSR2_PWM2_A
-		      | GPSR2_PWM1_A
-		      | GPSR2_IRQ5
-		      | GPSR2_IRQ4
-		      | GPSR2_IRQ3
-		      | GPSR2_IRQ2
-		      | GPSR2_IRQ1
-		      | GPSR2_IRQ0);
-	pfc_reg_write(PFC_GPSR3, GPSR3_SD0_WP
-		      | GPSR3_SD0_CD
-		      | GPSR3_SD1_DAT3
-		      | GPSR3_SD1_DAT2
-		      | GPSR3_SD1_DAT1
-		      | GPSR3_SD1_DAT0
-		      | GPSR3_SD0_DAT3
-		      | GPSR3_SD0_DAT2
-		      | GPSR3_SD0_DAT1
-		      | GPSR3_SD0_DAT0
-		      | GPSR3_SD0_CMD
-		      | GPSR3_SD0_CLK);
-	pfc_reg_write(PFC_GPSR4, GPSR4_SD3_DAT7
-		      | GPSR4_SD3_DAT6
-		      | GPSR4_SD3_DAT3
-		      | GPSR4_SD3_DAT2
-		      | GPSR4_SD3_DAT1
-		      | GPSR4_SD3_DAT0
-		      | GPSR4_SD3_CMD
-		      | GPSR4_SD3_CLK
-		      | GPSR4_SD2_DS
-		      | GPSR4_SD2_DAT3
-		      | GPSR4_SD2_DAT2
-		      | GPSR4_SD2_DAT1
-		      | GPSR4_SD2_DAT0
-		      | GPSR4_SD2_CMD
-		      | GPSR4_SD2_CLK);
-	pfc_reg_write(PFC_GPSR5, GPSR5_MSIOF0_SS2
-		      | GPSR5_MSIOF0_SS1
-		      | GPSR5_MSIOF0_SYNC
-		      | GPSR5_HRTS0
-		      | GPSR5_HCTS0
-		      | GPSR5_HTX0
-		      | GPSR5_HRX0
-		      | GPSR5_HSCK0
-		      | GPSR5_RX2_A
-		      | GPSR5_TX2_A
-		      | GPSR5_SCK2
-		      | GPSR5_RTS1_TANS
-		      | GPSR5_CTS1
-		      | GPSR5_TX1_A
-		      | GPSR5_RX1_A
-		      | GPSR5_RTS0_TANS
-		      | GPSR5_SCK0);
-	pfc_reg_write(PFC_GPSR6, GPSR6_USB30_OVC
-		      | GPSR6_USB30_PWEN
-		      | GPSR6_USB1_OVC
-		      | GPSR6_USB1_PWEN
-		      | GPSR6_USB0_OVC
-		      | GPSR6_USB0_PWEN
-		      | GPSR6_AUDIO_CLKB_B
-		      | GPSR6_AUDIO_CLKA_A
-		      | GPSR6_SSI_SDATA8
-		      | GPSR6_SSI_SDATA7
-		      | GPSR6_SSI_WS78
-		      | GPSR6_SSI_SCK78
-		      | GPSR6_SSI_WS6
-		      | GPSR6_SSI_SCK6
-		      | GPSR6_SSI_SDATA4
-		      | GPSR6_SSI_WS4
-		      | GPSR6_SSI_SCK4
-		      | GPSR6_SSI_SDATA1_A
-		      | GPSR6_SSI_SDATA0
-		      | GPSR6_SSI_WS0129
-		      | GPSR6_SSI_SCK0129);
-	pfc_reg_write(PFC_GPSR7, GPSR7_HDMI1_CEC
-		      | GPSR7_HDMI0_CEC
-		      | GPSR7_AVS2
-		      | GPSR7_AVS1);
-
-	/* initialize POC control register */
-	pfc_reg_write(PFC_POCCTRL0, POC_SD3_DS_33V
-		      | POC_SD3_DAT7_33V
-		      | POC_SD3_DAT6_33V
-		      | POC_SD3_DAT5_33V
-		      | POC_SD3_DAT4_33V
-		      | POC_SD3_DAT3_33V
-		      | POC_SD3_DAT2_33V
-		      | POC_SD3_DAT1_33V
-		      | POC_SD3_DAT0_33V
-		      | POC_SD3_CMD_33V
-		      | POC_SD3_CLK_33V
-		      | POC_SD0_DAT3_33V
-		      | POC_SD0_DAT2_33V
-		      | POC_SD0_DAT1_33V
-		      | POC_SD0_DAT0_33V
-		      | POC_SD0_CMD_33V
-		      | POC_SD0_CLK_33V);
-
-	/* initialize DRV control register */
-	reg = mmio_read_32(PFC_DRVCTRL0);
-	reg = ((reg & DRVCTRL0_MASK) | DRVCTRL0_QSPI0_SPCLK(3)
-	       | DRVCTRL0_QSPI0_MOSI_IO0(3)
-	       | DRVCTRL0_QSPI0_MISO_IO1(3)
-	       | DRVCTRL0_QSPI0_IO2(3)
-	       | DRVCTRL0_QSPI0_IO3(3)
-	       | DRVCTRL0_QSPI0_SSL(3)
-	       | DRVCTRL0_QSPI1_SPCLK(3)
-	       | DRVCTRL0_QSPI1_MOSI_IO0(3));
-	pfc_reg_write(PFC_DRVCTRL0, reg);
-	reg = mmio_read_32(PFC_DRVCTRL1);
-	reg = ((reg & DRVCTRL1_MASK) | DRVCTRL1_QSPI1_MISO_IO1(3)
-	       | DRVCTRL1_QSPI1_IO2(3)
-	       | DRVCTRL1_QSPI1_IO3(3)
-	       | DRVCTRL1_QSPI1_SS(3)
-	       | DRVCTRL1_RPC_INT(3)
-	       | DRVCTRL1_RPC_WP(3)
-	       | DRVCTRL1_RPC_RESET(3)
-	       | DRVCTRL1_AVB_RX_CTL(7));
-	pfc_reg_write(PFC_DRVCTRL1, reg);
-	reg = mmio_read_32(PFC_DRVCTRL2);
-	reg = ((reg & DRVCTRL2_MASK) | DRVCTRL2_AVB_RXC(7)
-	       | DRVCTRL2_AVB_RD0(7)
-	       | DRVCTRL2_AVB_RD1(7)
-	       | DRVCTRL2_AVB_RD2(7)
-	       | DRVCTRL2_AVB_RD3(7)
-	       | DRVCTRL2_AVB_TX_CTL(3)
-	       | DRVCTRL2_AVB_TXC(3)
-	       | DRVCTRL2_AVB_TD0(3));
-	pfc_reg_write(PFC_DRVCTRL2, reg);
-	reg = mmio_read_32(PFC_DRVCTRL3);
-	reg = ((reg & DRVCTRL3_MASK) | DRVCTRL3_AVB_TD1(3)
-	       | DRVCTRL3_AVB_TD2(3)
-	       | DRVCTRL3_AVB_TD3(3)
-	       | DRVCTRL3_AVB_TXCREFCLK(7)
-	       | DRVCTRL3_AVB_MDIO(7)
-	       | DRVCTRL3_AVB_MDC(7)
-	       | DRVCTRL3_AVB_MAGIC(7)
-	       | DRVCTRL3_AVB_PHY_INT(7));
-	pfc_reg_write(PFC_DRVCTRL3, reg);
-	reg = mmio_read_32(PFC_DRVCTRL4);
-	reg = ((reg & DRVCTRL4_MASK) | DRVCTRL4_AVB_LINK(7)
-	       | DRVCTRL4_AVB_AVTP_MATCH(7)
-	       | DRVCTRL4_AVB_AVTP_CAPTURE(7)
-	       | DRVCTRL4_IRQ0(7)
-	       | DRVCTRL4_IRQ1(7)
-	       | DRVCTRL4_IRQ2(7)
-	       | DRVCTRL4_IRQ3(7)
-	       | DRVCTRL4_IRQ4(7));
-	pfc_reg_write(PFC_DRVCTRL4, reg);
-	reg = mmio_read_32(PFC_DRVCTRL5);
-	reg = ((reg & DRVCTRL5_MASK) | DRVCTRL5_IRQ5(7)
-	       | DRVCTRL5_PWM0(7)
-	       | DRVCTRL5_PWM1(7)
-	       | DRVCTRL5_PWM2(7)
-	       | DRVCTRL5_A0(3)
-	       | DRVCTRL5_A1(3)
-	       | DRVCTRL5_A2(3)
-	       | DRVCTRL5_A3(3));
-	pfc_reg_write(PFC_DRVCTRL5, reg);
-	reg = mmio_read_32(PFC_DRVCTRL6);
-	reg = ((reg & DRVCTRL6_MASK) | DRVCTRL6_A4(3)
-	       | DRVCTRL6_A5(3)
-	       | DRVCTRL6_A6(3)
-	       | DRVCTRL6_A7(3)
-	       | DRVCTRL6_A8(7)
-	       | DRVCTRL6_A9(7)
-	       | DRVCTRL6_A10(7)
-	       | DRVCTRL6_A11(7));
-	pfc_reg_write(PFC_DRVCTRL6, reg);
-	reg = mmio_read_32(PFC_DRVCTRL7);
-	reg = ((reg & DRVCTRL7_MASK) | DRVCTRL7_A12(3)
-	       | DRVCTRL7_A13(3)
-	       | DRVCTRL7_A14(3)
-	       | DRVCTRL7_A15(3)
-	       | DRVCTRL7_A16(3)
-	       | DRVCTRL7_A17(3)
-	       | DRVCTRL7_A18(3)
-	       | DRVCTRL7_A19(3));
-	pfc_reg_write(PFC_DRVCTRL7, reg);
-	reg = mmio_read_32(PFC_DRVCTRL8);
-	reg = ((reg & DRVCTRL8_MASK) | DRVCTRL8_CLKOUT(7)
-	       | DRVCTRL8_CS0(7)
-	       | DRVCTRL8_CS1_A2(7)
-	       | DRVCTRL8_BS(7)
-	       | DRVCTRL8_RD(7)
-	       | DRVCTRL8_RD_W(7)
-	       | DRVCTRL8_WE0(7)
-	       | DRVCTRL8_WE1(7));
-	pfc_reg_write(PFC_DRVCTRL8, reg);
-	reg = mmio_read_32(PFC_DRVCTRL9);
-	reg = ((reg & DRVCTRL9_MASK) | DRVCTRL9_EX_WAIT0(7)
-	       | DRVCTRL9_PRESETOU(7)
-	       | DRVCTRL9_D0(7)
-	       | DRVCTRL9_D1(7)
-	       | DRVCTRL9_D2(7)
-	       | DRVCTRL9_D3(7)
-	       | DRVCTRL9_D4(7)
-	       | DRVCTRL9_D5(7));
-	pfc_reg_write(PFC_DRVCTRL9, reg);
-	reg = mmio_read_32(PFC_DRVCTRL10);
-	reg = ((reg & DRVCTRL10_MASK) | DRVCTRL10_D6(7)
-	       | DRVCTRL10_D7(7)
-	       | DRVCTRL10_D8(3)
-	       | DRVCTRL10_D9(3)
-	       | DRVCTRL10_D10(3)
-	       | DRVCTRL10_D11(3)
-	       | DRVCTRL10_D12(3)
-	       | DRVCTRL10_D13(3));
-	pfc_reg_write(PFC_DRVCTRL10, reg);
-	reg = mmio_read_32(PFC_DRVCTRL11);
-	reg = ((reg & DRVCTRL11_MASK) | DRVCTRL11_D14(3)
-	       | DRVCTRL11_D15(3)
-	       | DRVCTRL11_AVS1(7)
-	       | DRVCTRL11_AVS2(7)
-	       | DRVCTRL11_HDMI0_CEC(7)
-	       | DRVCTRL11_HDMI1_CEC(7)
-	       | DRVCTRL11_DU_DOTCLKIN0(3)
-	       | DRVCTRL11_DU_DOTCLKIN1(3));
-	pfc_reg_write(PFC_DRVCTRL11, reg);
-	reg = mmio_read_32(PFC_DRVCTRL12);
-	reg = ((reg & DRVCTRL12_MASK) | DRVCTRL12_DU_DOTCLKIN2(3)
-	       | DRVCTRL12_DU_DOTCLKIN3(3)
-	       | DRVCTRL12_DU_FSCLKST(3)
-	       | DRVCTRL12_DU_TMS(3));
-	pfc_reg_write(PFC_DRVCTRL12, reg);
-	reg = mmio_read_32(PFC_DRVCTRL13);
-	reg = ((reg & DRVCTRL13_MASK) | DRVCTRL13_TDO(3)
-	       | DRVCTRL13_ASEBRK(3)
-	       | DRVCTRL13_SD0_CLK(2)
-	       | DRVCTRL13_SD0_CMD(2)
-	       | DRVCTRL13_SD0_DAT0(2)
-	       | DRVCTRL13_SD0_DAT1(2)
-	       | DRVCTRL13_SD0_DAT2(2)
-	       | DRVCTRL13_SD0_DAT3(2));
-	pfc_reg_write(PFC_DRVCTRL13, reg);
-	reg = mmio_read_32(PFC_DRVCTRL14);
-	reg = ((reg & DRVCTRL14_MASK) | DRVCTRL14_SD1_CLK(7)
-	       | DRVCTRL14_SD1_CMD(7)
-	       | DRVCTRL14_SD1_DAT0(5)
-	       | DRVCTRL14_SD1_DAT1(5)
-	       | DRVCTRL14_SD1_DAT2(5)
-	       | DRVCTRL14_SD1_DAT3(5)
-	       | DRVCTRL14_SD2_CLK(5)
-	       | DRVCTRL14_SD2_CMD(5));
-	pfc_reg_write(PFC_DRVCTRL14, reg);
-	reg = mmio_read_32(PFC_DRVCTRL15);
-	reg = ((reg & DRVCTRL15_MASK) | DRVCTRL15_SD2_DAT0(5)
-	       | DRVCTRL15_SD2_DAT1(5)
-	       | DRVCTRL15_SD2_DAT2(5)
-	       | DRVCTRL15_SD2_DAT3(5)
-	       | DRVCTRL15_SD2_DS(5)
-	       | DRVCTRL15_SD3_CLK(2)
-	       | DRVCTRL15_SD3_CMD(2)
-	       | DRVCTRL15_SD3_DAT0(2));
-	pfc_reg_write(PFC_DRVCTRL15, reg);
-	reg = mmio_read_32(PFC_DRVCTRL16);
-	reg = ((reg & DRVCTRL16_MASK) | DRVCTRL16_SD3_DAT1(2)
-	       | DRVCTRL16_SD3_DAT2(2)
-	       | DRVCTRL16_SD3_DAT3(2)
-	       | DRVCTRL16_SD3_DAT4(7)
-	       | DRVCTRL16_SD3_DAT5(7)
-	       | DRVCTRL16_SD3_DAT6(7)
-	       | DRVCTRL16_SD3_DAT7(7)
-	       | DRVCTRL16_SD3_DS(7));
-	pfc_reg_write(PFC_DRVCTRL16, reg);
-	reg = mmio_read_32(PFC_DRVCTRL17);
-	reg = ((reg & DRVCTRL17_MASK) | DRVCTRL17_SD0_CD(7)
-	       | DRVCTRL17_SD0_WP(7)
-	       | DRVCTRL17_SD1_CD(7)
-	       | DRVCTRL17_SD1_WP(7)
-	       | DRVCTRL17_SCK0(7)
-	       | DRVCTRL17_RX0(7)
-	       | DRVCTRL17_TX0(7)
-	       | DRVCTRL17_CTS0(7));
-	pfc_reg_write(PFC_DRVCTRL17, reg);
-	reg = mmio_read_32(PFC_DRVCTRL18);
-	reg = ((reg & DRVCTRL18_MASK) | DRVCTRL18_RTS0_TANS(7)
-	       | DRVCTRL18_RX1(7)
-	       | DRVCTRL18_TX1(7)
-	       | DRVCTRL18_CTS1(7)
-	       | DRVCTRL18_RTS1_TANS(7)
-	       | DRVCTRL18_SCK2(7)
-	       | DRVCTRL18_TX2(7)
-	       | DRVCTRL18_RX2(7));
-	pfc_reg_write(PFC_DRVCTRL18, reg);
-	reg = mmio_read_32(PFC_DRVCTRL19);
-	reg = ((reg & DRVCTRL19_MASK) | DRVCTRL19_HSCK0(7)
-	       | DRVCTRL19_HRX0(7)
-	       | DRVCTRL19_HTX0(7)
-	       | DRVCTRL19_HCTS0(7)
-	       | DRVCTRL19_HRTS0(7)
-	       | DRVCTRL19_MSIOF0_SCK(7)
-	       | DRVCTRL19_MSIOF0_SYNC(7)
-	       | DRVCTRL19_MSIOF0_SS1(7));
-	pfc_reg_write(PFC_DRVCTRL19, reg);
-	reg = mmio_read_32(PFC_DRVCTRL20);
-	reg = ((reg & DRVCTRL20_MASK) | DRVCTRL20_MSIOF0_TXD(7)
-	       | DRVCTRL20_MSIOF0_SS2(7)
-	       | DRVCTRL20_MSIOF0_RXD(7)
-	       | DRVCTRL20_MLB_CLK(7)
-	       | DRVCTRL20_MLB_SIG(7)
-	       | DRVCTRL20_MLB_DAT(7)
-	       | DRVCTRL20_MLB_REF(7)
-	       | DRVCTRL20_SSI_SCK0129(7));
-	pfc_reg_write(PFC_DRVCTRL20, reg);
-	reg = mmio_read_32(PFC_DRVCTRL21);
-	reg = ((reg & DRVCTRL21_MASK) | DRVCTRL21_SSI_WS0129(7)
-	       | DRVCTRL21_SSI_SDATA0(7)
-	       | DRVCTRL21_SSI_SDATA1(7)
-	       | DRVCTRL21_SSI_SDATA2(7)
-	       | DRVCTRL21_SSI_SCK34(7)
-	       | DRVCTRL21_SSI_WS34(7)
-	       | DRVCTRL21_SSI_SDATA3(7)
-	       | DRVCTRL21_SSI_SCK4(7));
-	pfc_reg_write(PFC_DRVCTRL21, reg);
-	reg = mmio_read_32(PFC_DRVCTRL22);
-	reg = ((reg & DRVCTRL22_MASK) | DRVCTRL22_SSI_WS4(7)
-	       | DRVCTRL22_SSI_SDATA4(7)
-	       | DRVCTRL22_SSI_SCK5(7)
-	       | DRVCTRL22_SSI_WS5(7)
-	       | DRVCTRL22_SSI_SDATA5(7)
-	       | DRVCTRL22_SSI_SCK6(7)
-	       | DRVCTRL22_SSI_WS6(7)
-	       | DRVCTRL22_SSI_SDATA6(7));
-	pfc_reg_write(PFC_DRVCTRL22, reg);
-	reg = mmio_read_32(PFC_DRVCTRL23);
-	reg = ((reg & DRVCTRL23_MASK) | DRVCTRL23_SSI_SCK78(7)
-	       | DRVCTRL23_SSI_WS78(7)
-	       | DRVCTRL23_SSI_SDATA7(7)
-	       | DRVCTRL23_SSI_SDATA8(7)
-	       | DRVCTRL23_SSI_SDATA9(7)
-	       | DRVCTRL23_AUDIO_CLKA(7)
-	       | DRVCTRL23_AUDIO_CLKB(7)
-	       | DRVCTRL23_USB0_PWEN(7));
-	pfc_reg_write(PFC_DRVCTRL23, reg);
-	reg = mmio_read_32(PFC_DRVCTRL24);
-	reg = ((reg & DRVCTRL24_MASK) | DRVCTRL24_USB0_OVC(7)
-	       | DRVCTRL24_USB1_PWEN(7)
-	       | DRVCTRL24_USB1_OVC(7)
-	       | DRVCTRL24_USB30_PWEN(7)
-	       | DRVCTRL24_USB30_OVC(7)
-	       | DRVCTRL24_USB31_PWEN(7)
-	       | DRVCTRL24_USB31_OVC(7));
-	pfc_reg_write(PFC_DRVCTRL24, reg);
-
-	/* initialize LSI pin pull-up/down control */
-	pfc_reg_write(PFC_PUD0, 0x00005FBFU);
-	pfc_reg_write(PFC_PUD1, 0x00300FFEU);
-	pfc_reg_write(PFC_PUD2, 0x330001E6U);
-	pfc_reg_write(PFC_PUD3, 0x000002E0U);
-	pfc_reg_write(PFC_PUD4, 0xFFFFFF00U);
-	pfc_reg_write(PFC_PUD5, 0x7F5FFF87U);
-	pfc_reg_write(PFC_PUD6, 0x00000055U);
-
-	/* initialize LSI pin pull-enable register */
-	pfc_reg_write(PFC_PUEN0, 0x00000FFFU);
-	pfc_reg_write(PFC_PUEN1, 0x00100234U);
-	pfc_reg_write(PFC_PUEN2, 0x000004C4U);
-	pfc_reg_write(PFC_PUEN3, 0x00000200U);
-	pfc_reg_write(PFC_PUEN4, 0x3E000000U);
-	pfc_reg_write(PFC_PUEN5, 0x1F000805U);
-	pfc_reg_write(PFC_PUEN6, 0x00000006U);
-
-	/* initialize positive/negative logic select */
-	mmio_write_32(GPIO_POSNEG0, 0x00000000U);
-	mmio_write_32(GPIO_POSNEG1, 0x00000000U);
-	mmio_write_32(GPIO_POSNEG2, 0x00000000U);
-	mmio_write_32(GPIO_POSNEG3, 0x00000000U);
-	mmio_write_32(GPIO_POSNEG4, 0x00000000U);
-	mmio_write_32(GPIO_POSNEG5, 0x00000000U);
-	mmio_write_32(GPIO_POSNEG6, 0x00000000U);
-
-	/* initialize general IO/interrupt switching */
-	mmio_write_32(GPIO_IOINTSEL0, 0x00000000U);
-	mmio_write_32(GPIO_IOINTSEL1, 0x00000000U);
-	mmio_write_32(GPIO_IOINTSEL2, 0x00000000U);
-	mmio_write_32(GPIO_IOINTSEL3, 0x00000000U);
-	mmio_write_32(GPIO_IOINTSEL4, 0x00000000U);
-	mmio_write_32(GPIO_IOINTSEL5, 0x00000000U);
-	mmio_write_32(GPIO_IOINTSEL6, 0x00000000U);
-
-	/* initialize general output register */
-	mmio_write_32(GPIO_OUTDT1, 0x00000000U);
-	mmio_write_32(GPIO_OUTDT2, 0x00000400U);
-	mmio_write_32(GPIO_OUTDT3, 0x0000C000U);
-	mmio_write_32(GPIO_OUTDT5, 0x00000006U);
-	mmio_write_32(GPIO_OUTDT6, 0x00003880U);
-
-	/* initialize general input/output switching */
-	mmio_write_32(GPIO_INOUTSEL0, 0x00000000U);
-	mmio_write_32(GPIO_INOUTSEL1, 0x01000A00U);
-	mmio_write_32(GPIO_INOUTSEL2, 0x00000400U);
-	mmio_write_32(GPIO_INOUTSEL3, 0x0000C000U);
-	mmio_write_32(GPIO_INOUTSEL4, 0x00000000U);
-#if (RCAR_GEN3_ULCB == 1)
-	mmio_write_32(GPIO_INOUTSEL5, 0x0000000EU);
-#else
-	mmio_write_32(GPIO_INOUTSEL5, 0x0000020EU);
-#endif
-	mmio_write_32(GPIO_INOUTSEL6, 0x00013880U);
-}
diff --git a/drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v2.c b/drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v2.c
deleted file mode 100644
index fd9be59..0000000
--- a/drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v2.c
+++ /dev/null
@@ -1,1453 +0,0 @@
-/*
- * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <stdint.h>		/* for uint32_t */
-
-#include <lib/mmio.h>
-
-#include "pfc_init_h3_v2.h"
-#include "rcar_def.h"
-
-/* GPIO base address */
-#define	GPIO_BASE		(0xE6050000U)
-
-/* GPIO registers */
-#define	GPIO_IOINTSEL0		(GPIO_BASE + 0x0000U)
-#define	GPIO_INOUTSEL0		(GPIO_BASE + 0x0004U)
-#define	GPIO_OUTDT0		(GPIO_BASE + 0x0008U)
-#define	GPIO_INDT0		(GPIO_BASE + 0x000CU)
-#define	GPIO_INTDT0		(GPIO_BASE + 0x0010U)
-#define	GPIO_INTCLR0		(GPIO_BASE + 0x0014U)
-#define	GPIO_INTMSK0		(GPIO_BASE + 0x0018U)
-#define	GPIO_MSKCLR0		(GPIO_BASE + 0x001CU)
-#define	GPIO_POSNEG0		(GPIO_BASE + 0x0020U)
-#define	GPIO_EDGLEVEL0		(GPIO_BASE + 0x0024U)
-#define	GPIO_FILONOFF0		(GPIO_BASE + 0x0028U)
-#define	GPIO_INTMSKS0		(GPIO_BASE + 0x0038U)
-#define	GPIO_MSKCLRS0		(GPIO_BASE + 0x003CU)
-#define	GPIO_OUTDTSEL0		(GPIO_BASE + 0x0040U)
-#define	GPIO_OUTDTH0		(GPIO_BASE + 0x0044U)
-#define	GPIO_OUTDTL0		(GPIO_BASE + 0x0048U)
-#define	GPIO_BOTHEDGE0		(GPIO_BASE + 0x004CU)
-#define	GPIO_IOINTSEL1		(GPIO_BASE + 0x1000U)
-#define	GPIO_INOUTSEL1		(GPIO_BASE + 0x1004U)
-#define	GPIO_OUTDT1		(GPIO_BASE + 0x1008U)
-#define	GPIO_INDT1		(GPIO_BASE + 0x100CU)
-#define	GPIO_INTDT1		(GPIO_BASE + 0x1010U)
-#define	GPIO_INTCLR1		(GPIO_BASE + 0x1014U)
-#define	GPIO_INTMSK1		(GPIO_BASE + 0x1018U)
-#define	GPIO_MSKCLR1		(GPIO_BASE + 0x101CU)
-#define	GPIO_POSNEG1		(GPIO_BASE + 0x1020U)
-#define	GPIO_EDGLEVEL1		(GPIO_BASE + 0x1024U)
-#define	GPIO_FILONOFF1		(GPIO_BASE + 0x1028U)
-#define	GPIO_INTMSKS1		(GPIO_BASE + 0x1038U)
-#define	GPIO_MSKCLRS1		(GPIO_BASE + 0x103CU)
-#define	GPIO_OUTDTSEL1		(GPIO_BASE + 0x1040U)
-#define	GPIO_OUTDTH1		(GPIO_BASE + 0x1044U)
-#define	GPIO_OUTDTL1		(GPIO_BASE + 0x1048U)
-#define	GPIO_BOTHEDGE1		(GPIO_BASE + 0x104CU)
-#define	GPIO_IOINTSEL2		(GPIO_BASE + 0x2000U)
-#define	GPIO_INOUTSEL2		(GPIO_BASE + 0x2004U)
-#define	GPIO_OUTDT2		(GPIO_BASE + 0x2008U)
-#define	GPIO_INDT2		(GPIO_BASE + 0x200CU)
-#define	GPIO_INTDT2		(GPIO_BASE + 0x2010U)
-#define	GPIO_INTCLR2		(GPIO_BASE + 0x2014U)
-#define	GPIO_INTMSK2		(GPIO_BASE + 0x2018U)
-#define	GPIO_MSKCLR2		(GPIO_BASE + 0x201CU)
-#define	GPIO_POSNEG2		(GPIO_BASE + 0x2020U)
-#define	GPIO_EDGLEVEL2		(GPIO_BASE + 0x2024U)
-#define	GPIO_FILONOFF2		(GPIO_BASE + 0x2028U)
-#define	GPIO_INTMSKS2		(GPIO_BASE + 0x2038U)
-#define	GPIO_MSKCLRS2		(GPIO_BASE + 0x203CU)
-#define	GPIO_OUTDTSEL2		(GPIO_BASE + 0x2040U)
-#define	GPIO_OUTDTH2		(GPIO_BASE + 0x2044U)
-#define	GPIO_OUTDTL2		(GPIO_BASE + 0x2048U)
-#define	GPIO_BOTHEDGE2		(GPIO_BASE + 0x204CU)
-#define	GPIO_IOINTSEL3		(GPIO_BASE + 0x3000U)
-#define	GPIO_INOUTSEL3		(GPIO_BASE + 0x3004U)
-#define	GPIO_OUTDT3		(GPIO_BASE + 0x3008U)
-#define	GPIO_INDT3		(GPIO_BASE + 0x300CU)
-#define	GPIO_INTDT3		(GPIO_BASE + 0x3010U)
-#define	GPIO_INTCLR3		(GPIO_BASE + 0x3014U)
-#define	GPIO_INTMSK3		(GPIO_BASE + 0x3018U)
-#define	GPIO_MSKCLR3		(GPIO_BASE + 0x301CU)
-#define	GPIO_POSNEG3		(GPIO_BASE + 0x3020U)
-#define	GPIO_EDGLEVEL3		(GPIO_BASE + 0x3024U)
-#define	GPIO_FILONOFF3		(GPIO_BASE + 0x3028U)
-#define	GPIO_INTMSKS3		(GPIO_BASE + 0x3038U)
-#define	GPIO_MSKCLRS3		(GPIO_BASE + 0x303CU)
-#define	GPIO_OUTDTSEL3		(GPIO_BASE + 0x3040U)
-#define	GPIO_OUTDTH3		(GPIO_BASE + 0x3044U)
-#define	GPIO_OUTDTL3		(GPIO_BASE + 0x3048U)
-#define	GPIO_BOTHEDGE3		(GPIO_BASE + 0x304CU)
-#define	GPIO_IOINTSEL4		(GPIO_BASE + 0x4000U)
-#define	GPIO_INOUTSEL4		(GPIO_BASE + 0x4004U)
-#define	GPIO_OUTDT4		(GPIO_BASE + 0x4008U)
-#define	GPIO_INDT4		(GPIO_BASE + 0x400CU)
-#define	GPIO_INTDT4		(GPIO_BASE + 0x4010U)
-#define	GPIO_INTCLR4		(GPIO_BASE + 0x4014U)
-#define	GPIO_INTMSK4		(GPIO_BASE + 0x4018U)
-#define	GPIO_MSKCLR4		(GPIO_BASE + 0x401CU)
-#define	GPIO_POSNEG4		(GPIO_BASE + 0x4020U)
-#define	GPIO_EDGLEVEL4		(GPIO_BASE + 0x4024U)
-#define	GPIO_FILONOFF4		(GPIO_BASE + 0x4028U)
-#define	GPIO_INTMSKS4		(GPIO_BASE + 0x4038U)
-#define	GPIO_MSKCLRS4		(GPIO_BASE + 0x403CU)
-#define	GPIO_OUTDTSEL4		(GPIO_BASE + 0x4040U)
-#define	GPIO_OUTDTH4		(GPIO_BASE + 0x4044U)
-#define	GPIO_OUTDTL4		(GPIO_BASE + 0x4048U)
-#define	GPIO_BOTHEDGE4		(GPIO_BASE + 0x404CU)
-#define	GPIO_IOINTSEL5		(GPIO_BASE + 0x5000U)
-#define	GPIO_INOUTSEL5		(GPIO_BASE + 0x5004U)
-#define	GPIO_OUTDT5		(GPIO_BASE + 0x5008U)
-#define	GPIO_INDT5		(GPIO_BASE + 0x500CU)
-#define	GPIO_INTDT5		(GPIO_BASE + 0x5010U)
-#define	GPIO_INTCLR5		(GPIO_BASE + 0x5014U)
-#define	GPIO_INTMSK5		(GPIO_BASE + 0x5018U)
-#define	GPIO_MSKCLR5		(GPIO_BASE + 0x501CU)
-#define	GPIO_POSNEG5		(GPIO_BASE + 0x5020U)
-#define	GPIO_EDGLEVEL5		(GPIO_BASE + 0x5024U)
-#define	GPIO_FILONOFF5		(GPIO_BASE + 0x5028U)
-#define	GPIO_INTMSKS5		(GPIO_BASE + 0x5038U)
-#define	GPIO_MSKCLRS5		(GPIO_BASE + 0x503CU)
-#define	GPIO_OUTDTSEL5		(GPIO_BASE + 0x5040U)
-#define	GPIO_OUTDTH5		(GPIO_BASE + 0x5044U)
-#define	GPIO_OUTDTL5		(GPIO_BASE + 0x5048U)
-#define	GPIO_BOTHEDGE5		(GPIO_BASE + 0x504CU)
-#define	GPIO_IOINTSEL6		(GPIO_BASE + 0x5400U)
-#define	GPIO_INOUTSEL6		(GPIO_BASE + 0x5404U)
-#define	GPIO_OUTDT6		(GPIO_BASE + 0x5408U)
-#define	GPIO_INDT6		(GPIO_BASE + 0x540CU)
-#define	GPIO_INTDT6		(GPIO_BASE + 0x5410U)
-#define	GPIO_INTCLR6		(GPIO_BASE + 0x5414U)
-#define	GPIO_INTMSK6		(GPIO_BASE + 0x5418U)
-#define	GPIO_MSKCLR6		(GPIO_BASE + 0x541CU)
-#define	GPIO_POSNEG6		(GPIO_BASE + 0x5420U)
-#define	GPIO_EDGLEVEL6		(GPIO_BASE + 0x5424U)
-#define	GPIO_FILONOFF6		(GPIO_BASE + 0x5428U)
-#define	GPIO_INTMSKS6		(GPIO_BASE + 0x5438U)
-#define	GPIO_MSKCLRS6		(GPIO_BASE + 0x543CU)
-#define	GPIO_OUTDTSEL6		(GPIO_BASE + 0x5440U)
-#define	GPIO_OUTDTH6		(GPIO_BASE + 0x5444U)
-#define	GPIO_OUTDTL6		(GPIO_BASE + 0x5448U)
-#define	GPIO_BOTHEDGE6		(GPIO_BASE + 0x544CU)
-#define	GPIO_IOINTSEL7		(GPIO_BASE + 0x5800U)
-#define	GPIO_INOUTSEL7		(GPIO_BASE + 0x5804U)
-#define	GPIO_OUTDT7		(GPIO_BASE + 0x5808U)
-#define	GPIO_INDT7		(GPIO_BASE + 0x580CU)
-#define	GPIO_INTDT7		(GPIO_BASE + 0x5810U)
-#define	GPIO_INTCLR7		(GPIO_BASE + 0x5814U)
-#define	GPIO_INTMSK7		(GPIO_BASE + 0x5818U)
-#define	GPIO_MSKCLR7		(GPIO_BASE + 0x581CU)
-#define	GPIO_POSNEG7		(GPIO_BASE + 0x5820U)
-#define	GPIO_EDGLEVEL7		(GPIO_BASE + 0x5824U)
-#define	GPIO_FILONOFF7		(GPIO_BASE + 0x5828U)
-#define	GPIO_INTMSKS7		(GPIO_BASE + 0x5838U)
-#define	GPIO_MSKCLRS7		(GPIO_BASE + 0x583CU)
-#define	GPIO_OUTDTSEL7		(GPIO_BASE + 0x5840U)
-#define	GPIO_OUTDTH7		(GPIO_BASE + 0x5844U)
-#define	GPIO_OUTDTL7		(GPIO_BASE + 0x5848U)
-#define	GPIO_BOTHEDGE7		(GPIO_BASE + 0x584CU)
-
-/* Pin functon base address */
-#define	PFC_BASE		(0xE6060000U)
-
-/* Pin functon registers */
-#define	PFC_PMMR		(PFC_BASE + 0x0000U)
-#define PFC_GPSR0		(PFC_BASE + 0x0100U)
-#define PFC_GPSR1		(PFC_BASE + 0x0104U)
-#define PFC_GPSR2		(PFC_BASE + 0x0108U)
-#define PFC_GPSR3		(PFC_BASE + 0x010CU)
-#define PFC_GPSR4		(PFC_BASE + 0x0110U)
-#define	PFC_GPSR5		(PFC_BASE + 0x0114U)
-#define	PFC_GPSR6		(PFC_BASE + 0x0118U)
-#define	PFC_GPSR7		(PFC_BASE + 0x011CU)
-#define	PFC_IPSR0		(PFC_BASE + 0x0200U)
-#define	PFC_IPSR1		(PFC_BASE + 0x0204U)
-#define	PFC_IPSR2		(PFC_BASE + 0x0208U)
-#define	PFC_IPSR3		(PFC_BASE + 0x020CU)
-#define	PFC_IPSR4		(PFC_BASE + 0x0210U)
-#define	PFC_IPSR5		(PFC_BASE + 0x0214U)
-#define	PFC_IPSR6		(PFC_BASE + 0x0218U)
-#define	PFC_IPSR7		(PFC_BASE + 0x021CU)
-#define	PFC_IPSR8		(PFC_BASE + 0x0220U)
-#define	PFC_IPSR9		(PFC_BASE + 0x0224U)
-#define	PFC_IPSR10		(PFC_BASE + 0x0228U)
-#define	PFC_IPSR11		(PFC_BASE + 0x022CU)
-#define	PFC_IPSR12		(PFC_BASE + 0x0230U)
-#define	PFC_IPSR13		(PFC_BASE + 0x0234U)
-#define	PFC_IPSR14		(PFC_BASE + 0x0238U)
-#define	PFC_IPSR15		(PFC_BASE + 0x023CU)
-#define	PFC_IPSR16		(PFC_BASE + 0x0240U)
-#define	PFC_IPSR17		(PFC_BASE + 0x0244U)
-#define	PFC_IPSR18		(PFC_BASE + 0x0248U)
-#define PFC_DRVCTRL0		(PFC_BASE + 0x0300U)
-#define PFC_DRVCTRL1		(PFC_BASE + 0x0304U)
-#define PFC_DRVCTRL2		(PFC_BASE + 0x0308U)
-#define PFC_DRVCTRL3		(PFC_BASE + 0x030CU)
-#define PFC_DRVCTRL4		(PFC_BASE + 0x0310U)
-#define PFC_DRVCTRL5		(PFC_BASE + 0x0314U)
-#define PFC_DRVCTRL6		(PFC_BASE + 0x0318U)
-#define PFC_DRVCTRL7		(PFC_BASE + 0x031CU)
-#define PFC_DRVCTRL8		(PFC_BASE + 0x0320U)
-#define PFC_DRVCTRL9		(PFC_BASE + 0x0324U)
-#define PFC_DRVCTRL10		(PFC_BASE + 0x0328U)
-#define PFC_DRVCTRL11		(PFC_BASE + 0x032CU)
-#define PFC_DRVCTRL12		(PFC_BASE + 0x0330U)
-#define PFC_DRVCTRL13		(PFC_BASE + 0x0334U)
-#define PFC_DRVCTRL14		(PFC_BASE + 0x0338U)
-#define PFC_DRVCTRL15		(PFC_BASE + 0x033CU)
-#define PFC_DRVCTRL16		(PFC_BASE + 0x0340U)
-#define PFC_DRVCTRL17		(PFC_BASE + 0x0344U)
-#define PFC_DRVCTRL18		(PFC_BASE + 0x0348U)
-#define PFC_DRVCTRL19		(PFC_BASE + 0x034CU)
-#define PFC_DRVCTRL20		(PFC_BASE + 0x0350U)
-#define PFC_DRVCTRL21		(PFC_BASE + 0x0354U)
-#define PFC_DRVCTRL22		(PFC_BASE + 0x0358U)
-#define PFC_DRVCTRL23		(PFC_BASE + 0x035CU)
-#define PFC_DRVCTRL24		(PFC_BASE + 0x0360U)
-#define PFC_POCCTRL0		(PFC_BASE + 0x0380U)
-#define	PFC_TDSELCTRL0		(PFC_BASE + 0x03C0U)
-#define	PFC_IOCTRL		(PFC_BASE + 0x03E0U)
-#define	PFC_TSREG		(PFC_BASE + 0x03E4U)
-#define	PFC_PUEN0		(PFC_BASE + 0x0400U)
-#define	PFC_PUEN1		(PFC_BASE + 0x0404U)
-#define	PFC_PUEN2		(PFC_BASE + 0x0408U)
-#define	PFC_PUEN3		(PFC_BASE + 0x040CU)
-#define	PFC_PUEN4		(PFC_BASE + 0x0410U)
-#define	PFC_PUEN5		(PFC_BASE + 0x0414U)
-#define	PFC_PUEN6		(PFC_BASE + 0x0418U)
-#define	PFC_PUD0		(PFC_BASE + 0x0440U)
-#define	PFC_PUD1		(PFC_BASE + 0x0444U)
-#define	PFC_PUD2		(PFC_BASE + 0x0448U)
-#define	PFC_PUD3		(PFC_BASE + 0x044CU)
-#define	PFC_PUD4		(PFC_BASE + 0x0450U)
-#define	PFC_PUD5		(PFC_BASE + 0x0454U)
-#define	PFC_PUD6		(PFC_BASE + 0x0458U)
-#define	PFC_MOD_SEL0		(PFC_BASE + 0x0500U)
-#define	PFC_MOD_SEL1		(PFC_BASE + 0x0504U)
-#define	PFC_MOD_SEL2		(PFC_BASE + 0x0508U)
-
-#define	GPSR0_D15		((uint32_t)1U << 15U)
-#define	GPSR0_D14		((uint32_t)1U << 14U)
-#define	GPSR0_D13		((uint32_t)1U << 13U)
-#define	GPSR0_D12		((uint32_t)1U << 12U)
-#define	GPSR0_D11		((uint32_t)1U << 11U)
-#define	GPSR0_D10		((uint32_t)1U << 10U)
-#define	GPSR0_D9		((uint32_t)1U << 9U)
-#define	GPSR0_D8		((uint32_t)1U << 8U)
-#define	GPSR0_D7		((uint32_t)1U << 7U)
-#define	GPSR0_D6		((uint32_t)1U << 6U)
-#define	GPSR0_D5		((uint32_t)1U << 5U)
-#define	GPSR0_D4		((uint32_t)1U << 4U)
-#define	GPSR0_D3		((uint32_t)1U << 3U)
-#define	GPSR0_D2		((uint32_t)1U << 2U)
-#define	GPSR0_D1		((uint32_t)1U << 1U)
-#define	GPSR0_D0		((uint32_t)1U << 0U)
-#define	GPSR1_CLKOUT		((uint32_t)1U << 28U)
-#define	GPSR1_EX_WAIT0_A	((uint32_t)1U << 27U)
-#define	GPSR1_WE1		((uint32_t)1U << 26U)
-#define	GPSR1_WE0		((uint32_t)1U << 25U)
-#define	GPSR1_RD_WR		((uint32_t)1U << 24U)
-#define	GPSR1_RD		((uint32_t)1U << 23U)
-#define	GPSR1_BS		((uint32_t)1U << 22U)
-#define	GPSR1_CS1_A26		((uint32_t)1U << 21U)
-#define	GPSR1_CS0		((uint32_t)1U << 20U)
-#define	GPSR1_A19		((uint32_t)1U << 19U)
-#define	GPSR1_A18		((uint32_t)1U << 18U)
-#define	GPSR1_A17		((uint32_t)1U << 17U)
-#define	GPSR1_A16		((uint32_t)1U << 16U)
-#define	GPSR1_A15		((uint32_t)1U << 15U)
-#define	GPSR1_A14		((uint32_t)1U << 14U)
-#define	GPSR1_A13		((uint32_t)1U << 13U)
-#define	GPSR1_A12		((uint32_t)1U << 12U)
-#define	GPSR1_A11		((uint32_t)1U << 11U)
-#define	GPSR1_A10		((uint32_t)1U << 10U)
-#define	GPSR1_A9		((uint32_t)1U << 9U)
-#define	GPSR1_A8		((uint32_t)1U << 8U)
-#define	GPSR1_A7		((uint32_t)1U << 7U)
-#define	GPSR1_A6		((uint32_t)1U << 6U)
-#define	GPSR1_A5		((uint32_t)1U << 5U)
-#define	GPSR1_A4		((uint32_t)1U << 4U)
-#define	GPSR1_A3		((uint32_t)1U << 3U)
-#define	GPSR1_A2		((uint32_t)1U << 2U)
-#define	GPSR1_A1		((uint32_t)1U << 1U)
-#define	GPSR1_A0		((uint32_t)1U << 0U)
-#define	GPSR2_AVB_AVTP_CAPTURE_A	((uint32_t)1U << 14U)
-#define	GPSR2_AVB_AVTP_MATCH_A	((uint32_t)1U << 13U)
-#define	GPSR2_AVB_LINK		((uint32_t)1U << 12U)
-#define	GPSR2_AVB_PHY_INT	((uint32_t)1U << 11U)
-#define	GPSR2_AVB_MAGIC		((uint32_t)1U << 10U)
-#define	GPSR2_AVB_MDC		((uint32_t)1U << 9U)
-#define	GPSR2_PWM2_A		((uint32_t)1U << 8U)
-#define	GPSR2_PWM1_A		((uint32_t)1U << 7U)
-#define	GPSR2_PWM0		((uint32_t)1U << 6U)
-#define	GPSR2_IRQ5		((uint32_t)1U << 5U)
-#define	GPSR2_IRQ4		((uint32_t)1U << 4U)
-#define	GPSR2_IRQ3		((uint32_t)1U << 3U)
-#define	GPSR2_IRQ2		((uint32_t)1U << 2U)
-#define	GPSR2_IRQ1		((uint32_t)1U << 1U)
-#define	GPSR2_IRQ0		((uint32_t)1U << 0U)
-#define	GPSR3_SD1_WP		((uint32_t)1U << 15U)
-#define	GPSR3_SD1_CD		((uint32_t)1U << 14U)
-#define	GPSR3_SD0_WP		((uint32_t)1U << 13U)
-#define	GPSR3_SD0_CD		((uint32_t)1U << 12U)
-#define	GPSR3_SD1_DAT3		((uint32_t)1U << 11U)
-#define	GPSR3_SD1_DAT2		((uint32_t)1U << 10U)
-#define	GPSR3_SD1_DAT1		((uint32_t)1U << 9U)
-#define	GPSR3_SD1_DAT0		((uint32_t)1U << 8U)
-#define	GPSR3_SD1_CMD		((uint32_t)1U << 7U)
-#define	GPSR3_SD1_CLK		((uint32_t)1U << 6U)
-#define	GPSR3_SD0_DAT3		((uint32_t)1U << 5U)
-#define	GPSR3_SD0_DAT2		((uint32_t)1U << 4U)
-#define	GPSR3_SD0_DAT1		((uint32_t)1U << 3U)
-#define	GPSR3_SD0_DAT0		((uint32_t)1U << 2U)
-#define	GPSR3_SD0_CMD		((uint32_t)1U << 1U)
-#define	GPSR3_SD0_CLK		((uint32_t)1U << 0U)
-#define	GPSR4_SD3_DS		((uint32_t)1U << 17U)
-#define	GPSR4_SD3_DAT7		((uint32_t)1U << 16U)
-#define	GPSR4_SD3_DAT6		((uint32_t)1U << 15U)
-#define	GPSR4_SD3_DAT5		((uint32_t)1U << 14U)
-#define	GPSR4_SD3_DAT4		((uint32_t)1U << 13U)
-#define	GPSR4_SD3_DAT3		((uint32_t)1U << 12U)
-#define	GPSR4_SD3_DAT2		((uint32_t)1U << 11U)
-#define	GPSR4_SD3_DAT1		((uint32_t)1U << 10U)
-#define	GPSR4_SD3_DAT0		((uint32_t)1U << 9U)
-#define	GPSR4_SD3_CMD		((uint32_t)1U << 8U)
-#define	GPSR4_SD3_CLK		((uint32_t)1U << 7U)
-#define	GPSR4_SD2_DS		((uint32_t)1U << 6U)
-#define	GPSR4_SD2_DAT3		((uint32_t)1U << 5U)
-#define	GPSR4_SD2_DAT2		((uint32_t)1U << 4U)
-#define	GPSR4_SD2_DAT1		((uint32_t)1U << 3U)
-#define	GPSR4_SD2_DAT0		((uint32_t)1U << 2U)
-#define	GPSR4_SD2_CMD		((uint32_t)1U << 1U)
-#define	GPSR4_SD2_CLK		((uint32_t)1U << 0U)
-#define	GPSR5_MLB_DAT		((uint32_t)1U << 25U)
-#define	GPSR5_MLB_SIG		((uint32_t)1U << 24U)
-#define	GPSR5_MLB_CLK		((uint32_t)1U << 23U)
-#define	GPSR5_MSIOF0_RXD	((uint32_t)1U << 22U)
-#define	GPSR5_MSIOF0_SS2	((uint32_t)1U << 21U)
-#define	GPSR5_MSIOF0_TXD	((uint32_t)1U << 20U)
-#define	GPSR5_MSIOF0_SS1	((uint32_t)1U << 19U)
-#define	GPSR5_MSIOF0_SYNC	((uint32_t)1U << 18U)
-#define	GPSR5_MSIOF0_SCK	((uint32_t)1U << 17U)
-#define	GPSR5_HRTS0		((uint32_t)1U << 16U)
-#define	GPSR5_HCTS0		((uint32_t)1U << 15U)
-#define	GPSR5_HTX0		((uint32_t)1U << 14U)
-#define	GPSR5_HRX0		((uint32_t)1U << 13U)
-#define	GPSR5_HSCK0		((uint32_t)1U << 12U)
-#define	GPSR5_RX2_A		((uint32_t)1U << 11U)
-#define	GPSR5_TX2_A		((uint32_t)1U << 10U)
-#define	GPSR5_SCK2		((uint32_t)1U << 9U)
-#define	GPSR5_RTS1_TANS		((uint32_t)1U << 8U)
-#define	GPSR5_CTS1		((uint32_t)1U << 7U)
-#define	GPSR5_TX1_A		((uint32_t)1U << 6U)
-#define	GPSR5_RX1_A		((uint32_t)1U << 5U)
-#define	GPSR5_RTS0_TANS		((uint32_t)1U << 4U)
-#define	GPSR5_CTS0		((uint32_t)1U << 3U)
-#define	GPSR5_TX0		((uint32_t)1U << 2U)
-#define	GPSR5_RX0		((uint32_t)1U << 1U)
-#define	GPSR5_SCK0		((uint32_t)1U << 0U)
-#define	GPSR6_USB31_OVC		((uint32_t)1U << 31U)
-#define	GPSR6_USB31_PWEN	((uint32_t)1U << 30U)
-#define	GPSR6_USB30_OVC		((uint32_t)1U << 29U)
-#define	GPSR6_USB30_PWEN	((uint32_t)1U << 28U)
-#define	GPSR6_USB1_OVC		((uint32_t)1U << 27U)
-#define	GPSR6_USB1_PWEN		((uint32_t)1U << 26U)
-#define	GPSR6_USB0_OVC		((uint32_t)1U << 25U)
-#define	GPSR6_USB0_PWEN		((uint32_t)1U << 24U)
-#define	GPSR6_AUDIO_CLKB_B	((uint32_t)1U << 23U)
-#define	GPSR6_AUDIO_CLKA_A	((uint32_t)1U << 22U)
-#define	GPSR6_SSI_SDATA9_A	((uint32_t)1U << 21U)
-#define	GPSR6_SSI_SDATA8	((uint32_t)1U << 20U)
-#define	GPSR6_SSI_SDATA7	((uint32_t)1U << 19U)
-#define	GPSR6_SSI_WS78		((uint32_t)1U << 18U)
-#define	GPSR6_SSI_SCK78		((uint32_t)1U << 17U)
-#define	GPSR6_SSI_SDATA6	((uint32_t)1U << 16U)
-#define	GPSR6_SSI_WS6		((uint32_t)1U << 15U)
-#define	GPSR6_SSI_SCK6		((uint32_t)1U << 14U)
-#define	GPSR6_SSI_SDATA5	((uint32_t)1U << 13U)
-#define	GPSR6_SSI_WS5		((uint32_t)1U << 12U)
-#define	GPSR6_SSI_SCK5		((uint32_t)1U << 11U)
-#define	GPSR6_SSI_SDATA4	((uint32_t)1U << 10U)
-#define	GPSR6_SSI_WS4		((uint32_t)1U << 9U)
-#define	GPSR6_SSI_SCK4		((uint32_t)1U << 8U)
-#define	GPSR6_SSI_SDATA3	((uint32_t)1U << 7U)
-#define	GPSR6_SSI_WS34		((uint32_t)1U << 6U)
-#define	GPSR6_SSI_SCK34		((uint32_t)1U << 5U)
-#define	GPSR6_SSI_SDATA2_A	((uint32_t)1U << 4U)
-#define	GPSR6_SSI_SDATA1_A	((uint32_t)1U << 3U)
-#define	GPSR6_SSI_SDATA0	((uint32_t)1U << 2U)
-#define	GPSR6_SSI_WS0129	((uint32_t)1U << 1U)
-#define	GPSR6_SSI_SCK0129	((uint32_t)1U << 0U)
-#define	GPSR7_HDMI1_CEC		((uint32_t)1U << 3U)
-#define	GPSR7_HDMI0_CEC		((uint32_t)1U << 2U)
-#define	GPSR7_AVS2		((uint32_t)1U << 1U)
-#define	GPSR7_AVS1		((uint32_t)1U << 0U)
-
-#define	IPSR_28_FUNC(x)		((uint32_t)(x) << 28U)
-#define	IPSR_24_FUNC(x)		((uint32_t)(x) << 24U)
-#define	IPSR_20_FUNC(x)		((uint32_t)(x) << 20U)
-#define	IPSR_16_FUNC(x)		((uint32_t)(x) << 16U)
-#define	IPSR_12_FUNC(x)		((uint32_t)(x) << 12U)
-#define	IPSR_8_FUNC(x)		((uint32_t)(x) << 8U)
-#define	IPSR_4_FUNC(x)		((uint32_t)(x) << 4U)
-#define	IPSR_0_FUNC(x)		((uint32_t)(x) << 0U)
-
-#define	POC_SD3_DS_33V		((uint32_t)1U << 29U)
-#define	POC_SD3_DAT7_33V	((uint32_t)1U << 28U)
-#define	POC_SD3_DAT6_33V	((uint32_t)1U << 27U)
-#define	POC_SD3_DAT5_33V	((uint32_t)1U << 26U)
-#define	POC_SD3_DAT4_33V	((uint32_t)1U << 25U)
-#define	POC_SD3_DAT3_33V	((uint32_t)1U << 24U)
-#define	POC_SD3_DAT2_33V	((uint32_t)1U << 23U)
-#define	POC_SD3_DAT1_33V	((uint32_t)1U << 22U)
-#define	POC_SD3_DAT0_33V	((uint32_t)1U << 21U)
-#define	POC_SD3_CMD_33V		((uint32_t)1U << 20U)
-#define	POC_SD3_CLK_33V		((uint32_t)1U << 19U)
-#define	POC_SD2_DS_33V		((uint32_t)1U << 18U)
-#define	POC_SD2_DAT3_33V	((uint32_t)1U << 17U)
-#define	POC_SD2_DAT2_33V	((uint32_t)1U << 16U)
-#define	POC_SD2_DAT1_33V	((uint32_t)1U << 15U)
-#define	POC_SD2_DAT0_33V	((uint32_t)1U << 14U)
-#define	POC_SD2_CMD_33V		((uint32_t)1U << 13U)
-#define	POC_SD2_CLK_33V		((uint32_t)1U << 12U)
-#define	POC_SD1_DAT3_33V	((uint32_t)1U << 11U)
-#define	POC_SD1_DAT2_33V	((uint32_t)1U << 10U)
-#define	POC_SD1_DAT1_33V	((uint32_t)1U << 9U)
-#define	POC_SD1_DAT0_33V	((uint32_t)1U << 8U)
-#define	POC_SD1_CMD_33V		((uint32_t)1U << 7U)
-#define	POC_SD1_CLK_33V		((uint32_t)1U << 6U)
-#define	POC_SD0_DAT3_33V	((uint32_t)1U << 5U)
-#define	POC_SD0_DAT2_33V	((uint32_t)1U << 4U)
-#define	POC_SD0_DAT1_33V	((uint32_t)1U << 3U)
-#define	POC_SD0_DAT0_33V	((uint32_t)1U << 2U)
-#define	POC_SD0_CMD_33V		((uint32_t)1U << 1U)
-#define	POC_SD0_CLK_33V		((uint32_t)1U << 0U)
-
-#define	DRVCTRL0_MASK		(0xCCCCCCCCU)
-#define	DRVCTRL1_MASK		(0xCCCCCCC8U)
-#define	DRVCTRL2_MASK		(0x88888888U)
-#define	DRVCTRL3_MASK		(0x88888888U)
-#define	DRVCTRL4_MASK		(0x88888888U)
-#define	DRVCTRL5_MASK		(0x88888888U)
-#define	DRVCTRL6_MASK		(0x88888888U)
-#define	DRVCTRL7_MASK		(0x88888888U)
-#define	DRVCTRL8_MASK		(0x88888888U)
-#define	DRVCTRL9_MASK		(0x88888888U)
-#define	DRVCTRL10_MASK		(0x88888888U)
-#define	DRVCTRL11_MASK		(0x888888CCU)
-#define	DRVCTRL12_MASK		(0xCCCFFFCFU)
-#define	DRVCTRL13_MASK		(0xCC888888U)
-#define	DRVCTRL14_MASK		(0x88888888U)
-#define	DRVCTRL15_MASK		(0x88888888U)
-#define	DRVCTRL16_MASK		(0x88888888U)
-#define	DRVCTRL17_MASK		(0x88888888U)
-#define	DRVCTRL18_MASK		(0x88888888U)
-#define	DRVCTRL19_MASK		(0x88888888U)
-#define	DRVCTRL20_MASK		(0x88888888U)
-#define	DRVCTRL21_MASK		(0x88888888U)
-#define	DRVCTRL22_MASK		(0x88888888U)
-#define	DRVCTRL23_MASK		(0x88888888U)
-#define	DRVCTRL24_MASK		(0x8888888FU)
-
-#define	DRVCTRL0_QSPI0_SPCLK(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL0_QSPI0_MOSI_IO0(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL0_QSPI0_MISO_IO1(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL0_QSPI0_IO2(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL0_QSPI0_IO3(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL0_QSPI0_SSL(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL0_QSPI1_SPCLK(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL0_QSPI1_MOSI_IO0(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL1_QSPI1_MISO_IO1(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL1_QSPI1_IO2(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL1_QSPI1_IO3(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL1_QSPI1_SS(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL1_RPC_INT(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL1_RPC_WP(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL1_RPC_RESET(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL1_AVB_RX_CTL(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL2_AVB_RXC(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL2_AVB_RD0(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL2_AVB_RD1(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL2_AVB_RD2(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL2_AVB_RD3(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL2_AVB_TX_CTL(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL2_AVB_TXC(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL2_AVB_TD0(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL3_AVB_TD1(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL3_AVB_TD2(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL3_AVB_TD3(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL3_AVB_TXCREFCLK(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL3_AVB_MDIO(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL3_AVB_MDC(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL3_AVB_MAGIC(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL3_AVB_PHY_INT(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL4_AVB_LINK(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL4_AVB_AVTP_MATCH(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL4_AVB_AVTP_CAPTURE(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL4_IRQ0(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL4_IRQ1(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL4_IRQ2(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL4_IRQ3(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL4_IRQ4(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL5_IRQ5(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL5_PWM0(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL5_PWM1(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL5_PWM2(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL5_A0(x)		((uint32_t)(x) << 12U)
-#define	DRVCTRL5_A1(x)		((uint32_t)(x) << 8U)
-#define	DRVCTRL5_A2(x)		((uint32_t)(x) << 4U)
-#define	DRVCTRL5_A3(x)		((uint32_t)(x) << 0U)
-#define	DRVCTRL6_A4(x)		((uint32_t)(x) << 28U)
-#define	DRVCTRL6_A5(x)		((uint32_t)(x) << 24U)
-#define	DRVCTRL6_A6(x)		((uint32_t)(x) << 20U)
-#define	DRVCTRL6_A7(x)		((uint32_t)(x) << 16U)
-#define	DRVCTRL6_A8(x)		((uint32_t)(x) << 12U)
-#define	DRVCTRL6_A9(x)		((uint32_t)(x) << 8U)
-#define	DRVCTRL6_A10(x)		((uint32_t)(x) << 4U)
-#define	DRVCTRL6_A11(x)		((uint32_t)(x) << 0U)
-#define	DRVCTRL7_A12(x)		((uint32_t)(x) << 28U)
-#define	DRVCTRL7_A13(x)		((uint32_t)(x) << 24U)
-#define	DRVCTRL7_A14(x)		((uint32_t)(x) << 20U)
-#define	DRVCTRL7_A15(x)		((uint32_t)(x) << 16U)
-#define	DRVCTRL7_A16(x)		((uint32_t)(x) << 12U)
-#define	DRVCTRL7_A17(x)		((uint32_t)(x) << 8U)
-#define	DRVCTRL7_A18(x)		((uint32_t)(x) << 4U)
-#define	DRVCTRL7_A19(x)		((uint32_t)(x) << 0U)
-#define	DRVCTRL8_CLKOUT(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL8_CS0(x)		((uint32_t)(x) << 24U)
-#define	DRVCTRL8_CS1_A2(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL8_BS(x)		((uint32_t)(x) << 16U)
-#define	DRVCTRL8_RD(x)		((uint32_t)(x) << 12U)
-#define	DRVCTRL8_RD_W(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL8_WE0(x)		((uint32_t)(x) << 4U)
-#define	DRVCTRL8_WE1(x)		((uint32_t)(x) << 0U)
-#define	DRVCTRL9_EX_WAIT0(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL9_PRESETOU(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL9_D0(x)		((uint32_t)(x) << 20U)
-#define	DRVCTRL9_D1(x)		((uint32_t)(x) << 16U)
-#define	DRVCTRL9_D2(x)		((uint32_t)(x) << 12U)
-#define	DRVCTRL9_D3(x)		((uint32_t)(x) << 8U)
-#define	DRVCTRL9_D4(x)		((uint32_t)(x) << 4U)
-#define	DRVCTRL9_D5(x)		((uint32_t)(x) << 0U)
-#define	DRVCTRL10_D6(x)		((uint32_t)(x) << 28U)
-#define	DRVCTRL10_D7(x)		((uint32_t)(x) << 24U)
-#define	DRVCTRL10_D8(x)		((uint32_t)(x) << 20U)
-#define	DRVCTRL10_D9(x)		((uint32_t)(x) << 16U)
-#define	DRVCTRL10_D10(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL10_D11(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL10_D12(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL10_D13(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL11_D14(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL11_D15(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL11_AVS1(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL11_AVS2(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL11_HDMI0_CEC(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL11_HDMI1_CEC(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL11_DU_DOTCLKIN0(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL11_DU_DOTCLKIN1(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL12_DU_DOTCLKIN2(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL12_DU_DOTCLKIN3(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL12_DU_FSCLKST(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL12_DU_TMS(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL13_TDO(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL13_ASEBRK(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL13_SD0_CLK(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL13_SD0_CMD(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL13_SD0_DAT0(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL13_SD0_DAT1(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL13_SD0_DAT2(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL13_SD0_DAT3(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL14_SD1_CLK(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL14_SD1_CMD(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL14_SD1_DAT0(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL14_SD1_DAT1(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL14_SD1_DAT2(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL14_SD1_DAT3(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL14_SD2_CLK(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL14_SD2_CMD(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL15_SD2_DAT0(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL15_SD2_DAT1(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL15_SD2_DAT2(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL15_SD2_DAT3(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL15_SD2_DS(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL15_SD3_CLK(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL15_SD3_CMD(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL15_SD3_DAT0(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL16_SD3_DAT1(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL16_SD3_DAT2(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL16_SD3_DAT3(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL16_SD3_DAT4(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL16_SD3_DAT5(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL16_SD3_DAT6(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL16_SD3_DAT7(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL16_SD3_DS(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL17_SD0_CD(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL17_SD0_WP(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL17_SD1_CD(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL17_SD1_WP(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL17_SCK0(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL17_RX0(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL17_TX0(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL17_CTS0(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL18_RTS0_TANS(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL18_RX1(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL18_TX1(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL18_CTS1(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL18_RTS1_TANS(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL18_SCK2(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL18_TX2(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL18_RX2(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL19_HSCK0(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL19_HRX0(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL19_HTX0(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL19_HCTS0(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL19_HRTS0(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL19_MSIOF0_SCK(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL19_MSIOF0_SYNC(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL19_MSIOF0_SS1(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL20_MSIOF0_TXD(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL20_MSIOF0_SS2(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL20_MSIOF0_RXD(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL20_MLB_CLK(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL20_MLB_SIG(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL20_MLB_DAT(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL20_MLB_REF(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL20_SSI_SCK0129(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL21_SSI_WS0129(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL21_SSI_SDATA0(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL21_SSI_SDATA1(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL21_SSI_SDATA2(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL21_SSI_SCK34(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL21_SSI_WS34(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL21_SSI_SDATA3(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL21_SSI_SCK4(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL22_SSI_WS4(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL22_SSI_SDATA4(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL22_SSI_SCK5(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL22_SSI_WS5(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL22_SSI_SDATA5(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL22_SSI_SCK6(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL22_SSI_WS6(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL22_SSI_SDATA6(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL23_SSI_SCK78(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL23_SSI_WS78(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL23_SSI_SDATA7(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL23_SSI_SDATA8(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL23_SSI_SDATA9(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL23_AUDIO_CLKA(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL23_AUDIO_CLKB(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL23_USB0_PWEN(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL24_USB0_OVC(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL24_USB1_PWEN(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL24_USB1_OVC(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL24_USB30_PWEN(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL24_USB30_OVC(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL24_USB31_PWEN(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL24_USB31_OVC(x)	((uint32_t)(x) << 4U)
-
-#define	MOD_SEL0_MSIOF3_A	((uint32_t)0U << 29U)
-#define	MOD_SEL0_MSIOF3_B	((uint32_t)1U << 29U)
-#define	MOD_SEL0_MSIOF3_C	((uint32_t)2U << 29U)
-#define	MOD_SEL0_MSIOF3_D	((uint32_t)3U << 29U)
-#define	MOD_SEL0_MSIOF3_E	((uint32_t)4U << 29U)
-#define	MOD_SEL0_MSIOF2_A	((uint32_t)0U << 27U)
-#define	MOD_SEL0_MSIOF2_B	((uint32_t)1U << 27U)
-#define	MOD_SEL0_MSIOF2_C	((uint32_t)2U << 27U)
-#define	MOD_SEL0_MSIOF2_D	((uint32_t)3U << 27U)
-#define	MOD_SEL0_MSIOF1_A	((uint32_t)0U << 24U)
-#define	MOD_SEL0_MSIOF1_B	((uint32_t)1U << 24U)
-#define	MOD_SEL0_MSIOF1_C	((uint32_t)2U << 24U)
-#define	MOD_SEL0_MSIOF1_D	((uint32_t)3U << 24U)
-#define	MOD_SEL0_MSIOF1_E	((uint32_t)4U << 24U)
-#define	MOD_SEL0_MSIOF1_F	((uint32_t)5U << 24U)
-#define	MOD_SEL0_MSIOF1_G	((uint32_t)6U << 24U)
-#define	MOD_SEL0_LBSC_A		((uint32_t)0U << 23U)
-#define	MOD_SEL0_LBSC_B		((uint32_t)1U << 23U)
-#define	MOD_SEL0_IEBUS_A	((uint32_t)0U << 22U)
-#define	MOD_SEL0_IEBUS_B	((uint32_t)1U << 22U)
-#define	MOD_SEL0_I2C2_A		((uint32_t)0U << 21U)
-#define	MOD_SEL0_I2C2_B		((uint32_t)1U << 21U)
-#define	MOD_SEL0_I2C1_A		((uint32_t)0U << 20U)
-#define	MOD_SEL0_I2C1_B		((uint32_t)1U << 20U)
-#define	MOD_SEL0_HSCIF4_A	((uint32_t)0U << 19U)
-#define	MOD_SEL0_HSCIF4_B	((uint32_t)1U << 19U)
-#define	MOD_SEL0_HSCIF3_A	((uint32_t)0U << 17U)
-#define	MOD_SEL0_HSCIF3_B	((uint32_t)1U << 17U)
-#define	MOD_SEL0_HSCIF3_C	((uint32_t)2U << 17U)
-#define	MOD_SEL0_HSCIF3_D	((uint32_t)3U << 17U)
-#define	MOD_SEL0_HSCIF1_A	((uint32_t)0U << 16U)
-#define	MOD_SEL0_HSCIF1_B	((uint32_t)1U << 16U)
-#define	MOD_SEL0_FSO_A		((uint32_t)0U << 15U)
-#define	MOD_SEL0_FSO_B		((uint32_t)1U << 15U)
-#define	MOD_SEL0_HSCIF2_A	((uint32_t)0U << 13U)
-#define	MOD_SEL0_HSCIF2_B	((uint32_t)1U << 13U)
-#define	MOD_SEL0_HSCIF2_C	((uint32_t)2U << 13U)
-#define	MOD_SEL0_ETHERAVB_A	((uint32_t)0U << 12U)
-#define	MOD_SEL0_ETHERAVB_B	((uint32_t)1U << 12U)
-#define	MOD_SEL0_DRIF3_A	((uint32_t)0U << 11U)
-#define	MOD_SEL0_DRIF3_B	((uint32_t)1U << 11U)
-#define	MOD_SEL0_DRIF2_A	((uint32_t)0U << 10U)
-#define	MOD_SEL0_DRIF2_B	((uint32_t)1U << 10U)
-#define	MOD_SEL0_DRIF1_A	((uint32_t)0U << 8U)
-#define	MOD_SEL0_DRIF1_B	((uint32_t)1U << 8U)
-#define	MOD_SEL0_DRIF1_C	((uint32_t)2U << 8U)
-#define	MOD_SEL0_DRIF0_A	((uint32_t)0U << 6U)
-#define	MOD_SEL0_DRIF0_B	((uint32_t)1U << 6U)
-#define	MOD_SEL0_DRIF0_C	((uint32_t)2U << 6U)
-#define	MOD_SEL0_CANFD0_A	((uint32_t)0U << 5U)
-#define	MOD_SEL0_CANFD0_B	((uint32_t)1U << 5U)
-#define	MOD_SEL0_ADG_A_A	((uint32_t)0U << 3U)
-#define	MOD_SEL0_ADG_A_B	((uint32_t)1U << 3U)
-#define	MOD_SEL0_ADG_A_C	((uint32_t)2U << 3U)
-#define	MOD_SEL1_TSIF1_A	((uint32_t)0U << 30U)
-#define	MOD_SEL1_TSIF1_B	((uint32_t)1U << 30U)
-#define	MOD_SEL1_TSIF1_C	((uint32_t)2U << 30U)
-#define	MOD_SEL1_TSIF1_D	((uint32_t)3U << 30U)
-#define	MOD_SEL1_TSIF0_A	((uint32_t)0U << 27U)
-#define	MOD_SEL1_TSIF0_B	((uint32_t)1U << 27U)
-#define	MOD_SEL1_TSIF0_C	((uint32_t)2U << 27U)
-#define	MOD_SEL1_TSIF0_D	((uint32_t)3U << 27U)
-#define	MOD_SEL1_TSIF0_E	((uint32_t)4U << 27U)
-#define	MOD_SEL1_TIMER_TMU_A	((uint32_t)0U << 26U)
-#define	MOD_SEL1_TIMER_TMU_B	((uint32_t)1U << 26U)
-#define	MOD_SEL1_SSP1_1_A	((uint32_t)0U << 24U)
-#define	MOD_SEL1_SSP1_1_B	((uint32_t)1U << 24U)
-#define	MOD_SEL1_SSP1_1_C	((uint32_t)2U << 24U)
-#define	MOD_SEL1_SSP1_1_D	((uint32_t)3U << 24U)
-#define	MOD_SEL1_SSP1_0_A	((uint32_t)0U << 21U)
-#define	MOD_SEL1_SSP1_0_B	((uint32_t)1U << 21U)
-#define	MOD_SEL1_SSP1_0_C	((uint32_t)2U << 21U)
-#define	MOD_SEL1_SSP1_0_D	((uint32_t)3U << 21U)
-#define	MOD_SEL1_SSP1_0_E	((uint32_t)4U << 21U)
-#define	MOD_SEL1_SSI_A		((uint32_t)0U << 20U)
-#define	MOD_SEL1_SSI_B		((uint32_t)1U << 20U)
-#define	MOD_SEL1_SPEED_PULSE_IF_A	((uint32_t)0U << 19U)
-#define	MOD_SEL1_SPEED_PULSE_IF_B	((uint32_t)1U << 19U)
-#define	MOD_SEL1_SIMCARD_A	((uint32_t)0U << 17U)
-#define	MOD_SEL1_SIMCARD_B	((uint32_t)1U << 17U)
-#define	MOD_SEL1_SIMCARD_C	((uint32_t)2U << 17U)
-#define	MOD_SEL1_SIMCARD_D	((uint32_t)3U << 17U)
-#define	MOD_SEL1_SDHI2_A	((uint32_t)0U << 16U)
-#define	MOD_SEL1_SDHI2_B	((uint32_t)1U << 16U)
-#define	MOD_SEL1_SCIF4_A	((uint32_t)0U << 14U)
-#define	MOD_SEL1_SCIF4_B	((uint32_t)1U << 14U)
-#define	MOD_SEL1_SCIF4_C	((uint32_t)2U << 14U)
-#define	MOD_SEL1_SCIF3_A	((uint32_t)0U << 13U)
-#define	MOD_SEL1_SCIF3_B	((uint32_t)1U << 13U)
-#define	MOD_SEL1_SCIF2_A	((uint32_t)0U << 12U)
-#define	MOD_SEL1_SCIF2_B	((uint32_t)1U << 12U)
-#define	MOD_SEL1_SCIF1_A	((uint32_t)0U << 11U)
-#define	MOD_SEL1_SCIF1_B	((uint32_t)1U << 11U)
-#define	MOD_SEL1_SCIF_A		((uint32_t)0U << 10U)
-#define	MOD_SEL1_SCIF_B		((uint32_t)1U << 10U)
-#define	MOD_SEL1_REMOCON_A	((uint32_t)0U << 9U)
-#define	MOD_SEL1_REMOCON_B	((uint32_t)1U << 9U)
-#define	MOD_SEL1_RCAN0_A	((uint32_t)0U << 6U)
-#define	MOD_SEL1_RCAN0_B	((uint32_t)1U << 6U)
-#define	MOD_SEL1_PWM6_A		((uint32_t)0U << 5U)
-#define	MOD_SEL1_PWM6_B		((uint32_t)1U << 5U)
-#define	MOD_SEL1_PWM5_A		((uint32_t)0U << 4U)
-#define	MOD_SEL1_PWM5_B		((uint32_t)1U << 4U)
-#define	MOD_SEL1_PWM4_A		((uint32_t)0U << 3U)
-#define	MOD_SEL1_PWM4_B		((uint32_t)1U << 3U)
-#define	MOD_SEL1_PWM3_A		((uint32_t)0U << 2U)
-#define	MOD_SEL1_PWM3_B		((uint32_t)1U << 2U)
-#define	MOD_SEL1_PWM2_A		((uint32_t)0U << 1U)
-#define	MOD_SEL1_PWM2_B		((uint32_t)1U << 1U)
-#define	MOD_SEL1_PWM1_A		((uint32_t)0U << 0U)
-#define	MOD_SEL1_PWM1_B		((uint32_t)1U << 0U)
-#define	MOD_SEL2_I2C_5_A	((uint32_t)0U << 31U)
-#define	MOD_SEL2_I2C_5_B	((uint32_t)1U << 31U)
-#define	MOD_SEL2_I2C_3_A	((uint32_t)0U << 30U)
-#define	MOD_SEL2_I2C_3_B	((uint32_t)1U << 30U)
-#define	MOD_SEL2_I2C_0_A	((uint32_t)0U << 29U)
-#define	MOD_SEL2_I2C_0_B	((uint32_t)1U << 29U)
-#define	MOD_SEL2_FM_A		((uint32_t)0U << 27U)
-#define	MOD_SEL2_FM_B		((uint32_t)1U << 27U)
-#define	MOD_SEL2_FM_C		((uint32_t)2U << 27U)
-#define	MOD_SEL2_FM_D		((uint32_t)3U << 27U)
-#define	MOD_SEL2_SCIF5_A	((uint32_t)0U << 26U)
-#define	MOD_SEL2_SCIF5_B	((uint32_t)1U << 26U)
-#define	MOD_SEL2_I2C6_A		((uint32_t)0U << 23U)
-#define	MOD_SEL2_I2C6_B		((uint32_t)1U << 23U)
-#define	MOD_SEL2_I2C6_C		((uint32_t)2U << 23U)
-#define	MOD_SEL2_NDF_A		((uint32_t)0U << 22U)
-#define	MOD_SEL2_NDF_B		((uint32_t)1U << 22U)
-#define	MOD_SEL2_SSI2_A		((uint32_t)0U << 21U)
-#define	MOD_SEL2_SSI2_B		((uint32_t)1U << 21U)
-#define	MOD_SEL2_SSI9_A		((uint32_t)0U << 20U)
-#define	MOD_SEL2_SSI9_B		((uint32_t)1U << 20U)
-#define	MOD_SEL2_TIMER_TMU2_A	((uint32_t)0U << 19U)
-#define	MOD_SEL2_TIMER_TMU2_B	((uint32_t)1U << 19U)
-#define	MOD_SEL2_ADG_B_A	((uint32_t)0U << 18U)
-#define	MOD_SEL2_ADG_B_B	((uint32_t)1U << 18U)
-#define	MOD_SEL2_ADG_C_A	((uint32_t)0U << 17U)
-#define	MOD_SEL2_ADG_C_B	((uint32_t)1U << 17U)
-#define	MOD_SEL2_VIN4_A		((uint32_t)0U << 0U)
-#define	MOD_SEL2_VIN4_B		((uint32_t)1U << 0U)
-
-/* SCIF3 Registers for Dummy write */
-#define SCIF3_BASE		(0xE6C50000U)
-#define SCIF3_SCFCR		(SCIF3_BASE + 0x0018U)
-#define SCIF3_SCFDR		(SCIF3_BASE + 0x001CU)
-#define SCFCR_DATA		(0x0000U)
-
-/* Realtime module stop control */
-#define	CPG_BASE		(0xE6150000U)
-#define CPG_MSTPSR0		(CPG_BASE + 0x0030U)
-#define CPG_RMSTPCR0		(CPG_BASE + 0x0110U)
-#define RMSTPCR0_RTDMAC		(0x00200000U)
-
-static void pfc_reg_write(uint32_t addr, uint32_t data);
-
-static void pfc_reg_write(uint32_t addr, uint32_t data)
-{
-	mmio_write_32(PFC_PMMR, ~data);
-	mmio_write_32((uintptr_t) addr, data);
-}
-
-void pfc_init_h3_v2(void)
-{
-	uint32_t reg;
-
-	/* initialize module select */
-	pfc_reg_write(PFC_MOD_SEL0, MOD_SEL0_MSIOF3_A
-		      | MOD_SEL0_MSIOF2_A
-		      | MOD_SEL0_MSIOF1_A
-		      | MOD_SEL0_LBSC_A
-		      | MOD_SEL0_IEBUS_A
-		      | MOD_SEL0_I2C2_A
-		      | MOD_SEL0_I2C1_A
-		      | MOD_SEL0_HSCIF4_A
-		      | MOD_SEL0_HSCIF3_A
-		      | MOD_SEL0_HSCIF1_A
-		      | MOD_SEL0_FSO_A
-		      | MOD_SEL0_HSCIF2_A
-		      | MOD_SEL0_ETHERAVB_A
-		      | MOD_SEL0_DRIF3_A
-		      | MOD_SEL0_DRIF2_A
-		      | MOD_SEL0_DRIF1_A
-		      | MOD_SEL0_DRIF0_A
-		      | MOD_SEL0_CANFD0_A
-		      | MOD_SEL0_ADG_A_A);
-	pfc_reg_write(PFC_MOD_SEL1, MOD_SEL1_TSIF1_A
-		      | MOD_SEL1_TSIF0_A
-		      | MOD_SEL1_TIMER_TMU_A
-		      | MOD_SEL1_SSP1_1_A
-		      | MOD_SEL1_SSP1_0_A
-		      | MOD_SEL1_SSI_A
-		      | MOD_SEL1_SPEED_PULSE_IF_A
-		      | MOD_SEL1_SIMCARD_A
-		      | MOD_SEL1_SDHI2_A
-		      | MOD_SEL1_SCIF4_A
-		      | MOD_SEL1_SCIF3_A
-		      | MOD_SEL1_SCIF2_A
-		      | MOD_SEL1_SCIF1_A
-		      | MOD_SEL1_SCIF_A
-		      | MOD_SEL1_REMOCON_A
-		      | MOD_SEL1_RCAN0_A
-		      | MOD_SEL1_PWM6_A
-		      | MOD_SEL1_PWM5_A
-		      | MOD_SEL1_PWM4_A
-		      | MOD_SEL1_PWM3_A
-		      | MOD_SEL1_PWM2_A
-		      | MOD_SEL1_PWM1_A);
-	pfc_reg_write(PFC_MOD_SEL2, MOD_SEL2_I2C_5_A
-		      | MOD_SEL2_I2C_3_A
-		      | MOD_SEL2_I2C_0_A
-		      | MOD_SEL2_FM_A
-		      | MOD_SEL2_SCIF5_A
-		      | MOD_SEL2_I2C6_A
-		      | MOD_SEL2_NDF_A
-		      | MOD_SEL2_SSI2_A
-		      | MOD_SEL2_SSI9_A
-		      | MOD_SEL2_TIMER_TMU2_A
-		      | MOD_SEL2_ADG_B_A
-		      | MOD_SEL2_ADG_C_A
-		      | MOD_SEL2_VIN4_A);
-
-	/* initialize peripheral function select */
-	pfc_reg_write(PFC_IPSR0, IPSR_28_FUNC(0)
-		      | IPSR_24_FUNC(0)
-		      | IPSR_20_FUNC(0)
-		      | IPSR_16_FUNC(0)
-		      | IPSR_12_FUNC(0)
-		      | IPSR_8_FUNC(0)
-		      | IPSR_4_FUNC(0)
-		      | IPSR_0_FUNC(0));
-	pfc_reg_write(PFC_IPSR1, IPSR_28_FUNC(6)
-		      | IPSR_24_FUNC(0)
-		      | IPSR_20_FUNC(0)
-		      | IPSR_16_FUNC(0)
-		      | IPSR_12_FUNC(3)
-		      | IPSR_8_FUNC(3)
-		      | IPSR_4_FUNC(3)
-		      | IPSR_0_FUNC(3));
-	pfc_reg_write(PFC_IPSR2, IPSR_28_FUNC(0)
-		      | IPSR_24_FUNC(6)
-		      | IPSR_20_FUNC(6)
-		      | IPSR_16_FUNC(6)
-		      | IPSR_12_FUNC(6)
-		      | IPSR_8_FUNC(6)
-		      | IPSR_4_FUNC(6)
-		      | IPSR_0_FUNC(6));
-	pfc_reg_write(PFC_IPSR3, IPSR_28_FUNC(6)
-		      | IPSR_24_FUNC(6)
-		      | IPSR_20_FUNC(6)
-		      | IPSR_16_FUNC(6)
-		      | IPSR_12_FUNC(6)
-		      | IPSR_8_FUNC(0)
-		      | IPSR_4_FUNC(0)
-		      | IPSR_0_FUNC(0));
-	pfc_reg_write(PFC_IPSR4, IPSR_28_FUNC(0)
-		      | IPSR_24_FUNC(0)
-		      | IPSR_20_FUNC(0)
-		      | IPSR_16_FUNC(0)
-		      | IPSR_12_FUNC(0)
-		      | IPSR_8_FUNC(6)
-		      | IPSR_4_FUNC(6)
-		      | IPSR_0_FUNC(6));
-	pfc_reg_write(PFC_IPSR5, IPSR_28_FUNC(0)
-		      | IPSR_24_FUNC(0)
-		      | IPSR_20_FUNC(0)
-		      | IPSR_16_FUNC(0)
-		      | IPSR_12_FUNC(0)
-		      | IPSR_8_FUNC(6)
-		      | IPSR_4_FUNC(0)
-		      | IPSR_0_FUNC(0));
-	pfc_reg_write(PFC_IPSR6, IPSR_28_FUNC(6)
-		      | IPSR_24_FUNC(6)
-		      | IPSR_20_FUNC(6)
-		      | IPSR_16_FUNC(6)
-		      | IPSR_12_FUNC(6)
-		      | IPSR_8_FUNC(0)
-		      | IPSR_4_FUNC(0)
-		      | IPSR_0_FUNC(0));
-	pfc_reg_write(PFC_IPSR7, IPSR_28_FUNC(0)
-		      | IPSR_24_FUNC(0)
-		      | IPSR_20_FUNC(0)
-		      | IPSR_16_FUNC(0)
-		      | IPSR_12_FUNC(0)
-		      | IPSR_8_FUNC(6)
-		      | IPSR_4_FUNC(6)
-		      | IPSR_0_FUNC(6));
-	pfc_reg_write(PFC_IPSR8, IPSR_28_FUNC(1)
-		      | IPSR_24_FUNC(1)
-		      | IPSR_20_FUNC(1)
-		      | IPSR_16_FUNC(1)
-		      | IPSR_12_FUNC(0)
-		      | IPSR_8_FUNC(0)
-		      | IPSR_4_FUNC(0)
-		      | IPSR_0_FUNC(0));
-	pfc_reg_write(PFC_IPSR9, IPSR_28_FUNC(0)
-		      | IPSR_24_FUNC(0)
-		      | IPSR_20_FUNC(0)
-		      | IPSR_16_FUNC(0)
-		      | IPSR_12_FUNC(0)
-		      | IPSR_8_FUNC(0)
-		      | IPSR_4_FUNC(0)
-		      | IPSR_0_FUNC(0));
-	pfc_reg_write(PFC_IPSR10, IPSR_28_FUNC(1)
-		      | IPSR_24_FUNC(0)
-		      | IPSR_20_FUNC(0)
-		      | IPSR_16_FUNC(0)
-		      | IPSR_12_FUNC(0)
-		      | IPSR_8_FUNC(0)
-		      | IPSR_4_FUNC(0)
-		      | IPSR_0_FUNC(0));
-	pfc_reg_write(PFC_IPSR11, IPSR_28_FUNC(0)
-		      | IPSR_24_FUNC(4)
-		      | IPSR_20_FUNC(0)
-		      | IPSR_16_FUNC(0)
-		      | IPSR_12_FUNC(0)
-		      | IPSR_8_FUNC(0)
-		      | IPSR_4_FUNC(0)
-		      | IPSR_0_FUNC(1));
-	pfc_reg_write(PFC_IPSR12, IPSR_28_FUNC(0)
-		      | IPSR_24_FUNC(0)
-		      | IPSR_20_FUNC(0)
-		      | IPSR_16_FUNC(0)
-		      | IPSR_12_FUNC(0)
-		      | IPSR_8_FUNC(4)
-		      | IPSR_4_FUNC(0)
-		      | IPSR_0_FUNC(0));
-	pfc_reg_write(PFC_IPSR13, IPSR_28_FUNC(8)
-		      | IPSR_24_FUNC(0)
-		      | IPSR_20_FUNC(0)
-		      | IPSR_16_FUNC(0)
-		      | IPSR_12_FUNC(0)
-		      | IPSR_8_FUNC(3)
-		      | IPSR_4_FUNC(0)
-		      | IPSR_0_FUNC(0));
-	pfc_reg_write(PFC_IPSR14, IPSR_28_FUNC(0)
-		      | IPSR_24_FUNC(0)
-		      | IPSR_20_FUNC(0)
-		      | IPSR_16_FUNC(0)
-		      | IPSR_12_FUNC(0)
-		      | IPSR_8_FUNC(0)
-		      | IPSR_4_FUNC(3)
-		      | IPSR_0_FUNC(8));
-	pfc_reg_write(PFC_IPSR15, IPSR_28_FUNC(0)
-		      | IPSR_24_FUNC(0)
-		      | IPSR_20_FUNC(0)
-		      | IPSR_16_FUNC(0)
-		      | IPSR_12_FUNC(0)
-		      | IPSR_8_FUNC(0)
-		      | IPSR_4_FUNC(0)
-		      | IPSR_0_FUNC(0));
-	pfc_reg_write(PFC_IPSR16, IPSR_28_FUNC(0)
-		      | IPSR_24_FUNC(0)
-		      | IPSR_20_FUNC(0)
-		      | IPSR_16_FUNC(0)
-		      | IPSR_12_FUNC(0)
-		      | IPSR_8_FUNC(0)
-		      | IPSR_4_FUNC(0)
-		      | IPSR_0_FUNC(0));
-	pfc_reg_write(PFC_IPSR17, IPSR_28_FUNC(0)
-		      | IPSR_24_FUNC(0)
-		      | IPSR_20_FUNC(0)
-		      | IPSR_16_FUNC(0)
-		      | IPSR_12_FUNC(0)
-		      | IPSR_8_FUNC(0)
-		      | IPSR_4_FUNC(1)
-		      | IPSR_0_FUNC(0));
-	pfc_reg_write(PFC_IPSR18, IPSR_4_FUNC(0)
-		      | IPSR_0_FUNC(0));
-
-	/* initialize GPIO/perihperal function select */
-	pfc_reg_write(PFC_GPSR0, GPSR0_D15
-		      | GPSR0_D14
-		      | GPSR0_D13
-		      | GPSR0_D12
-		      | GPSR0_D11
-		      | GPSR0_D10
-		      | GPSR0_D9
-		      | GPSR0_D8);
-	pfc_reg_write(PFC_GPSR1, GPSR1_CLKOUT
-		      | GPSR1_EX_WAIT0_A
-		      | GPSR1_A19
-		      | GPSR1_A18
-		      | GPSR1_A17
-		      | GPSR1_A16
-		      | GPSR1_A15
-		      | GPSR1_A14
-		      | GPSR1_A13
-		      | GPSR1_A12
-		      | GPSR1_A7
-		      | GPSR1_A6
-		      | GPSR1_A5
-		      | GPSR1_A4
-		      | GPSR1_A3
-		      | GPSR1_A2
-		      | GPSR1_A1
-		      | GPSR1_A0);
-	pfc_reg_write(PFC_GPSR2, GPSR2_AVB_AVTP_CAPTURE_A
-		      | GPSR2_AVB_AVTP_MATCH_A
-		      | GPSR2_AVB_LINK
-		      | GPSR2_AVB_PHY_INT
-		      | GPSR2_AVB_MDC
-		      | GPSR2_PWM2_A
-		      | GPSR2_PWM1_A
-		      | GPSR2_IRQ5
-		      | GPSR2_IRQ4
-		      | GPSR2_IRQ3
-		      | GPSR2_IRQ2
-		      | GPSR2_IRQ1
-		      | GPSR2_IRQ0);
-	pfc_reg_write(PFC_GPSR3, GPSR3_SD0_WP
-		      | GPSR3_SD0_CD
-		      | GPSR3_SD1_DAT3
-		      | GPSR3_SD1_DAT2
-		      | GPSR3_SD1_DAT1
-		      | GPSR3_SD1_DAT0
-		      | GPSR3_SD0_DAT3
-		      | GPSR3_SD0_DAT2
-		      | GPSR3_SD0_DAT1
-		      | GPSR3_SD0_DAT0
-		      | GPSR3_SD0_CMD
-		      | GPSR3_SD0_CLK);
-	pfc_reg_write(PFC_GPSR4, GPSR4_SD3_DAT7
-		      | GPSR4_SD3_DAT6
-		      | GPSR4_SD3_DAT3
-		      | GPSR4_SD3_DAT2
-		      | GPSR4_SD3_DAT1
-		      | GPSR4_SD3_DAT0
-		      | GPSR4_SD3_CMD
-		      | GPSR4_SD3_CLK
-		      | GPSR4_SD2_DS
-		      | GPSR4_SD2_DAT3
-		      | GPSR4_SD2_DAT2
-		      | GPSR4_SD2_DAT1
-		      | GPSR4_SD2_DAT0
-		      | GPSR4_SD2_CMD
-		      | GPSR4_SD2_CLK);
-	pfc_reg_write(PFC_GPSR5, GPSR5_MSIOF0_SS2
-		      | GPSR5_MSIOF0_SS1
-		      | GPSR5_MSIOF0_SYNC
-		      | GPSR5_HRTS0
-		      | GPSR5_HCTS0
-		      | GPSR5_HTX0
-		      | GPSR5_HRX0
-		      | GPSR5_HSCK0
-		      | GPSR5_RX2_A
-		      | GPSR5_TX2_A
-		      | GPSR5_SCK2
-		      | GPSR5_RTS1_TANS
-		      | GPSR5_CTS1
-		      | GPSR5_TX1_A
-		      | GPSR5_RX1_A
-		      | GPSR5_RTS0_TANS
-		      | GPSR5_SCK0);
-	pfc_reg_write(PFC_GPSR6, GPSR6_USB30_OVC
-		      | GPSR6_USB30_PWEN
-		      | GPSR6_USB1_OVC
-		      | GPSR6_USB1_PWEN
-		      | GPSR6_USB0_OVC
-		      | GPSR6_USB0_PWEN
-		      | GPSR6_AUDIO_CLKB_B
-		      | GPSR6_AUDIO_CLKA_A
-		      | GPSR6_SSI_SDATA8
-		      | GPSR6_SSI_SDATA7
-		      | GPSR6_SSI_WS78
-		      | GPSR6_SSI_SCK78
-		      | GPSR6_SSI_WS6
-		      | GPSR6_SSI_SCK6
-		      | GPSR6_SSI_SDATA4
-		      | GPSR6_SSI_WS4
-		      | GPSR6_SSI_SCK4
-		      | GPSR6_SSI_SDATA1_A
-		      | GPSR6_SSI_SDATA0
-		      | GPSR6_SSI_WS0129
-		      | GPSR6_SSI_SCK0129);
-	pfc_reg_write(PFC_GPSR7, GPSR7_HDMI1_CEC
-		      | GPSR7_HDMI0_CEC
-		      | GPSR7_AVS2
-		      | GPSR7_AVS1);
-
-	/* initialize POC control register */
-	pfc_reg_write(PFC_POCCTRL0, POC_SD3_DS_33V
-		      | POC_SD3_DAT7_33V
-		      | POC_SD3_DAT6_33V
-		      | POC_SD3_DAT5_33V
-		      | POC_SD3_DAT4_33V
-		      | POC_SD3_DAT3_33V
-		      | POC_SD3_DAT2_33V
-		      | POC_SD3_DAT1_33V
-		      | POC_SD3_DAT0_33V
-		      | POC_SD3_CMD_33V
-		      | POC_SD3_CLK_33V
-		      | POC_SD0_DAT3_33V
-		      | POC_SD0_DAT2_33V
-		      | POC_SD0_DAT1_33V
-		      | POC_SD0_DAT0_33V
-		      | POC_SD0_CMD_33V
-		      | POC_SD0_CLK_33V);
-
-	/* initialize DRV control register */
-	reg = mmio_read_32(PFC_DRVCTRL0);
-	reg = ((reg & DRVCTRL0_MASK) | DRVCTRL0_QSPI0_SPCLK(3)
-	       | DRVCTRL0_QSPI0_MOSI_IO0(3)
-	       | DRVCTRL0_QSPI0_MISO_IO1(3)
-	       | DRVCTRL0_QSPI0_IO2(3)
-	       | DRVCTRL0_QSPI0_IO3(3)
-	       | DRVCTRL0_QSPI0_SSL(3)
-	       | DRVCTRL0_QSPI1_SPCLK(3)
-	       | DRVCTRL0_QSPI1_MOSI_IO0(3));
-	pfc_reg_write(PFC_DRVCTRL0, reg);
-	reg = mmio_read_32(PFC_DRVCTRL1);
-	reg = ((reg & DRVCTRL1_MASK) | DRVCTRL1_QSPI1_MISO_IO1(3)
-	       | DRVCTRL1_QSPI1_IO2(3)
-	       | DRVCTRL1_QSPI1_IO3(3)
-	       | DRVCTRL1_QSPI1_SS(3)
-	       | DRVCTRL1_RPC_INT(3)
-	       | DRVCTRL1_RPC_WP(3)
-	       | DRVCTRL1_RPC_RESET(3)
-	       | DRVCTRL1_AVB_RX_CTL(7));
-	pfc_reg_write(PFC_DRVCTRL1, reg);
-	reg = mmio_read_32(PFC_DRVCTRL2);
-	reg = ((reg & DRVCTRL2_MASK) | DRVCTRL2_AVB_RXC(7)
-	       | DRVCTRL2_AVB_RD0(7)
-	       | DRVCTRL2_AVB_RD1(7)
-	       | DRVCTRL2_AVB_RD2(7)
-	       | DRVCTRL2_AVB_RD3(7)
-	       | DRVCTRL2_AVB_TX_CTL(3)
-	       | DRVCTRL2_AVB_TXC(3)
-	       | DRVCTRL2_AVB_TD0(3));
-	pfc_reg_write(PFC_DRVCTRL2, reg);
-	reg = mmio_read_32(PFC_DRVCTRL3);
-	reg = ((reg & DRVCTRL3_MASK) | DRVCTRL3_AVB_TD1(3)
-	       | DRVCTRL3_AVB_TD2(3)
-	       | DRVCTRL3_AVB_TD3(3)
-	       | DRVCTRL3_AVB_TXCREFCLK(7)
-	       | DRVCTRL3_AVB_MDIO(7)
-	       | DRVCTRL3_AVB_MDC(7)
-	       | DRVCTRL3_AVB_MAGIC(7)
-	       | DRVCTRL3_AVB_PHY_INT(7));
-	pfc_reg_write(PFC_DRVCTRL3, reg);
-	reg = mmio_read_32(PFC_DRVCTRL4);
-	reg = ((reg & DRVCTRL4_MASK) | DRVCTRL4_AVB_LINK(7)
-	       | DRVCTRL4_AVB_AVTP_MATCH(7)
-	       | DRVCTRL4_AVB_AVTP_CAPTURE(7)
-	       | DRVCTRL4_IRQ0(7)
-	       | DRVCTRL4_IRQ1(7)
-	       | DRVCTRL4_IRQ2(7)
-	       | DRVCTRL4_IRQ3(7)
-	       | DRVCTRL4_IRQ4(7));
-	pfc_reg_write(PFC_DRVCTRL4, reg);
-	reg = mmio_read_32(PFC_DRVCTRL5);
-	reg = ((reg & DRVCTRL5_MASK) | DRVCTRL5_IRQ5(7)
-	       | DRVCTRL5_PWM0(7)
-	       | DRVCTRL5_PWM1(7)
-	       | DRVCTRL5_PWM2(7)
-	       | DRVCTRL5_A0(3)
-	       | DRVCTRL5_A1(3)
-	       | DRVCTRL5_A2(3)
-	       | DRVCTRL5_A3(3));
-	pfc_reg_write(PFC_DRVCTRL5, reg);
-	reg = mmio_read_32(PFC_DRVCTRL6);
-	reg = ((reg & DRVCTRL6_MASK) | DRVCTRL6_A4(3)
-	       | DRVCTRL6_A5(3)
-	       | DRVCTRL6_A6(3)
-	       | DRVCTRL6_A7(3)
-	       | DRVCTRL6_A8(7)
-	       | DRVCTRL6_A9(7)
-	       | DRVCTRL6_A10(7)
-	       | DRVCTRL6_A11(7));
-	pfc_reg_write(PFC_DRVCTRL6, reg);
-	reg = mmio_read_32(PFC_DRVCTRL7);
-	reg = ((reg & DRVCTRL7_MASK) | DRVCTRL7_A12(3)
-	       | DRVCTRL7_A13(3)
-	       | DRVCTRL7_A14(3)
-	       | DRVCTRL7_A15(3)
-	       | DRVCTRL7_A16(3)
-	       | DRVCTRL7_A17(3)
-	       | DRVCTRL7_A18(3)
-	       | DRVCTRL7_A19(3));
-	pfc_reg_write(PFC_DRVCTRL7, reg);
-	reg = mmio_read_32(PFC_DRVCTRL8);
-	reg = ((reg & DRVCTRL8_MASK) | DRVCTRL8_CLKOUT(7)
-	       | DRVCTRL8_CS0(7)
-	       | DRVCTRL8_CS1_A2(7)
-	       | DRVCTRL8_BS(7)
-	       | DRVCTRL8_RD(7)
-	       | DRVCTRL8_RD_W(7)
-	       | DRVCTRL8_WE0(7)
-	       | DRVCTRL8_WE1(7));
-	pfc_reg_write(PFC_DRVCTRL8, reg);
-	reg = mmio_read_32(PFC_DRVCTRL9);
-	reg = ((reg & DRVCTRL9_MASK) | DRVCTRL9_EX_WAIT0(7)
-	       | DRVCTRL9_PRESETOU(7)
-	       | DRVCTRL9_D0(7)
-	       | DRVCTRL9_D1(7)
-	       | DRVCTRL9_D2(7)
-	       | DRVCTRL9_D3(7)
-	       | DRVCTRL9_D4(7)
-	       | DRVCTRL9_D5(7));
-	pfc_reg_write(PFC_DRVCTRL9, reg);
-	reg = mmio_read_32(PFC_DRVCTRL10);
-	reg = ((reg & DRVCTRL10_MASK) | DRVCTRL10_D6(7)
-	       | DRVCTRL10_D7(7)
-	       | DRVCTRL10_D8(3)
-	       | DRVCTRL10_D9(3)
-	       | DRVCTRL10_D10(3)
-	       | DRVCTRL10_D11(3)
-	       | DRVCTRL10_D12(3)
-	       | DRVCTRL10_D13(3));
-	pfc_reg_write(PFC_DRVCTRL10, reg);
-	reg = mmio_read_32(PFC_DRVCTRL11);
-	reg = ((reg & DRVCTRL11_MASK) | DRVCTRL11_D14(3)
-	       | DRVCTRL11_D15(3)
-	       | DRVCTRL11_AVS1(7)
-	       | DRVCTRL11_AVS2(7)
-	       | DRVCTRL11_HDMI0_CEC(7)
-	       | DRVCTRL11_HDMI1_CEC(7)
-	       | DRVCTRL11_DU_DOTCLKIN0(3)
-	       | DRVCTRL11_DU_DOTCLKIN1(3));
-	pfc_reg_write(PFC_DRVCTRL11, reg);
-	reg = mmio_read_32(PFC_DRVCTRL12);
-	reg = ((reg & DRVCTRL12_MASK) | DRVCTRL12_DU_DOTCLKIN2(3)
-	       | DRVCTRL12_DU_DOTCLKIN3(3)
-	       | DRVCTRL12_DU_FSCLKST(3)
-	       | DRVCTRL12_DU_TMS(3));
-	pfc_reg_write(PFC_DRVCTRL12, reg);
-	reg = mmio_read_32(PFC_DRVCTRL13);
-	reg = ((reg & DRVCTRL13_MASK) | DRVCTRL13_TDO(3)
-	       | DRVCTRL13_ASEBRK(3)
-	       | DRVCTRL13_SD0_CLK(7)
-	       | DRVCTRL13_SD0_CMD(7)
-	       | DRVCTRL13_SD0_DAT0(7)
-	       | DRVCTRL13_SD0_DAT1(7)
-	       | DRVCTRL13_SD0_DAT2(7)
-	       | DRVCTRL13_SD0_DAT3(7));
-	pfc_reg_write(PFC_DRVCTRL13, reg);
-	reg = mmio_read_32(PFC_DRVCTRL14);
-	reg = ((reg & DRVCTRL14_MASK) | DRVCTRL14_SD1_CLK(7)
-	       | DRVCTRL14_SD1_CMD(7)
-	       | DRVCTRL14_SD1_DAT0(5)
-	       | DRVCTRL14_SD1_DAT1(5)
-	       | DRVCTRL14_SD1_DAT2(5)
-	       | DRVCTRL14_SD1_DAT3(5)
-	       | DRVCTRL14_SD2_CLK(5)
-	       | DRVCTRL14_SD2_CMD(5));
-	pfc_reg_write(PFC_DRVCTRL14, reg);
-	reg = mmio_read_32(PFC_DRVCTRL15);
-	reg = ((reg & DRVCTRL15_MASK) | DRVCTRL15_SD2_DAT0(5)
-	       | DRVCTRL15_SD2_DAT1(5)
-	       | DRVCTRL15_SD2_DAT2(5)
-	       | DRVCTRL15_SD2_DAT3(5)
-	       | DRVCTRL15_SD2_DS(5)
-	       | DRVCTRL15_SD3_CLK(7)
-	       | DRVCTRL15_SD3_CMD(7)
-	       | DRVCTRL15_SD3_DAT0(7));
-	pfc_reg_write(PFC_DRVCTRL15, reg);
-	reg = mmio_read_32(PFC_DRVCTRL16);
-	reg = ((reg & DRVCTRL16_MASK) | DRVCTRL16_SD3_DAT1(7)
-	       | DRVCTRL16_SD3_DAT2(7)
-	       | DRVCTRL16_SD3_DAT3(7)
-	       | DRVCTRL16_SD3_DAT4(7)
-	       | DRVCTRL16_SD3_DAT5(7)
-	       | DRVCTRL16_SD3_DAT6(7)
-	       | DRVCTRL16_SD3_DAT7(7)
-	       | DRVCTRL16_SD3_DS(7));
-	pfc_reg_write(PFC_DRVCTRL16, reg);
-	reg = mmio_read_32(PFC_DRVCTRL17);
-	reg = ((reg & DRVCTRL17_MASK) | DRVCTRL17_SD0_CD(7)
-	       | DRVCTRL17_SD0_WP(7)
-	       | DRVCTRL17_SD1_CD(7)
-	       | DRVCTRL17_SD1_WP(7)
-	       | DRVCTRL17_SCK0(7)
-	       | DRVCTRL17_RX0(7)
-	       | DRVCTRL17_TX0(7)
-	       | DRVCTRL17_CTS0(7));
-	pfc_reg_write(PFC_DRVCTRL17, reg);
-	reg = mmio_read_32(PFC_DRVCTRL18);
-	reg = ((reg & DRVCTRL18_MASK) | DRVCTRL18_RTS0_TANS(7)
-	       | DRVCTRL18_RX1(7)
-	       | DRVCTRL18_TX1(7)
-	       | DRVCTRL18_CTS1(7)
-	       | DRVCTRL18_RTS1_TANS(7)
-	       | DRVCTRL18_SCK2(7)
-	       | DRVCTRL18_TX2(7)
-	       | DRVCTRL18_RX2(7));
-	pfc_reg_write(PFC_DRVCTRL18, reg);
-	reg = mmio_read_32(PFC_DRVCTRL19);
-	reg = ((reg & DRVCTRL19_MASK) | DRVCTRL19_HSCK0(7)
-	       | DRVCTRL19_HRX0(7)
-	       | DRVCTRL19_HTX0(7)
-	       | DRVCTRL19_HCTS0(7)
-	       | DRVCTRL19_HRTS0(7)
-	       | DRVCTRL19_MSIOF0_SCK(7)
-	       | DRVCTRL19_MSIOF0_SYNC(7)
-	       | DRVCTRL19_MSIOF0_SS1(7));
-	pfc_reg_write(PFC_DRVCTRL19, reg);
-	reg = mmio_read_32(PFC_DRVCTRL20);
-	reg = ((reg & DRVCTRL20_MASK) | DRVCTRL20_MSIOF0_TXD(7)
-	       | DRVCTRL20_MSIOF0_SS2(7)
-	       | DRVCTRL20_MSIOF0_RXD(7)
-	       | DRVCTRL20_MLB_CLK(7)
-	       | DRVCTRL20_MLB_SIG(7)
-	       | DRVCTRL20_MLB_DAT(7)
-	       | DRVCTRL20_MLB_REF(7)
-	       | DRVCTRL20_SSI_SCK0129(7));
-	pfc_reg_write(PFC_DRVCTRL20, reg);
-	reg = mmio_read_32(PFC_DRVCTRL21);
-	reg = ((reg & DRVCTRL21_MASK) | DRVCTRL21_SSI_WS0129(7)
-	       | DRVCTRL21_SSI_SDATA0(7)
-	       | DRVCTRL21_SSI_SDATA1(7)
-	       | DRVCTRL21_SSI_SDATA2(7)
-	       | DRVCTRL21_SSI_SCK34(7)
-	       | DRVCTRL21_SSI_WS34(7)
-	       | DRVCTRL21_SSI_SDATA3(7)
-	       | DRVCTRL21_SSI_SCK4(7));
-	pfc_reg_write(PFC_DRVCTRL21, reg);
-	reg = mmio_read_32(PFC_DRVCTRL22);
-	reg = ((reg & DRVCTRL22_MASK) | DRVCTRL22_SSI_WS4(7)
-	       | DRVCTRL22_SSI_SDATA4(7)
-	       | DRVCTRL22_SSI_SCK5(7)
-	       | DRVCTRL22_SSI_WS5(7)
-	       | DRVCTRL22_SSI_SDATA5(7)
-	       | DRVCTRL22_SSI_SCK6(7)
-	       | DRVCTRL22_SSI_WS6(7)
-	       | DRVCTRL22_SSI_SDATA6(7));
-	pfc_reg_write(PFC_DRVCTRL22, reg);
-	reg = mmio_read_32(PFC_DRVCTRL23);
-	reg = ((reg & DRVCTRL23_MASK) | DRVCTRL23_SSI_SCK78(7)
-	       | DRVCTRL23_SSI_WS78(7)
-	       | DRVCTRL23_SSI_SDATA7(7)
-	       | DRVCTRL23_SSI_SDATA8(7)
-	       | DRVCTRL23_SSI_SDATA9(7)
-	       | DRVCTRL23_AUDIO_CLKA(7)
-	       | DRVCTRL23_AUDIO_CLKB(7)
-	       | DRVCTRL23_USB0_PWEN(7));
-	pfc_reg_write(PFC_DRVCTRL23, reg);
-	reg = mmio_read_32(PFC_DRVCTRL24);
-	reg = ((reg & DRVCTRL24_MASK) | DRVCTRL24_USB0_OVC(7)
-	       | DRVCTRL24_USB1_PWEN(7)
-	       | DRVCTRL24_USB1_OVC(7)
-	       | DRVCTRL24_USB30_PWEN(7)
-	       | DRVCTRL24_USB30_OVC(7)
-	       | DRVCTRL24_USB31_PWEN(7)
-	       | DRVCTRL24_USB31_OVC(7));
-	pfc_reg_write(PFC_DRVCTRL24, reg);
-
-	/* initialize LSI pin pull-up/down control */
-	pfc_reg_write(PFC_PUD0, 0x00005FBFU);
-	pfc_reg_write(PFC_PUD1, 0x00300FFEU);
-	pfc_reg_write(PFC_PUD2, 0x330001E6U);
-	pfc_reg_write(PFC_PUD3, 0x000002E0U);
-	pfc_reg_write(PFC_PUD4, 0xFFFFFF00U);
-	pfc_reg_write(PFC_PUD5, 0x7F5FFF87U);
-	pfc_reg_write(PFC_PUD6, 0x00000055U);
-
-	/* initialize LSI pin pull-enable register */
-	pfc_reg_write(PFC_PUEN0, 0x00000FFFU);
-	pfc_reg_write(PFC_PUEN1, 0x00100234U);
-	pfc_reg_write(PFC_PUEN2, 0x000004C4U);
-	pfc_reg_write(PFC_PUEN3, 0x00000200U);
-	pfc_reg_write(PFC_PUEN4, 0x3E000000U);
-	pfc_reg_write(PFC_PUEN5, 0x1F000805U);
-	pfc_reg_write(PFC_PUEN6, 0x00000006U);
-
-	/* initialize positive/negative logic select */
-	mmio_write_32(GPIO_POSNEG0, 0x00000000U);
-	mmio_write_32(GPIO_POSNEG1, 0x00000000U);
-	mmio_write_32(GPIO_POSNEG2, 0x00000000U);
-	mmio_write_32(GPIO_POSNEG3, 0x00000000U);
-	mmio_write_32(GPIO_POSNEG4, 0x00000000U);
-	mmio_write_32(GPIO_POSNEG5, 0x00000000U);
-	mmio_write_32(GPIO_POSNEG6, 0x00000000U);
-
-	/* initialize general IO/interrupt switching */
-	mmio_write_32(GPIO_IOINTSEL0, 0x00000000U);
-	mmio_write_32(GPIO_IOINTSEL1, 0x00000000U);
-	mmio_write_32(GPIO_IOINTSEL2, 0x00000000U);
-	mmio_write_32(GPIO_IOINTSEL3, 0x00000000U);
-	mmio_write_32(GPIO_IOINTSEL4, 0x00000000U);
-	mmio_write_32(GPIO_IOINTSEL5, 0x00000000U);
-	mmio_write_32(GPIO_IOINTSEL6, 0x00000000U);
-
-	/* initialize general output register */
-	mmio_write_32(GPIO_OUTDT1, 0x00000000U);
-	mmio_write_32(GPIO_OUTDT2, 0x00000400U);
-	mmio_write_32(GPIO_OUTDT3, 0x0000C000U);
-	mmio_write_32(GPIO_OUTDT5, 0x00000006U);
-	mmio_write_32(GPIO_OUTDT6, 0x00003880U);
-
-	/* initialize general input/output switching */
-	mmio_write_32(GPIO_INOUTSEL0, 0x00000000U);
-	mmio_write_32(GPIO_INOUTSEL1, 0x01000A00U);
-	mmio_write_32(GPIO_INOUTSEL2, 0x00000400U);
-	mmio_write_32(GPIO_INOUTSEL3, 0x0000C000U);
-	mmio_write_32(GPIO_INOUTSEL4, 0x00000000U);
-#if (RCAR_GEN3_ULCB == 1)
-	mmio_write_32(GPIO_INOUTSEL5, 0x0000000EU);
-#else
-	mmio_write_32(GPIO_INOUTSEL5, 0x0000020EU);
-#endif
-	mmio_write_32(GPIO_INOUTSEL6, 0x00013880U);
-}
diff --git a/drivers/staging/renesas/rcar/pfc/M3/pfc_init_m3.c b/drivers/staging/renesas/rcar/pfc/M3/pfc_init_m3.c
deleted file mode 100644
index 3bb560f..0000000
--- a/drivers/staging/renesas/rcar/pfc/M3/pfc_init_m3.c
+++ /dev/null
@@ -1,1535 +0,0 @@
-/*
- * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <stdint.h>		/* for uint32_t */
-
-#include <lib/mmio.h>
-
-#include "pfc_init_m3.h"
-#include "rcar_def.h"
-#include "rcar_private.h"
-
-/* GPIO base address */
-#define	GPIO_BASE		(0xE6050000U)
-
-/* GPIO registers */
-#define	GPIO_IOINTSEL0		(GPIO_BASE + 0x0000U)
-#define	GPIO_INOUTSEL0		(GPIO_BASE + 0x0004U)
-#define	GPIO_OUTDT0		(GPIO_BASE + 0x0008U)
-#define	GPIO_INDT0		(GPIO_BASE + 0x000CU)
-#define	GPIO_INTDT0		(GPIO_BASE + 0x0010U)
-#define	GPIO_INTCLR0		(GPIO_BASE + 0x0014U)
-#define	GPIO_INTMSK0		(GPIO_BASE + 0x0018U)
-#define	GPIO_MSKCLR0		(GPIO_BASE + 0x001CU)
-#define	GPIO_POSNEG0		(GPIO_BASE + 0x0020U)
-#define	GPIO_EDGLEVEL0		(GPIO_BASE + 0x0024U)
-#define	GPIO_FILONOFF0		(GPIO_BASE + 0x0028U)
-#define	GPIO_INTMSKS0		(GPIO_BASE + 0x0038U)
-#define	GPIO_MSKCLRS0		(GPIO_BASE + 0x003CU)
-#define	GPIO_OUTDTSEL0		(GPIO_BASE + 0x0040U)
-#define	GPIO_OUTDTH0		(GPIO_BASE + 0x0044U)
-#define	GPIO_OUTDTL0		(GPIO_BASE + 0x0048U)
-#define	GPIO_BOTHEDGE0		(GPIO_BASE + 0x004CU)
-#define	GPIO_IOINTSEL1		(GPIO_BASE + 0x1000U)
-#define	GPIO_INOUTSEL1		(GPIO_BASE + 0x1004U)
-#define	GPIO_OUTDT1		(GPIO_BASE + 0x1008U)
-#define	GPIO_INDT1		(GPIO_BASE + 0x100CU)
-#define	GPIO_INTDT1		(GPIO_BASE + 0x1010U)
-#define	GPIO_INTCLR1		(GPIO_BASE + 0x1014U)
-#define	GPIO_INTMSK1		(GPIO_BASE + 0x1018U)
-#define	GPIO_MSKCLR1		(GPIO_BASE + 0x101CU)
-#define	GPIO_POSNEG1		(GPIO_BASE + 0x1020U)
-#define	GPIO_EDGLEVEL1		(GPIO_BASE + 0x1024U)
-#define	GPIO_FILONOFF1		(GPIO_BASE + 0x1028U)
-#define	GPIO_INTMSKS1		(GPIO_BASE + 0x1038U)
-#define	GPIO_MSKCLRS1		(GPIO_BASE + 0x103CU)
-#define	GPIO_OUTDTSEL1		(GPIO_BASE + 0x1040U)
-#define	GPIO_OUTDTH1		(GPIO_BASE + 0x1044U)
-#define	GPIO_OUTDTL1		(GPIO_BASE + 0x1048U)
-#define	GPIO_BOTHEDGE1		(GPIO_BASE + 0x104CU)
-#define	GPIO_IOINTSEL2		(GPIO_BASE + 0x2000U)
-#define	GPIO_INOUTSEL2		(GPIO_BASE + 0x2004U)
-#define	GPIO_OUTDT2		(GPIO_BASE + 0x2008U)
-#define	GPIO_INDT2		(GPIO_BASE + 0x200CU)
-#define	GPIO_INTDT2		(GPIO_BASE + 0x2010U)
-#define	GPIO_INTCLR2		(GPIO_BASE + 0x2014U)
-#define	GPIO_INTMSK2		(GPIO_BASE + 0x2018U)
-#define	GPIO_MSKCLR2		(GPIO_BASE + 0x201CU)
-#define	GPIO_POSNEG2		(GPIO_BASE + 0x2020U)
-#define	GPIO_EDGLEVEL2		(GPIO_BASE + 0x2024U)
-#define	GPIO_FILONOFF2		(GPIO_BASE + 0x2028U)
-#define	GPIO_INTMSKS2		(GPIO_BASE + 0x2038U)
-#define	GPIO_MSKCLRS2		(GPIO_BASE + 0x203CU)
-#define	GPIO_OUTDTSEL2		(GPIO_BASE + 0x2040U)
-#define	GPIO_OUTDTH2		(GPIO_BASE + 0x2044U)
-#define	GPIO_OUTDTL2		(GPIO_BASE + 0x2048U)
-#define	GPIO_BOTHEDGE2		(GPIO_BASE + 0x204CU)
-#define	GPIO_IOINTSEL3		(GPIO_BASE + 0x3000U)
-#define	GPIO_INOUTSEL3		(GPIO_BASE + 0x3004U)
-#define	GPIO_OUTDT3		(GPIO_BASE + 0x3008U)
-#define	GPIO_INDT3		(GPIO_BASE + 0x300CU)
-#define	GPIO_INTDT3		(GPIO_BASE + 0x3010U)
-#define	GPIO_INTCLR3		(GPIO_BASE + 0x3014U)
-#define	GPIO_INTMSK3		(GPIO_BASE + 0x3018U)
-#define	GPIO_MSKCLR3		(GPIO_BASE + 0x301CU)
-#define	GPIO_POSNEG3		(GPIO_BASE + 0x3020U)
-#define	GPIO_EDGLEVEL3		(GPIO_BASE + 0x3024U)
-#define	GPIO_FILONOFF3		(GPIO_BASE + 0x3028U)
-#define	GPIO_INTMSKS3		(GPIO_BASE + 0x3038U)
-#define	GPIO_MSKCLRS3		(GPIO_BASE + 0x303CU)
-#define	GPIO_OUTDTSEL3		(GPIO_BASE + 0x3040U)
-#define	GPIO_OUTDTH3		(GPIO_BASE + 0x3044U)
-#define	GPIO_OUTDTL3		(GPIO_BASE + 0x3048U)
-#define	GPIO_BOTHEDGE3		(GPIO_BASE + 0x304CU)
-#define	GPIO_IOINTSEL4		(GPIO_BASE + 0x4000U)
-#define	GPIO_INOUTSEL4		(GPIO_BASE + 0x4004U)
-#define	GPIO_OUTDT4		(GPIO_BASE + 0x4008U)
-#define	GPIO_INDT4		(GPIO_BASE + 0x400CU)
-#define	GPIO_INTDT4		(GPIO_BASE + 0x4010U)
-#define	GPIO_INTCLR4		(GPIO_BASE + 0x4014U)
-#define	GPIO_INTMSK4		(GPIO_BASE + 0x4018U)
-#define	GPIO_MSKCLR4		(GPIO_BASE + 0x401CU)
-#define	GPIO_POSNEG4		(GPIO_BASE + 0x4020U)
-#define	GPIO_EDGLEVEL4		(GPIO_BASE + 0x4024U)
-#define	GPIO_FILONOFF4		(GPIO_BASE + 0x4028U)
-#define	GPIO_INTMSKS4		(GPIO_BASE + 0x4038U)
-#define	GPIO_MSKCLRS4		(GPIO_BASE + 0x403CU)
-#define	GPIO_OUTDTSEL4		(GPIO_BASE + 0x4040U)
-#define	GPIO_OUTDTH4		(GPIO_BASE + 0x4044U)
-#define	GPIO_OUTDTL4		(GPIO_BASE + 0x4048U)
-#define	GPIO_BOTHEDGE4		(GPIO_BASE + 0x404CU)
-#define	GPIO_IOINTSEL5		(GPIO_BASE + 0x5000U)
-#define	GPIO_INOUTSEL5		(GPIO_BASE + 0x5004U)
-#define	GPIO_OUTDT5		(GPIO_BASE + 0x5008U)
-#define	GPIO_INDT5		(GPIO_BASE + 0x500CU)
-#define	GPIO_INTDT5		(GPIO_BASE + 0x5010U)
-#define	GPIO_INTCLR5		(GPIO_BASE + 0x5014U)
-#define	GPIO_INTMSK5		(GPIO_BASE + 0x5018U)
-#define	GPIO_MSKCLR5		(GPIO_BASE + 0x501CU)
-#define	GPIO_POSNEG5		(GPIO_BASE + 0x5020U)
-#define	GPIO_EDGLEVEL5		(GPIO_BASE + 0x5024U)
-#define	GPIO_FILONOFF5		(GPIO_BASE + 0x5028U)
-#define	GPIO_INTMSKS5		(GPIO_BASE + 0x5038U)
-#define	GPIO_MSKCLRS5		(GPIO_BASE + 0x503CU)
-#define	GPIO_OUTDTSEL5		(GPIO_BASE + 0x5040U)
-#define	GPIO_OUTDTH5		(GPIO_BASE + 0x5044U)
-#define	GPIO_OUTDTL5		(GPIO_BASE + 0x5048U)
-#define	GPIO_BOTHEDGE5		(GPIO_BASE + 0x504CU)
-#define	GPIO_IOINTSEL6		(GPIO_BASE + 0x5400U)
-#define	GPIO_INOUTSEL6		(GPIO_BASE + 0x5404U)
-#define	GPIO_OUTDT6		(GPIO_BASE + 0x5408U)
-#define	GPIO_INDT6		(GPIO_BASE + 0x540CU)
-#define	GPIO_INTDT6		(GPIO_BASE + 0x5410U)
-#define	GPIO_INTCLR6		(GPIO_BASE + 0x5414U)
-#define	GPIO_INTMSK6		(GPIO_BASE + 0x5418U)
-#define	GPIO_MSKCLR6		(GPIO_BASE + 0x541CU)
-#define	GPIO_POSNEG6		(GPIO_BASE + 0x5420U)
-#define	GPIO_EDGLEVEL6		(GPIO_BASE + 0x5424U)
-#define	GPIO_FILONOFF6		(GPIO_BASE + 0x5428U)
-#define	GPIO_INTMSKS6		(GPIO_BASE + 0x5438U)
-#define	GPIO_MSKCLRS6		(GPIO_BASE + 0x543CU)
-#define	GPIO_OUTDTSEL6		(GPIO_BASE + 0x5440U)
-#define	GPIO_OUTDTH6		(GPIO_BASE + 0x5444U)
-#define	GPIO_OUTDTL6		(GPIO_BASE + 0x5448U)
-#define	GPIO_BOTHEDGE6		(GPIO_BASE + 0x544CU)
-#define	GPIO_IOINTSEL7		(GPIO_BASE + 0x5800U)
-#define	GPIO_INOUTSEL7		(GPIO_BASE + 0x5804U)
-#define	GPIO_OUTDT7		(GPIO_BASE + 0x5808U)
-#define	GPIO_INDT7		(GPIO_BASE + 0x580CU)
-#define	GPIO_INTDT7		(GPIO_BASE + 0x5810U)
-#define	GPIO_INTCLR7		(GPIO_BASE + 0x5814U)
-#define	GPIO_INTMSK7		(GPIO_BASE + 0x5818U)
-#define	GPIO_MSKCLR7		(GPIO_BASE + 0x581CU)
-#define	GPIO_POSNEG7		(GPIO_BASE + 0x5820U)
-#define	GPIO_EDGLEVEL7		(GPIO_BASE + 0x5824U)
-#define	GPIO_FILONOFF7		(GPIO_BASE + 0x5828U)
-#define	GPIO_INTMSKS7		(GPIO_BASE + 0x5838U)
-#define	GPIO_MSKCLRS7		(GPIO_BASE + 0x583CU)
-#define	GPIO_OUTDTSEL7		(GPIO_BASE + 0x5840U)
-#define	GPIO_OUTDTH7		(GPIO_BASE + 0x5844U)
-#define	GPIO_OUTDTL7		(GPIO_BASE + 0x5848U)
-#define	GPIO_BOTHEDGE7		(GPIO_BASE + 0x584CU)
-
-/* Pin functon base address */
-#define	PFC_BASE		(0xE6060000U)
-
-/* Pin functon registers */
-#define	PFC_PMMR		(PFC_BASE + 0x0000U)
-#define PFC_GPSR0		(PFC_BASE + 0x0100U)
-#define PFC_GPSR1		(PFC_BASE + 0x0104U)
-#define PFC_GPSR2		(PFC_BASE + 0x0108U)
-#define PFC_GPSR3		(PFC_BASE + 0x010CU)
-#define PFC_GPSR4		(PFC_BASE + 0x0110U)
-#define	PFC_GPSR5		(PFC_BASE + 0x0114U)
-#define	PFC_GPSR6		(PFC_BASE + 0x0118U)
-#define	PFC_GPSR7		(PFC_BASE + 0x011CU)
-#define	PFC_IPSR0		(PFC_BASE + 0x0200U)
-#define	PFC_IPSR1		(PFC_BASE + 0x0204U)
-#define	PFC_IPSR2		(PFC_BASE + 0x0208U)
-#define	PFC_IPSR3		(PFC_BASE + 0x020CU)
-#define	PFC_IPSR4		(PFC_BASE + 0x0210U)
-#define	PFC_IPSR5		(PFC_BASE + 0x0214U)
-#define	PFC_IPSR6		(PFC_BASE + 0x0218U)
-#define	PFC_IPSR7		(PFC_BASE + 0x021CU)
-#define	PFC_IPSR8		(PFC_BASE + 0x0220U)
-#define	PFC_IPSR9		(PFC_BASE + 0x0224U)
-#define	PFC_IPSR10		(PFC_BASE + 0x0228U)
-#define	PFC_IPSR11		(PFC_BASE + 0x022CU)
-#define	PFC_IPSR12		(PFC_BASE + 0x0230U)
-#define	PFC_IPSR13		(PFC_BASE + 0x0234U)
-#define	PFC_IPSR14		(PFC_BASE + 0x0238U)
-#define	PFC_IPSR15		(PFC_BASE + 0x023CU)
-#define	PFC_IPSR16		(PFC_BASE + 0x0240U)
-#define	PFC_IPSR17		(PFC_BASE + 0x0244U)
-#define	PFC_IPSR18		(PFC_BASE + 0x0248U)
-#define PFC_DRVCTRL0		(PFC_BASE + 0x0300U)
-#define PFC_DRVCTRL1		(PFC_BASE + 0x0304U)
-#define PFC_DRVCTRL2		(PFC_BASE + 0x0308U)
-#define PFC_DRVCTRL3		(PFC_BASE + 0x030CU)
-#define PFC_DRVCTRL4		(PFC_BASE + 0x0310U)
-#define PFC_DRVCTRL5		(PFC_BASE + 0x0314U)
-#define PFC_DRVCTRL6		(PFC_BASE + 0x0318U)
-#define PFC_DRVCTRL7		(PFC_BASE + 0x031CU)
-#define PFC_DRVCTRL8		(PFC_BASE + 0x0320U)
-#define PFC_DRVCTRL9		(PFC_BASE + 0x0324U)
-#define PFC_DRVCTRL10		(PFC_BASE + 0x0328U)
-#define PFC_DRVCTRL11		(PFC_BASE + 0x032CU)
-#define PFC_DRVCTRL12		(PFC_BASE + 0x0330U)
-#define PFC_DRVCTRL13		(PFC_BASE + 0x0334U)
-#define PFC_DRVCTRL14		(PFC_BASE + 0x0338U)
-#define PFC_DRVCTRL15		(PFC_BASE + 0x033CU)
-#define PFC_DRVCTRL16		(PFC_BASE + 0x0340U)
-#define PFC_DRVCTRL17		(PFC_BASE + 0x0344U)
-#define PFC_DRVCTRL18		(PFC_BASE + 0x0348U)
-#define PFC_DRVCTRL19		(PFC_BASE + 0x034CU)
-#define PFC_DRVCTRL20		(PFC_BASE + 0x0350U)
-#define PFC_DRVCTRL21		(PFC_BASE + 0x0354U)
-#define PFC_DRVCTRL22		(PFC_BASE + 0x0358U)
-#define PFC_DRVCTRL23		(PFC_BASE + 0x035CU)
-#define PFC_DRVCTRL24		(PFC_BASE + 0x0360U)
-#define PFC_POCCTRL0		(PFC_BASE + 0x0380U)
-#define	PFC_TDSELCTRL0		(PFC_BASE + 0x03C0U)
-#define	PFC_IOCTRL		(PFC_BASE + 0x03E0U)
-#define	PFC_TSREG		(PFC_BASE + 0x03E4U)
-#define	PFC_PUEN0		(PFC_BASE + 0x0400U)
-#define	PFC_PUEN1		(PFC_BASE + 0x0404U)
-#define	PFC_PUEN2		(PFC_BASE + 0x0408U)
-#define	PFC_PUEN3		(PFC_BASE + 0x040CU)
-#define	PFC_PUEN4		(PFC_BASE + 0x0410U)
-#define	PFC_PUEN5		(PFC_BASE + 0x0414U)
-#define	PFC_PUEN6		(PFC_BASE + 0x0418U)
-#define	PFC_PUD0		(PFC_BASE + 0x0440U)
-#define	PFC_PUD1		(PFC_BASE + 0x0444U)
-#define	PFC_PUD2		(PFC_BASE + 0x0448U)
-#define	PFC_PUD3		(PFC_BASE + 0x044CU)
-#define	PFC_PUD4		(PFC_BASE + 0x0450U)
-#define	PFC_PUD5		(PFC_BASE + 0x0454U)
-#define	PFC_PUD6		(PFC_BASE + 0x0458U)
-#define	PFC_MOD_SEL0		(PFC_BASE + 0x0500U)
-#define	PFC_MOD_SEL1		(PFC_BASE + 0x0504U)
-#define	PFC_MOD_SEL2		(PFC_BASE + 0x0508U)
-
-#define	GPSR0_D15		((uint32_t)1U << 15U)
-#define	GPSR0_D14		((uint32_t)1U << 14U)
-#define	GPSR0_D13		((uint32_t)1U << 13U)
-#define	GPSR0_D12		((uint32_t)1U << 12U)
-#define	GPSR0_D11		((uint32_t)1U << 11U)
-#define	GPSR0_D10		((uint32_t)1U << 10U)
-#define	GPSR0_D9		((uint32_t)1U << 9U)
-#define	GPSR0_D8		((uint32_t)1U << 8U)
-#define	GPSR0_D7		((uint32_t)1U << 7U)
-#define	GPSR0_D6		((uint32_t)1U << 6U)
-#define	GPSR0_D5		((uint32_t)1U << 5U)
-#define	GPSR0_D4		((uint32_t)1U << 4U)
-#define	GPSR0_D3		((uint32_t)1U << 3U)
-#define	GPSR0_D2		((uint32_t)1U << 2U)
-#define	GPSR0_D1		((uint32_t)1U << 1U)
-#define	GPSR0_D0		((uint32_t)1U << 0U)
-#define	GPSR1_CLKOUT		((uint32_t)1U << 28U)
-#define	GPSR1_EX_WAIT0_A	((uint32_t)1U << 27U)
-#define	GPSR1_WE1		((uint32_t)1U << 26U)
-#define	GPSR1_WE0		((uint32_t)1U << 25U)
-#define	GPSR1_RD_WR		((uint32_t)1U << 24U)
-#define	GPSR1_RD		((uint32_t)1U << 23U)
-#define	GPSR1_BS		((uint32_t)1U << 22U)
-#define	GPSR1_CS1_A26		((uint32_t)1U << 21U)
-#define	GPSR1_CS0		((uint32_t)1U << 20U)
-#define	GPSR1_A19		((uint32_t)1U << 19U)
-#define	GPSR1_A18		((uint32_t)1U << 18U)
-#define	GPSR1_A17		((uint32_t)1U << 17U)
-#define	GPSR1_A16		((uint32_t)1U << 16U)
-#define	GPSR1_A15		((uint32_t)1U << 15U)
-#define	GPSR1_A14		((uint32_t)1U << 14U)
-#define	GPSR1_A13		((uint32_t)1U << 13U)
-#define	GPSR1_A12		((uint32_t)1U << 12U)
-#define	GPSR1_A11		((uint32_t)1U << 11U)
-#define	GPSR1_A10		((uint32_t)1U << 10U)
-#define	GPSR1_A9		((uint32_t)1U << 9U)
-#define	GPSR1_A8		((uint32_t)1U << 8U)
-#define	GPSR1_A7		((uint32_t)1U << 7U)
-#define	GPSR1_A6		((uint32_t)1U << 6U)
-#define	GPSR1_A5		((uint32_t)1U << 5U)
-#define	GPSR1_A4		((uint32_t)1U << 4U)
-#define	GPSR1_A3		((uint32_t)1U << 3U)
-#define	GPSR1_A2		((uint32_t)1U << 2U)
-#define	GPSR1_A1		((uint32_t)1U << 1U)
-#define	GPSR1_A0		((uint32_t)1U << 0U)
-#define	GPSR2_AVB_AVTP_CAPTURE_A	((uint32_t)1U << 14U)
-#define	GPSR2_AVB_AVTP_MATCH_A	((uint32_t)1U << 13U)
-#define	GPSR2_AVB_LINK		((uint32_t)1U << 12U)
-#define	GPSR2_AVB_PHY_INT	((uint32_t)1U << 11U)
-#define	GPSR2_AVB_MAGIC		((uint32_t)1U << 10U)
-#define	GPSR2_AVB_MDC		((uint32_t)1U << 9U)
-#define	GPSR2_PWM2_A		((uint32_t)1U << 8U)
-#define	GPSR2_PWM1_A		((uint32_t)1U << 7U)
-#define	GPSR2_PWM0		((uint32_t)1U << 6U)
-#define	GPSR2_IRQ5		((uint32_t)1U << 5U)
-#define	GPSR2_IRQ4		((uint32_t)1U << 4U)
-#define	GPSR2_IRQ3		((uint32_t)1U << 3U)
-#define	GPSR2_IRQ2		((uint32_t)1U << 2U)
-#define	GPSR2_IRQ1		((uint32_t)1U << 1U)
-#define	GPSR2_IRQ0		((uint32_t)1U << 0U)
-#define	GPSR3_SD1_WP		((uint32_t)1U << 15U)
-#define	GPSR3_SD1_CD		((uint32_t)1U << 14U)
-#define	GPSR3_SD0_WP		((uint32_t)1U << 13U)
-#define	GPSR3_SD0_CD		((uint32_t)1U << 12U)
-#define	GPSR3_SD1_DAT3		((uint32_t)1U << 11U)
-#define	GPSR3_SD1_DAT2		((uint32_t)1U << 10U)
-#define	GPSR3_SD1_DAT1		((uint32_t)1U << 9U)
-#define	GPSR3_SD1_DAT0		((uint32_t)1U << 8U)
-#define	GPSR3_SD1_CMD		((uint32_t)1U << 7U)
-#define	GPSR3_SD1_CLK		((uint32_t)1U << 6U)
-#define	GPSR3_SD0_DAT3		((uint32_t)1U << 5U)
-#define	GPSR3_SD0_DAT2		((uint32_t)1U << 4U)
-#define	GPSR3_SD0_DAT1		((uint32_t)1U << 3U)
-#define	GPSR3_SD0_DAT0		((uint32_t)1U << 2U)
-#define	GPSR3_SD0_CMD		((uint32_t)1U << 1U)
-#define	GPSR3_SD0_CLK		((uint32_t)1U << 0U)
-#define	GPSR4_SD3_DS		((uint32_t)1U << 17U)
-#define	GPSR4_SD3_DAT7		((uint32_t)1U << 16U)
-#define	GPSR4_SD3_DAT6		((uint32_t)1U << 15U)
-#define	GPSR4_SD3_DAT5		((uint32_t)1U << 14U)
-#define	GPSR4_SD3_DAT4		((uint32_t)1U << 13U)
-#define	GPSR4_SD3_DAT3		((uint32_t)1U << 12U)
-#define	GPSR4_SD3_DAT2		((uint32_t)1U << 11U)
-#define	GPSR4_SD3_DAT1		((uint32_t)1U << 10U)
-#define	GPSR4_SD3_DAT0		((uint32_t)1U << 9U)
-#define	GPSR4_SD3_CMD		((uint32_t)1U << 8U)
-#define	GPSR4_SD3_CLK		((uint32_t)1U << 7U)
-#define	GPSR4_SD2_DS		((uint32_t)1U << 6U)
-#define	GPSR4_SD2_DAT3		((uint32_t)1U << 5U)
-#define	GPSR4_SD2_DAT2		((uint32_t)1U << 4U)
-#define	GPSR4_SD2_DAT1		((uint32_t)1U << 3U)
-#define	GPSR4_SD2_DAT0		((uint32_t)1U << 2U)
-#define	GPSR4_SD2_CMD		((uint32_t)1U << 1U)
-#define	GPSR4_SD2_CLK		((uint32_t)1U << 0U)
-#define	GPSR5_MLB_DAT		((uint32_t)1U << 25U)
-#define	GPSR5_MLB_SIG		((uint32_t)1U << 24U)
-#define	GPSR5_MLB_CLK		((uint32_t)1U << 23U)
-#define	GPSR5_MSIOF0_RXD	((uint32_t)1U << 22U)
-#define	GPSR5_MSIOF0_SS2	((uint32_t)1U << 21U)
-#define	GPSR5_MSIOF0_TXD	((uint32_t)1U << 20U)
-#define	GPSR5_MSIOF0_SS1	((uint32_t)1U << 19U)
-#define	GPSR5_MSIOF0_SYNC	((uint32_t)1U << 18U)
-#define	GPSR5_MSIOF0_SCK	((uint32_t)1U << 17U)
-#define	GPSR5_HRTS0		((uint32_t)1U << 16U)
-#define	GPSR5_HCTS0		((uint32_t)1U << 15U)
-#define	GPSR5_HTX0		((uint32_t)1U << 14U)
-#define	GPSR5_HRX0		((uint32_t)1U << 13U)
-#define	GPSR5_HSCK0		((uint32_t)1U << 12U)
-#define	GPSR5_RX2_A		((uint32_t)1U << 11U)
-#define	GPSR5_TX2_A		((uint32_t)1U << 10U)
-#define	GPSR5_SCK2		((uint32_t)1U << 9U)
-#define	GPSR5_RTS1_TANS		((uint32_t)1U << 8U)
-#define	GPSR5_CTS1		((uint32_t)1U << 7U)
-#define	GPSR5_TX1_A		((uint32_t)1U << 6U)
-#define	GPSR5_RX1_A		((uint32_t)1U << 5U)
-#define	GPSR5_RTS0_TANS		((uint32_t)1U << 4U)
-#define	GPSR5_CTS0		((uint32_t)1U << 3U)
-#define	GPSR5_TX0		((uint32_t)1U << 2U)
-#define	GPSR5_RX0		((uint32_t)1U << 1U)
-#define	GPSR5_SCK0		((uint32_t)1U << 0U)
-#define	GPSR6_USB31_OVC		((uint32_t)1U << 31U)
-#define	GPSR6_USB31_PWEN	((uint32_t)1U << 30U)
-#define	GPSR6_USB30_OVC		((uint32_t)1U << 29U)
-#define	GPSR6_USB30_PWEN	((uint32_t)1U << 28U)
-#define	GPSR6_USB1_OVC		((uint32_t)1U << 27U)
-#define	GPSR6_USB1_PWEN		((uint32_t)1U << 26U)
-#define	GPSR6_USB0_OVC		((uint32_t)1U << 25U)
-#define	GPSR6_USB0_PWEN		((uint32_t)1U << 24U)
-#define	GPSR6_AUDIO_CLKB_B	((uint32_t)1U << 23U)
-#define	GPSR6_AUDIO_CLKA_A	((uint32_t)1U << 22U)
-#define	GPSR6_SSI_SDATA9_A	((uint32_t)1U << 21U)
-#define	GPSR6_SSI_SDATA8	((uint32_t)1U << 20U)
-#define	GPSR6_SSI_SDATA7	((uint32_t)1U << 19U)
-#define	GPSR6_SSI_WS78		((uint32_t)1U << 18U)
-#define	GPSR6_SSI_SCK78		((uint32_t)1U << 17U)
-#define	GPSR6_SSI_SDATA6	((uint32_t)1U << 16U)
-#define	GPSR6_SSI_WS6		((uint32_t)1U << 15U)
-#define	GPSR6_SSI_SCK6		((uint32_t)1U << 14U)
-#define	GPSR6_SSI_SDATA5	((uint32_t)1U << 13U)
-#define	GPSR6_SSI_WS5		((uint32_t)1U << 12U)
-#define	GPSR6_SSI_SCK5		((uint32_t)1U << 11U)
-#define	GPSR6_SSI_SDATA4	((uint32_t)1U << 10U)
-#define	GPSR6_SSI_WS4		((uint32_t)1U << 9U)
-#define	GPSR6_SSI_SCK4		((uint32_t)1U << 8U)
-#define	GPSR6_SSI_SDATA3	((uint32_t)1U << 7U)
-#define	GPSR6_SSI_WS34		((uint32_t)1U << 6U)
-#define	GPSR6_SSI_SCK34		((uint32_t)1U << 5U)
-#define	GPSR6_SSI_SDATA2_A	((uint32_t)1U << 4U)
-#define	GPSR6_SSI_SDATA1_A	((uint32_t)1U << 3U)
-#define	GPSR6_SSI_SDATA0	((uint32_t)1U << 2U)
-#define	GPSR6_SSI_WS0129	((uint32_t)1U << 1U)
-#define	GPSR6_SSI_SCK0129	((uint32_t)1U << 0U)
-#define	GPSR7_HDMI1_CEC		((uint32_t)1U << 3U)
-#define	GPSR7_HDMI0_CEC		((uint32_t)1U << 2U)
-#define	GPSR7_AVS2		((uint32_t)1U << 1U)
-#define	GPSR7_AVS1		((uint32_t)1U << 0U)
-
-#define	IPSR_28_FUNC(x)		((uint32_t)(x) << 28U)
-#define	IPSR_24_FUNC(x)		((uint32_t)(x) << 24U)
-#define	IPSR_20_FUNC(x)		((uint32_t)(x) << 20U)
-#define	IPSR_16_FUNC(x)		((uint32_t)(x) << 16U)
-#define	IPSR_12_FUNC(x)		((uint32_t)(x) << 12U)
-#define	IPSR_8_FUNC(x)		((uint32_t)(x) << 8U)
-#define	IPSR_4_FUNC(x)		((uint32_t)(x) << 4U)
-#define	IPSR_0_FUNC(x)		((uint32_t)(x) << 0U)
-
-#define	POC_SD3_DS_33V		((uint32_t)1U << 29U)
-#define	POC_SD3_DAT7_33V	((uint32_t)1U << 28U)
-#define	POC_SD3_DAT6_33V	((uint32_t)1U << 27U)
-#define	POC_SD3_DAT5_33V	((uint32_t)1U << 26U)
-#define	POC_SD3_DAT4_33V	((uint32_t)1U << 25U)
-#define	POC_SD3_DAT3_33V	((uint32_t)1U << 24U)
-#define	POC_SD3_DAT2_33V	((uint32_t)1U << 23U)
-#define	POC_SD3_DAT1_33V	((uint32_t)1U << 22U)
-#define	POC_SD3_DAT0_33V	((uint32_t)1U << 21U)
-#define	POC_SD3_CMD_33V		((uint32_t)1U << 20U)
-#define	POC_SD3_CLK_33V		((uint32_t)1U << 19U)
-#define	POC_SD2_DS_33V		((uint32_t)1U << 18U)
-#define	POC_SD2_DAT3_33V	((uint32_t)1U << 17U)
-#define	POC_SD2_DAT2_33V	((uint32_t)1U << 16U)
-#define	POC_SD2_DAT1_33V	((uint32_t)1U << 15U)
-#define	POC_SD2_DAT0_33V	((uint32_t)1U << 14U)
-#define	POC_SD2_CMD_33V		((uint32_t)1U << 13U)
-#define	POC_SD2_CLK_33V		((uint32_t)1U << 12U)
-#define	POC_SD1_DAT3_33V	((uint32_t)1U << 11U)
-#define	POC_SD1_DAT2_33V	((uint32_t)1U << 10U)
-#define	POC_SD1_DAT1_33V	((uint32_t)1U << 9U)
-#define	POC_SD1_DAT0_33V	((uint32_t)1U << 8U)
-#define	POC_SD1_CMD_33V		((uint32_t)1U << 7U)
-#define	POC_SD1_CLK_33V		((uint32_t)1U << 6U)
-#define	POC_SD0_DAT3_33V	((uint32_t)1U << 5U)
-#define	POC_SD0_DAT2_33V	((uint32_t)1U << 4U)
-#define	POC_SD0_DAT1_33V	((uint32_t)1U << 3U)
-#define	POC_SD0_DAT0_33V	((uint32_t)1U << 2U)
-#define	POC_SD0_CMD_33V		((uint32_t)1U << 1U)
-#define	POC_SD0_CLK_33V		((uint32_t)1U << 0U)
-
-#define	DRVCTRL0_MASK		(0xCCCCCCCCU)
-#define	DRVCTRL1_MASK		(0xCCCCCCC8U)
-#define	DRVCTRL2_MASK		(0x88888888U)
-#define	DRVCTRL3_MASK		(0x88888888U)
-#define	DRVCTRL4_MASK		(0x88888888U)
-#define	DRVCTRL5_MASK		(0x88888888U)
-#define	DRVCTRL6_MASK		(0x88888888U)
-#define	DRVCTRL7_MASK		(0x88888888U)
-#define	DRVCTRL8_MASK		(0x88888888U)
-#define	DRVCTRL9_MASK		(0x88888888U)
-#define	DRVCTRL10_MASK		(0x88888888U)
-#define	DRVCTRL11_MASK		(0x888888CCU)
-#define	DRVCTRL12_MASK		(0xCCCFFFCFU)
-#define	DRVCTRL13_MASK		(0xCC888888U)
-#define	DRVCTRL14_MASK		(0x88888888U)
-#define	DRVCTRL15_MASK		(0x88888888U)
-#define	DRVCTRL16_MASK		(0x88888888U)
-#define	DRVCTRL17_MASK		(0x88888888U)
-#define	DRVCTRL18_MASK		(0x88888888U)
-#define	DRVCTRL19_MASK		(0x88888888U)
-#define	DRVCTRL20_MASK		(0x88888888U)
-#define	DRVCTRL21_MASK		(0x88888888U)
-#define	DRVCTRL22_MASK		(0x88888888U)
-#define	DRVCTRL23_MASK		(0x88888888U)
-#define	DRVCTRL24_MASK		(0x8888888FU)
-
-#define	DRVCTRL0_QSPI0_SPCLK(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL0_QSPI0_MOSI_IO0(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL0_QSPI0_MISO_IO1(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL0_QSPI0_IO2(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL0_QSPI0_IO3(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL0_QSPI0_SSL(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL0_QSPI1_SPCLK(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL0_QSPI1_MOSI_IO0(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL1_QSPI1_MISO_IO1(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL1_QSPI1_IO2(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL1_QSPI1_IO3(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL1_QSPI1_SS(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL1_RPC_INT(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL1_RPC_WP(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL1_RPC_RESET(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL1_AVB_RX_CTL(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL2_AVB_RXC(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL2_AVB_RD0(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL2_AVB_RD1(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL2_AVB_RD2(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL2_AVB_RD3(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL2_AVB_TX_CTL(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL2_AVB_TXC(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL2_AVB_TD0(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL3_AVB_TD1(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL3_AVB_TD2(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL3_AVB_TD3(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL3_AVB_TXCREFCLK(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL3_AVB_MDIO(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL3_AVB_MDC(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL3_AVB_MAGIC(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL3_AVB_PHY_INT(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL4_AVB_LINK(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL4_AVB_AVTP_MATCH(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL4_AVB_AVTP_CAPTURE(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL4_IRQ0(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL4_IRQ1(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL4_IRQ2(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL4_IRQ3(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL4_IRQ4(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL5_IRQ5(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL5_PWM0(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL5_PWM1(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL5_PWM2(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL5_A0(x)		((uint32_t)(x) << 12U)
-#define	DRVCTRL5_A1(x)		((uint32_t)(x) << 8U)
-#define	DRVCTRL5_A2(x)		((uint32_t)(x) << 4U)
-#define	DRVCTRL5_A3(x)		((uint32_t)(x) << 0U)
-#define	DRVCTRL6_A4(x)		((uint32_t)(x) << 28U)
-#define	DRVCTRL6_A5(x)		((uint32_t)(x) << 24U)
-#define	DRVCTRL6_A6(x)		((uint32_t)(x) << 20U)
-#define	DRVCTRL6_A7(x)		((uint32_t)(x) << 16U)
-#define	DRVCTRL6_A8(x)		((uint32_t)(x) << 12U)
-#define	DRVCTRL6_A9(x)		((uint32_t)(x) << 8U)
-#define	DRVCTRL6_A10(x)		((uint32_t)(x) << 4U)
-#define	DRVCTRL6_A11(x)		((uint32_t)(x) << 0U)
-#define	DRVCTRL7_A12(x)		((uint32_t)(x) << 28U)
-#define	DRVCTRL7_A13(x)		((uint32_t)(x) << 24U)
-#define	DRVCTRL7_A14(x)		((uint32_t)(x) << 20U)
-#define	DRVCTRL7_A15(x)		((uint32_t)(x) << 16U)
-#define	DRVCTRL7_A16(x)		((uint32_t)(x) << 12U)
-#define	DRVCTRL7_A17(x)		((uint32_t)(x) << 8U)
-#define	DRVCTRL7_A18(x)		((uint32_t)(x) << 4U)
-#define	DRVCTRL7_A19(x)		((uint32_t)(x) << 0U)
-#define	DRVCTRL8_CLKOUT(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL8_CS0(x)		((uint32_t)(x) << 24U)
-#define	DRVCTRL8_CS1_A2(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL8_BS(x)		((uint32_t)(x) << 16U)
-#define	DRVCTRL8_RD(x)		((uint32_t)(x) << 12U)
-#define	DRVCTRL8_RD_W(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL8_WE0(x)		((uint32_t)(x) << 4U)
-#define	DRVCTRL8_WE1(x)		((uint32_t)(x) << 0U)
-#define	DRVCTRL9_EX_WAIT0(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL9_PRESETOU(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL9_D0(x)		((uint32_t)(x) << 20U)
-#define	DRVCTRL9_D1(x)		((uint32_t)(x) << 16U)
-#define	DRVCTRL9_D2(x)		((uint32_t)(x) << 12U)
-#define	DRVCTRL9_D3(x)		((uint32_t)(x) << 8U)
-#define	DRVCTRL9_D4(x)		((uint32_t)(x) << 4U)
-#define	DRVCTRL9_D5(x)		((uint32_t)(x) << 0U)
-#define	DRVCTRL10_D6(x)		((uint32_t)(x) << 28U)
-#define	DRVCTRL10_D7(x)		((uint32_t)(x) << 24U)
-#define	DRVCTRL10_D8(x)		((uint32_t)(x) << 20U)
-#define	DRVCTRL10_D9(x)		((uint32_t)(x) << 16U)
-#define	DRVCTRL10_D10(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL10_D11(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL10_D12(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL10_D13(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL11_D14(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL11_D15(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL11_AVS1(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL11_AVS2(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL11_HDMI0_CEC(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL11_HDMI1_CEC(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL11_DU_DOTCLKIN0(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL11_DU_DOTCLKIN1(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL12_DU_DOTCLKIN2(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL12_DU_DOTCLKIN3(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL12_DU_FSCLKST(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL12_DU_TMS(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL13_TDO(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL13_ASEBRK(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL13_SD0_CLK(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL13_SD0_CMD(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL13_SD0_DAT0(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL13_SD0_DAT1(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL13_SD0_DAT2(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL13_SD0_DAT3(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL14_SD1_CLK(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL14_SD1_CMD(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL14_SD1_DAT0(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL14_SD1_DAT1(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL14_SD1_DAT2(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL14_SD1_DAT3(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL14_SD2_CLK(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL14_SD2_CMD(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL15_SD2_DAT0(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL15_SD2_DAT1(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL15_SD2_DAT2(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL15_SD2_DAT3(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL15_SD2_DS(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL15_SD3_CLK(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL15_SD3_CMD(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL15_SD3_DAT0(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL16_SD3_DAT1(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL16_SD3_DAT2(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL16_SD3_DAT3(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL16_SD3_DAT4(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL16_SD3_DAT5(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL16_SD3_DAT6(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL16_SD3_DAT7(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL16_SD3_DS(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL17_SD0_CD(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL17_SD0_WP(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL17_SD1_CD(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL17_SD1_WP(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL17_SCK0(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL17_RX0(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL17_TX0(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL17_CTS0(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL18_RTS0_TANS(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL18_RX1(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL18_TX1(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL18_CTS1(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL18_RTS1_TANS(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL18_SCK2(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL18_TX2(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL18_RX2(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL19_HSCK0(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL19_HRX0(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL19_HTX0(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL19_HCTS0(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL19_HRTS0(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL19_MSIOF0_SCK(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL19_MSIOF0_SYNC(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL19_MSIOF0_SS1(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL20_MSIOF0_TXD(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL20_MSIOF0_SS2(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL20_MSIOF0_RXD(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL20_MLB_CLK(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL20_MLB_SIG(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL20_MLB_DAT(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL20_MLB_REF(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL20_SSI_SCK0129(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL21_SSI_WS0129(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL21_SSI_SDATA0(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL21_SSI_SDATA1(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL21_SSI_SDATA2(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL21_SSI_SCK34(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL21_SSI_WS34(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL21_SSI_SDATA3(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL21_SSI_SCK4(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL22_SSI_WS4(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL22_SSI_SDATA4(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL22_SSI_SCK5(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL22_SSI_WS5(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL22_SSI_SDATA5(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL22_SSI_SCK6(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL22_SSI_WS6(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL22_SSI_SDATA6(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL23_SSI_SCK78(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL23_SSI_WS78(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL23_SSI_SDATA7(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL23_SSI_SDATA8(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL23_SSI_SDATA9(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL23_AUDIO_CLKA(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL23_AUDIO_CLKB(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL23_USB0_PWEN(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL24_USB0_OVC(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL24_USB1_PWEN(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL24_USB1_OVC(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL24_USB30_PWEN(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL24_USB30_OVC(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL24_USB31_PWEN(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL24_USB31_OVC(x)	((uint32_t)(x) << 4U)
-
-#define	MOD_SEL0_MSIOF3_A	((uint32_t)0U << 29U)
-#define	MOD_SEL0_MSIOF3_B	((uint32_t)1U << 29U)
-#define	MOD_SEL0_MSIOF3_C	((uint32_t)2U << 29U)
-#define	MOD_SEL0_MSIOF3_D	((uint32_t)3U << 29U)
-#define	MOD_SEL0_MSIOF3_E	((uint32_t)4U << 29U)
-#define	MOD_SEL0_MSIOF2_A	((uint32_t)0U << 27U)
-#define	MOD_SEL0_MSIOF2_B	((uint32_t)1U << 27U)
-#define	MOD_SEL0_MSIOF2_C	((uint32_t)2U << 27U)
-#define	MOD_SEL0_MSIOF2_D	((uint32_t)3U << 27U)
-#define	MOD_SEL0_MSIOF1_A	((uint32_t)0U << 24U)
-#define	MOD_SEL0_MSIOF1_B	((uint32_t)1U << 24U)
-#define	MOD_SEL0_MSIOF1_C	((uint32_t)2U << 24U)
-#define	MOD_SEL0_MSIOF1_D	((uint32_t)3U << 24U)
-#define	MOD_SEL0_MSIOF1_E	((uint32_t)4U << 24U)
-#define	MOD_SEL0_MSIOF1_F	((uint32_t)5U << 24U)
-#define	MOD_SEL0_MSIOF1_G	((uint32_t)6U << 24U)
-#define	MOD_SEL0_LBSC_A		((uint32_t)0U << 23U)
-#define	MOD_SEL0_LBSC_B		((uint32_t)1U << 23U)
-#define	MOD_SEL0_IEBUS_A	((uint32_t)0U << 22U)
-#define	MOD_SEL0_IEBUS_B	((uint32_t)1U << 22U)
-#define	MOD_SEL0_I2C2_A		((uint32_t)0U << 21U)
-#define	MOD_SEL0_I2C2_B		((uint32_t)1U << 21U)
-#define	MOD_SEL0_I2C1_A		((uint32_t)0U << 20U)
-#define	MOD_SEL0_I2C1_B		((uint32_t)1U << 20U)
-#define	MOD_SEL0_HSCIF4_A	((uint32_t)0U << 19U)
-#define	MOD_SEL0_HSCIF4_B	((uint32_t)1U << 19U)
-#define	MOD_SEL0_HSCIF3_A	((uint32_t)0U << 17U)
-#define	MOD_SEL0_HSCIF3_B	((uint32_t)1U << 17U)
-#define	MOD_SEL0_HSCIF3_C	((uint32_t)2U << 17U)
-#define	MOD_SEL0_HSCIF3_D	((uint32_t)3U << 17U)
-#define	MOD_SEL0_HSCIF1_A	((uint32_t)0U << 16U)
-#define	MOD_SEL0_HSCIF1_B	((uint32_t)1U << 16U)
-#define	MOD_SEL0_FSO_A		((uint32_t)0U << 15U)
-#define	MOD_SEL0_FSO_B		((uint32_t)1U << 15U)
-#define	MOD_SEL0_HSCIF2_A	((uint32_t)0U << 13U)
-#define	MOD_SEL0_HSCIF2_B	((uint32_t)1U << 13U)
-#define	MOD_SEL0_HSCIF2_C	((uint32_t)2U << 13U)
-#define	MOD_SEL0_ETHERAVB_A	((uint32_t)0U << 12U)
-#define	MOD_SEL0_ETHERAVB_B	((uint32_t)1U << 12U)
-#define	MOD_SEL0_DRIF3_A	((uint32_t)0U << 11U)
-#define	MOD_SEL0_DRIF3_B	((uint32_t)1U << 11U)
-#define	MOD_SEL0_DRIF2_A	((uint32_t)0U << 10U)
-#define	MOD_SEL0_DRIF2_B	((uint32_t)1U << 10U)
-#define	MOD_SEL0_DRIF1_A	((uint32_t)0U << 8U)
-#define	MOD_SEL0_DRIF1_B	((uint32_t)1U << 8U)
-#define	MOD_SEL0_DRIF1_C	((uint32_t)2U << 8U)
-#define	MOD_SEL0_DRIF0_A	((uint32_t)0U << 6U)
-#define	MOD_SEL0_DRIF0_B	((uint32_t)1U << 6U)
-#define	MOD_SEL0_DRIF0_C	((uint32_t)2U << 6U)
-#define	MOD_SEL0_CANFD0_A	((uint32_t)0U << 5U)
-#define	MOD_SEL0_CANFD0_B	((uint32_t)1U << 5U)
-#define	MOD_SEL0_ADG_A_A	((uint32_t)0U << 3U)
-#define	MOD_SEL0_ADG_A_B	((uint32_t)1U << 3U)
-#define	MOD_SEL0_ADG_A_C	((uint32_t)2U << 3U)
-#define	MOD_SEL1_TSIF1_A	((uint32_t)0U << 30U)
-#define	MOD_SEL1_TSIF1_B	((uint32_t)1U << 30U)
-#define	MOD_SEL1_TSIF1_C	((uint32_t)2U << 30U)
-#define	MOD_SEL1_TSIF1_D	((uint32_t)3U << 30U)
-#define	MOD_SEL1_TSIF0_A	((uint32_t)0U << 27U)
-#define	MOD_SEL1_TSIF0_B	((uint32_t)1U << 27U)
-#define	MOD_SEL1_TSIF0_C	((uint32_t)2U << 27U)
-#define	MOD_SEL1_TSIF0_D	((uint32_t)3U << 27U)
-#define	MOD_SEL1_TSIF0_E	((uint32_t)4U << 27U)
-#define	MOD_SEL1_TIMER_TMU_A	((uint32_t)0U << 26U)
-#define	MOD_SEL1_TIMER_TMU_B	((uint32_t)1U << 26U)
-#define	MOD_SEL1_SSP1_1_A	((uint32_t)0U << 24U)
-#define	MOD_SEL1_SSP1_1_B	((uint32_t)1U << 24U)
-#define	MOD_SEL1_SSP1_1_C	((uint32_t)2U << 24U)
-#define	MOD_SEL1_SSP1_1_D	((uint32_t)3U << 24U)
-#define	MOD_SEL1_SSP1_0_A	((uint32_t)0U << 21U)
-#define	MOD_SEL1_SSP1_0_B	((uint32_t)1U << 21U)
-#define	MOD_SEL1_SSP1_0_C	((uint32_t)2U << 21U)
-#define	MOD_SEL1_SSP1_0_D	((uint32_t)3U << 21U)
-#define	MOD_SEL1_SSP1_0_E	((uint32_t)4U << 21U)
-#define	MOD_SEL1_SSI_A		((uint32_t)0U << 20U)
-#define	MOD_SEL1_SSI_B		((uint32_t)1U << 20U)
-#define	MOD_SEL1_SPEED_PULSE_IF_A	((uint32_t)0U << 19U)
-#define	MOD_SEL1_SPEED_PULSE_IF_B	((uint32_t)1U << 19U)
-#define	MOD_SEL1_SIMCARD_A	((uint32_t)0U << 17U)
-#define	MOD_SEL1_SIMCARD_B	((uint32_t)1U << 17U)
-#define	MOD_SEL1_SIMCARD_C	((uint32_t)2U << 17U)
-#define	MOD_SEL1_SIMCARD_D	((uint32_t)3U << 17U)
-#define	MOD_SEL1_SDHI2_A	((uint32_t)0U << 16U)
-#define	MOD_SEL1_SDHI2_B	((uint32_t)1U << 16U)
-#define	MOD_SEL1_SCIF4_A	((uint32_t)0U << 14U)
-#define	MOD_SEL1_SCIF4_B	((uint32_t)1U << 14U)
-#define	MOD_SEL1_SCIF4_C	((uint32_t)2U << 14U)
-#define	MOD_SEL1_SCIF3_A	((uint32_t)0U << 13U)
-#define	MOD_SEL1_SCIF3_B	((uint32_t)1U << 13U)
-#define	MOD_SEL1_SCIF2_A	((uint32_t)0U << 12U)
-#define	MOD_SEL1_SCIF2_B	((uint32_t)1U << 12U)
-#define	MOD_SEL1_SCIF1_A	((uint32_t)0U << 11U)
-#define	MOD_SEL1_SCIF1_B	((uint32_t)1U << 11U)
-#define	MOD_SEL1_SCIF_A		((uint32_t)0U << 10U)
-#define	MOD_SEL1_SCIF_B		((uint32_t)1U << 10U)
-#define	MOD_SEL1_REMOCON_A	((uint32_t)0U << 9U)
-#define	MOD_SEL1_REMOCON_B	((uint32_t)1U << 9U)
-#define	MOD_SEL1_RCAN0_A	((uint32_t)0U << 6U)
-#define	MOD_SEL1_RCAN0_B	((uint32_t)1U << 6U)
-#define	MOD_SEL1_PWM6_A		((uint32_t)0U << 5U)
-#define	MOD_SEL1_PWM6_B		((uint32_t)1U << 5U)
-#define	MOD_SEL1_PWM5_A		((uint32_t)0U << 4U)
-#define	MOD_SEL1_PWM5_B		((uint32_t)1U << 4U)
-#define	MOD_SEL1_PWM4_A		((uint32_t)0U << 3U)
-#define	MOD_SEL1_PWM4_B		((uint32_t)1U << 3U)
-#define	MOD_SEL1_PWM3_A		((uint32_t)0U << 2U)
-#define	MOD_SEL1_PWM3_B		((uint32_t)1U << 2U)
-#define	MOD_SEL1_PWM2_A		((uint32_t)0U << 1U)
-#define	MOD_SEL1_PWM2_B		((uint32_t)1U << 1U)
-#define	MOD_SEL1_PWM1_A		((uint32_t)0U << 0U)
-#define	MOD_SEL1_PWM1_B		((uint32_t)1U << 0U)
-#define	MOD_SEL2_I2C_5_A	((uint32_t)0U << 31U)
-#define	MOD_SEL2_I2C_5_B	((uint32_t)1U << 31U)
-#define	MOD_SEL2_I2C_3_A	((uint32_t)0U << 30U)
-#define	MOD_SEL2_I2C_3_B	((uint32_t)1U << 30U)
-#define	MOD_SEL2_I2C_0_A	((uint32_t)0U << 29U)
-#define	MOD_SEL2_I2C_0_B	((uint32_t)1U << 29U)
-#define	MOD_SEL2_FM_A		((uint32_t)0U << 27U)
-#define	MOD_SEL2_FM_B		((uint32_t)1U << 27U)
-#define	MOD_SEL2_FM_C		((uint32_t)2U << 27U)
-#define	MOD_SEL2_FM_D		((uint32_t)3U << 27U)
-#define	MOD_SEL2_SCIF5_A	((uint32_t)0U << 26U)
-#define	MOD_SEL2_SCIF5_B	((uint32_t)1U << 26U)
-#define	MOD_SEL2_I2C6_A		((uint32_t)0U << 23U)
-#define	MOD_SEL2_I2C6_B		((uint32_t)1U << 23U)
-#define	MOD_SEL2_I2C6_C		((uint32_t)2U << 23U)
-#define	MOD_SEL2_NDF_A		((uint32_t)0U << 22U)
-#define	MOD_SEL2_NDF_B		((uint32_t)1U << 22U)
-#define	MOD_SEL2_SSI2_A		((uint32_t)0U << 21U)
-#define	MOD_SEL2_SSI2_B		((uint32_t)1U << 21U)
-#define	MOD_SEL2_SSI9_A		((uint32_t)0U << 20U)
-#define	MOD_SEL2_SSI9_B		((uint32_t)1U << 20U)
-#define	MOD_SEL2_TIMER_TMU2_A	((uint32_t)0U << 19U)
-#define	MOD_SEL2_TIMER_TMU2_B	((uint32_t)1U << 19U)
-#define	MOD_SEL2_ADG_B_A	((uint32_t)0U << 18U)
-#define	MOD_SEL2_ADG_B_B	((uint32_t)1U << 18U)
-#define	MOD_SEL2_ADG_C_A	((uint32_t)0U << 17U)
-#define	MOD_SEL2_ADG_C_B	((uint32_t)1U << 17U)
-#define	MOD_SEL2_VIN4_A		((uint32_t)0U << 0U)
-#define	MOD_SEL2_VIN4_B		((uint32_t)1U << 0U)
-
-/* SCIF3 Registers for Dummy write */
-#define SCIF3_BASE		(0xE6C50000U)
-#define SCIF3_SCFCR		(SCIF3_BASE + 0x0018U)
-#define SCIF3_SCFDR		(SCIF3_BASE + 0x001CU)
-#define SCFCR_DATA		(0x0000U)
-
-/* Realtime module stop control */
-#define	CPG_BASE		(0xE6150000U)
-#define CPG_SCMSTPCR0		(CPG_BASE + 0x0B20U)
-#define CPG_MSTPSR0		(CPG_BASE + 0x0030U)
-#define SCMSTPCR0_RTDMAC	(0x00200000U)
-
-/* RT-DMAC Registers */
-#define RTDMAC_CH		(0U)	/* choose 0 to 15 */
-
-#define RTDMAC_BASE		(0xFFC10000U)
-#define RTDMAC_RDMOR		(RTDMAC_BASE + 0x0060U)
-#define RTDMAC_RDMCHCLR		(RTDMAC_BASE + 0x0080U)
-#define RTDMAC_RDMSAR(x)	(RTDMAC_BASE + 0x8000U + (0x80U * (x)))
-#define RTDMAC_RDMDAR(x)	(RTDMAC_BASE + 0x8004U + (0x80U * (x)))
-#define RTDMAC_RDMTCR(x)	(RTDMAC_BASE + 0x8008U + (0x80U * (x)))
-#define RTDMAC_RDMCHCR(x)	(RTDMAC_BASE + 0x800CU + (0x80U * (x)))
-#define RTDMAC_RDMCHCRB(x)	(RTDMAC_BASE + 0x801CU + (0x80U * (x)))
-#define RTDMAC_RDMDPBASE(x)	(RTDMAC_BASE + 0x8050U + (0x80U * (x)))
-#define RTDMAC_DESC_BASE	(RTDMAC_BASE + 0xA000U)
-#define RTDMAC_DESC_RDMSAR	(RTDMAC_DESC_BASE + 0x0000U)
-#define RTDMAC_DESC_RDMDAR	(RTDMAC_DESC_BASE + 0x0004U)
-#define RTDMAC_DESC_RDMTCR	(RTDMAC_DESC_BASE + 0x0008U)
-
-#define RDMOR_DME		(0x0001U)	/* DMA Master Enable */
-#define RDMCHCR_DPM_INFINITE	(0x30000000U)	/* Infinite repeat mode */
-#define RDMCHCR_RPT_TCR		(0x02000000U)	/* enable to update TCR */
-#define RDMCHCR_TS_2		(0x00000008U)	/* Word(2byte) units transfer */
-#define RDMCHCR_RS_AUTO		(0x00000400U)	/* Auto request */
-#define RDMCHCR_DE		(0x00000001U)	/* DMA Enable */
-#define RDMCHCRB_DRST		(0x00008000U)	/* Descriptor reset */
-#define RDMCHCRB_SLM_256	(0x00000080U)	/* once in 256 clock cycle */
-#define RDMDPBASE_SEL_EXT	(0x00000001U)	/* External memory use */
-
-static void StartRtDma0_Descriptor(void);
-static void pfc_reg_write(uint32_t addr, uint32_t data);
-
-static void StartRtDma0_Descriptor(void)
-{
-	uint32_t reg;
-
-	reg = mmio_read_32(RCAR_PRR);
-	reg &= (RCAR_PRODUCT_MASK | RCAR_CUT_MASK);
-	if (reg == (RCAR_PRODUCT_M3_CUT10)) {
-		/* Enable clock supply to RTDMAC. */
-		mstpcr_write(CPG_SCMSTPCR0, CPG_MSTPSR0, SCMSTPCR0_RTDMAC);
-
-		/* Initialize ch0, Reset Descriptor */
-		mmio_write_32(RTDMAC_RDMCHCLR, ((uint32_t) 1U << RTDMAC_CH));
-		mmio_write_32(RTDMAC_RDMCHCRB(RTDMAC_CH), RDMCHCRB_DRST);
-
-		/* Enable DMA */
-		mmio_write_16(RTDMAC_RDMOR, RDMOR_DME);
-
-		/* Set first transfer */
-		mmio_write_32(RTDMAC_RDMSAR(RTDMAC_CH), RCAR_PRR);
-		mmio_write_32(RTDMAC_RDMDAR(RTDMAC_CH), SCIF3_SCFDR);
-		mmio_write_32(RTDMAC_RDMTCR(RTDMAC_CH), 0x00000001U);
-
-		/* Set descriptor */
-		mmio_write_32(RTDMAC_DESC_RDMSAR, 0x00000000U);
-		mmio_write_32(RTDMAC_DESC_RDMDAR, 0x00000000U);
-		mmio_write_32(RTDMAC_DESC_RDMTCR, 0x00200000U);
-		mmio_write_32(RTDMAC_RDMCHCRB(RTDMAC_CH), RDMCHCRB_SLM_256);
-		mmio_write_32(RTDMAC_RDMDPBASE(RTDMAC_CH), RTDMAC_DESC_BASE
-			      | RDMDPBASE_SEL_EXT);
-
-		/* Set transfer parameter, Start transfer */
-		mmio_write_32(RTDMAC_RDMCHCR(RTDMAC_CH), RDMCHCR_DPM_INFINITE
-			      | RDMCHCR_RPT_TCR
-			      | RDMCHCR_TS_2
-			      | RDMCHCR_RS_AUTO
-			      | RDMCHCR_DE);
-	}
-}
-
-static void pfc_reg_write(uint32_t addr, uint32_t data)
-{
-	uint32_t prr;
-
-	prr = mmio_read_32(RCAR_PRR);
-	prr &= (RCAR_PRODUCT_MASK | RCAR_CUT_MASK);
-
-	mmio_write_32(PFC_PMMR, ~data);
-	if (prr == (RCAR_PRODUCT_M3_CUT10)) {
-		mmio_write_16(SCIF3_SCFCR, SCFCR_DATA);	/* Dummy write */
-	}
-	mmio_write_32((uintptr_t) addr, data);
-	if (prr == (RCAR_PRODUCT_M3_CUT10)) {
-		mmio_write_16(SCIF3_SCFCR, SCFCR_DATA);	/* Dummy write */
-	}
-}
-
-void pfc_init_m3(void)
-{
-	uint32_t reg;
-
-	/* Work around for PFC eratta */
-	StartRtDma0_Descriptor();
-
-	/* initialize module select */
-	pfc_reg_write(PFC_MOD_SEL0, MOD_SEL0_MSIOF3_A
-		      | MOD_SEL0_MSIOF2_A
-		      | MOD_SEL0_MSIOF1_A
-		      | MOD_SEL0_LBSC_A
-		      | MOD_SEL0_IEBUS_A
-		      | MOD_SEL0_I2C2_A
-		      | MOD_SEL0_I2C1_A
-		      | MOD_SEL0_HSCIF4_A
-		      | MOD_SEL0_HSCIF3_A
-		      | MOD_SEL0_HSCIF1_A
-		      | MOD_SEL0_FSO_A
-		      | MOD_SEL0_HSCIF2_A
-		      | MOD_SEL0_ETHERAVB_A
-		      | MOD_SEL0_DRIF3_A
-		      | MOD_SEL0_DRIF2_A
-		      | MOD_SEL0_DRIF1_A
-		      | MOD_SEL0_DRIF0_A
-		      | MOD_SEL0_CANFD0_A
-		      | MOD_SEL0_ADG_A_A);
-	pfc_reg_write(PFC_MOD_SEL1, MOD_SEL1_TSIF1_A
-		      | MOD_SEL1_TSIF0_A
-		      | MOD_SEL1_TIMER_TMU_A
-		      | MOD_SEL1_SSP1_1_A
-		      | MOD_SEL1_SSP1_0_A
-		      | MOD_SEL1_SSI_A
-		      | MOD_SEL1_SPEED_PULSE_IF_A
-		      | MOD_SEL1_SIMCARD_A
-		      | MOD_SEL1_SDHI2_A
-		      | MOD_SEL1_SCIF4_A
-		      | MOD_SEL1_SCIF3_A
-		      | MOD_SEL1_SCIF2_A
-		      | MOD_SEL1_SCIF1_A
-		      | MOD_SEL1_SCIF_A
-		      | MOD_SEL1_REMOCON_A
-		      | MOD_SEL1_RCAN0_A
-		      | MOD_SEL1_PWM6_A
-		      | MOD_SEL1_PWM5_A
-		      | MOD_SEL1_PWM4_A
-		      | MOD_SEL1_PWM3_A
-		      | MOD_SEL1_PWM2_A
-		      | MOD_SEL1_PWM1_A);
-	pfc_reg_write(PFC_MOD_SEL2, MOD_SEL2_I2C_5_A
-		      | MOD_SEL2_I2C_3_A
-		      | MOD_SEL2_I2C_0_A
-		      | MOD_SEL2_FM_A
-		      | MOD_SEL2_SCIF5_A
-		      | MOD_SEL2_I2C6_A
-		      | MOD_SEL2_NDF_A
-		      | MOD_SEL2_SSI2_A
-		      | MOD_SEL2_SSI9_A
-		      | MOD_SEL2_TIMER_TMU2_A
-		      | MOD_SEL2_ADG_B_A
-		      | MOD_SEL2_ADG_C_A
-		      | MOD_SEL2_VIN4_A);
-
-	/* initialize peripheral function select */
-	pfc_reg_write(PFC_IPSR0, IPSR_28_FUNC(0)
-		      | IPSR_24_FUNC(0)
-		      | IPSR_20_FUNC(0)
-		      | IPSR_16_FUNC(0)
-		      | IPSR_12_FUNC(0)
-		      | IPSR_8_FUNC(0)
-		      | IPSR_4_FUNC(0)
-		      | IPSR_0_FUNC(0));
-	pfc_reg_write(PFC_IPSR1, IPSR_28_FUNC(6)
-		      | IPSR_24_FUNC(0)
-		      | IPSR_20_FUNC(0)
-		      | IPSR_16_FUNC(0)
-		      | IPSR_12_FUNC(3)
-		      | IPSR_8_FUNC(3)
-		      | IPSR_4_FUNC(3)
-		      | IPSR_0_FUNC(3));
-	pfc_reg_write(PFC_IPSR2, IPSR_28_FUNC(0)
-		      | IPSR_24_FUNC(6)
-		      | IPSR_20_FUNC(6)
-		      | IPSR_16_FUNC(6)
-		      | IPSR_12_FUNC(6)
-		      | IPSR_8_FUNC(6)
-		      | IPSR_4_FUNC(6)
-		      | IPSR_0_FUNC(6));
-	pfc_reg_write(PFC_IPSR3, IPSR_28_FUNC(6)
-		      | IPSR_24_FUNC(6)
-		      | IPSR_20_FUNC(6)
-		      | IPSR_16_FUNC(6)
-		      | IPSR_12_FUNC(6)
-		      | IPSR_8_FUNC(0)
-		      | IPSR_4_FUNC(0)
-		      | IPSR_0_FUNC(0));
-	pfc_reg_write(PFC_IPSR4, IPSR_28_FUNC(0)
-		      | IPSR_24_FUNC(0)
-		      | IPSR_20_FUNC(0)
-		      | IPSR_16_FUNC(0)
-		      | IPSR_12_FUNC(0)
-		      | IPSR_8_FUNC(6)
-		      | IPSR_4_FUNC(6)
-		      | IPSR_0_FUNC(6));
-	pfc_reg_write(PFC_IPSR5, IPSR_28_FUNC(0)
-		      | IPSR_24_FUNC(0)
-		      | IPSR_20_FUNC(0)
-		      | IPSR_16_FUNC(0)
-		      | IPSR_12_FUNC(0)
-		      | IPSR_8_FUNC(6)
-		      | IPSR_4_FUNC(0)
-		      | IPSR_0_FUNC(0));
-	pfc_reg_write(PFC_IPSR6, IPSR_28_FUNC(6)
-		      | IPSR_24_FUNC(6)
-		      | IPSR_20_FUNC(6)
-		      | IPSR_16_FUNC(6)
-		      | IPSR_12_FUNC(6)
-		      | IPSR_8_FUNC(0)
-		      | IPSR_4_FUNC(0)
-		      | IPSR_0_FUNC(0));
-	pfc_reg_write(PFC_IPSR7, IPSR_28_FUNC(0)
-		      | IPSR_24_FUNC(0)
-		      | IPSR_20_FUNC(0)
-		      | IPSR_16_FUNC(0)
-		      | IPSR_12_FUNC(0)
-		      | IPSR_8_FUNC(6)
-		      | IPSR_4_FUNC(6)
-		      | IPSR_0_FUNC(6));
-	pfc_reg_write(PFC_IPSR8, IPSR_28_FUNC(1)
-		      | IPSR_24_FUNC(1)
-		      | IPSR_20_FUNC(1)
-		      | IPSR_16_FUNC(1)
-		      | IPSR_12_FUNC(0)
-		      | IPSR_8_FUNC(0)
-		      | IPSR_4_FUNC(0)
-		      | IPSR_0_FUNC(0));
-	pfc_reg_write(PFC_IPSR9, IPSR_28_FUNC(0)
-		      | IPSR_24_FUNC(0)
-		      | IPSR_20_FUNC(0)
-		      | IPSR_16_FUNC(0)
-		      | IPSR_12_FUNC(0)
-		      | IPSR_8_FUNC(0)
-		      | IPSR_4_FUNC(0)
-		      | IPSR_0_FUNC(0));
-	pfc_reg_write(PFC_IPSR10, IPSR_28_FUNC(1)
-		      | IPSR_24_FUNC(0)
-		      | IPSR_20_FUNC(0)
-		      | IPSR_16_FUNC(0)
-		      | IPSR_12_FUNC(0)
-		      | IPSR_8_FUNC(0)
-		      | IPSR_4_FUNC(0)
-		      | IPSR_0_FUNC(0));
-	pfc_reg_write(PFC_IPSR11, IPSR_28_FUNC(0)
-		      | IPSR_24_FUNC(4)
-		      | IPSR_20_FUNC(0)
-		      | IPSR_16_FUNC(0)
-		      | IPSR_12_FUNC(0)
-		      | IPSR_8_FUNC(0)
-		      | IPSR_4_FUNC(0)
-		      | IPSR_0_FUNC(1));
-	pfc_reg_write(PFC_IPSR12, IPSR_28_FUNC(0)
-		      | IPSR_24_FUNC(0)
-		      | IPSR_20_FUNC(0)
-		      | IPSR_16_FUNC(0)
-		      | IPSR_12_FUNC(0)
-		      | IPSR_8_FUNC(4)
-		      | IPSR_4_FUNC(0)
-		      | IPSR_0_FUNC(0));
-	pfc_reg_write(PFC_IPSR13, IPSR_28_FUNC(8)
-		      | IPSR_24_FUNC(0)
-		      | IPSR_20_FUNC(0)
-		      | IPSR_16_FUNC(0)
-		      | IPSR_12_FUNC(0)
-		      | IPSR_8_FUNC(3)
-		      | IPSR_4_FUNC(0)
-		      | IPSR_0_FUNC(0));
-	pfc_reg_write(PFC_IPSR14, IPSR_28_FUNC(0)
-		      | IPSR_24_FUNC(0)
-		      | IPSR_20_FUNC(0)
-		      | IPSR_16_FUNC(0)
-		      | IPSR_12_FUNC(0)
-		      | IPSR_8_FUNC(0)
-		      | IPSR_4_FUNC(3)
-		      | IPSR_0_FUNC(8));
-	pfc_reg_write(PFC_IPSR15, IPSR_28_FUNC(0)
-		      | IPSR_24_FUNC(0)
-		      | IPSR_20_FUNC(0)
-		      | IPSR_16_FUNC(0)
-		      | IPSR_12_FUNC(0)
-		      | IPSR_8_FUNC(0)
-		      | IPSR_4_FUNC(0)
-		      | IPSR_0_FUNC(0));
-	pfc_reg_write(PFC_IPSR16, IPSR_28_FUNC(0)
-		      | IPSR_24_FUNC(0)
-		      | IPSR_20_FUNC(0)
-		      | IPSR_16_FUNC(0)
-		      | IPSR_12_FUNC(0)
-		      | IPSR_8_FUNC(0)
-		      | IPSR_4_FUNC(0)
-		      | IPSR_0_FUNC(0));
-	pfc_reg_write(PFC_IPSR17, IPSR_28_FUNC(0)
-		      | IPSR_24_FUNC(0)
-		      | IPSR_20_FUNC(0)
-		      | IPSR_16_FUNC(0)
-		      | IPSR_12_FUNC(0)
-		      | IPSR_8_FUNC(0)
-		      | IPSR_4_FUNC(1)
-		      | IPSR_0_FUNC(0));
-	pfc_reg_write(PFC_IPSR18, IPSR_4_FUNC(0)
-		      | IPSR_0_FUNC(0));
-
-	/* initialize GPIO/perihperal function select */
-	pfc_reg_write(PFC_GPSR0, GPSR0_D15
-		      | GPSR0_D14
-		      | GPSR0_D13
-		      | GPSR0_D12
-		      | GPSR0_D11
-		      | GPSR0_D10
-		      | GPSR0_D9
-		      | GPSR0_D8);
-	pfc_reg_write(PFC_GPSR1, GPSR1_CLKOUT
-		      | GPSR1_EX_WAIT0_A
-		      | GPSR1_A19
-		      | GPSR1_A18
-		      | GPSR1_A17
-		      | GPSR1_A16
-		      | GPSR1_A15
-		      | GPSR1_A14
-		      | GPSR1_A13
-		      | GPSR1_A12
-		      | GPSR1_A7
-		      | GPSR1_A6
-		      | GPSR1_A5
-		      | GPSR1_A4
-		      | GPSR1_A3
-		      | GPSR1_A2
-		      | GPSR1_A1
-		      | GPSR1_A0);
-	pfc_reg_write(PFC_GPSR2, GPSR2_AVB_AVTP_CAPTURE_A
-		      | GPSR2_AVB_AVTP_MATCH_A
-		      | GPSR2_AVB_LINK
-		      | GPSR2_AVB_PHY_INT
-		      | GPSR2_AVB_MDC
-		      | GPSR2_PWM2_A
-		      | GPSR2_PWM1_A
-		      | GPSR2_IRQ5
-		      | GPSR2_IRQ4
-		      | GPSR2_IRQ3
-		      | GPSR2_IRQ2
-		      | GPSR2_IRQ1
-		      | GPSR2_IRQ0);
-	pfc_reg_write(PFC_GPSR3, GPSR3_SD0_WP
-		      | GPSR3_SD0_CD
-		      | GPSR3_SD1_DAT3
-		      | GPSR3_SD1_DAT2
-		      | GPSR3_SD1_DAT1
-		      | GPSR3_SD1_DAT0
-		      | GPSR3_SD0_DAT3
-		      | GPSR3_SD0_DAT2
-		      | GPSR3_SD0_DAT1
-		      | GPSR3_SD0_DAT0
-		      | GPSR3_SD0_CMD
-		      | GPSR3_SD0_CLK);
-	pfc_reg_write(PFC_GPSR4, GPSR4_SD3_DAT7
-		      | GPSR4_SD3_DAT6
-		      | GPSR4_SD3_DAT3
-		      | GPSR4_SD3_DAT2
-		      | GPSR4_SD3_DAT1
-		      | GPSR4_SD3_DAT0
-		      | GPSR4_SD3_CMD
-		      | GPSR4_SD3_CLK
-		      | GPSR4_SD2_DS
-		      | GPSR4_SD2_DAT3
-		      | GPSR4_SD2_DAT2
-		      | GPSR4_SD2_DAT1
-		      | GPSR4_SD2_DAT0
-		      | GPSR4_SD2_CMD
-		      | GPSR4_SD2_CLK);
-	pfc_reg_write(PFC_GPSR5, GPSR5_MSIOF0_SS2
-		      | GPSR5_MSIOF0_SS1
-		      | GPSR5_MSIOF0_SYNC
-		      | GPSR5_HRTS0
-		      | GPSR5_HCTS0
-		      | GPSR5_HTX0
-		      | GPSR5_HRX0
-		      | GPSR5_HSCK0
-		      | GPSR5_RX2_A
-		      | GPSR5_TX2_A
-		      | GPSR5_SCK2
-		      | GPSR5_RTS1_TANS
-		      | GPSR5_CTS1
-		      | GPSR5_TX1_A
-		      | GPSR5_RX1_A
-		      | GPSR5_RTS0_TANS
-		      | GPSR5_SCK0);
-	pfc_reg_write(PFC_GPSR6, GPSR6_USB30_OVC
-		      | GPSR6_USB30_PWEN
-		      | GPSR6_USB1_OVC
-		      | GPSR6_USB1_PWEN
-		      | GPSR6_USB0_OVC
-		      | GPSR6_USB0_PWEN
-		      | GPSR6_AUDIO_CLKB_B
-		      | GPSR6_AUDIO_CLKA_A
-		      | GPSR6_SSI_SDATA8
-		      | GPSR6_SSI_SDATA7
-		      | GPSR6_SSI_WS78
-		      | GPSR6_SSI_SCK78
-		      | GPSR6_SSI_WS6
-		      | GPSR6_SSI_SCK6
-		      | GPSR6_SSI_SDATA4
-		      | GPSR6_SSI_WS4
-		      | GPSR6_SSI_SCK4
-		      | GPSR6_SSI_SDATA1_A
-		      | GPSR6_SSI_SDATA0
-		      | GPSR6_SSI_WS0129
-		      | GPSR6_SSI_SCK0129);
-	pfc_reg_write(PFC_GPSR7, GPSR7_HDMI1_CEC
-		      | GPSR7_HDMI0_CEC
-		      | GPSR7_AVS2
-		      | GPSR7_AVS1);
-
-	/* initialize POC control register */
-	pfc_reg_write(PFC_POCCTRL0, POC_SD3_DS_33V
-		      | POC_SD3_DAT7_33V
-		      | POC_SD3_DAT6_33V
-		      | POC_SD3_DAT5_33V
-		      | POC_SD3_DAT4_33V
-		      | POC_SD3_DAT3_33V
-		      | POC_SD3_DAT2_33V
-		      | POC_SD3_DAT1_33V
-		      | POC_SD3_DAT0_33V
-		      | POC_SD3_CMD_33V
-		      | POC_SD3_CLK_33V
-		      | POC_SD0_DAT3_33V
-		      | POC_SD0_DAT2_33V
-		      | POC_SD0_DAT1_33V
-		      | POC_SD0_DAT0_33V
-		      | POC_SD0_CMD_33V
-		      | POC_SD0_CLK_33V);
-
-	/* initialize DRV control register */
-	reg = mmio_read_32(PFC_DRVCTRL0);
-	reg = ((reg & DRVCTRL0_MASK) | DRVCTRL0_QSPI0_SPCLK(3)
-	       | DRVCTRL0_QSPI0_MOSI_IO0(3)
-	       | DRVCTRL0_QSPI0_MISO_IO1(3)
-	       | DRVCTRL0_QSPI0_IO2(3)
-	       | DRVCTRL0_QSPI0_IO3(3)
-	       | DRVCTRL0_QSPI0_SSL(3)
-	       | DRVCTRL0_QSPI1_SPCLK(3)
-	       | DRVCTRL0_QSPI1_MOSI_IO0(3));
-	pfc_reg_write(PFC_DRVCTRL0, reg);
-	reg = mmio_read_32(PFC_DRVCTRL1);
-	reg = ((reg & DRVCTRL1_MASK) | DRVCTRL1_QSPI1_MISO_IO1(3)
-	       | DRVCTRL1_QSPI1_IO2(3)
-	       | DRVCTRL1_QSPI1_IO3(3)
-	       | DRVCTRL1_QSPI1_SS(3)
-	       | DRVCTRL1_RPC_INT(3)
-	       | DRVCTRL1_RPC_WP(3)
-	       | DRVCTRL1_RPC_RESET(3)
-	       | DRVCTRL1_AVB_RX_CTL(7));
-	pfc_reg_write(PFC_DRVCTRL1, reg);
-	reg = mmio_read_32(PFC_DRVCTRL2);
-	reg = ((reg & DRVCTRL2_MASK) | DRVCTRL2_AVB_RXC(7)
-	       | DRVCTRL2_AVB_RD0(7)
-	       | DRVCTRL2_AVB_RD1(7)
-	       | DRVCTRL2_AVB_RD2(7)
-	       | DRVCTRL2_AVB_RD3(7)
-	       | DRVCTRL2_AVB_TX_CTL(3)
-	       | DRVCTRL2_AVB_TXC(3)
-	       | DRVCTRL2_AVB_TD0(3));
-	pfc_reg_write(PFC_DRVCTRL2, reg);
-	reg = mmio_read_32(PFC_DRVCTRL3);
-	reg = ((reg & DRVCTRL3_MASK) | DRVCTRL3_AVB_TD1(3)
-	       | DRVCTRL3_AVB_TD2(3)
-	       | DRVCTRL3_AVB_TD3(3)
-	       | DRVCTRL3_AVB_TXCREFCLK(7)
-	       | DRVCTRL3_AVB_MDIO(7)
-	       | DRVCTRL3_AVB_MDC(7)
-	       | DRVCTRL3_AVB_MAGIC(7)
-	       | DRVCTRL3_AVB_PHY_INT(7));
-	pfc_reg_write(PFC_DRVCTRL3, reg);
-	reg = mmio_read_32(PFC_DRVCTRL4);
-	reg = ((reg & DRVCTRL4_MASK) | DRVCTRL4_AVB_LINK(7)
-	       | DRVCTRL4_AVB_AVTP_MATCH(7)
-	       | DRVCTRL4_AVB_AVTP_CAPTURE(7)
-	       | DRVCTRL4_IRQ0(7)
-	       | DRVCTRL4_IRQ1(7)
-	       | DRVCTRL4_IRQ2(7)
-	       | DRVCTRL4_IRQ3(7)
-	       | DRVCTRL4_IRQ4(7));
-	pfc_reg_write(PFC_DRVCTRL4, reg);
-	reg = mmio_read_32(PFC_DRVCTRL5);
-	reg = ((reg & DRVCTRL5_MASK) | DRVCTRL5_IRQ5(7)
-	       | DRVCTRL5_PWM0(7)
-	       | DRVCTRL5_PWM1(7)
-	       | DRVCTRL5_PWM2(7)
-	       | DRVCTRL5_A0(3)
-	       | DRVCTRL5_A1(3)
-	       | DRVCTRL5_A2(3)
-	       | DRVCTRL5_A3(3));
-	pfc_reg_write(PFC_DRVCTRL5, reg);
-	reg = mmio_read_32(PFC_DRVCTRL6);
-	reg = ((reg & DRVCTRL6_MASK) | DRVCTRL6_A4(3)
-	       | DRVCTRL6_A5(3)
-	       | DRVCTRL6_A6(3)
-	       | DRVCTRL6_A7(3)
-	       | DRVCTRL6_A8(7)
-	       | DRVCTRL6_A9(7)
-	       | DRVCTRL6_A10(7)
-	       | DRVCTRL6_A11(7));
-	pfc_reg_write(PFC_DRVCTRL6, reg);
-	reg = mmio_read_32(PFC_DRVCTRL7);
-	reg = ((reg & DRVCTRL7_MASK) | DRVCTRL7_A12(3)
-	       | DRVCTRL7_A13(3)
-	       | DRVCTRL7_A14(3)
-	       | DRVCTRL7_A15(3)
-	       | DRVCTRL7_A16(3)
-	       | DRVCTRL7_A17(3)
-	       | DRVCTRL7_A18(3)
-	       | DRVCTRL7_A19(3));
-	pfc_reg_write(PFC_DRVCTRL7, reg);
-	reg = mmio_read_32(PFC_DRVCTRL8);
-	reg = ((reg & DRVCTRL8_MASK) | DRVCTRL8_CLKOUT(7)
-	       | DRVCTRL8_CS0(7)
-	       | DRVCTRL8_CS1_A2(7)
-	       | DRVCTRL8_BS(7)
-	       | DRVCTRL8_RD(7)
-	       | DRVCTRL8_RD_W(7)
-	       | DRVCTRL8_WE0(7)
-	       | DRVCTRL8_WE1(7));
-	pfc_reg_write(PFC_DRVCTRL8, reg);
-	reg = mmio_read_32(PFC_DRVCTRL9);
-	reg = ((reg & DRVCTRL9_MASK) | DRVCTRL9_EX_WAIT0(7)
-	       | DRVCTRL9_PRESETOU(7)
-	       | DRVCTRL9_D0(7)
-	       | DRVCTRL9_D1(7)
-	       | DRVCTRL9_D2(7)
-	       | DRVCTRL9_D3(7)
-	       | DRVCTRL9_D4(7)
-	       | DRVCTRL9_D5(7));
-	pfc_reg_write(PFC_DRVCTRL9, reg);
-	reg = mmio_read_32(PFC_DRVCTRL10);
-	reg = ((reg & DRVCTRL10_MASK) | DRVCTRL10_D6(7)
-	       | DRVCTRL10_D7(7)
-	       | DRVCTRL10_D8(3)
-	       | DRVCTRL10_D9(3)
-	       | DRVCTRL10_D10(3)
-	       | DRVCTRL10_D11(3)
-	       | DRVCTRL10_D12(3)
-	       | DRVCTRL10_D13(3));
-	pfc_reg_write(PFC_DRVCTRL10, reg);
-	reg = mmio_read_32(PFC_DRVCTRL11);
-	reg = ((reg & DRVCTRL11_MASK) | DRVCTRL11_D14(3)
-	       | DRVCTRL11_D15(3)
-	       | DRVCTRL11_AVS1(7)
-	       | DRVCTRL11_AVS2(7)
-	       | DRVCTRL11_HDMI0_CEC(7)
-	       | DRVCTRL11_HDMI1_CEC(7)
-	       | DRVCTRL11_DU_DOTCLKIN0(3)
-	       | DRVCTRL11_DU_DOTCLKIN1(3));
-	pfc_reg_write(PFC_DRVCTRL11, reg);
-	reg = mmio_read_32(PFC_DRVCTRL12);
-	reg = ((reg & DRVCTRL12_MASK) | DRVCTRL12_DU_DOTCLKIN2(3)
-	       | DRVCTRL12_DU_DOTCLKIN3(3)
-	       | DRVCTRL12_DU_FSCLKST(3)
-	       | DRVCTRL12_DU_TMS(3));
-	pfc_reg_write(PFC_DRVCTRL12, reg);
-	reg = mmio_read_32(PFC_DRVCTRL13);
-	reg = ((reg & DRVCTRL13_MASK) | DRVCTRL13_TDO(3)
-	       | DRVCTRL13_ASEBRK(3)
-	       | DRVCTRL13_SD0_CLK(7)
-	       | DRVCTRL13_SD0_CMD(7)
-	       | DRVCTRL13_SD0_DAT0(7)
-	       | DRVCTRL13_SD0_DAT1(7)
-	       | DRVCTRL13_SD0_DAT2(7)
-	       | DRVCTRL13_SD0_DAT3(7));
-	pfc_reg_write(PFC_DRVCTRL13, reg);
-	reg = mmio_read_32(PFC_DRVCTRL14);
-	reg = ((reg & DRVCTRL14_MASK) | DRVCTRL14_SD1_CLK(7)
-	       | DRVCTRL14_SD1_CMD(7)
-	       | DRVCTRL14_SD1_DAT0(5)
-	       | DRVCTRL14_SD1_DAT1(5)
-	       | DRVCTRL14_SD1_DAT2(5)
-	       | DRVCTRL14_SD1_DAT3(5)
-	       | DRVCTRL14_SD2_CLK(5)
-	       | DRVCTRL14_SD2_CMD(5));
-	pfc_reg_write(PFC_DRVCTRL14, reg);
-	reg = mmio_read_32(PFC_DRVCTRL15);
-	reg = ((reg & DRVCTRL15_MASK) | DRVCTRL15_SD2_DAT0(5)
-	       | DRVCTRL15_SD2_DAT1(5)
-	       | DRVCTRL15_SD2_DAT2(5)
-	       | DRVCTRL15_SD2_DAT3(5)
-	       | DRVCTRL15_SD2_DS(5)
-	       | DRVCTRL15_SD3_CLK(7)
-	       | DRVCTRL15_SD3_CMD(7)
-	       | DRVCTRL15_SD3_DAT0(7));
-	pfc_reg_write(PFC_DRVCTRL15, reg);
-	reg = mmio_read_32(PFC_DRVCTRL16);
-	reg = ((reg & DRVCTRL16_MASK) | DRVCTRL16_SD3_DAT1(7)
-	       | DRVCTRL16_SD3_DAT2(7)
-	       | DRVCTRL16_SD3_DAT3(7)
-	       | DRVCTRL16_SD3_DAT4(7)
-	       | DRVCTRL16_SD3_DAT5(7)
-	       | DRVCTRL16_SD3_DAT6(7)
-	       | DRVCTRL16_SD3_DAT7(7)
-	       | DRVCTRL16_SD3_DS(7));
-	pfc_reg_write(PFC_DRVCTRL16, reg);
-	reg = mmio_read_32(PFC_DRVCTRL17);
-	reg = ((reg & DRVCTRL17_MASK) | DRVCTRL17_SD0_CD(7)
-	       | DRVCTRL17_SD0_WP(7)
-	       | DRVCTRL17_SD1_CD(7)
-	       | DRVCTRL17_SD1_WP(7)
-	       | DRVCTRL17_SCK0(7)
-	       | DRVCTRL17_RX0(7)
-	       | DRVCTRL17_TX0(7)
-	       | DRVCTRL17_CTS0(7));
-	pfc_reg_write(PFC_DRVCTRL17, reg);
-	reg = mmio_read_32(PFC_DRVCTRL18);
-	reg = ((reg & DRVCTRL18_MASK) | DRVCTRL18_RTS0_TANS(7)
-	       | DRVCTRL18_RX1(7)
-	       | DRVCTRL18_TX1(7)
-	       | DRVCTRL18_CTS1(7)
-	       | DRVCTRL18_RTS1_TANS(7)
-	       | DRVCTRL18_SCK2(7)
-	       | DRVCTRL18_TX2(7)
-	       | DRVCTRL18_RX2(7));
-	pfc_reg_write(PFC_DRVCTRL18, reg);
-	reg = mmio_read_32(PFC_DRVCTRL19);
-	reg = ((reg & DRVCTRL19_MASK) | DRVCTRL19_HSCK0(7)
-	       | DRVCTRL19_HRX0(7)
-	       | DRVCTRL19_HTX0(7)
-	       | DRVCTRL19_HCTS0(7)
-	       | DRVCTRL19_HRTS0(7)
-	       | DRVCTRL19_MSIOF0_SCK(7)
-	       | DRVCTRL19_MSIOF0_SYNC(7)
-	       | DRVCTRL19_MSIOF0_SS1(7));
-	pfc_reg_write(PFC_DRVCTRL19, reg);
-	reg = mmio_read_32(PFC_DRVCTRL20);
-	reg = ((reg & DRVCTRL20_MASK) | DRVCTRL20_MSIOF0_TXD(7)
-	       | DRVCTRL20_MSIOF0_SS2(7)
-	       | DRVCTRL20_MSIOF0_RXD(7)
-	       | DRVCTRL20_MLB_CLK(7)
-	       | DRVCTRL20_MLB_SIG(7)
-	       | DRVCTRL20_MLB_DAT(7)
-	       | DRVCTRL20_MLB_REF(7)
-	       | DRVCTRL20_SSI_SCK0129(7));
-	pfc_reg_write(PFC_DRVCTRL20, reg);
-	reg = mmio_read_32(PFC_DRVCTRL21);
-	reg = ((reg & DRVCTRL21_MASK) | DRVCTRL21_SSI_WS0129(7)
-	       | DRVCTRL21_SSI_SDATA0(7)
-	       | DRVCTRL21_SSI_SDATA1(7)
-	       | DRVCTRL21_SSI_SDATA2(7)
-	       | DRVCTRL21_SSI_SCK34(7)
-	       | DRVCTRL21_SSI_WS34(7)
-	       | DRVCTRL21_SSI_SDATA3(7)
-	       | DRVCTRL21_SSI_SCK4(7));
-	pfc_reg_write(PFC_DRVCTRL21, reg);
-	reg = mmio_read_32(PFC_DRVCTRL22);
-	reg = ((reg & DRVCTRL22_MASK) | DRVCTRL22_SSI_WS4(7)
-	       | DRVCTRL22_SSI_SDATA4(7)
-	       | DRVCTRL22_SSI_SCK5(7)
-	       | DRVCTRL22_SSI_WS5(7)
-	       | DRVCTRL22_SSI_SDATA5(7)
-	       | DRVCTRL22_SSI_SCK6(7)
-	       | DRVCTRL22_SSI_WS6(7)
-	       | DRVCTRL22_SSI_SDATA6(7));
-	pfc_reg_write(PFC_DRVCTRL22, reg);
-	reg = mmio_read_32(PFC_DRVCTRL23);
-	reg = ((reg & DRVCTRL23_MASK) | DRVCTRL23_SSI_SCK78(7)
-	       | DRVCTRL23_SSI_WS78(7)
-	       | DRVCTRL23_SSI_SDATA7(7)
-	       | DRVCTRL23_SSI_SDATA8(7)
-	       | DRVCTRL23_SSI_SDATA9(7)
-	       | DRVCTRL23_AUDIO_CLKA(7)
-	       | DRVCTRL23_AUDIO_CLKB(7)
-	       | DRVCTRL23_USB0_PWEN(7));
-	pfc_reg_write(PFC_DRVCTRL23, reg);
-	reg = mmio_read_32(PFC_DRVCTRL24);
-	reg = ((reg & DRVCTRL24_MASK) | DRVCTRL24_USB0_OVC(7)
-	       | DRVCTRL24_USB1_PWEN(7)
-	       | DRVCTRL24_USB1_OVC(7)
-	       | DRVCTRL24_USB30_PWEN(7)
-	       | DRVCTRL24_USB30_OVC(7)
-	       | DRVCTRL24_USB31_PWEN(7)
-	       | DRVCTRL24_USB31_OVC(7));
-	pfc_reg_write(PFC_DRVCTRL24, reg);
-
-	/* initialize LSI pin pull-up/down control */
-	pfc_reg_write(PFC_PUD0, 0x00005FBFU);
-	pfc_reg_write(PFC_PUD1, 0x00300FFEU);
-	pfc_reg_write(PFC_PUD2, 0x330001E6U);
-	pfc_reg_write(PFC_PUD3, 0x000002E0U);
-	pfc_reg_write(PFC_PUD4, 0xFFFFFF00U);
-	pfc_reg_write(PFC_PUD5, 0x7F5FFF87U);
-	pfc_reg_write(PFC_PUD6, 0x00000055U);
-
-	/* initialize LSI pin pull-enable register */
-	pfc_reg_write(PFC_PUEN0, 0x00000FFFU);
-	pfc_reg_write(PFC_PUEN1, 0x00100234U);
-	pfc_reg_write(PFC_PUEN2, 0x000004C4U);
-	pfc_reg_write(PFC_PUEN3, 0x00000200U);
-	pfc_reg_write(PFC_PUEN4, 0x3E000000U);
-	pfc_reg_write(PFC_PUEN5, 0x1F000805U);
-	pfc_reg_write(PFC_PUEN6, 0x00000006U);
-
-	/* initialize positive/negative logic select */
-	mmio_write_32(GPIO_POSNEG0, 0x00000000U);
-	mmio_write_32(GPIO_POSNEG1, 0x00000000U);
-	mmio_write_32(GPIO_POSNEG2, 0x00000000U);
-	mmio_write_32(GPIO_POSNEG3, 0x00000000U);
-	mmio_write_32(GPIO_POSNEG4, 0x00000000U);
-	mmio_write_32(GPIO_POSNEG5, 0x00000000U);
-	mmio_write_32(GPIO_POSNEG6, 0x00000000U);
-
-	/* initialize general IO/interrupt switching */
-	mmio_write_32(GPIO_IOINTSEL0, 0x00000000U);
-	mmio_write_32(GPIO_IOINTSEL1, 0x00000000U);
-	mmio_write_32(GPIO_IOINTSEL2, 0x00000000U);
-	mmio_write_32(GPIO_IOINTSEL3, 0x00000000U);
-	mmio_write_32(GPIO_IOINTSEL4, 0x00000000U);
-	mmio_write_32(GPIO_IOINTSEL5, 0x00000000U);
-	mmio_write_32(GPIO_IOINTSEL6, 0x00000000U);
-
-	/* initialize general output register */
-	mmio_write_32(GPIO_OUTDT1, 0x00000000U);
-	mmio_write_32(GPIO_OUTDT2, 0x00000400U);
-	mmio_write_32(GPIO_OUTDT3, 0x0000C000U);
-	mmio_write_32(GPIO_OUTDT5, 0x00000006U);
-	mmio_write_32(GPIO_OUTDT6, 0x00003880U);
-
-	/* initialize general input/output switching */
-	mmio_write_32(GPIO_INOUTSEL0, 0x00000000U);
-	mmio_write_32(GPIO_INOUTSEL1, 0x01000A00U);
-	mmio_write_32(GPIO_INOUTSEL2, 0x00000400U);
-	mmio_write_32(GPIO_INOUTSEL3, 0x0000C000U);
-	mmio_write_32(GPIO_INOUTSEL4, 0x00000000U);
-#if (RCAR_GEN3_ULCB == 1)
-	mmio_write_32(GPIO_INOUTSEL5, 0x0000000EU);
-#else
-	mmio_write_32(GPIO_INOUTSEL5, 0x0000020EU);
-#endif
-	mmio_write_32(GPIO_INOUTSEL6, 0x00013880U);
-}
diff --git a/drivers/staging/renesas/rcar/pfc/M3N/pfc_init_m3n.c b/drivers/staging/renesas/rcar/pfc/M3N/pfc_init_m3n.c
deleted file mode 100644
index 408d879..0000000
--- a/drivers/staging/renesas/rcar/pfc/M3N/pfc_init_m3n.c
+++ /dev/null
@@ -1,1441 +0,0 @@
-/*
- * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <stdint.h>		/* for uint32_t */
-
-#include <lib/mmio.h>
-
-#include "pfc_init_m3n.h"
-#include "rcar_def.h"
-
-/* GPIO base address */
-#define	GPIO_BASE		(0xE6050000U)
-
-/* GPIO registers */
-#define	GPIO_IOINTSEL0		(GPIO_BASE + 0x0000U)
-#define	GPIO_INOUTSEL0		(GPIO_BASE + 0x0004U)
-#define	GPIO_OUTDT0		(GPIO_BASE + 0x0008U)
-#define	GPIO_INDT0		(GPIO_BASE + 0x000CU)
-#define	GPIO_INTDT0		(GPIO_BASE + 0x0010U)
-#define	GPIO_INTCLR0		(GPIO_BASE + 0x0014U)
-#define	GPIO_INTMSK0		(GPIO_BASE + 0x0018U)
-#define	GPIO_MSKCLR0		(GPIO_BASE + 0x001CU)
-#define	GPIO_POSNEG0		(GPIO_BASE + 0x0020U)
-#define	GPIO_EDGLEVEL0		(GPIO_BASE + 0x0024U)
-#define	GPIO_FILONOFF0		(GPIO_BASE + 0x0028U)
-#define	GPIO_INTMSKS0		(GPIO_BASE + 0x0038U)
-#define	GPIO_MSKCLRS0		(GPIO_BASE + 0x003CU)
-#define	GPIO_OUTDTSEL0		(GPIO_BASE + 0x0040U)
-#define	GPIO_OUTDTH0		(GPIO_BASE + 0x0044U)
-#define	GPIO_OUTDTL0		(GPIO_BASE + 0x0048U)
-#define	GPIO_BOTHEDGE0		(GPIO_BASE + 0x004CU)
-#define	GPIO_IOINTSEL1		(GPIO_BASE + 0x1000U)
-#define	GPIO_INOUTSEL1		(GPIO_BASE + 0x1004U)
-#define	GPIO_OUTDT1		(GPIO_BASE + 0x1008U)
-#define	GPIO_INDT1		(GPIO_BASE + 0x100CU)
-#define	GPIO_INTDT1		(GPIO_BASE + 0x1010U)
-#define	GPIO_INTCLR1		(GPIO_BASE + 0x1014U)
-#define	GPIO_INTMSK1		(GPIO_BASE + 0x1018U)
-#define	GPIO_MSKCLR1		(GPIO_BASE + 0x101CU)
-#define	GPIO_POSNEG1		(GPIO_BASE + 0x1020U)
-#define	GPIO_EDGLEVEL1		(GPIO_BASE + 0x1024U)
-#define	GPIO_FILONOFF1		(GPIO_BASE + 0x1028U)
-#define	GPIO_INTMSKS1		(GPIO_BASE + 0x1038U)
-#define	GPIO_MSKCLRS1		(GPIO_BASE + 0x103CU)
-#define	GPIO_OUTDTSEL1		(GPIO_BASE + 0x1040U)
-#define	GPIO_OUTDTH1		(GPIO_BASE + 0x1044U)
-#define	GPIO_OUTDTL1		(GPIO_BASE + 0x1048U)
-#define	GPIO_BOTHEDGE1		(GPIO_BASE + 0x104CU)
-#define	GPIO_IOINTSEL2		(GPIO_BASE + 0x2000U)
-#define	GPIO_INOUTSEL2		(GPIO_BASE + 0x2004U)
-#define	GPIO_OUTDT2		(GPIO_BASE + 0x2008U)
-#define	GPIO_INDT2		(GPIO_BASE + 0x200CU)
-#define	GPIO_INTDT2		(GPIO_BASE + 0x2010U)
-#define	GPIO_INTCLR2		(GPIO_BASE + 0x2014U)
-#define	GPIO_INTMSK2		(GPIO_BASE + 0x2018U)
-#define	GPIO_MSKCLR2		(GPIO_BASE + 0x201CU)
-#define	GPIO_POSNEG2		(GPIO_BASE + 0x2020U)
-#define	GPIO_EDGLEVEL2		(GPIO_BASE + 0x2024U)
-#define	GPIO_FILONOFF2		(GPIO_BASE + 0x2028U)
-#define	GPIO_INTMSKS2		(GPIO_BASE + 0x2038U)
-#define	GPIO_MSKCLRS2		(GPIO_BASE + 0x203CU)
-#define	GPIO_OUTDTSEL2		(GPIO_BASE + 0x2040U)
-#define	GPIO_OUTDTH2		(GPIO_BASE + 0x2044U)
-#define	GPIO_OUTDTL2		(GPIO_BASE + 0x2048U)
-#define	GPIO_BOTHEDGE2		(GPIO_BASE + 0x204CU)
-#define	GPIO_IOINTSEL3		(GPIO_BASE + 0x3000U)
-#define	GPIO_INOUTSEL3		(GPIO_BASE + 0x3004U)
-#define	GPIO_OUTDT3		(GPIO_BASE + 0x3008U)
-#define	GPIO_INDT3		(GPIO_BASE + 0x300CU)
-#define	GPIO_INTDT3		(GPIO_BASE + 0x3010U)
-#define	GPIO_INTCLR3		(GPIO_BASE + 0x3014U)
-#define	GPIO_INTMSK3		(GPIO_BASE + 0x3018U)
-#define	GPIO_MSKCLR3		(GPIO_BASE + 0x301CU)
-#define	GPIO_POSNEG3		(GPIO_BASE + 0x3020U)
-#define	GPIO_EDGLEVEL3		(GPIO_BASE + 0x3024U)
-#define	GPIO_FILONOFF3		(GPIO_BASE + 0x3028U)
-#define	GPIO_INTMSKS3		(GPIO_BASE + 0x3038U)
-#define	GPIO_MSKCLRS3		(GPIO_BASE + 0x303CU)
-#define	GPIO_OUTDTSEL3		(GPIO_BASE + 0x3040U)
-#define	GPIO_OUTDTH3		(GPIO_BASE + 0x3044U)
-#define	GPIO_OUTDTL3		(GPIO_BASE + 0x3048U)
-#define	GPIO_BOTHEDGE3		(GPIO_BASE + 0x304CU)
-#define	GPIO_IOINTSEL4		(GPIO_BASE + 0x4000U)
-#define	GPIO_INOUTSEL4		(GPIO_BASE + 0x4004U)
-#define	GPIO_OUTDT4		(GPIO_BASE + 0x4008U)
-#define	GPIO_INDT4		(GPIO_BASE + 0x400CU)
-#define	GPIO_INTDT4		(GPIO_BASE + 0x4010U)
-#define	GPIO_INTCLR4		(GPIO_BASE + 0x4014U)
-#define	GPIO_INTMSK4		(GPIO_BASE + 0x4018U)
-#define	GPIO_MSKCLR4		(GPIO_BASE + 0x401CU)
-#define	GPIO_POSNEG4		(GPIO_BASE + 0x4020U)
-#define	GPIO_EDGLEVEL4		(GPIO_BASE + 0x4024U)
-#define	GPIO_FILONOFF4		(GPIO_BASE + 0x4028U)
-#define	GPIO_INTMSKS4		(GPIO_BASE + 0x4038U)
-#define	GPIO_MSKCLRS4		(GPIO_BASE + 0x403CU)
-#define	GPIO_OUTDTSEL4		(GPIO_BASE + 0x4040U)
-#define	GPIO_OUTDTH4		(GPIO_BASE + 0x4044U)
-#define	GPIO_OUTDTL4		(GPIO_BASE + 0x4048U)
-#define	GPIO_BOTHEDGE4		(GPIO_BASE + 0x404CU)
-#define	GPIO_IOINTSEL5		(GPIO_BASE + 0x5000U)
-#define	GPIO_INOUTSEL5		(GPIO_BASE + 0x5004U)
-#define	GPIO_OUTDT5		(GPIO_BASE + 0x5008U)
-#define	GPIO_INDT5		(GPIO_BASE + 0x500CU)
-#define	GPIO_INTDT5		(GPIO_BASE + 0x5010U)
-#define	GPIO_INTCLR5		(GPIO_BASE + 0x5014U)
-#define	GPIO_INTMSK5		(GPIO_BASE + 0x5018U)
-#define	GPIO_MSKCLR5		(GPIO_BASE + 0x501CU)
-#define	GPIO_POSNEG5		(GPIO_BASE + 0x5020U)
-#define	GPIO_EDGLEVEL5		(GPIO_BASE + 0x5024U)
-#define	GPIO_FILONOFF5		(GPIO_BASE + 0x5028U)
-#define	GPIO_INTMSKS5		(GPIO_BASE + 0x5038U)
-#define	GPIO_MSKCLRS5		(GPIO_BASE + 0x503CU)
-#define	GPIO_OUTDTSEL5		(GPIO_BASE + 0x5040U)
-#define	GPIO_OUTDTH5		(GPIO_BASE + 0x5044U)
-#define	GPIO_OUTDTL5		(GPIO_BASE + 0x5048U)
-#define	GPIO_BOTHEDGE5		(GPIO_BASE + 0x504CU)
-#define	GPIO_IOINTSEL6		(GPIO_BASE + 0x5400U)
-#define	GPIO_INOUTSEL6		(GPIO_BASE + 0x5404U)
-#define	GPIO_OUTDT6		(GPIO_BASE + 0x5408U)
-#define	GPIO_INDT6		(GPIO_BASE + 0x540CU)
-#define	GPIO_INTDT6		(GPIO_BASE + 0x5410U)
-#define	GPIO_INTCLR6		(GPIO_BASE + 0x5414U)
-#define	GPIO_INTMSK6		(GPIO_BASE + 0x5418U)
-#define	GPIO_MSKCLR6		(GPIO_BASE + 0x541CU)
-#define	GPIO_POSNEG6		(GPIO_BASE + 0x5420U)
-#define	GPIO_EDGLEVEL6		(GPIO_BASE + 0x5424U)
-#define	GPIO_FILONOFF6		(GPIO_BASE + 0x5428U)
-#define	GPIO_INTMSKS6		(GPIO_BASE + 0x5438U)
-#define	GPIO_MSKCLRS6		(GPIO_BASE + 0x543CU)
-#define	GPIO_OUTDTSEL6		(GPIO_BASE + 0x5440U)
-#define	GPIO_OUTDTH6		(GPIO_BASE + 0x5444U)
-#define	GPIO_OUTDTL6		(GPIO_BASE + 0x5448U)
-#define	GPIO_BOTHEDGE6		(GPIO_BASE + 0x544CU)
-#define	GPIO_IOINTSEL7		(GPIO_BASE + 0x5800U)
-#define	GPIO_INOUTSEL7		(GPIO_BASE + 0x5804U)
-#define	GPIO_OUTDT7		(GPIO_BASE + 0x5808U)
-#define	GPIO_INDT7		(GPIO_BASE + 0x580CU)
-#define	GPIO_INTDT7		(GPIO_BASE + 0x5810U)
-#define	GPIO_INTCLR7		(GPIO_BASE + 0x5814U)
-#define	GPIO_INTMSK7		(GPIO_BASE + 0x5818U)
-#define	GPIO_MSKCLR7		(GPIO_BASE + 0x581CU)
-#define	GPIO_POSNEG7		(GPIO_BASE + 0x5820U)
-#define	GPIO_EDGLEVEL7		(GPIO_BASE + 0x5824U)
-#define	GPIO_FILONOFF7		(GPIO_BASE + 0x5828U)
-#define	GPIO_INTMSKS7		(GPIO_BASE + 0x5838U)
-#define	GPIO_MSKCLRS7		(GPIO_BASE + 0x583CU)
-#define	GPIO_OUTDTSEL7		(GPIO_BASE + 0x5840U)
-#define	GPIO_OUTDTH7		(GPIO_BASE + 0x5844U)
-#define	GPIO_OUTDTL7		(GPIO_BASE + 0x5848U)
-#define	GPIO_BOTHEDGE7		(GPIO_BASE + 0x584CU)
-
-/* Pin functon base address */
-#define	PFC_BASE		(0xE6060000U)
-
-/* Pin functon registers */
-#define	PFC_PMMR		(PFC_BASE + 0x0000U)
-#define PFC_GPSR0		(PFC_BASE + 0x0100U)
-#define PFC_GPSR1		(PFC_BASE + 0x0104U)
-#define PFC_GPSR2		(PFC_BASE + 0x0108U)
-#define PFC_GPSR3		(PFC_BASE + 0x010CU)
-#define PFC_GPSR4		(PFC_BASE + 0x0110U)
-#define	PFC_GPSR5		(PFC_BASE + 0x0114U)
-#define	PFC_GPSR6		(PFC_BASE + 0x0118U)
-#define	PFC_GPSR7		(PFC_BASE + 0x011CU)
-#define	PFC_IPSR0		(PFC_BASE + 0x0200U)
-#define	PFC_IPSR1		(PFC_BASE + 0x0204U)
-#define	PFC_IPSR2		(PFC_BASE + 0x0208U)
-#define	PFC_IPSR3		(PFC_BASE + 0x020CU)
-#define	PFC_IPSR4		(PFC_BASE + 0x0210U)
-#define	PFC_IPSR5		(PFC_BASE + 0x0214U)
-#define	PFC_IPSR6		(PFC_BASE + 0x0218U)
-#define	PFC_IPSR7		(PFC_BASE + 0x021CU)
-#define	PFC_IPSR8		(PFC_BASE + 0x0220U)
-#define	PFC_IPSR9		(PFC_BASE + 0x0224U)
-#define	PFC_IPSR10		(PFC_BASE + 0x0228U)
-#define	PFC_IPSR11		(PFC_BASE + 0x022CU)
-#define	PFC_IPSR12		(PFC_BASE + 0x0230U)
-#define	PFC_IPSR13		(PFC_BASE + 0x0234U)
-#define	PFC_IPSR14		(PFC_BASE + 0x0238U)
-#define	PFC_IPSR15		(PFC_BASE + 0x023CU)
-#define	PFC_IPSR16		(PFC_BASE + 0x0240U)
-#define	PFC_IPSR17		(PFC_BASE + 0x0244U)
-#define	PFC_IPSR18		(PFC_BASE + 0x0248U)
-#define PFC_DRVCTRL0		(PFC_BASE + 0x0300U)
-#define PFC_DRVCTRL1		(PFC_BASE + 0x0304U)
-#define PFC_DRVCTRL2		(PFC_BASE + 0x0308U)
-#define PFC_DRVCTRL3		(PFC_BASE + 0x030CU)
-#define PFC_DRVCTRL4		(PFC_BASE + 0x0310U)
-#define PFC_DRVCTRL5		(PFC_BASE + 0x0314U)
-#define PFC_DRVCTRL6		(PFC_BASE + 0x0318U)
-#define PFC_DRVCTRL7		(PFC_BASE + 0x031CU)
-#define PFC_DRVCTRL8		(PFC_BASE + 0x0320U)
-#define PFC_DRVCTRL9		(PFC_BASE + 0x0324U)
-#define PFC_DRVCTRL10		(PFC_BASE + 0x0328U)
-#define PFC_DRVCTRL11		(PFC_BASE + 0x032CU)
-#define PFC_DRVCTRL12		(PFC_BASE + 0x0330U)
-#define PFC_DRVCTRL13		(PFC_BASE + 0x0334U)
-#define PFC_DRVCTRL14		(PFC_BASE + 0x0338U)
-#define PFC_DRVCTRL15		(PFC_BASE + 0x033CU)
-#define PFC_DRVCTRL16		(PFC_BASE + 0x0340U)
-#define PFC_DRVCTRL17		(PFC_BASE + 0x0344U)
-#define PFC_DRVCTRL18		(PFC_BASE + 0x0348U)
-#define PFC_DRVCTRL19		(PFC_BASE + 0x034CU)
-#define PFC_DRVCTRL20		(PFC_BASE + 0x0350U)
-#define PFC_DRVCTRL21		(PFC_BASE + 0x0354U)
-#define PFC_DRVCTRL22		(PFC_BASE + 0x0358U)
-#define PFC_DRVCTRL23		(PFC_BASE + 0x035CU)
-#define PFC_DRVCTRL24		(PFC_BASE + 0x0360U)
-#define PFC_POCCTRL0		(PFC_BASE + 0x0380U)
-#define	PFC_TDSELCTRL0		(PFC_BASE + 0x03C0U)
-#define	PFC_IOCTRL		(PFC_BASE + 0x03E0U)
-#define	PFC_TSREG		(PFC_BASE + 0x03E4U)
-#define	PFC_PUEN0		(PFC_BASE + 0x0400U)
-#define	PFC_PUEN1		(PFC_BASE + 0x0404U)
-#define	PFC_PUEN2		(PFC_BASE + 0x0408U)
-#define	PFC_PUEN3		(PFC_BASE + 0x040CU)
-#define	PFC_PUEN4		(PFC_BASE + 0x0410U)
-#define	PFC_PUEN5		(PFC_BASE + 0x0414U)
-#define	PFC_PUEN6		(PFC_BASE + 0x0418U)
-#define	PFC_PUD0		(PFC_BASE + 0x0440U)
-#define	PFC_PUD1		(PFC_BASE + 0x0444U)
-#define	PFC_PUD2		(PFC_BASE + 0x0448U)
-#define	PFC_PUD3		(PFC_BASE + 0x044CU)
-#define	PFC_PUD4		(PFC_BASE + 0x0450U)
-#define	PFC_PUD5		(PFC_BASE + 0x0454U)
-#define	PFC_PUD6		(PFC_BASE + 0x0458U)
-#define	PFC_MOD_SEL0		(PFC_BASE + 0x0500U)
-#define	PFC_MOD_SEL1		(PFC_BASE + 0x0504U)
-#define	PFC_MOD_SEL2		(PFC_BASE + 0x0508U)
-
-#define	GPSR0_D15		((uint32_t)1U << 15U)
-#define	GPSR0_D14		((uint32_t)1U << 14U)
-#define	GPSR0_D13		((uint32_t)1U << 13U)
-#define	GPSR0_D12		((uint32_t)1U << 12U)
-#define	GPSR0_D11		((uint32_t)1U << 11U)
-#define	GPSR0_D10		((uint32_t)1U << 10U)
-#define	GPSR0_D9		((uint32_t)1U << 9U)
-#define	GPSR0_D8		((uint32_t)1U << 8U)
-#define	GPSR0_D7		((uint32_t)1U << 7U)
-#define	GPSR0_D6		((uint32_t)1U << 6U)
-#define	GPSR0_D5		((uint32_t)1U << 5U)
-#define	GPSR0_D4		((uint32_t)1U << 4U)
-#define	GPSR0_D3		((uint32_t)1U << 3U)
-#define	GPSR0_D2		((uint32_t)1U << 2U)
-#define	GPSR0_D1		((uint32_t)1U << 1U)
-#define	GPSR0_D0		((uint32_t)1U << 0U)
-#define	GPSR1_CLKOUT		((uint32_t)1U << 28U)
-#define	GPSR1_EX_WAIT0_A	((uint32_t)1U << 27U)
-#define	GPSR1_WE1		((uint32_t)1U << 26U)
-#define	GPSR1_WE0		((uint32_t)1U << 25U)
-#define	GPSR1_RD_WR		((uint32_t)1U << 24U)
-#define	GPSR1_RD		((uint32_t)1U << 23U)
-#define	GPSR1_BS		((uint32_t)1U << 22U)
-#define	GPSR1_CS1_A26		((uint32_t)1U << 21U)
-#define	GPSR1_CS0		((uint32_t)1U << 20U)
-#define	GPSR1_A19		((uint32_t)1U << 19U)
-#define	GPSR1_A18		((uint32_t)1U << 18U)
-#define	GPSR1_A17		((uint32_t)1U << 17U)
-#define	GPSR1_A16		((uint32_t)1U << 16U)
-#define	GPSR1_A15		((uint32_t)1U << 15U)
-#define	GPSR1_A14		((uint32_t)1U << 14U)
-#define	GPSR1_A13		((uint32_t)1U << 13U)
-#define	GPSR1_A12		((uint32_t)1U << 12U)
-#define	GPSR1_A11		((uint32_t)1U << 11U)
-#define	GPSR1_A10		((uint32_t)1U << 10U)
-#define	GPSR1_A9		((uint32_t)1U << 9U)
-#define	GPSR1_A8		((uint32_t)1U << 8U)
-#define	GPSR1_A7		((uint32_t)1U << 7U)
-#define	GPSR1_A6		((uint32_t)1U << 6U)
-#define	GPSR1_A5		((uint32_t)1U << 5U)
-#define	GPSR1_A4		((uint32_t)1U << 4U)
-#define	GPSR1_A3		((uint32_t)1U << 3U)
-#define	GPSR1_A2		((uint32_t)1U << 2U)
-#define	GPSR1_A1		((uint32_t)1U << 1U)
-#define	GPSR1_A0		((uint32_t)1U << 0U)
-#define	GPSR2_AVB_AVTP_CAPTURE_A	((uint32_t)1U << 14U)
-#define	GPSR2_AVB_AVTP_MATCH_A	((uint32_t)1U << 13U)
-#define	GPSR2_AVB_LINK		((uint32_t)1U << 12U)
-#define	GPSR2_AVB_PHY_INT	((uint32_t)1U << 11U)
-#define	GPSR2_AVB_MAGIC		((uint32_t)1U << 10U)
-#define	GPSR2_AVB_MDC		((uint32_t)1U << 9U)
-#define	GPSR2_PWM2_A		((uint32_t)1U << 8U)
-#define	GPSR2_PWM1_A		((uint32_t)1U << 7U)
-#define	GPSR2_PWM0		((uint32_t)1U << 6U)
-#define	GPSR2_IRQ5		((uint32_t)1U << 5U)
-#define	GPSR2_IRQ4		((uint32_t)1U << 4U)
-#define	GPSR2_IRQ3		((uint32_t)1U << 3U)
-#define	GPSR2_IRQ2		((uint32_t)1U << 2U)
-#define	GPSR2_IRQ1		((uint32_t)1U << 1U)
-#define	GPSR2_IRQ0		((uint32_t)1U << 0U)
-#define	GPSR3_SD1_WP		((uint32_t)1U << 15U)
-#define	GPSR3_SD1_CD		((uint32_t)1U << 14U)
-#define	GPSR3_SD0_WP		((uint32_t)1U << 13U)
-#define	GPSR3_SD0_CD		((uint32_t)1U << 12U)
-#define	GPSR3_SD1_DAT3		((uint32_t)1U << 11U)
-#define	GPSR3_SD1_DAT2		((uint32_t)1U << 10U)
-#define	GPSR3_SD1_DAT1		((uint32_t)1U << 9U)
-#define	GPSR3_SD1_DAT0		((uint32_t)1U << 8U)
-#define	GPSR3_SD1_CMD		((uint32_t)1U << 7U)
-#define	GPSR3_SD1_CLK		((uint32_t)1U << 6U)
-#define	GPSR3_SD0_DAT3		((uint32_t)1U << 5U)
-#define	GPSR3_SD0_DAT2		((uint32_t)1U << 4U)
-#define	GPSR3_SD0_DAT1		((uint32_t)1U << 3U)
-#define	GPSR3_SD0_DAT0		((uint32_t)1U << 2U)
-#define	GPSR3_SD0_CMD		((uint32_t)1U << 1U)
-#define	GPSR3_SD0_CLK		((uint32_t)1U << 0U)
-#define	GPSR4_SD3_DS		((uint32_t)1U << 17U)
-#define	GPSR4_SD3_DAT7		((uint32_t)1U << 16U)
-#define	GPSR4_SD3_DAT6		((uint32_t)1U << 15U)
-#define	GPSR4_SD3_DAT5		((uint32_t)1U << 14U)
-#define	GPSR4_SD3_DAT4		((uint32_t)1U << 13U)
-#define	GPSR4_SD3_DAT3		((uint32_t)1U << 12U)
-#define	GPSR4_SD3_DAT2		((uint32_t)1U << 11U)
-#define	GPSR4_SD3_DAT1		((uint32_t)1U << 10U)
-#define	GPSR4_SD3_DAT0		((uint32_t)1U << 9U)
-#define	GPSR4_SD3_CMD		((uint32_t)1U << 8U)
-#define	GPSR4_SD3_CLK		((uint32_t)1U << 7U)
-#define	GPSR4_SD2_DS		((uint32_t)1U << 6U)
-#define	GPSR4_SD2_DAT3		((uint32_t)1U << 5U)
-#define	GPSR4_SD2_DAT2		((uint32_t)1U << 4U)
-#define	GPSR4_SD2_DAT1		((uint32_t)1U << 3U)
-#define	GPSR4_SD2_DAT0		((uint32_t)1U << 2U)
-#define	GPSR4_SD2_CMD		((uint32_t)1U << 1U)
-#define	GPSR4_SD2_CLK		((uint32_t)1U << 0U)
-#define	GPSR5_MLB_DAT		((uint32_t)1U << 25U)
-#define	GPSR5_MLB_SIG		((uint32_t)1U << 24U)
-#define	GPSR5_MLB_CLK		((uint32_t)1U << 23U)
-#define	GPSR5_MSIOF0_RXD	((uint32_t)1U << 22U)
-#define	GPSR5_MSIOF0_SS2	((uint32_t)1U << 21U)
-#define	GPSR5_MSIOF0_TXD	((uint32_t)1U << 20U)
-#define	GPSR5_MSIOF0_SS1	((uint32_t)1U << 19U)
-#define	GPSR5_MSIOF0_SYNC	((uint32_t)1U << 18U)
-#define	GPSR5_MSIOF0_SCK	((uint32_t)1U << 17U)
-#define	GPSR5_HRTS0		((uint32_t)1U << 16U)
-#define	GPSR5_HCTS0		((uint32_t)1U << 15U)
-#define	GPSR5_HTX0		((uint32_t)1U << 14U)
-#define	GPSR5_HRX0		((uint32_t)1U << 13U)
-#define	GPSR5_HSCK0		((uint32_t)1U << 12U)
-#define	GPSR5_RX2_A		((uint32_t)1U << 11U)
-#define	GPSR5_TX2_A		((uint32_t)1U << 10U)
-#define	GPSR5_SCK2		((uint32_t)1U << 9U)
-#define	GPSR5_RTS1_TANS		((uint32_t)1U << 8U)
-#define	GPSR5_CTS1		((uint32_t)1U << 7U)
-#define	GPSR5_TX1_A		((uint32_t)1U << 6U)
-#define	GPSR5_RX1_A		((uint32_t)1U << 5U)
-#define	GPSR5_RTS0_TANS		((uint32_t)1U << 4U)
-#define	GPSR5_CTS0		((uint32_t)1U << 3U)
-#define	GPSR5_TX0		((uint32_t)1U << 2U)
-#define	GPSR5_RX0		((uint32_t)1U << 1U)
-#define	GPSR5_SCK0		((uint32_t)1U << 0U)
-#define	GPSR6_USB31_OVC		((uint32_t)1U << 31U)
-#define	GPSR6_USB31_PWEN	((uint32_t)1U << 30U)
-#define	GPSR6_USB30_OVC		((uint32_t)1U << 29U)
-#define	GPSR6_USB30_PWEN	((uint32_t)1U << 28U)
-#define	GPSR6_USB1_OVC		((uint32_t)1U << 27U)
-#define	GPSR6_USB1_PWEN		((uint32_t)1U << 26U)
-#define	GPSR6_USB0_OVC		((uint32_t)1U << 25U)
-#define	GPSR6_USB0_PWEN		((uint32_t)1U << 24U)
-#define	GPSR6_AUDIO_CLKB_B	((uint32_t)1U << 23U)
-#define	GPSR6_AUDIO_CLKA_A	((uint32_t)1U << 22U)
-#define	GPSR6_SSI_SDATA9_A	((uint32_t)1U << 21U)
-#define	GPSR6_SSI_SDATA8	((uint32_t)1U << 20U)
-#define	GPSR6_SSI_SDATA7	((uint32_t)1U << 19U)
-#define	GPSR6_SSI_WS78		((uint32_t)1U << 18U)
-#define	GPSR6_SSI_SCK78		((uint32_t)1U << 17U)
-#define	GPSR6_SSI_SDATA6	((uint32_t)1U << 16U)
-#define	GPSR6_SSI_WS6		((uint32_t)1U << 15U)
-#define	GPSR6_SSI_SCK6		((uint32_t)1U << 14U)
-#define	GPSR6_SSI_SDATA5	((uint32_t)1U << 13U)
-#define	GPSR6_SSI_WS5		((uint32_t)1U << 12U)
-#define	GPSR6_SSI_SCK5		((uint32_t)1U << 11U)
-#define	GPSR6_SSI_SDATA4	((uint32_t)1U << 10U)
-#define	GPSR6_SSI_WS4		((uint32_t)1U << 9U)
-#define	GPSR6_SSI_SCK4		((uint32_t)1U << 8U)
-#define	GPSR6_SSI_SDATA3	((uint32_t)1U << 7U)
-#define	GPSR6_SSI_WS34		((uint32_t)1U << 6U)
-#define	GPSR6_SSI_SCK34		((uint32_t)1U << 5U)
-#define	GPSR6_SSI_SDATA2_A	((uint32_t)1U << 4U)
-#define	GPSR6_SSI_SDATA1_A	((uint32_t)1U << 3U)
-#define	GPSR6_SSI_SDATA0	((uint32_t)1U << 2U)
-#define	GPSR6_SSI_WS0129	((uint32_t)1U << 1U)
-#define	GPSR6_SSI_SCK0129	((uint32_t)1U << 0U)
-#define	GPSR7_HDMI1_CEC		((uint32_t)1U << 3U)
-#define	GPSR7_HDMI0_CEC		((uint32_t)1U << 2U)
-#define	GPSR7_AVS2		((uint32_t)1U << 1U)
-#define	GPSR7_AVS1		((uint32_t)1U << 0U)
-
-#define	IPSR_28_FUNC(x)		((uint32_t)(x) << 28U)
-#define	IPSR_24_FUNC(x)		((uint32_t)(x) << 24U)
-#define	IPSR_20_FUNC(x)		((uint32_t)(x) << 20U)
-#define	IPSR_16_FUNC(x)		((uint32_t)(x) << 16U)
-#define	IPSR_12_FUNC(x)		((uint32_t)(x) << 12U)
-#define	IPSR_8_FUNC(x)		((uint32_t)(x) << 8U)
-#define	IPSR_4_FUNC(x)		((uint32_t)(x) << 4U)
-#define	IPSR_0_FUNC(x)		((uint32_t)(x) << 0U)
-
-#define	POC_SD3_DS_33V		((uint32_t)1U << 29U)
-#define	POC_SD3_DAT7_33V	((uint32_t)1U << 28U)
-#define	POC_SD3_DAT6_33V	((uint32_t)1U << 27U)
-#define	POC_SD3_DAT5_33V	((uint32_t)1U << 26U)
-#define	POC_SD3_DAT4_33V	((uint32_t)1U << 25U)
-#define	POC_SD3_DAT3_33V	((uint32_t)1U << 24U)
-#define	POC_SD3_DAT2_33V	((uint32_t)1U << 23U)
-#define	POC_SD3_DAT1_33V	((uint32_t)1U << 22U)
-#define	POC_SD3_DAT0_33V	((uint32_t)1U << 21U)
-#define	POC_SD3_CMD_33V		((uint32_t)1U << 20U)
-#define	POC_SD3_CLK_33V		((uint32_t)1U << 19U)
-#define	POC_SD2_DS_33V		((uint32_t)1U << 18U)
-#define	POC_SD2_DAT3_33V	((uint32_t)1U << 17U)
-#define	POC_SD2_DAT2_33V	((uint32_t)1U << 16U)
-#define	POC_SD2_DAT1_33V	((uint32_t)1U << 15U)
-#define	POC_SD2_DAT0_33V	((uint32_t)1U << 14U)
-#define	POC_SD2_CMD_33V		((uint32_t)1U << 13U)
-#define	POC_SD2_CLK_33V		((uint32_t)1U << 12U)
-#define	POC_SD1_DAT3_33V	((uint32_t)1U << 11U)
-#define	POC_SD1_DAT2_33V	((uint32_t)1U << 10U)
-#define	POC_SD1_DAT1_33V	((uint32_t)1U << 9U)
-#define	POC_SD1_DAT0_33V	((uint32_t)1U << 8U)
-#define	POC_SD1_CMD_33V		((uint32_t)1U << 7U)
-#define	POC_SD1_CLK_33V		((uint32_t)1U << 6U)
-#define	POC_SD0_DAT3_33V	((uint32_t)1U << 5U)
-#define	POC_SD0_DAT2_33V	((uint32_t)1U << 4U)
-#define	POC_SD0_DAT1_33V	((uint32_t)1U << 3U)
-#define	POC_SD0_DAT0_33V	((uint32_t)1U << 2U)
-#define	POC_SD0_CMD_33V		((uint32_t)1U << 1U)
-#define	POC_SD0_CLK_33V		((uint32_t)1U << 0U)
-
-#define	DRVCTRL0_MASK		(0xCCCCCCCCU)
-#define	DRVCTRL1_MASK		(0xCCCCCCC8U)
-#define	DRVCTRL2_MASK		(0x88888888U)
-#define	DRVCTRL3_MASK		(0x88888888U)
-#define	DRVCTRL4_MASK		(0x88888888U)
-#define	DRVCTRL5_MASK		(0x88888888U)
-#define	DRVCTRL6_MASK		(0x88888888U)
-#define	DRVCTRL7_MASK		(0x88888888U)
-#define	DRVCTRL8_MASK		(0x88888888U)
-#define	DRVCTRL9_MASK		(0x88888888U)
-#define	DRVCTRL10_MASK		(0x88888888U)
-#define	DRVCTRL11_MASK		(0x888888CCU)
-#define	DRVCTRL12_MASK		(0xCCCFFFCFU)
-#define	DRVCTRL13_MASK		(0xCC888888U)
-#define	DRVCTRL14_MASK		(0x88888888U)
-#define	DRVCTRL15_MASK		(0x88888888U)
-#define	DRVCTRL16_MASK		(0x88888888U)
-#define	DRVCTRL17_MASK		(0x88888888U)
-#define	DRVCTRL18_MASK		(0x88888888U)
-#define	DRVCTRL19_MASK		(0x88888888U)
-#define	DRVCTRL20_MASK		(0x88888888U)
-#define	DRVCTRL21_MASK		(0x88888888U)
-#define	DRVCTRL22_MASK		(0x88888888U)
-#define	DRVCTRL23_MASK		(0x88888888U)
-#define	DRVCTRL24_MASK		(0x8888888FU)
-
-#define	DRVCTRL0_QSPI0_SPCLK(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL0_QSPI0_MOSI_IO0(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL0_QSPI0_MISO_IO1(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL0_QSPI0_IO2(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL0_QSPI0_IO3(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL0_QSPI0_SSL(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL0_QSPI1_SPCLK(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL0_QSPI1_MOSI_IO0(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL1_QSPI1_MISO_IO1(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL1_QSPI1_IO2(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL1_QSPI1_IO3(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL1_QSPI1_SS(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL1_RPC_INT(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL1_RPC_WP(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL1_RPC_RESET(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL1_AVB_RX_CTL(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL2_AVB_RXC(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL2_AVB_RD0(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL2_AVB_RD1(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL2_AVB_RD2(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL2_AVB_RD3(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL2_AVB_TX_CTL(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL2_AVB_TXC(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL2_AVB_TD0(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL3_AVB_TD1(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL3_AVB_TD2(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL3_AVB_TD3(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL3_AVB_TXCREFCLK(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL3_AVB_MDIO(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL3_AVB_MDC(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL3_AVB_MAGIC(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL3_AVB_PHY_INT(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL4_AVB_LINK(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL4_AVB_AVTP_MATCH(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL4_AVB_AVTP_CAPTURE(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL4_IRQ0(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL4_IRQ1(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL4_IRQ2(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL4_IRQ3(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL4_IRQ4(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL5_IRQ5(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL5_PWM0(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL5_PWM1(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL5_PWM2(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL5_A0(x)		((uint32_t)(x) << 12U)
-#define	DRVCTRL5_A1(x)		((uint32_t)(x) << 8U)
-#define	DRVCTRL5_A2(x)		((uint32_t)(x) << 4U)
-#define	DRVCTRL5_A3(x)		((uint32_t)(x) << 0U)
-#define	DRVCTRL6_A4(x)		((uint32_t)(x) << 28U)
-#define	DRVCTRL6_A5(x)		((uint32_t)(x) << 24U)
-#define	DRVCTRL6_A6(x)		((uint32_t)(x) << 20U)
-#define	DRVCTRL6_A7(x)		((uint32_t)(x) << 16U)
-#define	DRVCTRL6_A8(x)		((uint32_t)(x) << 12U)
-#define	DRVCTRL6_A9(x)		((uint32_t)(x) << 8U)
-#define	DRVCTRL6_A10(x)		((uint32_t)(x) << 4U)
-#define	DRVCTRL6_A11(x)		((uint32_t)(x) << 0U)
-#define	DRVCTRL7_A12(x)		((uint32_t)(x) << 28U)
-#define	DRVCTRL7_A13(x)		((uint32_t)(x) << 24U)
-#define	DRVCTRL7_A14(x)		((uint32_t)(x) << 20U)
-#define	DRVCTRL7_A15(x)		((uint32_t)(x) << 16U)
-#define	DRVCTRL7_A16(x)		((uint32_t)(x) << 12U)
-#define	DRVCTRL7_A17(x)		((uint32_t)(x) << 8U)
-#define	DRVCTRL7_A18(x)		((uint32_t)(x) << 4U)
-#define	DRVCTRL7_A19(x)		((uint32_t)(x) << 0U)
-#define	DRVCTRL8_CLKOUT(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL8_CS0(x)		((uint32_t)(x) << 24U)
-#define	DRVCTRL8_CS1_A2(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL8_BS(x)		((uint32_t)(x) << 16U)
-#define	DRVCTRL8_RD(x)		((uint32_t)(x) << 12U)
-#define	DRVCTRL8_RD_W(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL8_WE0(x)		((uint32_t)(x) << 4U)
-#define	DRVCTRL8_WE1(x)		((uint32_t)(x) << 0U)
-#define	DRVCTRL9_EX_WAIT0(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL9_PRESETOU(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL9_D0(x)		((uint32_t)(x) << 20U)
-#define	DRVCTRL9_D1(x)		((uint32_t)(x) << 16U)
-#define	DRVCTRL9_D2(x)		((uint32_t)(x) << 12U)
-#define	DRVCTRL9_D3(x)		((uint32_t)(x) << 8U)
-#define	DRVCTRL9_D4(x)		((uint32_t)(x) << 4U)
-#define	DRVCTRL9_D5(x)		((uint32_t)(x) << 0U)
-#define	DRVCTRL10_D6(x)		((uint32_t)(x) << 28U)
-#define	DRVCTRL10_D7(x)		((uint32_t)(x) << 24U)
-#define	DRVCTRL10_D8(x)		((uint32_t)(x) << 20U)
-#define	DRVCTRL10_D9(x)		((uint32_t)(x) << 16U)
-#define	DRVCTRL10_D10(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL10_D11(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL10_D12(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL10_D13(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL11_D14(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL11_D15(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL11_AVS1(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL11_AVS2(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL11_HDMI0_CEC(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL11_HDMI1_CEC(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL11_DU_DOTCLKIN0(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL11_DU_DOTCLKIN1(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL12_DU_DOTCLKIN2(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL12_DU_DOTCLKIN3(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL12_DU_FSCLKST(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL12_DU_TMS(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL13_TDO(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL13_ASEBRK(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL13_SD0_CLK(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL13_SD0_CMD(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL13_SD0_DAT0(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL13_SD0_DAT1(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL13_SD0_DAT2(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL13_SD0_DAT3(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL14_SD1_CLK(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL14_SD1_CMD(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL14_SD1_DAT0(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL14_SD1_DAT1(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL14_SD1_DAT2(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL14_SD1_DAT3(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL14_SD2_CLK(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL14_SD2_CMD(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL15_SD2_DAT0(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL15_SD2_DAT1(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL15_SD2_DAT2(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL15_SD2_DAT3(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL15_SD2_DS(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL15_SD3_CLK(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL15_SD3_CMD(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL15_SD3_DAT0(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL16_SD3_DAT1(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL16_SD3_DAT2(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL16_SD3_DAT3(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL16_SD3_DAT4(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL16_SD3_DAT5(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL16_SD3_DAT6(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL16_SD3_DAT7(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL16_SD3_DS(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL17_SD0_CD(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL17_SD0_WP(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL17_SD1_CD(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL17_SD1_WP(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL17_SCK0(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL17_RX0(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL17_TX0(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL17_CTS0(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL18_RTS0_TANS(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL18_RX1(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL18_TX1(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL18_CTS1(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL18_RTS1_TANS(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL18_SCK2(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL18_TX2(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL18_RX2(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL19_HSCK0(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL19_HRX0(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL19_HTX0(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL19_HCTS0(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL19_HRTS0(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL19_MSIOF0_SCK(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL19_MSIOF0_SYNC(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL19_MSIOF0_SS1(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL20_MSIOF0_TXD(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL20_MSIOF0_SS2(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL20_MSIOF0_RXD(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL20_MLB_CLK(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL20_MLB_SIG(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL20_MLB_DAT(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL20_MLB_REF(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL20_SSI_SCK0129(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL21_SSI_WS0129(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL21_SSI_SDATA0(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL21_SSI_SDATA1(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL21_SSI_SDATA2(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL21_SSI_SCK34(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL21_SSI_WS34(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL21_SSI_SDATA3(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL21_SSI_SCK4(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL22_SSI_WS4(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL22_SSI_SDATA4(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL22_SSI_SCK5(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL22_SSI_WS5(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL22_SSI_SDATA5(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL22_SSI_SCK6(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL22_SSI_WS6(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL22_SSI_SDATA6(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL23_SSI_SCK78(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL23_SSI_WS78(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL23_SSI_SDATA7(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL23_SSI_SDATA8(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL23_SSI_SDATA9(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL23_AUDIO_CLKA(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL23_AUDIO_CLKB(x)	((uint32_t)(x) << 4U)
-#define	DRVCTRL23_USB0_PWEN(x)	((uint32_t)(x) << 0U)
-#define	DRVCTRL24_USB0_OVC(x)	((uint32_t)(x) << 28U)
-#define	DRVCTRL24_USB1_PWEN(x)	((uint32_t)(x) << 24U)
-#define	DRVCTRL24_USB1_OVC(x)	((uint32_t)(x) << 20U)
-#define	DRVCTRL24_USB30_PWEN(x)	((uint32_t)(x) << 16U)
-#define	DRVCTRL24_USB30_OVC(x)	((uint32_t)(x) << 12U)
-#define	DRVCTRL24_USB31_PWEN(x)	((uint32_t)(x) << 8U)
-#define	DRVCTRL24_USB31_OVC(x)	((uint32_t)(x) << 4U)
-
-#define	MOD_SEL0_MSIOF3_A	((uint32_t)0U << 29U)
-#define	MOD_SEL0_MSIOF3_B	((uint32_t)1U << 29U)
-#define	MOD_SEL0_MSIOF3_C	((uint32_t)2U << 29U)
-#define	MOD_SEL0_MSIOF3_D	((uint32_t)3U << 29U)
-#define	MOD_SEL0_MSIOF3_E	((uint32_t)4U << 29U)
-#define	MOD_SEL0_MSIOF2_A	((uint32_t)0U << 27U)
-#define	MOD_SEL0_MSIOF2_B	((uint32_t)1U << 27U)
-#define	MOD_SEL0_MSIOF2_C	((uint32_t)2U << 27U)
-#define	MOD_SEL0_MSIOF2_D	((uint32_t)3U << 27U)
-#define	MOD_SEL0_MSIOF1_A	((uint32_t)0U << 24U)
-#define	MOD_SEL0_MSIOF1_B	((uint32_t)1U << 24U)
-#define	MOD_SEL0_MSIOF1_C	((uint32_t)2U << 24U)
-#define	MOD_SEL0_MSIOF1_D	((uint32_t)3U << 24U)
-#define	MOD_SEL0_MSIOF1_E	((uint32_t)4U << 24U)
-#define	MOD_SEL0_MSIOF1_F	((uint32_t)5U << 24U)
-#define	MOD_SEL0_MSIOF1_G	((uint32_t)6U << 24U)
-#define	MOD_SEL0_LBSC_A		((uint32_t)0U << 23U)
-#define	MOD_SEL0_LBSC_B		((uint32_t)1U << 23U)
-#define	MOD_SEL0_IEBUS_A	((uint32_t)0U << 22U)
-#define	MOD_SEL0_IEBUS_B	((uint32_t)1U << 22U)
-#define	MOD_SEL0_I2C2_A		((uint32_t)0U << 21U)
-#define	MOD_SEL0_I2C2_B		((uint32_t)1U << 21U)
-#define	MOD_SEL0_I2C1_A		((uint32_t)0U << 20U)
-#define	MOD_SEL0_I2C1_B		((uint32_t)1U << 20U)
-#define	MOD_SEL0_HSCIF4_A	((uint32_t)0U << 19U)
-#define	MOD_SEL0_HSCIF4_B	((uint32_t)1U << 19U)
-#define	MOD_SEL0_HSCIF3_A	((uint32_t)0U << 17U)
-#define	MOD_SEL0_HSCIF3_B	((uint32_t)1U << 17U)
-#define	MOD_SEL0_HSCIF3_C	((uint32_t)2U << 17U)
-#define	MOD_SEL0_HSCIF3_D	((uint32_t)3U << 17U)
-#define	MOD_SEL0_HSCIF1_A	((uint32_t)0U << 16U)
-#define	MOD_SEL0_HSCIF1_B	((uint32_t)1U << 16U)
-#define	MOD_SEL0_FSO_A		((uint32_t)0U << 15U)
-#define	MOD_SEL0_FSO_B		((uint32_t)1U << 15U)
-#define	MOD_SEL0_HSCIF2_A	((uint32_t)0U << 13U)
-#define	MOD_SEL0_HSCIF2_B	((uint32_t)1U << 13U)
-#define	MOD_SEL0_HSCIF2_C	((uint32_t)2U << 13U)
-#define	MOD_SEL0_ETHERAVB_A	((uint32_t)0U << 12U)
-#define	MOD_SEL0_ETHERAVB_B	((uint32_t)1U << 12U)
-#define	MOD_SEL0_DRIF3_A	((uint32_t)0U << 11U)
-#define	MOD_SEL0_DRIF3_B	((uint32_t)1U << 11U)
-#define	MOD_SEL0_DRIF2_A	((uint32_t)0U << 10U)
-#define	MOD_SEL0_DRIF2_B	((uint32_t)1U << 10U)
-#define	MOD_SEL0_DRIF1_A	((uint32_t)0U << 8U)
-#define	MOD_SEL0_DRIF1_B	((uint32_t)1U << 8U)
-#define	MOD_SEL0_DRIF1_C	((uint32_t)2U << 8U)
-#define	MOD_SEL0_DRIF0_A	((uint32_t)0U << 6U)
-#define	MOD_SEL0_DRIF0_B	((uint32_t)1U << 6U)
-#define	MOD_SEL0_DRIF0_C	((uint32_t)2U << 6U)
-#define	MOD_SEL0_CANFD0_A	((uint32_t)0U << 5U)
-#define	MOD_SEL0_CANFD0_B	((uint32_t)1U << 5U)
-#define	MOD_SEL0_ADG_A_A	((uint32_t)0U << 3U)
-#define	MOD_SEL0_ADG_A_B	((uint32_t)1U << 3U)
-#define	MOD_SEL0_ADG_A_C	((uint32_t)2U << 3U)
-#define	MOD_SEL1_TSIF1_A	((uint32_t)0U << 30U)
-#define	MOD_SEL1_TSIF1_B	((uint32_t)1U << 30U)
-#define	MOD_SEL1_TSIF1_C	((uint32_t)2U << 30U)
-#define	MOD_SEL1_TSIF1_D	((uint32_t)3U << 30U)
-#define	MOD_SEL1_TSIF0_A	((uint32_t)0U << 27U)
-#define	MOD_SEL1_TSIF0_B	((uint32_t)1U << 27U)
-#define	MOD_SEL1_TSIF0_C	((uint32_t)2U << 27U)
-#define	MOD_SEL1_TSIF0_D	((uint32_t)3U << 27U)
-#define	MOD_SEL1_TSIF0_E	((uint32_t)4U << 27U)
-#define	MOD_SEL1_TIMER_TMU_A	((uint32_t)0U << 26U)
-#define	MOD_SEL1_TIMER_TMU_B	((uint32_t)1U << 26U)
-#define	MOD_SEL1_SSP1_1_A	((uint32_t)0U << 24U)
-#define	MOD_SEL1_SSP1_1_B	((uint32_t)1U << 24U)
-#define	MOD_SEL1_SSP1_1_C	((uint32_t)2U << 24U)
-#define	MOD_SEL1_SSP1_1_D	((uint32_t)3U << 24U)
-#define	MOD_SEL1_SSP1_0_A	((uint32_t)0U << 21U)
-#define	MOD_SEL1_SSP1_0_B	((uint32_t)1U << 21U)
-#define	MOD_SEL1_SSP1_0_C	((uint32_t)2U << 21U)
-#define	MOD_SEL1_SSP1_0_D	((uint32_t)3U << 21U)
-#define	MOD_SEL1_SSP1_0_E	((uint32_t)4U << 21U)
-#define	MOD_SEL1_SSI_A		((uint32_t)0U << 20U)
-#define	MOD_SEL1_SSI_B		((uint32_t)1U << 20U)
-#define	MOD_SEL1_SPEED_PULSE_IF_A	((uint32_t)0U << 19U)
-#define	MOD_SEL1_SPEED_PULSE_IF_B	((uint32_t)1U << 19U)
-#define	MOD_SEL1_SIMCARD_A	((uint32_t)0U << 17U)
-#define	MOD_SEL1_SIMCARD_B	((uint32_t)1U << 17U)
-#define	MOD_SEL1_SIMCARD_C	((uint32_t)2U << 17U)
-#define	MOD_SEL1_SIMCARD_D	((uint32_t)3U << 17U)
-#define	MOD_SEL1_SDHI2_A	((uint32_t)0U << 16U)
-#define	MOD_SEL1_SDHI2_B	((uint32_t)1U << 16U)
-#define	MOD_SEL1_SCIF4_A	((uint32_t)0U << 14U)
-#define	MOD_SEL1_SCIF4_B	((uint32_t)1U << 14U)
-#define	MOD_SEL1_SCIF4_C	((uint32_t)2U << 14U)
-#define	MOD_SEL1_SCIF3_A	((uint32_t)0U << 13U)
-#define	MOD_SEL1_SCIF3_B	((uint32_t)1U << 13U)
-#define	MOD_SEL1_SCIF2_A	((uint32_t)0U << 12U)
-#define	MOD_SEL1_SCIF2_B	((uint32_t)1U << 12U)
-#define	MOD_SEL1_SCIF1_A	((uint32_t)0U << 11U)
-#define	MOD_SEL1_SCIF1_B	((uint32_t)1U << 11U)
-#define	MOD_SEL1_SCIF_A		((uint32_t)0U << 10U)
-#define	MOD_SEL1_SCIF_B		((uint32_t)1U << 10U)
-#define	MOD_SEL1_REMOCON_A	((uint32_t)0U << 9U)
-#define	MOD_SEL1_REMOCON_B	((uint32_t)1U << 9U)
-#define	MOD_SEL1_RCAN0_A	((uint32_t)0U << 6U)
-#define	MOD_SEL1_RCAN0_B	((uint32_t)1U << 6U)
-#define	MOD_SEL1_PWM6_A		((uint32_t)0U << 5U)
-#define	MOD_SEL1_PWM6_B		((uint32_t)1U << 5U)
-#define	MOD_SEL1_PWM5_A		((uint32_t)0U << 4U)
-#define	MOD_SEL1_PWM5_B		((uint32_t)1U << 4U)
-#define	MOD_SEL1_PWM4_A		((uint32_t)0U << 3U)
-#define	MOD_SEL1_PWM4_B		((uint32_t)1U << 3U)
-#define	MOD_SEL1_PWM3_A		((uint32_t)0U << 2U)
-#define	MOD_SEL1_PWM3_B		((uint32_t)1U << 2U)
-#define	MOD_SEL1_PWM2_A		((uint32_t)0U << 1U)
-#define	MOD_SEL1_PWM2_B		((uint32_t)1U << 1U)
-#define	MOD_SEL1_PWM1_A		((uint32_t)0U << 0U)
-#define	MOD_SEL1_PWM1_B		((uint32_t)1U << 0U)
-#define	MOD_SEL2_I2C_5_A	((uint32_t)0U << 31U)
-#define	MOD_SEL2_I2C_5_B	((uint32_t)1U << 31U)
-#define	MOD_SEL2_I2C_3_A	((uint32_t)0U << 30U)
-#define	MOD_SEL2_I2C_3_B	((uint32_t)1U << 30U)
-#define	MOD_SEL2_I2C_0_A	((uint32_t)0U << 29U)
-#define	MOD_SEL2_I2C_0_B	((uint32_t)1U << 29U)
-#define	MOD_SEL2_FM_A		((uint32_t)0U << 27U)
-#define	MOD_SEL2_FM_B		((uint32_t)1U << 27U)
-#define	MOD_SEL2_FM_C		((uint32_t)2U << 27U)
-#define	MOD_SEL2_FM_D		((uint32_t)3U << 27U)
-#define	MOD_SEL2_SCIF5_A	((uint32_t)0U << 26U)
-#define	MOD_SEL2_SCIF5_B	((uint32_t)1U << 26U)
-#define	MOD_SEL2_I2C6_A		((uint32_t)0U << 23U)
-#define	MOD_SEL2_I2C6_B		((uint32_t)1U << 23U)
-#define	MOD_SEL2_I2C6_C		((uint32_t)2U << 23U)
-#define	MOD_SEL2_NDF_A		((uint32_t)0U << 22U)
-#define	MOD_SEL2_NDF_B		((uint32_t)1U << 22U)
-#define	MOD_SEL2_SSI2_A		((uint32_t)0U << 21U)
-#define	MOD_SEL2_SSI2_B		((uint32_t)1U << 21U)
-#define	MOD_SEL2_SSI9_A		((uint32_t)0U << 20U)
-#define	MOD_SEL2_SSI9_B		((uint32_t)1U << 20U)
-#define	MOD_SEL2_TIMER_TMU2_A	((uint32_t)0U << 19U)
-#define	MOD_SEL2_TIMER_TMU2_B	((uint32_t)1U << 19U)
-#define	MOD_SEL2_ADG_B_A	((uint32_t)0U << 18U)
-#define	MOD_SEL2_ADG_B_B	((uint32_t)1U << 18U)
-#define	MOD_SEL2_ADG_C_A	((uint32_t)0U << 17U)
-#define	MOD_SEL2_ADG_C_B	((uint32_t)1U << 17U)
-#define	MOD_SEL2_VIN4_A		((uint32_t)0U << 0U)
-#define	MOD_SEL2_VIN4_B		((uint32_t)1U << 0U)
-
-static void pfc_reg_write(uint32_t addr, uint32_t data);
-
-static void pfc_reg_write(uint32_t addr, uint32_t data)
-{
-	mmio_write_32(PFC_PMMR, ~data);
-	mmio_write_32((uintptr_t) addr, data);
-}
-
-void pfc_init_m3n(void)
-{
-	uint32_t reg;
-
-	/* initialize module select */
-	pfc_reg_write(PFC_MOD_SEL0, MOD_SEL0_MSIOF3_A
-		      | MOD_SEL0_MSIOF2_A
-		      | MOD_SEL0_MSIOF1_A
-		      | MOD_SEL0_LBSC_A
-		      | MOD_SEL0_IEBUS_A
-		      | MOD_SEL0_I2C2_A
-		      | MOD_SEL0_I2C1_A
-		      | MOD_SEL0_HSCIF4_A
-		      | MOD_SEL0_HSCIF3_A
-		      | MOD_SEL0_HSCIF1_A
-		      | MOD_SEL0_FSO_A
-		      | MOD_SEL0_HSCIF2_A
-		      | MOD_SEL0_ETHERAVB_A
-		      | MOD_SEL0_DRIF3_A
-		      | MOD_SEL0_DRIF2_A
-		      | MOD_SEL0_DRIF1_A
-		      | MOD_SEL0_DRIF0_A
-		      | MOD_SEL0_CANFD0_A
-		      | MOD_SEL0_ADG_A_A);
-	pfc_reg_write(PFC_MOD_SEL1, MOD_SEL1_TSIF1_A
-		      | MOD_SEL1_TSIF0_A
-		      | MOD_SEL1_TIMER_TMU_A
-		      | MOD_SEL1_SSP1_1_A
-		      | MOD_SEL1_SSP1_0_A
-		      | MOD_SEL1_SSI_A
-		      | MOD_SEL1_SPEED_PULSE_IF_A
-		      | MOD_SEL1_SIMCARD_A
-		      | MOD_SEL1_SDHI2_A
-		      | MOD_SEL1_SCIF4_A
-		      | MOD_SEL1_SCIF3_A
-		      | MOD_SEL1_SCIF2_A
-		      | MOD_SEL1_SCIF1_A
-		      | MOD_SEL1_SCIF_A
-		      | MOD_SEL1_REMOCON_A
-		      | MOD_SEL1_RCAN0_A
-		      | MOD_SEL1_PWM6_A
-		      | MOD_SEL1_PWM5_A
-		      | MOD_SEL1_PWM4_A
-		      | MOD_SEL1_PWM3_A
-		      | MOD_SEL1_PWM2_A
-		      | MOD_SEL1_PWM1_A);
-	pfc_reg_write(PFC_MOD_SEL2, MOD_SEL2_I2C_5_A
-		      | MOD_SEL2_I2C_3_A
-		      | MOD_SEL2_I2C_0_A
-		      | MOD_SEL2_FM_A
-		      | MOD_SEL2_SCIF5_A
-		      | MOD_SEL2_I2C6_A
-		      | MOD_SEL2_NDF_A
-		      | MOD_SEL2_SSI2_A
-		      | MOD_SEL2_SSI9_A
-		      | MOD_SEL2_TIMER_TMU2_A
-		      | MOD_SEL2_ADG_B_A
-		      | MOD_SEL2_ADG_C_A
-		      | MOD_SEL2_VIN4_A);
-
-	/* initialize peripheral function select */
-	pfc_reg_write(PFC_IPSR0, IPSR_28_FUNC(0)
-		      | IPSR_24_FUNC(0)
-		      | IPSR_20_FUNC(0)
-		      | IPSR_16_FUNC(0)
-		      | IPSR_12_FUNC(0)
-		      | IPSR_8_FUNC(0)
-		      | IPSR_4_FUNC(0)
-		      | IPSR_0_FUNC(0));
-	pfc_reg_write(PFC_IPSR1, IPSR_28_FUNC(6)
-		      | IPSR_24_FUNC(0)
-		      | IPSR_20_FUNC(0)
-		      | IPSR_16_FUNC(0)
-		      | IPSR_12_FUNC(3)
-		      | IPSR_8_FUNC(3)
-		      | IPSR_4_FUNC(3)
-		      | IPSR_0_FUNC(3));
-	pfc_reg_write(PFC_IPSR2, IPSR_28_FUNC(0)
-		      | IPSR_24_FUNC(6)
-		      | IPSR_20_FUNC(6)
-		      | IPSR_16_FUNC(6)
-		      | IPSR_12_FUNC(6)
-		      | IPSR_8_FUNC(6)
-		      | IPSR_4_FUNC(6)
-		      | IPSR_0_FUNC(6));
-	pfc_reg_write(PFC_IPSR3, IPSR_28_FUNC(6)
-		      | IPSR_24_FUNC(6)
-		      | IPSR_20_FUNC(6)
-		      | IPSR_16_FUNC(6)
-		      | IPSR_12_FUNC(6)
-		      | IPSR_8_FUNC(0)
-		      | IPSR_4_FUNC(0)
-		      | IPSR_0_FUNC(0));
-	pfc_reg_write(PFC_IPSR4, IPSR_28_FUNC(0)
-		      | IPSR_24_FUNC(0)
-		      | IPSR_20_FUNC(0)
-		      | IPSR_16_FUNC(0)
-		      | IPSR_12_FUNC(0)
-		      | IPSR_8_FUNC(6)
-		      | IPSR_4_FUNC(6)
-		      | IPSR_0_FUNC(6));
-	pfc_reg_write(PFC_IPSR5, IPSR_28_FUNC(0)
-		      | IPSR_24_FUNC(0)
-		      | IPSR_20_FUNC(0)
-		      | IPSR_16_FUNC(0)
-		      | IPSR_12_FUNC(0)
-		      | IPSR_8_FUNC(6)
-		      | IPSR_4_FUNC(0)
-		      | IPSR_0_FUNC(0));
-	pfc_reg_write(PFC_IPSR6, IPSR_28_FUNC(6)
-		      | IPSR_24_FUNC(6)
-		      | IPSR_20_FUNC(6)
-		      | IPSR_16_FUNC(6)
-		      | IPSR_12_FUNC(6)
-		      | IPSR_8_FUNC(0)
-		      | IPSR_4_FUNC(0)
-		      | IPSR_0_FUNC(0));
-	pfc_reg_write(PFC_IPSR7, IPSR_28_FUNC(0)
-		      | IPSR_24_FUNC(0)
-		      | IPSR_20_FUNC(0)
-		      | IPSR_16_FUNC(0)
-		      | IPSR_12_FUNC(0)
-		      | IPSR_8_FUNC(6)
-		      | IPSR_4_FUNC(6)
-		      | IPSR_0_FUNC(6));
-	pfc_reg_write(PFC_IPSR8, IPSR_28_FUNC(1)
-		      | IPSR_24_FUNC(1)
-		      | IPSR_20_FUNC(1)
-		      | IPSR_16_FUNC(1)
-		      | IPSR_12_FUNC(0)
-		      | IPSR_8_FUNC(0)
-		      | IPSR_4_FUNC(0)
-		      | IPSR_0_FUNC(0));
-	pfc_reg_write(PFC_IPSR9, IPSR_28_FUNC(0)
-		      | IPSR_24_FUNC(0)
-		      | IPSR_20_FUNC(0)
-		      | IPSR_16_FUNC(0)
-		      | IPSR_12_FUNC(0)
-		      | IPSR_8_FUNC(0)
-		      | IPSR_4_FUNC(0)
-		      | IPSR_0_FUNC(0));
-	pfc_reg_write(PFC_IPSR10, IPSR_28_FUNC(1)
-		      | IPSR_24_FUNC(0)
-		      | IPSR_20_FUNC(0)
-		      | IPSR_16_FUNC(0)
-		      | IPSR_12_FUNC(0)
-		      | IPSR_8_FUNC(0)
-		      | IPSR_4_FUNC(0)
-		      | IPSR_0_FUNC(0));
-	pfc_reg_write(PFC_IPSR11, IPSR_28_FUNC(0)
-		      | IPSR_24_FUNC(4)
-		      | IPSR_20_FUNC(0)
-		      | IPSR_16_FUNC(0)
-		      | IPSR_12_FUNC(0)
-		      | IPSR_8_FUNC(0)
-		      | IPSR_4_FUNC(0)
-		      | IPSR_0_FUNC(1));
-	pfc_reg_write(PFC_IPSR12, IPSR_28_FUNC(0)
-		      | IPSR_24_FUNC(0)
-		      | IPSR_20_FUNC(0)
-		      | IPSR_16_FUNC(0)
-		      | IPSR_12_FUNC(0)
-		      | IPSR_8_FUNC(4)
-		      | IPSR_4_FUNC(0)
-		      | IPSR_0_FUNC(0));
-	pfc_reg_write(PFC_IPSR13, IPSR_28_FUNC(8)
-		      | IPSR_24_FUNC(0)
-		      | IPSR_20_FUNC(0)
-		      | IPSR_16_FUNC(0)
-		      | IPSR_12_FUNC(0)
-		      | IPSR_8_FUNC(3)
-		      | IPSR_4_FUNC(0)
-		      | IPSR_0_FUNC(0));
-	pfc_reg_write(PFC_IPSR14, IPSR_28_FUNC(0)
-		      | IPSR_24_FUNC(0)
-		      | IPSR_20_FUNC(0)
-		      | IPSR_16_FUNC(0)
-		      | IPSR_12_FUNC(0)
-		      | IPSR_8_FUNC(0)
-		      | IPSR_4_FUNC(3)
-		      | IPSR_0_FUNC(8));
-	pfc_reg_write(PFC_IPSR15, IPSR_28_FUNC(0)
-		      | IPSR_24_FUNC(0)
-		      | IPSR_20_FUNC(0)
-		      | IPSR_16_FUNC(0)
-		      | IPSR_12_FUNC(0)
-		      | IPSR_8_FUNC(0)
-		      | IPSR_4_FUNC(0)
-		      | IPSR_0_FUNC(0));
-	pfc_reg_write(PFC_IPSR16, IPSR_28_FUNC(0)
-		      | IPSR_24_FUNC(0)
-		      | IPSR_20_FUNC(0)
-		      | IPSR_16_FUNC(0)
-		      | IPSR_12_FUNC(0)
-		      | IPSR_8_FUNC(0)
-		      | IPSR_4_FUNC(0)
-		      | IPSR_0_FUNC(0));
-	pfc_reg_write(PFC_IPSR17, IPSR_28_FUNC(0)
-		      | IPSR_24_FUNC(0)
-		      | IPSR_20_FUNC(0)
-		      | IPSR_16_FUNC(0)
-		      | IPSR_12_FUNC(0)
-		      | IPSR_8_FUNC(0)
-		      | IPSR_4_FUNC(1)
-		      | IPSR_0_FUNC(0));
-	pfc_reg_write(PFC_IPSR18, IPSR_4_FUNC(0)
-		      | IPSR_0_FUNC(0));
-
-	/* initialize GPIO/perihperal function select */
-	pfc_reg_write(PFC_GPSR0, GPSR0_D15
-		      | GPSR0_D14
-		      | GPSR0_D13
-		      | GPSR0_D12
-		      | GPSR0_D11
-		      | GPSR0_D10
-		      | GPSR0_D9
-		      | GPSR0_D8);
-	pfc_reg_write(PFC_GPSR1, GPSR1_CLKOUT
-		      | GPSR1_EX_WAIT0_A
-		      | GPSR1_A19
-		      | GPSR1_A18
-		      | GPSR1_A17
-		      | GPSR1_A16
-		      | GPSR1_A15
-		      | GPSR1_A14
-		      | GPSR1_A13
-		      | GPSR1_A12
-		      | GPSR1_A7
-		      | GPSR1_A6
-		      | GPSR1_A5
-		      | GPSR1_A4
-		      | GPSR1_A3
-		      | GPSR1_A2
-		      | GPSR1_A1
-		      | GPSR1_A0);
-	pfc_reg_write(PFC_GPSR2, GPSR2_AVB_AVTP_CAPTURE_A
-		      | GPSR2_AVB_AVTP_MATCH_A
-		      | GPSR2_AVB_LINK
-		      | GPSR2_AVB_PHY_INT
-		      | GPSR2_AVB_MDC
-		      | GPSR2_PWM2_A
-		      | GPSR2_PWM1_A
-		      | GPSR2_IRQ5
-		      | GPSR2_IRQ4
-		      | GPSR2_IRQ3
-		      | GPSR2_IRQ2
-		      | GPSR2_IRQ1
-		      | GPSR2_IRQ0);
-	pfc_reg_write(PFC_GPSR3, GPSR3_SD0_WP
-		      | GPSR3_SD0_CD
-		      | GPSR3_SD1_DAT3
-		      | GPSR3_SD1_DAT2
-		      | GPSR3_SD1_DAT1
-		      | GPSR3_SD1_DAT0
-		      | GPSR3_SD0_DAT3
-		      | GPSR3_SD0_DAT2
-		      | GPSR3_SD0_DAT1
-		      | GPSR3_SD0_DAT0
-		      | GPSR3_SD0_CMD
-		      | GPSR3_SD0_CLK);
-	pfc_reg_write(PFC_GPSR4, GPSR4_SD3_DAT7
-		      | GPSR4_SD3_DAT6
-		      | GPSR4_SD3_DAT3
-		      | GPSR4_SD3_DAT2
-		      | GPSR4_SD3_DAT1
-		      | GPSR4_SD3_DAT0
-		      | GPSR4_SD3_CMD
-		      | GPSR4_SD3_CLK
-		      | GPSR4_SD2_DS
-		      | GPSR4_SD2_DAT3
-		      | GPSR4_SD2_DAT2
-		      | GPSR4_SD2_DAT1
-		      | GPSR4_SD2_DAT0
-		      | GPSR4_SD2_CMD
-		      | GPSR4_SD2_CLK);
-	pfc_reg_write(PFC_GPSR5, GPSR5_MSIOF0_SS2
-		      | GPSR5_MSIOF0_SS1
-		      | GPSR5_MSIOF0_SYNC
-		      | GPSR5_HRTS0
-		      | GPSR5_HCTS0
-		      | GPSR5_HTX0
-		      | GPSR5_HRX0
-		      | GPSR5_HSCK0
-		      | GPSR5_RX2_A
-		      | GPSR5_TX2_A
-		      | GPSR5_SCK2
-		      | GPSR5_RTS1_TANS
-		      | GPSR5_CTS1
-		      | GPSR5_TX1_A
-		      | GPSR5_RX1_A
-		      | GPSR5_RTS0_TANS
-		      | GPSR5_SCK0);
-	pfc_reg_write(PFC_GPSR6, GPSR6_USB30_OVC
-		      | GPSR6_USB30_PWEN
-		      | GPSR6_USB1_OVC
-		      | GPSR6_USB1_PWEN
-		      | GPSR6_USB0_OVC
-		      | GPSR6_USB0_PWEN
-		      | GPSR6_AUDIO_CLKB_B
-		      | GPSR6_AUDIO_CLKA_A
-		      | GPSR6_SSI_SDATA8
-		      | GPSR6_SSI_SDATA7
-		      | GPSR6_SSI_WS78
-		      | GPSR6_SSI_SCK78
-		      | GPSR6_SSI_WS6
-		      | GPSR6_SSI_SCK6
-		      | GPSR6_SSI_SDATA4
-		      | GPSR6_SSI_WS4
-		      | GPSR6_SSI_SCK4
-		      | GPSR6_SSI_SDATA1_A
-		      | GPSR6_SSI_SDATA0
-		      | GPSR6_SSI_WS0129
-		      | GPSR6_SSI_SCK0129);
-	pfc_reg_write(PFC_GPSR7, GPSR7_HDMI1_CEC
-		      | GPSR7_HDMI0_CEC
-		      | GPSR7_AVS2
-		      | GPSR7_AVS1);
-
-	/* initialize POC control register */
-	pfc_reg_write(PFC_POCCTRL0, POC_SD3_DS_33V
-		      | POC_SD3_DAT7_33V
-		      | POC_SD3_DAT6_33V
-		      | POC_SD3_DAT5_33V
-		      | POC_SD3_DAT4_33V
-		      | POC_SD3_DAT3_33V
-		      | POC_SD3_DAT2_33V
-		      | POC_SD3_DAT1_33V
-		      | POC_SD3_DAT0_33V
-		      | POC_SD3_CMD_33V
-		      | POC_SD3_CLK_33V
-		      | POC_SD0_DAT3_33V
-		      | POC_SD0_DAT2_33V
-		      | POC_SD0_DAT1_33V
-		      | POC_SD0_DAT0_33V
-		      | POC_SD0_CMD_33V
-		      | POC_SD0_CLK_33V);
-
-	/* initialize DRV control register */
-	reg = mmio_read_32(PFC_DRVCTRL0);
-	reg = ((reg & DRVCTRL0_MASK) | DRVCTRL0_QSPI0_SPCLK(3)
-	       | DRVCTRL0_QSPI0_MOSI_IO0(3)
-	       | DRVCTRL0_QSPI0_MISO_IO1(3)
-	       | DRVCTRL0_QSPI0_IO2(3)
-	       | DRVCTRL0_QSPI0_IO3(3)
-	       | DRVCTRL0_QSPI0_SSL(3)
-	       | DRVCTRL0_QSPI1_SPCLK(3)
-	       | DRVCTRL0_QSPI1_MOSI_IO0(3));
-	pfc_reg_write(PFC_DRVCTRL0, reg);
-	reg = mmio_read_32(PFC_DRVCTRL1);
-	reg = ((reg & DRVCTRL1_MASK) | DRVCTRL1_QSPI1_MISO_IO1(3)
-	       | DRVCTRL1_QSPI1_IO2(3)
-	       | DRVCTRL1_QSPI1_IO3(3)
-	       | DRVCTRL1_QSPI1_SS(3)
-	       | DRVCTRL1_RPC_INT(3)
-	       | DRVCTRL1_RPC_WP(3)
-	       | DRVCTRL1_RPC_RESET(3)
-	       | DRVCTRL1_AVB_RX_CTL(7));
-	pfc_reg_write(PFC_DRVCTRL1, reg);
-	reg = mmio_read_32(PFC_DRVCTRL2);
-	reg = ((reg & DRVCTRL2_MASK) | DRVCTRL2_AVB_RXC(7)
-	       | DRVCTRL2_AVB_RD0(7)
-	       | DRVCTRL2_AVB_RD1(7)
-	       | DRVCTRL2_AVB_RD2(7)
-	       | DRVCTRL2_AVB_RD3(7)
-	       | DRVCTRL2_AVB_TX_CTL(3)
-	       | DRVCTRL2_AVB_TXC(3)
-	       | DRVCTRL2_AVB_TD0(3));
-	pfc_reg_write(PFC_DRVCTRL2, reg);
-	reg = mmio_read_32(PFC_DRVCTRL3);
-	reg = ((reg & DRVCTRL3_MASK) | DRVCTRL3_AVB_TD1(3)
-	       | DRVCTRL3_AVB_TD2(3)
-	       | DRVCTRL3_AVB_TD3(3)
-	       | DRVCTRL3_AVB_TXCREFCLK(7)
-	       | DRVCTRL3_AVB_MDIO(7)
-	       | DRVCTRL3_AVB_MDC(7)
-	       | DRVCTRL3_AVB_MAGIC(7)
-	       | DRVCTRL3_AVB_PHY_INT(7));
-	pfc_reg_write(PFC_DRVCTRL3, reg);
-	reg = mmio_read_32(PFC_DRVCTRL4);
-	reg = ((reg & DRVCTRL4_MASK) | DRVCTRL4_AVB_LINK(7)
-	       | DRVCTRL4_AVB_AVTP_MATCH(7)
-	       | DRVCTRL4_AVB_AVTP_CAPTURE(7)
-	       | DRVCTRL4_IRQ0(7)
-	       | DRVCTRL4_IRQ1(7)
-	       | DRVCTRL4_IRQ2(7)
-	       | DRVCTRL4_IRQ3(7)
-	       | DRVCTRL4_IRQ4(7));
-	pfc_reg_write(PFC_DRVCTRL4, reg);
-	reg = mmio_read_32(PFC_DRVCTRL5);
-	reg = ((reg & DRVCTRL5_MASK) | DRVCTRL5_IRQ5(7)
-	       | DRVCTRL5_PWM0(7)
-	       | DRVCTRL5_PWM1(7)
-	       | DRVCTRL5_PWM2(7)
-	       | DRVCTRL5_A0(3)
-	       | DRVCTRL5_A1(3)
-	       | DRVCTRL5_A2(3)
-	       | DRVCTRL5_A3(3));
-	pfc_reg_write(PFC_DRVCTRL5, reg);
-	reg = mmio_read_32(PFC_DRVCTRL6);
-	reg = ((reg & DRVCTRL6_MASK) | DRVCTRL6_A4(3)
-	       | DRVCTRL6_A5(3)
-	       | DRVCTRL6_A6(3)
-	       | DRVCTRL6_A7(3)
-	       | DRVCTRL6_A8(7)
-	       | DRVCTRL6_A9(7)
-	       | DRVCTRL6_A10(7)
-	       | DRVCTRL6_A11(7));
-	pfc_reg_write(PFC_DRVCTRL6, reg);
-	reg = mmio_read_32(PFC_DRVCTRL7);
-	reg = ((reg & DRVCTRL7_MASK) | DRVCTRL7_A12(3)
-	       | DRVCTRL7_A13(3)
-	       | DRVCTRL7_A14(3)
-	       | DRVCTRL7_A15(3)
-	       | DRVCTRL7_A16(3)
-	       | DRVCTRL7_A17(3)
-	       | DRVCTRL7_A18(3)
-	       | DRVCTRL7_A19(3));
-	pfc_reg_write(PFC_DRVCTRL7, reg);
-	reg = mmio_read_32(PFC_DRVCTRL8);
-	reg = ((reg & DRVCTRL8_MASK) | DRVCTRL8_CLKOUT(7)
-	       | DRVCTRL8_CS0(7)
-	       | DRVCTRL8_CS1_A2(7)
-	       | DRVCTRL8_BS(7)
-	       | DRVCTRL8_RD(7)
-	       | DRVCTRL8_RD_W(7)
-	       | DRVCTRL8_WE0(7)
-	       | DRVCTRL8_WE1(7));
-	pfc_reg_write(PFC_DRVCTRL8, reg);
-	reg = mmio_read_32(PFC_DRVCTRL9);
-	reg = ((reg & DRVCTRL9_MASK) | DRVCTRL9_EX_WAIT0(7)
-	       | DRVCTRL9_PRESETOU(7)
-	       | DRVCTRL9_D0(7)
-	       | DRVCTRL9_D1(7)
-	       | DRVCTRL9_D2(7)
-	       | DRVCTRL9_D3(7)
-	       | DRVCTRL9_D4(7)
-	       | DRVCTRL9_D5(7));
-	pfc_reg_write(PFC_DRVCTRL9, reg);
-	reg = mmio_read_32(PFC_DRVCTRL10);
-	reg = ((reg & DRVCTRL10_MASK) | DRVCTRL10_D6(7)
-	       | DRVCTRL10_D7(7)
-	       | DRVCTRL10_D8(3)
-	       | DRVCTRL10_D9(3)
-	       | DRVCTRL10_D10(3)
-	       | DRVCTRL10_D11(3)
-	       | DRVCTRL10_D12(3)
-	       | DRVCTRL10_D13(3));
-	pfc_reg_write(PFC_DRVCTRL10, reg);
-	reg = mmio_read_32(PFC_DRVCTRL11);
-	reg = ((reg & DRVCTRL11_MASK) | DRVCTRL11_D14(3)
-	       | DRVCTRL11_D15(3)
-	       | DRVCTRL11_AVS1(7)
-	       | DRVCTRL11_AVS2(7)
-	       | DRVCTRL11_HDMI0_CEC(7)
-	       | DRVCTRL11_HDMI1_CEC(7)
-	       | DRVCTRL11_DU_DOTCLKIN0(3)
-	       | DRVCTRL11_DU_DOTCLKIN1(3));
-	pfc_reg_write(PFC_DRVCTRL11, reg);
-	reg = mmio_read_32(PFC_DRVCTRL12);
-	reg = ((reg & DRVCTRL12_MASK) | DRVCTRL12_DU_DOTCLKIN2(3)
-	       | DRVCTRL12_DU_DOTCLKIN3(3)
-	       | DRVCTRL12_DU_FSCLKST(3)
-	       | DRVCTRL12_DU_TMS(3));
-	pfc_reg_write(PFC_DRVCTRL12, reg);
-	reg = mmio_read_32(PFC_DRVCTRL13);
-	reg = ((reg & DRVCTRL13_MASK) | DRVCTRL13_TDO(3)
-	       | DRVCTRL13_ASEBRK(3)
-	       | DRVCTRL13_SD0_CLK(7)
-	       | DRVCTRL13_SD0_CMD(7)
-	       | DRVCTRL13_SD0_DAT0(7)
-	       | DRVCTRL13_SD0_DAT1(7)
-	       | DRVCTRL13_SD0_DAT2(7)
-	       | DRVCTRL13_SD0_DAT3(7));
-	pfc_reg_write(PFC_DRVCTRL13, reg);
-	reg = mmio_read_32(PFC_DRVCTRL14);
-	reg = ((reg & DRVCTRL14_MASK) | DRVCTRL14_SD1_CLK(7)
-	       | DRVCTRL14_SD1_CMD(7)
-	       | DRVCTRL14_SD1_DAT0(5)
-	       | DRVCTRL14_SD1_DAT1(5)
-	       | DRVCTRL14_SD1_DAT2(5)
-	       | DRVCTRL14_SD1_DAT3(5)
-	       | DRVCTRL14_SD2_CLK(5)
-	       | DRVCTRL14_SD2_CMD(5));
-	pfc_reg_write(PFC_DRVCTRL14, reg);
-	reg = mmio_read_32(PFC_DRVCTRL15);
-	reg = ((reg & DRVCTRL15_MASK) | DRVCTRL15_SD2_DAT0(5)
-	       | DRVCTRL15_SD2_DAT1(5)
-	       | DRVCTRL15_SD2_DAT2(5)
-	       | DRVCTRL15_SD2_DAT3(5)
-	       | DRVCTRL15_SD2_DS(5)
-	       | DRVCTRL15_SD3_CLK(7)
-	       | DRVCTRL15_SD3_CMD(7)
-	       | DRVCTRL15_SD3_DAT0(7));
-	pfc_reg_write(PFC_DRVCTRL15, reg);
-	reg = mmio_read_32(PFC_DRVCTRL16);
-	reg = ((reg & DRVCTRL16_MASK) | DRVCTRL16_SD3_DAT1(7)
-	       | DRVCTRL16_SD3_DAT2(7)
-	       | DRVCTRL16_SD3_DAT3(7)
-	       | DRVCTRL16_SD3_DAT4(7)
-	       | DRVCTRL16_SD3_DAT5(7)
-	       | DRVCTRL16_SD3_DAT6(7)
-	       | DRVCTRL16_SD3_DAT7(7)
-	       | DRVCTRL16_SD3_DS(7));
-	pfc_reg_write(PFC_DRVCTRL16, reg);
-	reg = mmio_read_32(PFC_DRVCTRL17);
-	reg = ((reg & DRVCTRL17_MASK) | DRVCTRL17_SD0_CD(7)
-	       | DRVCTRL17_SD0_WP(7)
-	       | DRVCTRL17_SD1_CD(7)
-	       | DRVCTRL17_SD1_WP(7)
-	       | DRVCTRL17_SCK0(7)
-	       | DRVCTRL17_RX0(7)
-	       | DRVCTRL17_TX0(7)
-	       | DRVCTRL17_CTS0(7));
-	pfc_reg_write(PFC_DRVCTRL17, reg);
-	reg = mmio_read_32(PFC_DRVCTRL18);
-	reg = ((reg & DRVCTRL18_MASK) | DRVCTRL18_RTS0_TANS(7)
-	       | DRVCTRL18_RX1(7)
-	       | DRVCTRL18_TX1(7)
-	       | DRVCTRL18_CTS1(7)
-	       | DRVCTRL18_RTS1_TANS(7)
-	       | DRVCTRL18_SCK2(7)
-	       | DRVCTRL18_TX2(7)
-	       | DRVCTRL18_RX2(7));
-	pfc_reg_write(PFC_DRVCTRL18, reg);
-	reg = mmio_read_32(PFC_DRVCTRL19);
-	reg = ((reg & DRVCTRL19_MASK) | DRVCTRL19_HSCK0(7)
-	       | DRVCTRL19_HRX0(7)
-	       | DRVCTRL19_HTX0(7)
-	       | DRVCTRL19_HCTS0(7)
-	       | DRVCTRL19_HRTS0(7)
-	       | DRVCTRL19_MSIOF0_SCK(7)
-	       | DRVCTRL19_MSIOF0_SYNC(7)
-	       | DRVCTRL19_MSIOF0_SS1(7));
-	pfc_reg_write(PFC_DRVCTRL19, reg);
-	reg = mmio_read_32(PFC_DRVCTRL20);
-	reg = ((reg & DRVCTRL20_MASK) | DRVCTRL20_MSIOF0_TXD(7)
-	       | DRVCTRL20_MSIOF0_SS2(7)
-	       | DRVCTRL20_MSIOF0_RXD(7)
-	       | DRVCTRL20_MLB_CLK(7)
-	       | DRVCTRL20_MLB_SIG(7)
-	       | DRVCTRL20_MLB_DAT(7)
-	       | DRVCTRL20_MLB_REF(7)
-	       | DRVCTRL20_SSI_SCK0129(7));
-	pfc_reg_write(PFC_DRVCTRL20, reg);
-	reg = mmio_read_32(PFC_DRVCTRL21);
-	reg = ((reg & DRVCTRL21_MASK) | DRVCTRL21_SSI_WS0129(7)
-	       | DRVCTRL21_SSI_SDATA0(7)
-	       | DRVCTRL21_SSI_SDATA1(7)
-	       | DRVCTRL21_SSI_SDATA2(7)
-	       | DRVCTRL21_SSI_SCK34(7)
-	       | DRVCTRL21_SSI_WS34(7)
-	       | DRVCTRL21_SSI_SDATA3(7)
-	       | DRVCTRL21_SSI_SCK4(7));
-	pfc_reg_write(PFC_DRVCTRL21, reg);
-	reg = mmio_read_32(PFC_DRVCTRL22);
-	reg = ((reg & DRVCTRL22_MASK) | DRVCTRL22_SSI_WS4(7)
-	       | DRVCTRL22_SSI_SDATA4(7)
-	       | DRVCTRL22_SSI_SCK5(7)
-	       | DRVCTRL22_SSI_WS5(7)
-	       | DRVCTRL22_SSI_SDATA5(7)
-	       | DRVCTRL22_SSI_SCK6(7)
-	       | DRVCTRL22_SSI_WS6(7)
-	       | DRVCTRL22_SSI_SDATA6(7));
-	pfc_reg_write(PFC_DRVCTRL22, reg);
-	reg = mmio_read_32(PFC_DRVCTRL23);
-	reg = ((reg & DRVCTRL23_MASK) | DRVCTRL23_SSI_SCK78(7)
-	       | DRVCTRL23_SSI_WS78(7)
-	       | DRVCTRL23_SSI_SDATA7(7)
-	       | DRVCTRL23_SSI_SDATA8(7)
-	       | DRVCTRL23_SSI_SDATA9(7)
-	       | DRVCTRL23_AUDIO_CLKA(7)
-	       | DRVCTRL23_AUDIO_CLKB(7)
-	       | DRVCTRL23_USB0_PWEN(7));
-	pfc_reg_write(PFC_DRVCTRL23, reg);
-	reg = mmio_read_32(PFC_DRVCTRL24);
-	reg = ((reg & DRVCTRL24_MASK) | DRVCTRL24_USB0_OVC(7)
-	       | DRVCTRL24_USB1_PWEN(7)
-	       | DRVCTRL24_USB1_OVC(7)
-	       | DRVCTRL24_USB30_PWEN(7)
-	       | DRVCTRL24_USB30_OVC(7)
-	       | DRVCTRL24_USB31_PWEN(7)
-	       | DRVCTRL24_USB31_OVC(7));
-	pfc_reg_write(PFC_DRVCTRL24, reg);
-
-	/* initialize LSI pin pull-up/down control */
-	pfc_reg_write(PFC_PUD0, 0x00005FBFU);
-	pfc_reg_write(PFC_PUD1, 0x00300FFEU);
-	pfc_reg_write(PFC_PUD2, 0x330001E6U);
-	pfc_reg_write(PFC_PUD3, 0x000002E0U);
-	pfc_reg_write(PFC_PUD4, 0xFFFFFF00U);
-	pfc_reg_write(PFC_PUD5, 0x7F5FFF87U);
-	pfc_reg_write(PFC_PUD6, 0x00000055U);
-
-	/* initialize LSI pin pull-enable register */
-	pfc_reg_write(PFC_PUEN0, 0x00000FFFU);
-	pfc_reg_write(PFC_PUEN1, 0x00100234U);
-	pfc_reg_write(PFC_PUEN2, 0x000004C4U);
-	pfc_reg_write(PFC_PUEN3, 0x00000200U);
-	pfc_reg_write(PFC_PUEN4, 0x3E000000U);
-	pfc_reg_write(PFC_PUEN5, 0x1F000805U);
-	pfc_reg_write(PFC_PUEN6, 0x00000006U);
-
-	/* initialize positive/negative logic select */
-	mmio_write_32(GPIO_POSNEG0, 0x00000000U);
-	mmio_write_32(GPIO_POSNEG1, 0x00000000U);
-	mmio_write_32(GPIO_POSNEG2, 0x00000000U);
-	mmio_write_32(GPIO_POSNEG3, 0x00000000U);
-	mmio_write_32(GPIO_POSNEG4, 0x00000000U);
-	mmio_write_32(GPIO_POSNEG5, 0x00000000U);
-	mmio_write_32(GPIO_POSNEG6, 0x00000000U);
-
-	/* initialize general IO/interrupt switching */
-	mmio_write_32(GPIO_IOINTSEL0, 0x00000000U);
-	mmio_write_32(GPIO_IOINTSEL1, 0x00000000U);
-	mmio_write_32(GPIO_IOINTSEL2, 0x00000000U);
-	mmio_write_32(GPIO_IOINTSEL3, 0x00000000U);
-	mmio_write_32(GPIO_IOINTSEL4, 0x00000000U);
-	mmio_write_32(GPIO_IOINTSEL5, 0x00000000U);
-	mmio_write_32(GPIO_IOINTSEL6, 0x00000000U);
-
-	/* initialize general output register */
-	mmio_write_32(GPIO_OUTDT1, 0x00000000U);
-	mmio_write_32(GPIO_OUTDT2, 0x00000400U);
-	mmio_write_32(GPIO_OUTDT3, 0x0000C000U);
-	mmio_write_32(GPIO_OUTDT5, 0x00000006U);
-	mmio_write_32(GPIO_OUTDT6, 0x00003880U);
-
-	/* initialize general input/output switching */
-	mmio_write_32(GPIO_INOUTSEL0, 0x00000000U);
-	mmio_write_32(GPIO_INOUTSEL1, 0x01000A00U);
-	mmio_write_32(GPIO_INOUTSEL2, 0x00000400U);
-	mmio_write_32(GPIO_INOUTSEL3, 0x0000C000U);
-	mmio_write_32(GPIO_INOUTSEL4, 0x00000000U);
-#if (RCAR_GEN3_ULCB == 1)
-	mmio_write_32(GPIO_INOUTSEL5, 0x0000000EU);
-#else
-	mmio_write_32(GPIO_INOUTSEL5, 0x0000020EU);
-#endif
-	mmio_write_32(GPIO_INOUTSEL6, 0x00013880U);
-}
diff --git a/drivers/staging/renesas/rcar/pfc/V3M/pfc_init_v3m.c b/drivers/staging/renesas/rcar/pfc/V3M/pfc_init_v3m.c
deleted file mode 100644
index caa6048..0000000
--- a/drivers/staging/renesas/rcar/pfc/V3M/pfc_init_v3m.c
+++ /dev/null
@@ -1,1052 +0,0 @@
-/*
- * Copyright (c) 2015-2017, Renesas Electronics Corporation
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <stdint.h>		/* for uint32_t */
-#include <lib/mmio.h>
-#include "pfc_init_v3m.h"
-#include "include/rcar_def.h"
-#include "rcar_private.h"
-
-#define	RST_MODEMR		0xE6160060		// Mode Monitor Register
-
-/* GPIO base address */
-#define	GPIO_BASE		(0xE6050000U)
-
-/* GPIO registers */
-#define	GPIO_IOINTSEL0		(GPIO_BASE + 0x0000U)
-#define	GPIO_INOUTSEL0		(GPIO_BASE + 0x0004U)
-#define	GPIO_OUTDT0			(GPIO_BASE + 0x0008U)
-#define	GPIO_INDT0			(GPIO_BASE + 0x000CU)
-#define	GPIO_INTDT0			(GPIO_BASE + 0x0010U)
-#define	GPIO_INTCLR0		(GPIO_BASE + 0x0014U)
-#define	GPIO_INTMSK0		(GPIO_BASE + 0x0018U)
-#define	GPIO_MSKCLR0		(GPIO_BASE + 0x001CU)
-#define	GPIO_POSNEG0		(GPIO_BASE + 0x0020U)
-#define	GPIO_EDGLEVEL0		(GPIO_BASE + 0x0024U)
-#define	GPIO_FILONOFF0		(GPIO_BASE + 0x0028U)
-#define	GPIO_INTMSKS0		(GPIO_BASE + 0x0038U)
-#define	GPIO_MSKCLRS0		(GPIO_BASE + 0x003CU)
-#define	GPIO_OUTDTSEL0		(GPIO_BASE + 0x0040U)
-#define	GPIO_OUTDTH0		(GPIO_BASE + 0x0044U)
-#define	GPIO_OUTDTL0		(GPIO_BASE + 0x0048U)
-#define	GPIO_BOTHEDGE0		(GPIO_BASE + 0x004CU)
-#define	GPIO_IOINTSEL1		(GPIO_BASE + 0x1000U)
-#define	GPIO_INOUTSEL1		(GPIO_BASE + 0x1004U)
-#define	GPIO_OUTDT1			(GPIO_BASE + 0x1008U)
-#define	GPIO_INDT1			(GPIO_BASE + 0x100CU)
-#define	GPIO_INTDT1			(GPIO_BASE + 0x1010U)
-#define	GPIO_INTCLR1		(GPIO_BASE + 0x1014U)
-#define	GPIO_INTMSK1		(GPIO_BASE + 0x1018U)
-#define	GPIO_MSKCLR1		(GPIO_BASE + 0x101CU)
-#define	GPIO_POSNEG1		(GPIO_BASE + 0x1020U)
-#define	GPIO_EDGLEVEL1		(GPIO_BASE + 0x1024U)
-#define	GPIO_FILONOFF1		(GPIO_BASE + 0x1028U)
-#define	GPIO_INTMSKS1		(GPIO_BASE + 0x1038U)
-#define	GPIO_MSKCLRS1		(GPIO_BASE + 0x103CU)
-#define	GPIO_OUTDTSEL1		(GPIO_BASE + 0x1040U)
-#define	GPIO_OUTDTH1		(GPIO_BASE + 0x1044U)
-#define	GPIO_OUTDTL1		(GPIO_BASE + 0x1048U)
-#define	GPIO_BOTHEDGE1		(GPIO_BASE + 0x104CU)
-#define	GPIO_IOINTSEL2		(GPIO_BASE + 0x2000U)
-#define	GPIO_INOUTSEL2		(GPIO_BASE + 0x2004U)
-#define	GPIO_OUTDT2			(GPIO_BASE + 0x2008U)
-#define	GPIO_INDT2			(GPIO_BASE + 0x200CU)
-#define	GPIO_INTDT2			(GPIO_BASE + 0x2010U)
-#define	GPIO_INTCLR2		(GPIO_BASE + 0x2014U)
-#define	GPIO_INTMSK2		(GPIO_BASE + 0x2018U)
-#define	GPIO_MSKCLR2		(GPIO_BASE + 0x201CU)
-#define	GPIO_POSNEG2		(GPIO_BASE + 0x2020U)
-#define	GPIO_EDGLEVEL2		(GPIO_BASE + 0x2024U)
-#define	GPIO_FILONOFF2		(GPIO_BASE + 0x2028U)
-#define	GPIO_INTMSKS2		(GPIO_BASE + 0x2038U)
-#define	GPIO_MSKCLRS2		(GPIO_BASE + 0x203CU)
-#define	GPIO_OUTDTSEL2		(GPIO_BASE + 0x2040U)
-#define	GPIO_OUTDTH2		(GPIO_BASE + 0x2044U)
-#define	GPIO_OUTDTL2		(GPIO_BASE + 0x2048U)
-#define	GPIO_BOTHEDGE2		(GPIO_BASE + 0x204CU)
-#define	GPIO_IOINTSEL3		(GPIO_BASE + 0x3000U)
-#define	GPIO_INOUTSEL3		(GPIO_BASE + 0x3004U)
-#define	GPIO_OUTDT3			(GPIO_BASE + 0x3008U)
-#define	GPIO_INDT3			(GPIO_BASE + 0x300CU)
-#define	GPIO_INTDT3			(GPIO_BASE + 0x3010U)
-#define	GPIO_INTCLR3		(GPIO_BASE + 0x3014U)
-#define	GPIO_INTMSK3		(GPIO_BASE + 0x3018U)
-#define	GPIO_MSKCLR3		(GPIO_BASE + 0x301CU)
-#define	GPIO_POSNEG3		(GPIO_BASE + 0x3020U)
-#define	GPIO_EDGLEVEL3		(GPIO_BASE + 0x3024U)
-#define	GPIO_FILONOFF3		(GPIO_BASE + 0x3028U)
-#define	GPIO_INTMSKS3		(GPIO_BASE + 0x3038U)
-#define	GPIO_MSKCLRS3		(GPIO_BASE + 0x303CU)
-#define	GPIO_OUTDTSEL3		(GPIO_BASE + 0x3040U)
-#define	GPIO_OUTDTH3		(GPIO_BASE + 0x3044U)
-#define	GPIO_OUTDTL3		(GPIO_BASE + 0x3048U)
-#define	GPIO_BOTHEDGE3		(GPIO_BASE + 0x304CU)
-#define	GPIO_IOINTSEL4		(GPIO_BASE + 0x4000U)
-#define	GPIO_INOUTSEL4		(GPIO_BASE + 0x4004U)
-#define	GPIO_OUTDT4			(GPIO_BASE + 0x4008U)
-#define	GPIO_INDT4			(GPIO_BASE + 0x400CU)
-#define	GPIO_INTDT4			(GPIO_BASE + 0x4010U)
-#define	GPIO_INTCLR4		(GPIO_BASE + 0x4014U)
-#define	GPIO_INTMSK4		(GPIO_BASE + 0x4018U)
-#define	GPIO_MSKCLR4		(GPIO_BASE + 0x401CU)
-#define	GPIO_POSNEG4		(GPIO_BASE + 0x4020U)
-#define	GPIO_EDGLEVEL4		(GPIO_BASE + 0x4024U)
-#define	GPIO_FILONOFF4		(GPIO_BASE + 0x4028U)
-#define	GPIO_INTMSKS4		(GPIO_BASE + 0x4038U)
-#define	GPIO_MSKCLRS4		(GPIO_BASE + 0x403CU)
-#define	GPIO_OUTDTSEL4		(GPIO_BASE + 0x4040U)
-#define	GPIO_OUTDTH4		(GPIO_BASE + 0x4044U)
-#define	GPIO_OUTDTL4		(GPIO_BASE + 0x4048U)
-#define	GPIO_BOTHEDGE4		(GPIO_BASE + 0x404CU)
-#define	GPIO_IOINTSEL5		(GPIO_BASE + 0x5000U)
-#define	GPIO_INOUTSEL5		(GPIO_BASE + 0x5004U)
-#define	GPIO_OUTDT5			(GPIO_BASE + 0x5008U)
-#define	GPIO_INDT5			(GPIO_BASE + 0x500CU)
-#define	GPIO_INTDT5			(GPIO_BASE + 0x5010U)
-#define	GPIO_INTCLR5		(GPIO_BASE + 0x5014U)
-#define	GPIO_INTMSK5		(GPIO_BASE + 0x5018U)
-#define	GPIO_MSKCLR5		(GPIO_BASE + 0x501CU)
-#define	GPIO_POSNEG5		(GPIO_BASE + 0x5020U)
-#define	GPIO_EDGLEVEL5		(GPIO_BASE + 0x5024U)
-#define	GPIO_FILONOFF5		(GPIO_BASE + 0x5028U)
-#define	GPIO_INTMSKS5		(GPIO_BASE + 0x5038U)
-#define	GPIO_MSKCLRS5		(GPIO_BASE + 0x503CU)
-#define	GPIO_OUTDTSEL5		(GPIO_BASE + 0x5040U)
-#define	GPIO_OUTDTH5		(GPIO_BASE + 0x5044U)
-#define	GPIO_OUTDTL5		(GPIO_BASE + 0x5048U)
-#define	GPIO_BOTHEDGE5		(GPIO_BASE + 0x504CU)
-
-/* Pin functon base address */
-#define	PFC_BASE		(0xE6060000U)
-
-/* Pin functon registers */
-#define	PFC_PMMR		(PFC_BASE + 0x0000U)
-#define PFC_GPSR0		(PFC_BASE + 0x0100U)
-#define PFC_GPSR1		(PFC_BASE + 0x0104U)
-#define PFC_GPSR2		(PFC_BASE + 0x0108U)
-#define PFC_GPSR3		(PFC_BASE + 0x010CU)
-#define PFC_GPSR4		(PFC_BASE + 0x0110U)
-#define	PFC_GPSR5		(PFC_BASE + 0x0114U)
-#define	PFC_IPSR0		(PFC_BASE + 0x0200U)
-#define	PFC_IPSR1		(PFC_BASE + 0x0204U)
-#define	PFC_IPSR2		(PFC_BASE + 0x0208U)
-#define	PFC_IPSR3		(PFC_BASE + 0x020CU)
-#define	PFC_IPSR4		(PFC_BASE + 0x0210U)
-#define	PFC_IPSR5		(PFC_BASE + 0x0214U)
-#define	PFC_IPSR6		(PFC_BASE + 0x0218U)
-#define	PFC_IPSR7		(PFC_BASE + 0x021CU)
-#define	PFC_IPSR8		(PFC_BASE + 0x0220U)
-#define	PFC_IOCTRL30	(PFC_BASE + 0x0380U)
-#define	PFC_IOCTRL31	(PFC_BASE + 0x0384U)
-#define	PFC_IOCTRL32	(PFC_BASE + 0x0388U)
-#define	PFC_IOCTRL40	(PFC_BASE + 0x03C0U)
-#define	PFC_PUEN0		(PFC_BASE + 0x0400U)
-#define	PFC_PUEN1		(PFC_BASE + 0x0404U)
-#define	PFC_PUEN2		(PFC_BASE + 0x0408U)
-#define	PFC_PUEN3		(PFC_BASE + 0x040CU)
-#define	PFC_PUD0		(PFC_BASE + 0x0440U)
-#define	PFC_PUD1		(PFC_BASE + 0x0444U)
-#define	PFC_PUD2		(PFC_BASE + 0x0448U)
-#define	PFC_PUD3		(PFC_BASE + 0x044CU)
-#define	PFC_MOD_SEL0	(PFC_BASE + 0x0500U)
-
-/* Pin functon bit */
-#define GPSR0_DU_EXODDF_DU_ODDF_DISP_CDE			((uint32_t)1U << 21U)
-#define GPSR0_DU_EXVSYNC_DU_VSYNC					((uint32_t)1U << 20U)
-#define GPSR0_DU_EXHSYNC_DU_HSYNC					((uint32_t)1U << 19U)
-#define GPSR0_DU_DOTCLKOUT							((uint32_t)1U << 18U)
-#define GPSR0_DU_DB7								((uint32_t)1U << 17U)
-#define GPSR0_DU_DB6								((uint32_t)1U << 16U)
-#define GPSR0_DU_DB5								((uint32_t)1U << 15U)
-#define GPSR0_DU_DB4								((uint32_t)1U << 14U)
-#define GPSR0_DU_DB3								((uint32_t)1U << 13U)
-#define GPSR0_DU_DB2								((uint32_t)1U << 12U)
-#define GPSR0_DU_DG7								((uint32_t)1U << 11U)
-#define GPSR0_DU_DG6								((uint32_t)1U << 10U)
-#define GPSR0_DU_DG5								((uint32_t)1U << 9U)
-#define GPSR0_DU_DG4								((uint32_t)1U << 8U)
-#define GPSR0_DU_DG3								((uint32_t)1U << 7U)
-#define GPSR0_DU_DG2								((uint32_t)1U << 6U)
-#define GPSR0_DU_DR7								((uint32_t)1U << 5U)
-#define GPSR0_DU_DR6								((uint32_t)1U << 4U)
-#define GPSR0_DU_DR5								((uint32_t)1U << 3U)
-#define GPSR0_DU_DR4								((uint32_t)1U << 2U)
-#define GPSR0_DU_DR3								((uint32_t)1U << 1U)
-#define GPSR0_DU_DR2								((uint32_t)1U << 0U)
-
-#define GPSR1_DIGRF_CLKOUT							((uint32_t)1U << 27U)
-#define GPSR1_DIGRF_CLKIN							((uint32_t)1U << 26U)
-#define GPSR1_CANFD_CLK								((uint32_t)1U << 25U)
-#define GPSR1_CANFD1_RX								((uint32_t)1U << 24U)
-#define GPSR1_CANFD1_TX								((uint32_t)1U << 23U)
-#define GPSR1_CANFD0_RX								((uint32_t)1U << 22U)
-#define GPSR1_CANFD0_TX								((uint32_t)1U << 21U)
-#define GPSR1_AVB0_AVTP_CAPTURE						((uint32_t)1U << 20U)
-#define GPSR1_AVB0_AVTP_MATCH						((uint32_t)1U << 19U)
-#define GPSR1_AVB0_LINK								((uint32_t)1U << 18U)
-#define GPSR1_AVB0_PHY_INT							((uint32_t)1U << 17U)
-#define GPSR1_AVB0_MAGIC							((uint32_t)1U << 16U)
-#define GPSR1_AVB0_MDC								((uint32_t)1U << 15U)
-#define GPSR1_AVB0_MDIO								((uint32_t)1U << 14U)
-#define GPSR1_AVB0_TXCREFCLK						((uint32_t)1U << 13U)
-#define GPSR1_AVB0_TD3								((uint32_t)1U << 12U)
-#define GPSR1_AVB0_TD2								((uint32_t)1U << 11U)
-#define GPSR1_AVB0_TD1								((uint32_t)1U << 10U)
-#define GPSR1_AVB0_TD0								((uint32_t)1U << 9U)
-#define GPSR1_AVB0_TXC								((uint32_t)1U << 8U)
-#define GPSR1_AVB0_TX_CTL							((uint32_t)1U << 7U)
-#define GPSR1_AVB0_RD3								((uint32_t)1U << 6U)
-#define GPSR1_AVB0_RD2								((uint32_t)1U << 5U)
-#define GPSR1_AVB0_RD1								((uint32_t)1U << 4U)
-#define GPSR1_AVB0_RD0								((uint32_t)1U << 3U)
-#define GPSR1_AVB0_RXC								((uint32_t)1U << 2U)
-#define GPSR1_AVB0_RX_CTL							((uint32_t)1U << 1U)
-#define GPSR1_IRQ0									((uint32_t)1U << 0U)
-
-#define GPSR2_VI0_FIELD								((uint32_t)1U << 16U)
-#define GPSR2_VI0_DATA11							((uint32_t)1U << 15U)
-#define GPSR2_VI0_DATA10							((uint32_t)1U << 14U)
-#define GPSR2_VI0_DATA9								((uint32_t)1U << 13U)
-#define GPSR2_VI0_DATA8								((uint32_t)1U << 12U)
-#define GPSR2_VI0_DATA7								((uint32_t)1U << 11U)
-#define GPSR2_VI0_DATA6								((uint32_t)1U << 10U)
-#define GPSR2_VI0_DATA5								((uint32_t)1U << 9U)
-#define GPSR2_VI0_DATA4								((uint32_t)1U << 8U)
-#define GPSR2_VI0_DATA3								((uint32_t)1U << 7U)
-#define GPSR2_VI0_DATA2								((uint32_t)1U << 6U)
-#define GPSR2_VI0_DATA1								((uint32_t)1U << 5U)
-#define GPSR2_VI0_DATA0								((uint32_t)1U << 4U)
-#define GPSR2_VI0_VSYNC_N							((uint32_t)1U << 3U)
-#define GPSR2_VI0_HSYNC_N							((uint32_t)1U << 2U)
-#define GPSR2_VI0_CLKENB							((uint32_t)1U << 1U)
-#define GPSR2_VI0_CLK								((uint32_t)1U << 0U)
-
-#define GPSR3_VI1_FIELD								((uint32_t)1U << 16U)
-#define GPSR3_VI1_DATA11							((uint32_t)1U << 15U)
-#define GPSR3_VI1_DATA10							((uint32_t)1U << 14U)
-#define GPSR3_VI1_DATA9								((uint32_t)1U << 13U)
-#define GPSR3_VI1_DATA8								((uint32_t)1U << 12U)
-#define GPSR3_VI1_DATA7								((uint32_t)1U << 11U)
-#define GPSR3_VI1_DATA6								((uint32_t)1U << 10U)
-#define GPSR3_VI1_DATA5								((uint32_t)1U << 9U)
-#define GPSR3_VI1_DATA4								((uint32_t)1U << 8U)
-#define GPSR3_VI1_DATA3								((uint32_t)1U << 7U)
-#define GPSR3_VI1_DATA2								((uint32_t)1U << 6U)
-#define GPSR3_VI1_DATA1								((uint32_t)1U << 5U)
-#define GPSR3_VI1_DATA0								((uint32_t)1U << 4U)
-#define GPSR3_VI1_VSYNC_N							((uint32_t)1U << 3U)
-#define GPSR3_VI1_HSYNC_N							((uint32_t)1U << 2U)
-#define GPSR3_VI1_CLKENB							((uint32_t)1U << 1U)
-#define GPSR3_VI1_CLK								((uint32_t)1U << 0U)
-
-#define GPSR4_SDA2									((uint32_t)1U << 5U)
-#define GPSR4_SCL2									((uint32_t)1U << 4U)
-#define GPSR4_SDA1									((uint32_t)1U << 3U)
-#define GPSR4_SCL1									((uint32_t)1U << 2U)
-#define GPSR4_SDA0									((uint32_t)1U << 1U)
-#define GPSR4_SCL0									((uint32_t)1U << 0U)
-
-#define GPSR5_RPC_INT_N								((uint32_t)1U << 14U)
-#define GPSR5_RPC_WP_N								((uint32_t)1U << 13U)
-#define GPSR5_RPC_RESET_N							((uint32_t)1U << 12U)
-#define GPSR5_QSPI1_SSL								((uint32_t)1U << 11U)
-#define GPSR5_QSPI1_IO3								((uint32_t)1U << 10U)
-#define GPSR5_QSPI1_IO2								((uint32_t)1U << 9U)
-#define GPSR5_QSPI1_MISO_IO1						((uint32_t)1U << 8U)
-#define GPSR5_QSPI1_MOSI_IO0						((uint32_t)1U << 7U)
-#define GPSR5_QSPI1_SPCLK							((uint32_t)1U << 6U)
-#define GPSR5_QSPI0_SSL								((uint32_t)1U << 5U)
-#define GPSR5_QSPI0_IO3								((uint32_t)1U << 4U)
-#define GPSR5_QSPI0_IO2								((uint32_t)1U << 3U)
-#define GPSR5_QSPI0_MISO_IO1						((uint32_t)1U << 2U)
-#define GPSR5_QSPI0_MOSI_IO0						((uint32_t)1U << 1U)
-#define GPSR5_QSPI0_SPCLK							((uint32_t)1U << 0U)
-
-#define	IPSR_28_FUNC(x)								((uint32_t)(x) << 28U)
-#define	IPSR_24_FUNC(x)								((uint32_t)(x) << 24U)
-#define	IPSR_20_FUNC(x)								((uint32_t)(x) << 20U)
-#define	IPSR_16_FUNC(x)								((uint32_t)(x) << 16U)
-#define	IPSR_12_FUNC(x)								((uint32_t)(x) << 12U)
-#define	IPSR_8_FUNC(x)								((uint32_t)(x) << 8U)
-#define	IPSR_4_FUNC(x)								((uint32_t)(x) << 4U)
-#define	IPSR_0_FUNC(x)								((uint32_t)(x) << 0U)
-
-#define IOCTRL30_POC_VI0_DATA5						((uint32_t)1U << 31U)
-#define IOCTRL30_POC_VI0_DATA4						((uint32_t)1U << 30U)
-#define IOCTRL30_POC_VI0_DATA3						((uint32_t)1U << 29U)
-#define IOCTRL30_POC_VI0_DATA2						((uint32_t)1U << 28U)
-#define IOCTRL30_POC_VI0_DATA1						((uint32_t)1U << 27U)
-#define IOCTRL30_POC_VI0_DATA0						((uint32_t)1U << 26U)
-#define IOCTRL30_POC_VI0_VSYNC_N					((uint32_t)1U << 25U)
-#define IOCTRL30_POC_VI0_HSYNC_N					((uint32_t)1U << 24U)
-#define IOCTRL30_POC_VI0_CLKENB						((uint32_t)1U << 23U)
-#define IOCTRL30_POC_VI0_CLK						((uint32_t)1U << 22U)
-#define IOCTRL30_POC_DU_EXODDF_DU_ODDF_DISP_CDE		((uint32_t)1U << 21U)
-#define IOCTRL30_POC_DU_EXVSYNC_DU_VSYNC			((uint32_t)1U << 20U)
-#define IOCTRL30_POC_DU_EXHSYNC_DU_HSYNC			((uint32_t)1U << 19U)
-#define IOCTRL30_POC_DU_DOTCLKOUT					((uint32_t)1U << 18U)
-#define IOCTRL30_POC_DU_DB7							((uint32_t)1U << 17U)
-#define IOCTRL30_POC_DU_DB6							((uint32_t)1U << 16U)
-#define IOCTRL30_POC_DU_DB5							((uint32_t)1U << 15U)
-#define IOCTRL30_POC_DU_DB4							((uint32_t)1U << 14U)
-#define IOCTRL30_POC_DU_DB3							((uint32_t)1U << 13U)
-#define IOCTRL30_POC_DU_DB2							((uint32_t)1U << 12U)
-#define IOCTRL30_POC_DU_DG7							((uint32_t)1U << 11U)
-#define IOCTRL30_POC_DU_DG6							((uint32_t)1U << 10U)
-#define IOCTRL30_POC_DU_DG5							((uint32_t)1U << 9U)
-#define IOCTRL30_POC_DU_DG4							((uint32_t)1U << 8U)
-#define IOCTRL30_POC_DU_DG3							((uint32_t)1U << 7U)
-#define IOCTRL30_POC_DU_DG2							((uint32_t)1U << 6U)
-#define IOCTRL30_POC_DU_DR7							((uint32_t)1U << 5U)
-#define IOCTRL30_POC_DU_DR6							((uint32_t)1U << 4U)
-#define IOCTRL30_POC_DU_DR5							((uint32_t)1U << 3U)
-#define IOCTRL30_POC_DU_DR4							((uint32_t)1U << 2U)
-#define IOCTRL30_POC_DU_DR3							((uint32_t)1U << 1U)
-#define IOCTRL30_POC_DU_DR2							((uint32_t)1U << 0U)
-
-#define IOCTRL31_POC_DUMMY_31						((uint32_t)1U << 31U)
-#define IOCTRL31_POC_DUMMY_30						((uint32_t)1U << 30U)
-#define IOCTRL31_POC_DUMMY_29						((uint32_t)1U << 29U)
-#define IOCTRL31_POC_DUMMY_28						((uint32_t)1U << 28U)
-#define IOCTRL31_POC_DUMMY_27						((uint32_t)1U << 27U)
-#define IOCTRL31_POC_DUMMY_26						((uint32_t)1U << 26U)
-#define IOCTRL31_POC_DUMMY_25						((uint32_t)1U << 25U)
-#define IOCTRL31_POC_DUMMY_24						((uint32_t)1U << 24U)
-#define IOCTRL31_POC_VI1_FIELD						((uint32_t)1U << 23U)
-#define IOCTRL31_POC_VI1_DATA11						((uint32_t)1U << 22U)
-#define IOCTRL31_POC_VI1_DATA10						((uint32_t)1U << 21U)
-#define IOCTRL31_POC_VI1_DATA9						((uint32_t)1U << 20U)
-#define IOCTRL31_POC_VI1_DATA8						((uint32_t)1U << 19U)
-#define IOCTRL31_POC_VI1_DATA7						((uint32_t)1U << 18U)
-#define IOCTRL31_POC_VI1_DATA6						((uint32_t)1U << 17U)
-#define IOCTRL31_POC_VI1_DATA5						((uint32_t)1U << 16U)
-#define IOCTRL31_POC_VI1_DATA4						((uint32_t)1U << 15U)
-#define IOCTRL31_POC_VI1_DATA3						((uint32_t)1U << 14U)
-#define IOCTRL31_POC_VI1_DATA2						((uint32_t)1U << 13U)
-#define IOCTRL31_POC_VI1_DATA1						((uint32_t)1U << 12U)
-#define IOCTRL31_POC_VI1_DATA0						((uint32_t)1U << 11U)
-#define IOCTRL31_POC_VI1_VSYNC_N					((uint32_t)1U << 10U)
-#define IOCTRL31_POC_VI1_HSYNC_N					((uint32_t)1U << 9U)
-#define IOCTRL31_POC_VI1_CLKENB						((uint32_t)1U << 8U)
-#define IOCTRL31_POC_VI1_CLK						((uint32_t)1U << 7U)
-#define IOCTRL31_POC_VI0_FIELD						((uint32_t)1U << 6U)
-#define IOCTRL31_POC_VI0_DATA11						((uint32_t)1U << 5U)
-#define IOCTRL31_POC_VI0_DATA10						((uint32_t)1U << 4U)
-#define IOCTRL31_POC_VI0_DATA9						((uint32_t)1U << 3U)
-#define IOCTRL31_POC_VI0_DATA8						((uint32_t)1U << 2U)
-#define IOCTRL31_POC_VI0_DATA7						((uint32_t)1U << 1U)
-#define IOCTRL31_POC_VI0_DATA6						((uint32_t)1U << 0U)
-#define IOCTRL32_POC2_VREF							((uint32_t)1U << 0U)
-#define IOCTRL40_SD0TDSEL1							((uint32_t)1U << 1U)
-#define IOCTRL40_SD0TDSEL0							((uint32_t)1U << 0U)
-
-#define PUEN0_PUEN_VI0_CLK							((uint32_t)1U << 31U)
-#define PUEN0_PUEN_TDI								((uint32_t)1U << 30U)
-#define PUEN0_PUEN_TMS								((uint32_t)1U << 29U)
-#define PUEN0_PUEN_TCK								((uint32_t)1U << 28U)
-#define PUEN0_PUEN_TRST_N							((uint32_t)1U << 27U)
-#define PUEN0_PUEN_IRQ0								((uint32_t)1U << 26U)
-#define PUEN0_PUEN_FSCLKST_N						((uint32_t)1U << 25U)
-#define PUEN0_PUEN_EXTALR							((uint32_t)1U << 24U)
-#define PUEN0_PUEN_PRESETOUT_N						((uint32_t)1U << 23U)
-#define PUEN0_PUEN_DU_DOTCLKIN						((uint32_t)1U << 22U)
-#define PUEN0_PUEN_DU_EXODDF_DU_ODDF_DISP_CDE		((uint32_t)1U << 21U)
-#define PUEN0_PUEN_DU_EXVSYNC_DU_VSYNC				((uint32_t)1U << 20U)
-#define PUEN0_PUEN_DU_EXHSYNC_DU_HSYNC				((uint32_t)1U << 19U)
-#define PUEN0_PUEN_DU_DOTCLKOUT						((uint32_t)1U << 18U)
-#define PUEN0_PUEN_DU_DB7							((uint32_t)1U << 17U)
-#define PUEN0_PUEN_DU_DB6							((uint32_t)1U << 16U)
-#define PUEN0_PUEN_DU_DB5							((uint32_t)1U << 15U)
-#define PUEN0_PUEN_DU_DB4							((uint32_t)1U << 14U)
-#define PUEN0_PUEN_DU_DB3							((uint32_t)1U << 13U)
-#define PUEN0_PUEN_DU_DB2							((uint32_t)1U << 12U)
-#define PUEN0_PUEN_DU_DG7							((uint32_t)1U << 11U)
-#define PUEN0_PUEN_DU_DG6							((uint32_t)1U << 10U)
-#define PUEN0_PUEN_DU_DG5							((uint32_t)1U << 9U)
-#define PUEN0_PUEN_DU_DG4							((uint32_t)1U << 8U)
-#define PUEN0_PUEN_DU_DG3							((uint32_t)1U << 7U)
-#define PUEN0_PUEN_DU_DG2							((uint32_t)1U << 6U)
-#define PUEN0_PUEN_DU_DR7							((uint32_t)1U << 5U)
-#define PUEN0_PUEN_DU_DR6							((uint32_t)1U << 4U)
-#define PUEN0_PUEN_DU_DR5							((uint32_t)1U << 3U)
-#define PUEN0_PUEN_DU_DR4							((uint32_t)1U << 2U)
-#define PUEN0_PUEN_DU_DR3							((uint32_t)1U << 1U)
-#define PUEN0_PUEN_DU_DR2							((uint32_t)1U << 0U)
-
-#define PUEN1_PUEN_VI1_DATA11						((uint32_t)1U << 31U)
-#define PUEN1_PUEN_VI1_DATA10						((uint32_t)1U << 30U)
-#define PUEN1_PUEN_VI1_DATA9						((uint32_t)1U << 29U)
-#define PUEN1_PUEN_VI1_DATA8						((uint32_t)1U << 28U)
-#define PUEN1_PUEN_VI1_DATA7						((uint32_t)1U << 27U)
-#define PUEN1_PUEN_VI1_DATA6						((uint32_t)1U << 26U)
-#define PUEN1_PUEN_VI1_DATA5						((uint32_t)1U << 25U)
-#define PUEN1_PUEN_VI1_DATA4						((uint32_t)1U << 24U)
-#define PUEN1_PUEN_VI1_DATA3						((uint32_t)1U << 23U)
-#define PUEN1_PUEN_VI1_DATA2						((uint32_t)1U << 22U)
-#define PUEN1_PUEN_VI1_DATA1						((uint32_t)1U << 21U)
-#define PUEN1_PUEN_VI1_DATA0						((uint32_t)1U << 20U)
-#define PUEN1_PUEN_VI1_VSYNC_N						((uint32_t)1U << 19U)
-#define PUEN1_PUEN_VI1_HSYNC_N						((uint32_t)1U << 18U)
-#define PUEN1_PUEN_VI1_CLKENB						((uint32_t)1U << 17U)
-#define PUEN1_PUEN_VI1_CLK							((uint32_t)1U << 16U)
-#define PUEN1_PUEN_VI0_FIELD						((uint32_t)1U << 15U)
-#define PUEN1_PUEN_VI0_DATA11						((uint32_t)1U << 14U)
-#define PUEN1_PUEN_VI0_DATA10						((uint32_t)1U << 13U)
-#define PUEN1_PUEN_VI0_DATA9						((uint32_t)1U << 12U)
-#define PUEN1_PUEN_VI0_DATA8						((uint32_t)1U << 11U)
-#define PUEN1_PUEN_VI0_DATA7						((uint32_t)1U << 10U)
-#define PUEN1_PUEN_VI0_DATA6						((uint32_t)1U << 9U)
-#define PUEN1_PUEN_VI0_DATA5						((uint32_t)1U << 8U)
-#define PUEN1_PUEN_VI0_DATA4						((uint32_t)1U << 7U)
-#define PUEN1_PUEN_VI0_DATA3						((uint32_t)1U << 6U)
-#define PUEN1_PUEN_VI0_DATA2						((uint32_t)1U << 5U)
-#define PUEN1_PUEN_VI0_DATA1						((uint32_t)1U << 4U)
-#define PUEN1_PUEN_VI0_DATA0						((uint32_t)1U << 3U)
-#define PUEN1_PUEN_VI0_VSYNC_N						((uint32_t)1U << 2U)
-#define PUEN1_PUEN_VI0_HSYNC_N						((uint32_t)1U << 1U)
-#define PUEN1_PUEN_VI0_CLKENB						((uint32_t)1U << 0U)
-
-#define PUEN2_PUEN_CANFD_CLK						((uint32_t)1U << 31U)
-#define PUEN2_PUEN_CANFD1_RX						((uint32_t)1U << 30U)
-#define PUEN2_PUEN_CANFD1_TX						((uint32_t)1U << 29U)
-#define PUEN2_PUEN_CANFD0_RX						((uint32_t)1U << 28U)
-#define PUEN2_PUEN_CANFD0_TX						((uint32_t)1U << 27U)
-#define PUEN2_PUEN_AVB0_AVTP_CAPTURE				((uint32_t)1U << 26U)
-#define PUEN2_PUEN_AVB0_AVTP_MATCH					((uint32_t)1U << 25U)
-#define PUEN2_PUEN_AVB0_LINK						((uint32_t)1U << 24U)
-#define PUEN2_PUEN_AVB0_PHY_INT						((uint32_t)1U << 23U)
-#define PUEN2_PUEN_AVB0_MAGIC						((uint32_t)1U << 22U)
-#define PUEN2_PUEN_AVB0_MDC							((uint32_t)1U << 21U)
-#define PUEN2_PUEN_AVB0_MDIO						((uint32_t)1U << 20U)
-#define PUEN2_PUEN_AVB0_TXCREFCLK					((uint32_t)1U << 19U)
-#define PUEN2_PUEN_AVB0_TD3							((uint32_t)1U << 18U)
-#define PUEN2_PUEN_AVB0_TD2							((uint32_t)1U << 17U)
-#define PUEN2_PUEN_AVB0_TD1							((uint32_t)1U << 16U)
-#define PUEN2_PUEN_AVB0_TD0							((uint32_t)1U << 15U)
-#define PUEN2_PUEN_AVB0_TXC							((uint32_t)1U << 14U)
-#define PUEN2_PUEN_AVB0_TX_CTL						((uint32_t)1U << 13U)
-#define PUEN2_PUEN_AVB0_RD3							((uint32_t)1U << 12U)
-#define PUEN2_PUEN_AVB0_RD2							((uint32_t)1U << 11U)
-#define PUEN2_PUEN_AVB0_RD1							((uint32_t)1U << 10U)
-#define PUEN2_PUEN_AVB0_RD0							((uint32_t)1U << 9U)
-#define PUEN2_PUEN_AVB0_RXC							((uint32_t)1U << 8U)
-#define PUEN2_PUEN_AVB0_RX_CTL						((uint32_t)1U << 7U)
-#define PUEN2_PUEN_SDA2								((uint32_t)1U << 6U)
-#define PUEN2_PUEN_SCL2								((uint32_t)1U << 5U)
-#define PUEN2_PUEN_SDA1								((uint32_t)1U << 4U)
-#define PUEN2_PUEN_SCL1								((uint32_t)1U << 3U)
-#define PUEN2_PUEN_SDA0								((uint32_t)1U << 2U)
-#define PUEN2_PUEN_SCL0								((uint32_t)1U << 1U)
-#define PUEN2_PUEN_VI1_FIELD						((uint32_t)1U << 0U)
-
-#define PUEN3_PUEN_DIGRF_CLKOUT						((uint32_t)1U << 16U)
-#define PUEN3_PUEN_DIGRF_CLKIN						((uint32_t)1U << 15U)
-#define PUEN3_PUEN_RPC_INT_N						((uint32_t)1U << 14U)
-#define PUEN3_PUEN_RPC_WP_N							((uint32_t)1U << 13U)
-#define PUEN3_PUEN_RPC_RESET_N						((uint32_t)1U << 12U)
-#define PUEN3_PUEN_QSPI1_SSL						((uint32_t)1U << 11U)
-#define PUEN3_PUEN_QSPI1_IO3						((uint32_t)1U << 10U)
-#define PUEN3_PUEN_QSPI1_IO2						((uint32_t)1U << 9U)
-#define PUEN3_PUEN_QSPI1_MISO_IO1					((uint32_t)1U << 8U)
-#define PUEN3_PUEN_QSPI1_MOSI_IO0					((uint32_t)1U << 7U)
-#define PUEN3_PUEN_QSPI1_SPCLK						((uint32_t)1U << 6U)
-#define PUEN3_PUEN_QSPI0_SSL						((uint32_t)1U << 5U)
-#define PUEN3_PUEN_QSPI0_IO3						((uint32_t)1U << 4U)
-#define PUEN3_PUEN_QSPI0_IO2						((uint32_t)1U << 3U)
-#define PUEN3_PUEN_QSPI0_MISO_IO1					((uint32_t)1U << 2U)
-#define PUEN3_PUEN_QSPI0_MOSI_IO0					((uint32_t)1U << 1U)
-#define PUEN3_PUEN_QSPI0_SPCLK						((uint32_t)1U << 0U)
-
-#define PUD0_PUD_VI0_CLK							((uint32_t)1U << 31U)
-#define PUD0_PUD_IRQ0								((uint32_t)1U << 26U)
-#define PUD0_PUD_FSCLKST_N							((uint32_t)1U << 25U)
-#define PUD0_PUD_PRESETOUT_N						((uint32_t)1U << 23U)
-#define PUD0_PUD_DU_EXODDF_DU_ODDF_DISP_CDE			((uint32_t)1U << 21U)
-#define PUD0_PUD_DU_EXVSYNC_DU_VSYNC				((uint32_t)1U << 20U)
-#define PUD0_PUD_DU_EXHSYNC_DU_HSYNC				((uint32_t)1U << 19U)
-#define PUD0_PUD_DU_DOTCLKOUT						((uint32_t)1U << 18U)
-#define PUD0_PUD_DU_DB7								((uint32_t)1U << 17U)
-#define PUD0_PUD_DU_DB6								((uint32_t)1U << 16U)
-#define PUD0_PUD_DU_DB5								((uint32_t)1U << 15U)
-#define PUD0_PUD_DU_DB4								((uint32_t)1U << 14U)
-#define PUD0_PUD_DU_DB3								((uint32_t)1U << 13U)
-#define PUD0_PUD_DU_DB2								((uint32_t)1U << 12U)
-#define PUD0_PUD_DU_DG7								((uint32_t)1U << 11U)
-#define PUD0_PUD_DU_DG6								((uint32_t)1U << 10U)
-#define PUD0_PUD_DU_DG5								((uint32_t)1U << 9U)
-#define PUD0_PUD_DU_DG4								((uint32_t)1U << 8U)
-#define PUD0_PUD_DU_DG3								((uint32_t)1U << 7U)
-#define PUD0_PUD_DU_DG2								((uint32_t)1U << 6U)
-#define PUD0_PUD_DU_DR7								((uint32_t)1U << 5U)
-#define PUD0_PUD_DU_DR6								((uint32_t)1U << 4U)
-#define PUD0_PUD_DU_DR5								((uint32_t)1U << 3U)
-#define PUD0_PUD_DU_DR4								((uint32_t)1U << 2U)
-#define PUD0_PUD_DU_DR3								((uint32_t)1U << 1U)
-#define PUD0_PUD_DU_DR2								((uint32_t)1U << 0U)
-
-#define PUD1_PUD_VI1_DATA11							((uint32_t)1U << 31U)
-#define PUD1_PUD_VI1_DATA10							((uint32_t)1U << 30U)
-#define PUD1_PUD_VI1_DATA9 							((uint32_t)1U << 29U)
-#define PUD1_PUD_VI1_DATA8 							((uint32_t)1U << 28U)
-#define PUD1_PUD_VI1_DATA7 							((uint32_t)1U << 27U)
-#define PUD1_PUD_VI1_DATA6 							((uint32_t)1U << 26U)
-#define PUD1_PUD_VI1_DATA5 							((uint32_t)1U << 25U)
-#define PUD1_PUD_VI1_DATA4 							((uint32_t)1U << 24U)
-#define PUD1_PUD_VI1_DATA3 							((uint32_t)1U << 23U)
-#define PUD1_PUD_VI1_DATA2 							((uint32_t)1U << 22U)
-#define PUD1_PUD_VI1_DATA1 							((uint32_t)1U << 21U)
-#define PUD1_PUD_VI1_DATA0 							((uint32_t)1U << 20U)
-#define PUD1_PUD_VI1_VSYNC_N						((uint32_t)1U << 19U)
-#define PUD1_PUD_VI1_HSYNC_N						((uint32_t)1U << 18U)
-#define PUD1_PUD_VI1_CLKENB							((uint32_t)1U << 17U)
-#define PUD1_PUD_VI1_CLK							((uint32_t)1U << 16U)
-#define PUD1_PUD_VI0_FIELD 							((uint32_t)1U << 15U)
-#define PUD1_PUD_VI0_DATA11							((uint32_t)1U << 14U)
-#define PUD1_PUD_VI0_DATA10							((uint32_t)1U << 13U)
-#define PUD1_PUD_VI0_DATA9 							((uint32_t)1U << 12U)
-#define PUD1_PUD_VI0_DATA8 							((uint32_t)1U << 11U)
-#define PUD1_PUD_VI0_DATA7 							((uint32_t)1U << 10U)
-#define PUD1_PUD_VI0_DATA6 							((uint32_t)1U << 9U)
-#define PUD1_PUD_VI0_DATA5 							((uint32_t)1U << 8U)
-#define PUD1_PUD_VI0_DATA4 							((uint32_t)1U << 7U)
-#define PUD1_PUD_VI0_DATA3 							((uint32_t)1U << 6U)
-#define PUD1_PUD_VI0_DATA2 							((uint32_t)1U << 5U)
-#define PUD1_PUD_VI0_DATA1 							((uint32_t)1U << 4U)
-#define PUD1_PUD_VI0_DATA0 							((uint32_t)1U << 3U)
-#define PUD1_PUD_VI0_VSYNC_N						((uint32_t)1U << 2U)
-#define PUD1_PUD_VI0_HSYNC_N						((uint32_t)1U << 1U)
-#define PUD1_PUD_VI0_CLKENB							((uint32_t)1U << 0U)
-
-#define PUD2_PUD_CANFD_CLK							((uint32_t)1U << 31U)
-#define PUD2_PUD_CANFD1_RX							((uint32_t)1U << 30U)
-#define PUD2_PUD_CANFD1_TX							((uint32_t)1U << 29U)
-#define PUD2_PUD_CANFD0_RX							((uint32_t)1U << 28U)
-#define PUD2_PUD_CANFD0_TX							((uint32_t)1U << 27U)
-#define PUD2_PUD_AVB0_AVTP_CAPTURE					((uint32_t)1U << 26U)
-#define PUD2_PUD_AVB0_AVTP_MATCH					((uint32_t)1U << 25U)
-#define PUD2_PUD_AVB0_LINK							((uint32_t)1U << 24U)
-#define PUD2_PUD_AVB0_PHY_INT						((uint32_t)1U << 23U)
-#define PUD2_PUD_AVB0_MAGIC							((uint32_t)1U << 22U)
-#define PUD2_PUD_AVB0_MDC							((uint32_t)1U << 21U)
-#define PUD2_PUD_AVB0_MDIO							((uint32_t)1U << 20U)
-#define PUD2_PUD_AVB0_TXCREFCLK						((uint32_t)1U << 19U)
-#define PUD2_PUD_AVB0_TD3							((uint32_t)1U << 18U)
-#define PUD2_PUD_AVB0_TD2							((uint32_t)1U << 17U)
-#define PUD2_PUD_AVB0_TD1							((uint32_t)1U << 16U)
-#define PUD2_PUD_AVB0_TD0							((uint32_t)1U << 15U)
-#define PUD2_PUD_AVB0_TXC							((uint32_t)1U << 14U)
-#define PUD2_PUD_AVB0_TX_CTL						((uint32_t)1U << 13U)
-#define PUD2_PUD_AVB0_RD3							((uint32_t)1U << 12U)
-#define PUD2_PUD_AVB0_RD2							((uint32_t)1U << 11U)
-#define PUD2_PUD_AVB0_RD1							((uint32_t)1U << 10U)
-#define PUD2_PUD_AVB0_RD0							((uint32_t)1U << 9U)
-#define PUD2_PUD_AVB0_RXC							((uint32_t)1U << 8U)
-#define PUD2_PUD_AVB0_RX_CTL						((uint32_t)1U << 7U)
-#define PUD2_PUD_SDA2								((uint32_t)1U << 6U)
-#define PUD2_PUD_SCL2								((uint32_t)1U << 5U)
-#define PUD2_PUD_SDA1								((uint32_t)1U << 4U)
-#define PUD2_PUD_SCL1								((uint32_t)1U << 3U)
-#define PUD2_PUD_SDA0								((uint32_t)1U << 2U)
-#define PUD2_PUD_SCL0								((uint32_t)1U << 1U)
-#define PUD2_PUD_VI1_FIELD							((uint32_t)1U << 0U)
-
-#define PUD3_PUD_DIGRF_CLKOUT						((uint32_t)1U << 16U)
-#define PUD3_PUD_DIGRF_CLKIN						((uint32_t)1U << 15U)
-#define PUD3_PUD_RPC_INT_N							((uint32_t)1U << 14U)
-#define PUD3_PUD_RPC_WP_N							((uint32_t)1U << 13U)
-#define PUD3_PUD_RPC_RESET_N						((uint32_t)1U << 12U)
-#define PUD3_PUD_QSPI1_SSL							((uint32_t)1U << 11U)
-#define PUD3_PUD_QSPI1_IO3							((uint32_t)1U << 10U)
-#define PUD3_PUD_QSPI1_IO2							((uint32_t)1U << 9U)
-#define PUD3_PUD_QSPI1_MISO_IO1						((uint32_t)1U << 8U)
-#define PUD3_PUD_QSPI1_MOSI_IO0						((uint32_t)1U << 7U)
-#define PUD3_PUD_QSPI1_SPCLK						((uint32_t)1U << 6U)
-#define PUD3_PUD_QSPI0_SSL							((uint32_t)1U << 5U)
-#define PUD3_PUD_QSPI0_IO3							((uint32_t)1U << 4U)
-#define PUD3_PUD_QSPI0_IO2							((uint32_t)1U << 3U)
-#define PUD3_PUD_QSPI0_MISO_IO1						((uint32_t)1U << 2U)
-#define PUD3_PUD_QSPI0_MOSI_IO0						((uint32_t)1U << 1U)
-#define PUD3_PUD_QSPI0_SPCLK						((uint32_t)1U << 0U)
-
-#define MOD_SEL0_sel_hscif0							((uint32_t)1U << 10U)
-#define MOD_SEL0_sel_scif1							((uint32_t)1U << 9U)
-#define MOD_SEL0_sel_canfd0							((uint32_t)1U << 8U)
-#define MOD_SEL0_sel_pwm4							((uint32_t)1U << 7U)
-#define MOD_SEL0_sel_pwm3							((uint32_t)1U << 6U)
-#define MOD_SEL0_sel_pwm2							((uint32_t)1U << 5U)
-#define MOD_SEL0_sel_pwm1							((uint32_t)1U << 4U)
-#define MOD_SEL0_sel_pwm0							((uint32_t)1U << 3U)
-#define MOD_SEL0_sel_rfso							((uint32_t)1U << 2U)
-#define MOD_SEL0_sel_rsp							((uint32_t)1U << 1U)
-#define MOD_SEL0_sel_tmu							((uint32_t)1U << 0U)
-
-/* SCIF3 Registers for Dummy write */
-#define SCIF3_BASE		(0xE6C50000U)
-#define SCIF3_SCFCR		(SCIF3_BASE + 0x0018U)
-#define SCIF3_SCFDR		(SCIF3_BASE + 0x001CU)
-#define SCFCR_DATA		(0x0000U)
-
-/* Realtime module stop control */
-#define	CPG_BASE		(0xE6150000U)
-#define CPG_MSTPSR0		(CPG_BASE + 0x0030U)
-#define CPG_RMSTPCR0		(CPG_BASE + 0x0110U)
-#define RMSTPCR0_RTDMAC		(0x00200000U)
-
-/* RT-DMAC Registers */
-#define RTDMAC_CH		(0U)		/* choose 0 to 15 */
-
-#define RTDMAC_BASE		(0xFFC10000U)
-#define RTDMAC_RDMOR		(RTDMAC_BASE + 0x0060U)
-#define RTDMAC_RDMCHCLR		(RTDMAC_BASE + 0x0080U)
-#define RTDMAC_RDMSAR(x)	(RTDMAC_BASE + 0x8000U + (0x80U * (x)))
-#define RTDMAC_RDMDAR(x)	(RTDMAC_BASE + 0x8004U + (0x80U * (x)))
-#define RTDMAC_RDMTCR(x)	(RTDMAC_BASE + 0x8008U + (0x80U * (x)))
-#define RTDMAC_RDMCHCR(x)	(RTDMAC_BASE + 0x800CU + (0x80U * (x)))
-#define RTDMAC_RDMCHCRB(x)	(RTDMAC_BASE + 0x801CU + (0x80U * (x)))
-#define RTDMAC_RDMDPBASE(x)	(RTDMAC_BASE + 0x8050U + (0x80U * (x)))
-#define RTDMAC_DESC_BASE	(RTDMAC_BASE + 0xA000U)
-#define RTDMAC_DESC_RDMSAR	(RTDMAC_DESC_BASE + 0x0000U)
-#define RTDMAC_DESC_RDMDAR	(RTDMAC_DESC_BASE + 0x0004U)
-#define RTDMAC_DESC_RDMTCR	(RTDMAC_DESC_BASE + 0x0008U)
-
-#define RDMOR_DME		(0x0001U)	/* DMA Master Enable */
-#define RDMCHCR_DPM_INFINITE	(0x30000000U)	/* Infinite repeat mode */
-#define RDMCHCR_RPT_TCR		(0x02000000U)	/* enable to update TCR */
-#define RDMCHCR_TS_2		(0x00000008U)	/* Word(2byte) units transfer */
-#define RDMCHCR_RS_AUTO		(0x00000400U)	/* Auto request */
-#define RDMCHCR_DE		(0x00000001U)	/* DMA Enable */
-#define RDMCHCRB_DRST		(0x00008000U)	/* Descriptor reset */
-#define RDMCHCRB_SLM_256	(0x00000080U)	/* once in 256 clock cycle */
-#define RDMDPBASE_SEL_EXT	(0x00000001U)	/* External memory use */
-
-static void pfc_reg_write(uint32_t addr, uint32_t data);
-static void StartRtDma0_Descriptor(void);
-
-static void pfc_reg_write(uint32_t addr, uint32_t data)
-{
-	mmio_write_32(PFC_PMMR, ~data);
-	mmio_write_32((uintptr_t)addr, data);
-}
-
-static void StartRtDma0_Descriptor(void)
-{
-	uint32_t reg;
-
-	/* Module stop clear */
-	while((mmio_read_32(CPG_MSTPSR0) & RMSTPCR0_RTDMAC) != 0U) {
-		reg = mmio_read_32(CPG_RMSTPCR0);
-		reg &= ~RMSTPCR0_RTDMAC;
-		cpg_write(CPG_RMSTPCR0, reg);
-	}
-
-	/* Initialize ch0, Reset Descriptor */
-	mmio_write_32(RTDMAC_RDMCHCLR, ((uint32_t)1U << RTDMAC_CH));
-	mmio_write_32(RTDMAC_RDMCHCRB(RTDMAC_CH), RDMCHCRB_DRST);
-
-	/* Enable DMA */
-	mmio_write_16(RTDMAC_RDMOR, RDMOR_DME);
-
-	/* Set first transfer */
-	mmio_write_32(RTDMAC_RDMSAR(RTDMAC_CH), RCAR_PRR);
-	mmio_write_32(RTDMAC_RDMDAR(RTDMAC_CH), SCIF3_SCFDR);
-	mmio_write_32(RTDMAC_RDMTCR(RTDMAC_CH), 0x00000001U);
-
-	/* Set descriptor */
-	mmio_write_32(RTDMAC_DESC_RDMSAR, 0x00000000U);
-	mmio_write_32(RTDMAC_DESC_RDMDAR, 0x00000000U);
-	mmio_write_32(RTDMAC_DESC_RDMTCR, 0x00200000U);
-	mmio_write_32(RTDMAC_RDMCHCRB(RTDMAC_CH), RDMCHCRB_SLM_256);
-	mmio_write_32(RTDMAC_RDMDPBASE(RTDMAC_CH), RTDMAC_DESC_BASE
-						 | RDMDPBASE_SEL_EXT);
-
-	/* Set transfer parameter, Start transfer */
-	mmio_write_32(RTDMAC_RDMCHCR(RTDMAC_CH), RDMCHCR_DPM_INFINITE
-					       | RDMCHCR_RPT_TCR
-					       | RDMCHCR_TS_2
-					       | RDMCHCR_RS_AUTO
-					       | RDMCHCR_DE);
-}
-
-void pfc_init_v3m(void)
-{
-	/* Work around for PFC eratta */
-	StartRtDma0_Descriptor();
-
-	// pin function
-	// md[4:1]!=0000
-	/* initialize GPIO/perihperal function select */
-
-	pfc_reg_write(PFC_GPSR0, 0x00000000);
-
-	pfc_reg_write(PFC_GPSR1, GPSR1_CANFD_CLK);
-
-	pfc_reg_write(PFC_GPSR2, 0x00000000);
-
-	pfc_reg_write(PFC_GPSR3, 0x00000000);
-
-	pfc_reg_write(PFC_GPSR4, GPSR4_SDA2
-				   | GPSR4_SCL2);
-
-	pfc_reg_write(PFC_GPSR5, GPSR5_QSPI1_SSL
-				   | GPSR5_QSPI1_IO3
-				   | GPSR5_QSPI1_IO2
-				   | GPSR5_QSPI1_MISO_IO1
-				   | GPSR5_QSPI1_MOSI_IO0
-				   | GPSR5_QSPI1_SPCLK
-				   | GPSR5_QSPI0_SSL
-				   | GPSR5_QSPI0_IO3
-				   | GPSR5_QSPI0_IO2
-				   | GPSR5_QSPI0_MISO_IO1
-				   | GPSR5_QSPI0_MOSI_IO0
-				   | GPSR5_QSPI0_SPCLK);
-
-
-	/* initialize peripheral function select */
-	pfc_reg_write(PFC_IPSR0, IPSR_28_FUNC(0)
-				   | IPSR_24_FUNC(0)
-				   | IPSR_20_FUNC(0)
-				   | IPSR_16_FUNC(0)
-				   | IPSR_12_FUNC(0)
-				   | IPSR_8_FUNC(0)
-				   | IPSR_4_FUNC(0)
-				   | IPSR_0_FUNC(0));
-
-	pfc_reg_write(PFC_IPSR1, IPSR_28_FUNC(0)
-				   | IPSR_24_FUNC(0)
-				   | IPSR_20_FUNC(0)
-				   | IPSR_16_FUNC(0)
-				   | IPSR_12_FUNC(0)
-				   | IPSR_8_FUNC(0)
-				   | IPSR_4_FUNC(0)
-				   | IPSR_0_FUNC(0));
-
-	pfc_reg_write(PFC_IPSR2, IPSR_28_FUNC(0)
-				   | IPSR_24_FUNC(0)
-				   | IPSR_20_FUNC(0)
-				   | IPSR_16_FUNC(0)
-				   | IPSR_12_FUNC(0)
-				   | IPSR_8_FUNC(0)
-				   | IPSR_4_FUNC(0)
-				   | IPSR_0_FUNC(0));
-
-	pfc_reg_write(PFC_IPSR3, IPSR_28_FUNC(0)
-				   | IPSR_24_FUNC(0)
-				   | IPSR_20_FUNC(0)
-				   | IPSR_16_FUNC(0)
-				   | IPSR_12_FUNC(0)
-				   | IPSR_8_FUNC(0)
-				   | IPSR_4_FUNC(0)
-				   | IPSR_0_FUNC(0));
-
-	pfc_reg_write(PFC_IPSR4, IPSR_28_FUNC(0)
-				   | IPSR_24_FUNC(0)
-				   | IPSR_20_FUNC(0)
-				   | IPSR_16_FUNC(0)
-				   | IPSR_12_FUNC(0)
-				   | IPSR_8_FUNC(0)
-				   | IPSR_4_FUNC(0)
-				   | IPSR_0_FUNC(0));
-
-	pfc_reg_write(PFC_IPSR5, IPSR_28_FUNC(0)
-				   | IPSR_24_FUNC(0)
-				   | IPSR_20_FUNC(0)
-				   | IPSR_16_FUNC(0)
-				   | IPSR_12_FUNC(0)
-				   | IPSR_8_FUNC(0)
-				   | IPSR_4_FUNC(0)
-				   | IPSR_0_FUNC(0));
-
-	pfc_reg_write(PFC_IPSR6, IPSR_28_FUNC(0)
-				   | IPSR_24_FUNC(0)
-				   | IPSR_20_FUNC(0)
-				   | IPSR_16_FUNC(0)
-				   | IPSR_12_FUNC(0)
-				   | IPSR_8_FUNC(0)
-				   | IPSR_4_FUNC(0)
-				   | IPSR_0_FUNC(0));
-
-	pfc_reg_write(PFC_IPSR7, IPSR_28_FUNC(0)
-				   | IPSR_24_FUNC(4)
-				   | IPSR_20_FUNC(4)
-				   | IPSR_16_FUNC(4)
-				   | IPSR_12_FUNC(4)
-				   | IPSR_8_FUNC(0)
-				   | IPSR_4_FUNC(0)
-				   | IPSR_0_FUNC(0));
-
-	pfc_reg_write(PFC_IPSR8, IPSR_28_FUNC(0)
-				   | IPSR_24_FUNC(0)
-				   | IPSR_20_FUNC(0)
-				   | IPSR_16_FUNC(4)
-				   | IPSR_12_FUNC(0)
-				   | IPSR_8_FUNC(0)
-				   | IPSR_4_FUNC(0)
-				   | IPSR_0_FUNC(0));
-
-	/* initialize POC Control */
-
-	pfc_reg_write(PFC_IOCTRL30, IOCTRL30_POC_VI0_DATA5
-				   | IOCTRL30_POC_VI0_DATA4
-				   | IOCTRL30_POC_VI0_DATA3
-				   | IOCTRL30_POC_VI0_DATA2
-				   | IOCTRL30_POC_VI0_DATA1
-				   | IOCTRL30_POC_VI0_DATA0
-				   | IOCTRL30_POC_VI0_VSYNC_N
-				   | IOCTRL30_POC_VI0_HSYNC_N
-				   | IOCTRL30_POC_VI0_CLKENB
-				   | IOCTRL30_POC_VI0_CLK
-				   | IOCTRL30_POC_DU_EXODDF_DU_ODDF_DISP_CDE
-				   | IOCTRL30_POC_DU_EXVSYNC_DU_VSYNC
-				   | IOCTRL30_POC_DU_EXHSYNC_DU_HSYNC
-				   | IOCTRL30_POC_DU_DOTCLKOUT
-				   | IOCTRL30_POC_DU_DB7
-				   | IOCTRL30_POC_DU_DB6
-				   | IOCTRL30_POC_DU_DB5
-				   | IOCTRL30_POC_DU_DB4
-				   | IOCTRL30_POC_DU_DB3
-				   | IOCTRL30_POC_DU_DB2
-				   | IOCTRL30_POC_DU_DG7
-				   | IOCTRL30_POC_DU_DG6
-				   | IOCTRL30_POC_DU_DG5
-				   | IOCTRL30_POC_DU_DG4
-				   | IOCTRL30_POC_DU_DG3
-				   | IOCTRL30_POC_DU_DG2
-				   | IOCTRL30_POC_DU_DR7
-				   | IOCTRL30_POC_DU_DR6
-				   | IOCTRL30_POC_DU_DR5
-				   | IOCTRL30_POC_DU_DR4
-				   | IOCTRL30_POC_DU_DR3
-				   | IOCTRL30_POC_DU_DR2);
-
-	pfc_reg_write(PFC_IOCTRL31, IOCTRL31_POC_DUMMY_31
-				   | IOCTRL31_POC_DUMMY_30
-				   | IOCTRL31_POC_DUMMY_29
-				   | IOCTRL31_POC_DUMMY_28
-				   | IOCTRL31_POC_DUMMY_27
-				   | IOCTRL31_POC_DUMMY_26
-				   | IOCTRL31_POC_DUMMY_25
-				   | IOCTRL31_POC_DUMMY_24
-				   | IOCTRL31_POC_VI1_FIELD
-				   | IOCTRL31_POC_VI1_DATA11
-				   | IOCTRL31_POC_VI1_DATA10
-				   | IOCTRL31_POC_VI1_DATA9
-				   | IOCTRL31_POC_VI1_DATA8
-				   | IOCTRL31_POC_VI1_DATA7
-				   | IOCTRL31_POC_VI1_DATA6
-				   | IOCTRL31_POC_VI1_DATA5
-				   | IOCTRL31_POC_VI1_DATA4
-				   | IOCTRL31_POC_VI1_DATA3
-				   | IOCTRL31_POC_VI1_DATA2
-				   | IOCTRL31_POC_VI1_DATA1
-				   | IOCTRL31_POC_VI1_DATA0
-				   | IOCTRL31_POC_VI1_VSYNC_N
-				   | IOCTRL31_POC_VI1_HSYNC_N
-				   | IOCTRL31_POC_VI1_CLKENB
-				   | IOCTRL31_POC_VI1_CLK
-				   | IOCTRL31_POC_VI0_FIELD
-				   | IOCTRL31_POC_VI0_DATA11
-				   | IOCTRL31_POC_VI0_DATA10
-				   | IOCTRL31_POC_VI0_DATA9
-				   | IOCTRL31_POC_VI0_DATA8
-				   | IOCTRL31_POC_VI0_DATA7
-				   | IOCTRL31_POC_VI0_DATA6);
-
-	pfc_reg_write(PFC_IOCTRL32,0x00000000);
-
-	pfc_reg_write(PFC_IOCTRL40,0x00000000);
-
-	/* initialize Pull enable */
-	pfc_reg_write(PFC_PUEN0,PUEN0_PUEN_VI0_CLK
-				   | PUEN0_PUEN_TDI
-				   | PUEN0_PUEN_TMS
-				   | PUEN0_PUEN_TCK
-				   | PUEN0_PUEN_TRST_N
-				   | PUEN0_PUEN_IRQ0
-				   | PUEN0_PUEN_FSCLKST_N
-				   | PUEN0_PUEN_DU_EXHSYNC_DU_HSYNC
-				   | PUEN0_PUEN_DU_DOTCLKOUT
-				   | PUEN0_PUEN_DU_DB7
-				   | PUEN0_PUEN_DU_DB6
-				   | PUEN0_PUEN_DU_DB5
-				   | PUEN0_PUEN_DU_DB4
-				   | PUEN0_PUEN_DU_DB3
-				   | PUEN0_PUEN_DU_DB2
-				   | PUEN0_PUEN_DU_DG7
-				   | PUEN0_PUEN_DU_DG6
-				   | PUEN0_PUEN_DU_DG5
-				   | PUEN0_PUEN_DU_DG4
-				   | PUEN0_PUEN_DU_DG3
-				   | PUEN0_PUEN_DU_DG2
-				   | PUEN0_PUEN_DU_DR7
-				   | PUEN0_PUEN_DU_DR6
-				   | PUEN0_PUEN_DU_DR5
-				   | PUEN0_PUEN_DU_DR4
-				   | PUEN0_PUEN_DU_DR3
-				   | PUEN0_PUEN_DU_DR2);
-
-	pfc_reg_write(PFC_PUEN1,PUEN1_PUEN_VI1_DATA11
-				   | PUEN1_PUEN_VI1_DATA10
-				   | PUEN1_PUEN_VI1_DATA9
-				   | PUEN1_PUEN_VI1_DATA8
-				   | PUEN1_PUEN_VI1_DATA7
-				   | PUEN1_PUEN_VI1_DATA6
-				   | PUEN1_PUEN_VI1_DATA5
-				   | PUEN1_PUEN_VI1_DATA4
-				   | PUEN1_PUEN_VI1_DATA3
-				   | PUEN1_PUEN_VI1_DATA2
-				   | PUEN1_PUEN_VI1_DATA1
-				   | PUEN1_PUEN_VI1_DATA0
-				   | PUEN1_PUEN_VI1_VSYNC_N
-				   | PUEN1_PUEN_VI1_HSYNC_N
-				   | PUEN1_PUEN_VI1_CLKENB
-				   | PUEN1_PUEN_VI1_CLK
-				   | PUEN1_PUEN_VI0_DATA11
-				   | PUEN1_PUEN_VI0_DATA10
-				   | PUEN1_PUEN_VI0_DATA9
-				   | PUEN1_PUEN_VI0_DATA8
-				   | PUEN1_PUEN_VI0_DATA7
-				   | PUEN1_PUEN_VI0_DATA6
-				   | PUEN1_PUEN_VI0_DATA5
-				   | PUEN1_PUEN_VI0_DATA4
-				   | PUEN1_PUEN_VI0_DATA3
-				   | PUEN1_PUEN_VI0_DATA2
-				   | PUEN1_PUEN_VI0_DATA1);
-
-	pfc_reg_write(PFC_PUEN2,PUEN2_PUEN_CANFD_CLK
-				   | PUEN2_PUEN_CANFD1_RX
-				   | PUEN2_PUEN_CANFD1_TX
-				   | PUEN2_PUEN_CANFD0_RX
-				   | PUEN2_PUEN_CANFD0_TX
-				   | PUEN2_PUEN_AVB0_AVTP_CAPTURE
-				   | PUEN2_PUEN_AVB0_AVTP_MATCH
-				   | PUEN2_PUEN_AVB0_LINK
-				   | PUEN2_PUEN_AVB0_PHY_INT
-				   | PUEN2_PUEN_AVB0_MAGIC
-				   | PUEN2_PUEN_AVB0_TXCREFCLK
-				   | PUEN2_PUEN_AVB0_TD3
-				   | PUEN2_PUEN_AVB0_TD2
-				   | PUEN2_PUEN_AVB0_TD1
-				   | PUEN2_PUEN_AVB0_TD0
-				   | PUEN2_PUEN_AVB0_TXC
-				   | PUEN2_PUEN_AVB0_TX_CTL
-				   | PUEN2_PUEN_AVB0_RD3
-				   | PUEN2_PUEN_AVB0_RD2
-				   | PUEN2_PUEN_AVB0_RD1
-				   | PUEN2_PUEN_AVB0_RD0
-				   | PUEN2_PUEN_AVB0_RXC
-				   | PUEN2_PUEN_AVB0_RX_CTL
-				   | PUEN2_PUEN_VI1_FIELD);
-
-	pfc_reg_write(PFC_PUEN3,PUEN3_PUEN_DIGRF_CLKOUT
-				   | PUEN3_PUEN_DIGRF_CLKIN);
-
-	/* initialize PUD Control */
-	pfc_reg_write(PFC_PUD0,PUD0_PUD_VI0_CLK
-				   | PUD0_PUD_IRQ0
-				   | PUD0_PUD_FSCLKST_N
-				   | PUD0_PUD_DU_EXODDF_DU_ODDF_DISP_CDE
-				   | PUD0_PUD_DU_EXVSYNC_DU_VSYNC
-				   | PUD0_PUD_DU_EXHSYNC_DU_HSYNC
-				   | PUD0_PUD_DU_DOTCLKOUT
-				   | PUD0_PUD_DU_DB7
-				   | PUD0_PUD_DU_DB6
-				   | PUD0_PUD_DU_DB5
-				   | PUD0_PUD_DU_DB4
-				   | PUD0_PUD_DU_DB3
-				   | PUD0_PUD_DU_DB2
-				   | PUD0_PUD_DU_DG7
-				   | PUD0_PUD_DU_DG6
-				   | PUD0_PUD_DU_DG5
-				   | PUD0_PUD_DU_DG4
-				   | PUD0_PUD_DU_DG3
-				   | PUD0_PUD_DU_DG2
-				   | PUD0_PUD_DU_DR7
-				   | PUD0_PUD_DU_DR6
-				   | PUD0_PUD_DU_DR5
-				   | PUD0_PUD_DU_DR4
-				   | PUD0_PUD_DU_DR3
-				   | PUD0_PUD_DU_DR2);
-
-	pfc_reg_write(PFC_PUD1,PUD1_PUD_VI1_DATA11
-				   | PUD1_PUD_VI1_DATA10
-				   | PUD1_PUD_VI1_DATA9
-				   | PUD1_PUD_VI1_DATA8
-				   | PUD1_PUD_VI1_DATA7
-				   | PUD1_PUD_VI1_DATA6
-				   | PUD1_PUD_VI1_DATA5
-				   | PUD1_PUD_VI1_DATA4
-				   | PUD1_PUD_VI1_DATA3
-				   | PUD1_PUD_VI1_DATA2
-				   | PUD1_PUD_VI1_DATA1
-				   | PUD1_PUD_VI1_DATA0
-				   | PUD1_PUD_VI1_VSYNC_N
-				   | PUD1_PUD_VI1_HSYNC_N
-				   | PUD1_PUD_VI1_CLKENB
-				   | PUD1_PUD_VI1_CLK
-				   | PUD1_PUD_VI0_DATA11
-				   | PUD1_PUD_VI0_DATA10
-				   | PUD1_PUD_VI0_DATA9
-				   | PUD1_PUD_VI0_DATA8
-				   | PUD1_PUD_VI0_DATA7
-				   | PUD1_PUD_VI0_DATA6
-				   | PUD1_PUD_VI0_DATA5
-				   | PUD1_PUD_VI0_DATA4
-				   | PUD1_PUD_VI0_DATA3
-				   | PUD1_PUD_VI0_DATA2
-				   | PUD1_PUD_VI0_DATA1
-				   | PUD1_PUD_VI0_DATA0
-				   | PUD1_PUD_VI0_VSYNC_N
-				   | PUD1_PUD_VI0_HSYNC_N
-				   | PUD1_PUD_VI0_CLKENB);
-
-	pfc_reg_write(PFC_PUD2,PUD2_PUD_CANFD_CLK
-				   | PUD2_PUD_CANFD1_RX
-				   | PUD2_PUD_CANFD1_TX
-				   | PUD2_PUD_CANFD0_RX
-				   | PUD2_PUD_CANFD0_TX
-				   | PUD2_PUD_AVB0_AVTP_CAPTURE
-				   | PUD2_PUD_VI1_FIELD);
-
-	pfc_reg_write(PFC_PUD3,PUD3_PUD_DIGRF_CLKOUT
-				   | PUD3_PUD_DIGRF_CLKIN);
-
-	/* initialize Module Select */
-	pfc_reg_write(PFC_MOD_SEL0,0x00000000);
-
-	// gpio
-	/* initialize positive/negative logic select */
-	mmio_write_32(GPIO_POSNEG0, 0x00000000U);
-	mmio_write_32(GPIO_POSNEG1, 0x00000000U);
-	mmio_write_32(GPIO_POSNEG2, 0x00000000U);
-	mmio_write_32(GPIO_POSNEG3, 0x00000000U);
-	mmio_write_32(GPIO_POSNEG4, 0x00000000U);
-	mmio_write_32(GPIO_POSNEG5, 0x00000000U);
-
-	/* initialize general IO/interrupt switching */
-	mmio_write_32(GPIO_IOINTSEL0, 0x00000000U);
-	mmio_write_32(GPIO_IOINTSEL1, 0x00000000U);
-	mmio_write_32(GPIO_IOINTSEL2, 0x00000000U);
-	mmio_write_32(GPIO_IOINTSEL3, 0x00000000U);
-	mmio_write_32(GPIO_IOINTSEL4, 0x00000000U);
-	mmio_write_32(GPIO_IOINTSEL5, 0x00000000U);
-
-	/* initialize general output register */
-	mmio_write_32(GPIO_OUTDT0, 0x00000000U);
-	mmio_write_32(GPIO_OUTDT1, 0x00000000U);
-	mmio_write_32(GPIO_OUTDT2, 0x00000000U);
-	mmio_write_32(GPIO_OUTDT3, 0x00000000U);
-	mmio_write_32(GPIO_OUTDT4, 0x00000000U);
-	mmio_write_32(GPIO_OUTDT5, 0x00000000U);
-
-	/* initialize general input/output switching */
-	mmio_write_32(GPIO_INOUTSEL0, 0x00000000U);
-	mmio_write_32(GPIO_INOUTSEL1, 0x00000000U);
-	mmio_write_32(GPIO_INOUTSEL2, 0x00000000U);
-	mmio_write_32(GPIO_INOUTSEL3, 0x00000000U);
-	mmio_write_32(GPIO_INOUTSEL4, 0x00000000U);
-	mmio_write_32(GPIO_INOUTSEL5, 0x00000000U);
-}
diff --git a/drivers/staging/renesas/rcar/pfc/pfc.mk b/drivers/staging/renesas/rcar/pfc/pfc.mk
deleted file mode 100644
index 2c55cb0..0000000
--- a/drivers/staging/renesas/rcar/pfc/pfc.mk
+++ /dev/null
@@ -1,69 +0,0 @@
-#
-# Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-ifeq (${RCAR_LSI},${RCAR_AUTO})
-    BL2_SOURCES += drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v1.c
-    BL2_SOURCES += drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v2.c
-    BL2_SOURCES += drivers/staging/renesas/rcar/pfc/M3/pfc_init_m3.c
-    BL2_SOURCES += drivers/staging/renesas/rcar/pfc/M3N/pfc_init_m3n.c
-    BL2_SOURCES += drivers/staging/renesas/rcar/pfc/V3M/pfc_init_v3m.c
-
-else ifdef RCAR_LSI_CUT_COMPAT
-  ifeq (${RCAR_LSI},${RCAR_H3})
-    BL2_SOURCES += drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v1.c
-    BL2_SOURCES += drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v2.c
-  endif
-  ifeq (${RCAR_LSI},${RCAR_H3N})
-    BL2_SOURCES += drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v1.c
-    BL2_SOURCES += drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v2.c
-  endif
-  ifeq (${RCAR_LSI},${RCAR_M3})
-    BL2_SOURCES += drivers/staging/renesas/rcar/pfc/M3/pfc_init_m3.c
-  endif
-  ifeq (${RCAR_LSI},${RCAR_M3N})
-    BL2_SOURCES += drivers/staging/renesas/rcar/pfc/M3N/pfc_init_m3n.c
-  endif
-  ifeq (${RCAR_LSI},${RCAR_V3M})
-    BL2_SOURCES += drivers/staging/renesas/rcar/pfc/V3M/pfc_init_v3m.c
-  endif
-  ifeq (${RCAR_LSI},${RCAR_E3})
-    BL2_SOURCES += drivers/staging/renesas/rcar/pfc/E3/pfc_init_e3.c
-  endif
-  ifeq (${RCAR_LSI},${RCAR_D3})
-    BL2_SOURCES += drivers/staging/renesas/rcar/pfc/D3/pfc_init_d3.c
-  endif
-else
-  ifeq (${RCAR_LSI},${RCAR_H3})
-    ifeq (${LSI_CUT},10)
-      BL2_SOURCES += drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v1.c
-    else ifeq (${LSI_CUT},11)
-      BL2_SOURCES += drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v1.c
-    else
-#     LSI_CUT 20 or later
-      BL2_SOURCES += drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v2.c
-    endif
-  endif
-  ifeq (${RCAR_LSI},${RCAR_H3N})
-    BL2_SOURCES += drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v2.c
-  endif
-  ifeq (${RCAR_LSI},${RCAR_M3})
-    BL2_SOURCES += drivers/staging/renesas/rcar/pfc/M3/pfc_init_m3.c
-  endif
-  ifeq (${RCAR_LSI},${RCAR_M3N})
-    BL2_SOURCES += drivers/staging/renesas/rcar/pfc/M3N/pfc_init_m3n.c
-  endif
-  ifeq (${RCAR_LSI},${RCAR_V3M})
-    BL2_SOURCES += drivers/staging/renesas/rcar/pfc/V3M/pfc_init_v3m.c
-  endif
-  ifeq (${RCAR_LSI},${RCAR_E3})
-    BL2_SOURCES += drivers/staging/renesas/rcar/pfc/E3/pfc_init_e3.c
-  endif
-  ifeq (${RCAR_LSI},${RCAR_D3})
-    BL2_SOURCES += drivers/staging/renesas/rcar/pfc/D3/pfc_init_d3.c
-  endif
-endif
-
-BL2_SOURCES += drivers/staging/renesas/rcar/pfc/pfc_init.c
diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h
index 69a9959..ead1a8b 100644
--- a/include/plat/arm/common/arm_def.h
+++ b/include/plat/arm/common/arm_def.h
@@ -312,19 +312,6 @@
  *****************************************************************************/
 
 /*
- * We need to access DRAM2 from BL2 for PSCI_MEM_PROTECT for
- * AArch64 builds
- */
-#ifdef AARCH64
-#define PLAT_PHY_ADDR_SPACE_SIZE			(1ULL << 36)
-#define PLAT_VIRT_ADDR_SPACE_SIZE			(1ULL << 36)
-#else
-#define PLAT_PHY_ADDR_SPACE_SIZE			(1ULL << 32)
-#define PLAT_VIRT_ADDR_SPACE_SIZE			(1ULL << 32)
-#endif
-
-
-/*
  * This macro defines the deepest retention state possible. A higher state
  * id will represent an invalid or a power down state.
  */
diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h
index 2313ab0..207cd31 100644
--- a/plat/arm/board/fvp/include/platform_def.h
+++ b/plat/arm/board/fvp/include/platform_def.h
@@ -256,4 +256,15 @@
 
 #define PLAT_SP_PRI			PLAT_RAS_PRI
 
+/*
+ * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes
+ */
+#ifdef AARCH64
+#define PLAT_PHY_ADDR_SPACE_SIZE	(1ULL << 36)
+#define PLAT_VIRT_ADDR_SPACE_SIZE	(1ULL << 36)
+#else
+#define PLAT_PHY_ADDR_SPACE_SIZE	(1ULL << 32)
+#define PLAT_VIRT_ADDR_SPACE_SIZE	(1ULL << 32)
+#endif
+
 #endif /* PLATFORM_DEF_H */
diff --git a/plat/arm/board/fvp_ve/include/platform_def.h b/plat/arm/board/fvp_ve/include/platform_def.h
index 1b21c79..b3b3672 100644
--- a/plat/arm/board/fvp_ve/include/platform_def.h
+++ b/plat/arm/board/fvp_ve/include/platform_def.h
@@ -328,4 +328,15 @@
 
 #define PLAT_ARM_G0_IRQ_PROPS(grp)	ARM_G0_IRQ_PROPS(grp)
 
+/*
+ * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes
+ */
+#ifdef AARCH64
+#define PLAT_PHY_ADDR_SPACE_SIZE	(1ULL << 36)
+#define PLAT_VIRT_ADDR_SPACE_SIZE	(1ULL << 36)
+#else
+#define PLAT_PHY_ADDR_SPACE_SIZE	(1ULL << 32)
+#define PLAT_VIRT_ADDR_SPACE_SIZE	(1ULL << 32)
+#endif
+
 #endif /* PLATFORM_H */
diff --git a/plat/arm/board/juno/include/platform_def.h b/plat/arm/board/juno/include/platform_def.h
index e096e33..d693c26 100644
--- a/plat/arm/board/juno/include/platform_def.h
+++ b/plat/arm/board/juno/include/platform_def.h
@@ -288,4 +288,15 @@
 /* System power domain level */
 #define CSS_SYSTEM_PWR_DMN_LVL		ARM_PWR_LVL2
 
+/*
+ * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes
+ */
+#ifdef AARCH64
+#define PLAT_PHY_ADDR_SPACE_SIZE	(1ULL << 36)
+#define PLAT_VIRT_ADDR_SPACE_SIZE	(1ULL << 36)
+#else
+#define PLAT_PHY_ADDR_SPACE_SIZE	(1ULL << 32)
+#define PLAT_VIRT_ADDR_SPACE_SIZE	(1ULL << 32)
+#endif
+
 #endif /* PLATFORM_DEF_H */
diff --git a/plat/arm/board/n1sdp/include/platform_def.h b/plat/arm/board/n1sdp/include/platform_def.h
index 0964f56..ff583a9 100644
--- a/plat/arm/board/n1sdp/include/platform_def.h
+++ b/plat/arm/board/n1sdp/include/platform_def.h
@@ -25,7 +25,22 @@
 #define PLAT_ARM_CRASH_UART_CLK_IN_HZ		PLAT_ARM_RUN_UART_CLK_IN_HZ
 
 #define PLAT_ARM_DRAM2_BASE			ULL(0x8080000000)
-#define PLAT_ARM_DRAM2_SIZE			ULL(0x780000000)
+#define PLAT_ARM_DRAM2_SIZE			ULL(0xF80000000)
+
+/*
+ * N1SDP platform supports RDIMMs with ECC capability. To use the ECC
+ * capability, the entire DDR memory space has to be zeroed out before
+ * enabling the ECC bits in DMC620. The access the complete DDR memory
+ * space the physical & virtual address space limits are extended to
+ * 40-bits.
+ */
+#ifndef AARCH32
+#define PLAT_PHY_ADDR_SPACE_SIZE		(1ULL << 40)
+#define PLAT_VIRT_ADDR_SPACE_SIZE		(1ULL << 40)
+#else
+#define PLAT_PHY_ADDR_SPACE_SIZE		(1ULL << 32)
+#define PLAT_VIRT_ADDR_SPACE_SIZE		(1ULL << 32)
+#endif
 
 #if CSS_USE_SCMI_SDS_DRIVER
 #define N1SDP_SCMI_PAYLOAD_BASE			0x45400000
@@ -55,8 +70,8 @@
  * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the
  * plat_arm_mmap array defined for each BL stage.
  */
-#define PLAT_ARM_MMAP_ENTRIES			3
-#define MAX_XLAT_TABLES				4
+#define PLAT_ARM_MMAP_ENTRIES			6
+#define MAX_XLAT_TABLES				7
 
 #define PLATFORM_STACK_SIZE			0x400
 
@@ -73,13 +88,18 @@
 #define PLAT_ARM_G0_IRQ_PROPS(grp)		ARM_G0_IRQ_PROPS(grp)
 
 
-#define N1SDP_DEVICE_BASE			(0x20000000)
-#define N1SDP_DEVICE_SIZE			(0x30000000)
+#define N1SDP_DEVICE_BASE			(0x08000000)
+#define N1SDP_DEVICE_SIZE			(0x48000000)
 #define N1SDP_MAP_DEVICE			MAP_REGION_FLAT(	\
 						N1SDP_DEVICE_BASE,	\
 						N1SDP_DEVICE_SIZE,	\
 						MT_DEVICE | MT_RW | MT_SECURE)
 
+#define ARM_MAP_DRAM1				MAP_REGION_FLAT(	\
+						ARM_DRAM1_BASE,		\
+						ARM_DRAM1_SIZE,		\
+						MT_MEMORY | MT_RW | MT_NS)
+
 /* GIC related constants */
 #define PLAT_ARM_GICD_BASE			0x30000000
 #define PLAT_ARM_GICC_BASE			0x2C000000
diff --git a/plat/arm/board/n1sdp/n1sdp_bl31_setup.c b/plat/arm/board/n1sdp/n1sdp_bl31_setup.c
index 18a0dea..a831b89 100644
--- a/plat/arm/board/n1sdp/n1sdp_bl31_setup.c
+++ b/plat/arm/board/n1sdp/n1sdp_bl31_setup.c
@@ -8,8 +8,35 @@
 
 #include <drivers/arm/css/css_mhu_doorbell.h>
 #include <drivers/arm/css/scmi.h>
+#include <drivers/arm/css/sds.h>
+#include <common/debug.h>
+#include <lib/mmio.h>
+#include <lib/utils.h>
 #include <plat/arm/common/plat_arm.h>
 
+#include "n1sdp_def.h"
+
+/*
+ * Memory information structure stored in SDS.
+ * This structure holds the total DDR memory size which will be
+ * used when zeroing out the entire DDR memory before enabling
+ * the ECC capability in DMCs.
+ */
+struct n1sdp_mem_info {
+	uint32_t ddr_size_gb;
+};
+
+/*
+ * BL33 image information structure stored in SDS.
+ * This structure holds the source & destination addresses and
+ * the size of the BL33 image which will be loaded by BL31.
+ */
+struct n1sdp_bl33_info {
+	uint32_t bl33_src_addr;
+	uint32_t bl33_dst_addr;
+	uint32_t bl33_size;
+};
+
 static scmi_channel_plat_info_t n1sdp_scmi_plat_info = {
 		.scmi_mbx_mem = N1SDP_SCMI_PAYLOAD_BASE,
 		.db_reg_addr = PLAT_CSS_MHU_BASE + CSS_SCMI_MHU_DB_REG_OFF,
@@ -27,3 +54,95 @@
 {
 	return css_scmi_override_pm_ops(ops);
 }
+
+/*
+ * N1SDP platform supports RDIMMs with ECC capability. To use the ECC
+ * capability, the entire DDR memory space has to be zeroed out before
+ * enabling the ECC bits in DMC620. Zeroing out several gigabytes of
+ * memory from SCP is quite time consuming so the following function
+ * is added to zero out the DDR memory from application processor which is
+ * much faster compared to SCP. BL33 binary cannot be copied to DDR memory
+ * before enabling ECC so copy_bl33 function is added to copy BL33 binary
+ * from IOFPGA-DDR3 memory to main DDR4 memory.
+ */
+
+void dmc_ecc_setup(uint32_t ddr_size_gb)
+{
+	uint64_t dram2_size;
+
+	dram2_size = (ddr_size_gb * 1024UL * 1024UL * 1024UL) -
+			ARM_DRAM1_SIZE;
+
+	INFO("Zeroing DDR memories\n");
+	zero_normalmem((void *)ARM_DRAM1_BASE, ARM_DRAM1_SIZE);
+	flush_dcache_range(ARM_DRAM1_BASE, ARM_DRAM1_SIZE);
+	zero_normalmem((void *)ARM_DRAM2_BASE, dram2_size);
+	flush_dcache_range(ARM_DRAM2_BASE, dram2_size);
+
+	INFO("Enabling ECC on DMCs\n");
+	mmio_setbits_32(N1SDP_DMC0_ERR0CTLR0_REG, N1SDP_DMC_ERR0CTLR0_ECC_EN);
+	mmio_setbits_32(N1SDP_DMC1_ERR0CTLR0_REG, N1SDP_DMC_ERR0CTLR0_ECC_EN);
+}
+
+void copy_bl33(uint32_t src, uint32_t dst, uint32_t size)
+{
+	uint32_t i;
+
+	INFO("Copying BL33 to DDR memory\n");
+	for (i = 0; i < size; i = i + 8)
+		mmio_write_64((dst + i), mmio_read_64(src + i));
+
+	for (i = 0; i < size; i = i + 8) {
+		if (mmio_read_64(src + i) != mmio_read_64(dst + i)) {
+			ERROR("Copy failed!\n");
+			panic();
+		}
+	}
+}
+
+void bl31_platform_setup(void)
+{
+	int ret;
+	struct n1sdp_mem_info mem_info;
+	struct n1sdp_bl33_info bl33_info;
+
+	arm_bl31_platform_setup();
+
+	ret = sds_init();
+	if (ret != SDS_OK) {
+		ERROR("SDS initialization failed\n");
+		panic();
+	}
+
+	ret = sds_struct_read(N1SDP_SDS_MEM_INFO_STRUCT_ID,
+				N1SDP_SDS_MEM_INFO_OFFSET,
+				&mem_info,
+				N1SDP_SDS_MEM_INFO_SIZE,
+				SDS_ACCESS_MODE_NON_CACHED);
+	if (ret != SDS_OK) {
+		ERROR("Error getting memory info from SDS\n");
+		panic();
+	}
+	dmc_ecc_setup(mem_info.ddr_size_gb);
+
+	ret = sds_struct_read(N1SDP_SDS_BL33_INFO_STRUCT_ID,
+				N1SDP_SDS_BL33_INFO_OFFSET,
+				&bl33_info,
+				N1SDP_SDS_BL33_INFO_SIZE,
+				SDS_ACCESS_MODE_NON_CACHED);
+	if (ret != SDS_OK) {
+		ERROR("Error getting BL33 info from SDS\n");
+		panic();
+	}
+	copy_bl33(bl33_info.bl33_src_addr,
+			bl33_info.bl33_dst_addr,
+			bl33_info.bl33_size);
+	/*
+	 * Pass DDR memory size info to BL33. This method is followed as
+	 * currently there is no BL1/BL2 involved in boot flow of N1SDP.
+	 * When TBBR is implemented for N1SDP, this method should be removed
+	 * and DDR memory size shoule be passed to BL33 using NT_FW_CONFIG
+	 * passing mechanism.
+	 */
+	mmio_write_32(N1SDP_DDR_MEM_INFO_BASE, mem_info.ddr_size_gb);
+}
diff --git a/plat/arm/board/n1sdp/n1sdp_def.h b/plat/arm/board/n1sdp/n1sdp_def.h
new file mode 100644
index 0000000..b7f7213
--- /dev/null
+++ b/plat/arm/board/n1sdp/n1sdp_def.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef N1SDP_DEF_H
+#define N1SDP_DEF_H
+
+/* Non-secure SRAM MMU mapping */
+#define N1SDP_NS_SRAM_BASE			(0x06000000)
+#define N1SDP_NS_SRAM_SIZE			(0x00010000)
+#define N1SDP_MAP_NS_SRAM			MAP_REGION_FLAT(	\
+						N1SDP_NS_SRAM_BASE,	\
+						N1SDP_NS_SRAM_SIZE,	\
+						MT_DEVICE | MT_RW | MT_SECURE)
+
+/* SDS memory information defines */
+#define N1SDP_SDS_MEM_INFO_STRUCT_ID		8
+#define N1SDP_SDS_MEM_INFO_OFFSET		0
+#define N1SDP_SDS_MEM_INFO_SIZE			4
+
+/* SDS BL33 image information defines */
+#define N1SDP_SDS_BL33_INFO_STRUCT_ID		9
+#define N1SDP_SDS_BL33_INFO_OFFSET		0
+#define N1SDP_SDS_BL33_INFO_SIZE		12
+
+/* DMC ERR0CTLR0 registers */
+#define N1SDP_DMC0_ERR0CTLR0_REG		0x4E000708
+#define N1SDP_DMC1_ERR0CTLR0_REG		0x4E100708
+
+/* DMC ECC enable bit in ERR0CTLR0 register */
+#define N1SDP_DMC_ERR0CTLR0_ECC_EN		0x1
+
+/* Base address of non-secure SRAM where DDR memory size will be filled */
+#define N1SDP_DDR_MEM_INFO_BASE			0x06008000
+
+#endif /* N1SDP_DEF_H */
diff --git a/plat/arm/board/n1sdp/n1sdp_plat.c b/plat/arm/board/n1sdp/n1sdp_plat.c
index f36f9e2..a32ca72 100644
--- a/plat/arm/board/n1sdp/n1sdp_plat.c
+++ b/plat/arm/board/n1sdp/n1sdp_plat.c
@@ -12,6 +12,8 @@
 #include <plat/common/platform.h>
 #include <drivers/arm/sbsa.h>
 
+#include "n1sdp_def.h"
+
 /*
  * Table of regions to map using the MMU.
  * Replace or extend the below regions as required
@@ -20,6 +22,9 @@
 const mmap_region_t plat_arm_mmap[] = {
 	ARM_MAP_SHARED_RAM,
 	N1SDP_MAP_DEVICE,
+	N1SDP_MAP_NS_SRAM,
+	ARM_MAP_DRAM1,
+	ARM_MAP_DRAM2,
 	{0}
 };
 
diff --git a/plat/arm/board/n1sdp/platform.mk b/plat/arm/board/n1sdp/platform.mk
index d0c34c8..986bd70 100644
--- a/plat/arm/board/n1sdp/platform.mk
+++ b/plat/arm/board/n1sdp/platform.mk
@@ -32,7 +32,8 @@
 				${N1SDP_GIC_SOURCES}			\
 				${N1SDP_BASE}/n1sdp_bl31_setup.c	        \
 				${N1SDP_BASE}/n1sdp_topology.c	        \
-				${N1SDP_BASE}/n1sdp_security.c
+				${N1SDP_BASE}/n1sdp_security.c		\
+				drivers/arm/css/sds/sds.c
 
 
 # TF-A not required to load the SCP Images
diff --git a/plat/arm/board/rde1edge/include/platform_def.h b/plat/arm/board/rde1edge/include/platform_def.h
index 3b3ade0..c62cda8 100644
--- a/plat/arm/board/rde1edge/include/platform_def.h
+++ b/plat/arm/board/rde1edge/include/platform_def.h
@@ -26,4 +26,15 @@
 
 #define CSS_SYSTEM_PWR_DMN_LVL		ARM_PWR_LVL3
 
+/*
+ * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes
+ */
+#ifndef AARCH32
+#define PLAT_PHY_ADDR_SPACE_SIZE	(1ULL << 36)
+#define PLAT_VIRT_ADDR_SPACE_SIZE	(1ULL << 36)
+#else
+#define PLAT_PHY_ADDR_SPACE_SIZE	(1ULL << 32)
+#define PLAT_VIRT_ADDR_SPACE_SIZE	(1ULL << 32)
+#endif
+
 #endif /* PLATFORM_DEF_H */
diff --git a/plat/arm/board/rdn1edge/include/platform_def.h b/plat/arm/board/rdn1edge/include/platform_def.h
index 8480c08..2c7b8bd 100644
--- a/plat/arm/board/rdn1edge/include/platform_def.h
+++ b/plat/arm/board/rdn1edge/include/platform_def.h
@@ -27,4 +27,15 @@
 
 #define PLAT_MAX_PWR_LVL		ARM_PWR_LVL1
 
+/*
+ * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes
+ */
+#ifndef AARCH32
+#define PLAT_PHY_ADDR_SPACE_SIZE	(1ULL << 36)
+#define PLAT_VIRT_ADDR_SPACE_SIZE	(1ULL << 36)
+#else
+#define PLAT_PHY_ADDR_SPACE_SIZE	(1ULL << 32)
+#define PLAT_VIRT_ADDR_SPACE_SIZE	(1ULL << 32)
+#endif
+
 #endif /* PLATFORM_DEF_H */
diff --git a/plat/arm/board/sgi575/include/platform_def.h b/plat/arm/board/sgi575/include/platform_def.h
index ec51c9e..883403b 100644
--- a/plat/arm/board/sgi575/include/platform_def.h
+++ b/plat/arm/board/sgi575/include/platform_def.h
@@ -27,4 +27,15 @@
 
 #define PLAT_MAX_PWR_LVL		ARM_PWR_LVL1
 
+/*
+ * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes
+ */
+#ifndef AARCH32
+#define PLAT_PHY_ADDR_SPACE_SIZE	(1ULL << 36)
+#define PLAT_VIRT_ADDR_SPACE_SIZE	(1ULL << 36)
+#else
+#define PLAT_PHY_ADDR_SPACE_SIZE	(1ULL << 32)
+#define PLAT_VIRT_ADDR_SPACE_SIZE	(1ULL << 32)
+#endif
+
 #endif /* PLATFORM_DEF_H */
diff --git a/plat/arm/board/sgm775/include/platform_def.h b/plat/arm/board/sgm775/include/platform_def.h
index 8a3431b..3e1fdd1 100644
--- a/plat/arm/board/sgm775/include/platform_def.h
+++ b/plat/arm/board/sgm775/include/platform_def.h
@@ -12,4 +12,15 @@
 #define PLAT_MAX_CPUS_PER_CLUSTER	8
 #define PLAT_MAX_PE_PER_CPU		1
 
+/*
+ * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes
+ */
+#ifndef AARCH32
+#define PLAT_PHY_ADDR_SPACE_SIZE	(1ULL << 36)
+#define PLAT_VIRT_ADDR_SPACE_SIZE	(1ULL << 36)
+#else
+#define PLAT_PHY_ADDR_SPACE_SIZE	(1ULL << 32)
+#define PLAT_VIRT_ADDR_SPACE_SIZE	(1ULL << 32)
+#endif
+
 #endif /* PLATFORM_DEF_H */
diff --git a/plat/intel/soc/common/drivers/ccu/ncore_ccu.c b/plat/intel/soc/common/drivers/ccu/ncore_ccu.c
new file mode 100644
index 0000000..ac8218e
--- /dev/null
+++ b/plat/intel/soc/common/drivers/ccu/ncore_ccu.c
@@ -0,0 +1,126 @@
+/*
+ * Copyright (c) 2019, Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <common/debug.h>
+#include <errno.h>
+#include <lib/mmio.h>
+
+#include "ncore_ccu.h"
+#include <platform_def.h>
+
+uint32_t poll_active_bit(uint32_t dir);
+
+static coh_ss_id_t subsystem_id;
+
+
+void get_subsystem_id(void)
+{
+	uint32_t snoop_filter, directory, coh_agent;
+
+	snoop_filter = CSIDR_NUM_SF(mmio_read_32(NCORE_CCU_CSR(NCORE_CSIDR)));
+	directory = CSUIDR_NUM_DIR(mmio_read_32(NCORE_CCU_CSR(NCORE_CSUIDR)));
+	coh_agent = CSUIDR_NUM_CAI(mmio_read_32(NCORE_CCU_CSR(NCORE_CSUIDR)));
+
+	subsystem_id.num_snoop_filter = snoop_filter + 1;
+	subsystem_id.num_directory = directory;
+	subsystem_id.num_coh_agent = coh_agent;
+}
+
+uint32_t directory_init(void)
+{
+	uint32_t dir_sf_mtn, dir_sf_en;
+	uint32_t dir, sf, ret;
+
+	for (dir = 0; dir < subsystem_id.num_directory; dir++) {
+
+		dir_sf_mtn = DIRECTORY_UNIT(dir, NCORE_DIRUSFMCR);
+		dir_sf_en = DIRECTORY_UNIT(dir, NCORE_DIRUSFER);
+
+		for (sf = 0; sf < subsystem_id.num_snoop_filter; sf++) {
+
+			/* Initialize All Entries */
+			mmio_write_32(dir_sf_mtn, SNOOP_FILTER_ID(sf));
+
+			/* Poll Active Bit */
+			ret = poll_active_bit(dir);
+			if (ret != 0) {
+				ERROR("Timeout during active bit polling");
+				return -ETIMEDOUT;
+			}
+
+			/* Snoope Filter Enable */
+			mmio_write_32(dir_sf_en, BIT(sf));
+		}
+	}
+
+	return 0;
+}
+
+uint32_t coherent_agent_intfc_init(void)
+{
+	uint32_t dir, ca, ca_id, ca_type, ca_snoop_en;
+
+	for (dir = 0; dir < subsystem_id.num_directory; dir++) {
+
+		ca_snoop_en = DIRECTORY_UNIT(dir, NCORE_DIRUCASER0);
+
+		for (ca = 0; ca < subsystem_id.num_coh_agent; ca++) {
+
+			ca_id = mmio_read_32(COH_AGENT_UNIT(ca, NCORE_CAIUIDR));
+
+			/* Coh Agent Snoop Enable */
+			if (CACHING_AGENT_BIT(ca_id))
+				mmio_write_32(ca_snoop_en, BIT(ca));
+
+			/* Coh Agent Snoop DVM Enable */
+			ca_type = CACHING_AGENT_TYPE(ca_id);
+			if (ca_type == ACE_W_DVM || ca_type == ACE_L_W_DVM)
+				mmio_write_32(NCORE_CCU_CSR(NCORE_CSADSER0),
+				BIT(ca));
+		}
+	}
+
+	return 0;
+}
+
+uint32_t poll_active_bit(uint32_t dir)
+{
+	uint32_t timeout = 80000;
+	uint32_t poll_dir =  DIRECTORY_UNIT(dir, NCORE_DIRUSFMAR);
+
+	while (timeout > 0) {
+		if (mmio_read_32(poll_dir) == 0)
+			return 0;
+		timeout--;
+	}
+
+	return -1;
+}
+
+void bypass_ocram_firewall(void)
+{
+	mmio_clrbits_32(COH_CPU0_BYPASS_REG(NCORE_FW_OCRAM_BLK_CGF1),
+			OCRAM_PRIVILEGED_MASK | OCRAM_SECURE_MASK);
+	mmio_clrbits_32(COH_CPU0_BYPASS_REG(NCORE_FW_OCRAM_BLK_CGF2),
+			OCRAM_PRIVILEGED_MASK | OCRAM_SECURE_MASK);
+	mmio_clrbits_32(COH_CPU0_BYPASS_REG(NCORE_FW_OCRAM_BLK_CGF3),
+			OCRAM_PRIVILEGED_MASK | OCRAM_SECURE_MASK);
+	mmio_clrbits_32(COH_CPU0_BYPASS_REG(NCORE_FW_OCRAM_BLK_CGF4),
+			OCRAM_PRIVILEGED_MASK | OCRAM_SECURE_MASK);
+}
+
+uint32_t init_ncore_ccu(void)
+{
+	uint32_t status;
+
+	get_subsystem_id();
+	status = directory_init();
+	status = coherent_agent_intfc_init();
+	bypass_ocram_firewall();
+
+	return status;
+}
diff --git a/plat/intel/soc/common/drivers/ccu/ncore_ccu.h b/plat/intel/soc/common/drivers/ccu/ncore_ccu.h
new file mode 100644
index 0000000..d25ecac
--- /dev/null
+++ b/plat/intel/soc/common/drivers/ccu/ncore_ccu.h
@@ -0,0 +1,108 @@
+/*
+ * Copyright (c) 2019, Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef NCORE_CCU_H
+#define NCORE_CCU_H
+
+
+#define NCORE_CCU_OFFSET		0xf7000000
+
+
+/* Coherent Sub-System Address Map */
+#define NCORE_CAIU_OFFSET		0x00000
+#define NCORE_CAIU_SIZE			0x01000
+
+#define NCORE_NCBU_OFFSET		0x60000
+#define NCORE_NCBU_SIZE			0x01000
+
+#define NCORE_DIRU_OFFSET		0x80000
+#define NCORE_DIRU_SIZE			0x01000
+
+#define NCORE_CMIU_OFFSET		0xc0000
+#define NCORE_CMIU_SIZE			0x01000
+
+#define NCORE_CSR_OFFSET		0xff000
+#define NCORE_CSADSERO			0x00040
+#define NCORE_CSUIDR			0x00ff8
+#define NCORE_CSIDR			0x00ffc
+
+/* Directory Unit Register Map */
+#define NCORE_DIRUSFER			0x00010
+#define NCORE_DIRUMRHER			0x00070
+#define NCORE_DIRUSFMCR			0x00080
+#define NCORE_DIRUSFMAR			0x00084
+
+/* Coherent Agent Interface Unit Register Map */
+#define NCORE_CAIUIDR			0x00ffc
+
+/* Snoop Enable Register */
+#define NCORE_DIRUCASER0		0x00040
+#define NCORE_DIRUCASER1		0x00044
+#define NCORE_DIRUCASER2		0x00048
+#define NCORE_DIRUCASER3		0x0004c
+
+#define NCORE_CSADSER0			0x00040
+#define NCORE_CSADSER1			0x00044
+#define NCORE_CSADSER2			0x00048
+#define NCORE_CSADSER3			0x0004c
+
+/* Protocols Definition */
+#define ACE_W_DVM			0
+#define ACE_L_W_DVM			1
+#define ACE_WO_DVM			2
+#define ACE_L_WO_DVM			3
+
+/* Bypass OC Ram Firewall */
+#define NCORE_FW_OCRAM_BLK_BASE		0x100200
+#define NCORE_FW_OCRAM_BLK_CGF1		0x04
+#define NCORE_FW_OCRAM_BLK_CGF2		0x08
+#define NCORE_FW_OCRAM_BLK_CGF3		0x0c
+#define NCORE_FW_OCRAM_BLK_CGF4		0x10
+
+#define OCRAM_PRIVILEGED_MASK		BIT(29)
+#define OCRAM_SECURE_MASK		BIT(30)
+
+/* Macros */
+#define NCORE_CCU_REG(base)		(NCORE_CCU_OFFSET + (base))
+#define NCORE_CCU_CSR(reg)		(NCORE_CCU_REG(NCORE_CSR_OFFSET)\
+						+ (reg))
+#define NCORE_CCU_DIR(reg)		(NCORE_CCU_REG(NCORE_DIRU_OFFSET)\
+						+ (reg))
+#define NCORE_CCU_CAI(reg)		(NCORE_CCU_REG(NCORE_CAIU_OFFSET)\
+						+ (reg))
+
+#define DIRECTORY_UNIT(x, reg)		(NCORE_CCU_DIR(reg)\
+						+ NCORE_DIRU_SIZE * (x))
+#define COH_AGENT_UNIT(x, reg)		(NCORE_CCU_CAI(reg)\
+						+ NCORE_CAIU_SIZE * (x))
+
+#define COH_CPU0_BYPASS_REG(reg)	(NCORE_CCU_REG(NCORE_FW_OCRAM_BLK_BASE)\
+						+ (reg))
+
+#define CSUIDR_NUM_CMI(x)		(((x) & 0x3f000000) >> 24)
+#define CSUIDR_NUM_DIR(x)		(((x) & 0x003f0000) >> 16)
+#define CSUIDR_NUM_NCB(x)		(((x) & 0x00003f00) >> 8)
+#define CSUIDR_NUM_CAI(x)		(((x) & 0x0000007f) >> 0)
+
+#define CSIDR_NUM_SF(x)			(((x) & 0x007c0000) >> 18)
+
+#define SNOOP_FILTER_ID(x)		(((x) << 16))
+
+#define CACHING_AGENT_BIT(x)		(((x) & 0x08000) >> 15)
+#define CACHING_AGENT_TYPE(x)		(((x) & 0xf0000) >> 16)
+
+
+typedef struct coh_ss_id {
+	uint8_t num_coh_mem;
+	uint8_t num_directory;
+	uint8_t num_non_coh_bridge;
+	uint8_t num_coh_agent;
+	uint8_t num_snoop_filter;
+} coh_ss_id_t;
+
+uint32_t init_ncore_ccu(void);
+
+#endif
diff --git a/plat/intel/soc/stratix10/drivers/qspi/cadence_qspi.c b/plat/intel/soc/common/drivers/qspi/cadence_qspi.c
similarity index 97%
rename from plat/intel/soc/stratix10/drivers/qspi/cadence_qspi.c
rename to plat/intel/soc/common/drivers/qspi/cadence_qspi.c
index 506a633..0fd11ec 100644
--- a/plat/intel/soc/stratix10/drivers/qspi/cadence_qspi.c
+++ b/plat/intel/soc/common/drivers/qspi/cadence_qspi.c
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2019, Intel Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -65,13 +66,13 @@
 	return 0;
 }
 
-int cat_qspi_set_write_config(uint32_t addr_type, uint32_t data_type,
-		uint32_t mode_bit, uint32_t dummy_clk_cycle)
+int cad_qspi_set_write_config(uint32_t opcode, uint32_t addr_type,
+		uint32_t data_type, uint32_t dummy_clk_cycle)
 {
 	mmio_write_32(CAD_QSPI_OFFSET + CAD_QSPI_DEVWR,
+			CAD_QSPI_DEV_OPCODE(opcode) |
 			CAD_QSPI_DEV_ADDR_TYPE(addr_type) |
 			CAD_QSPI_DEV_DATA_TYPE(data_type) |
-			CAD_QSPI_DEV_MODE_BIT(mode_bit) |
 			CAD_QSPI_DEV_DUMMY_CLK_CYCLE(dummy_clk_cycle));
 
 	return 0;
@@ -161,7 +162,7 @@
 		CAD_QSPI_FLASHCMD_NUMDUMMYBYTES(dummy);
 
 	if (cad_qspi_stig_cmd_helper(cad_qspi_cs, cmd)) {
-		ERROR("failed to send stig cmd");
+		ERROR("failed to send stig cmd\n");
 		return -1;
 	}
 
@@ -249,6 +250,8 @@
 	cad_qspi_set_read_config(QSPI_FAST_READ, CAD_QSPI_INST_SINGLE,
 			CAD_QSPI_ADDR_FASTREAD, CAT_QSPI_ADDR_SINGLE_IO, 1,
 			0);
+	cad_qspi_set_write_config(QSPI_WRITE, 0, 0, 0);
+
 	return 0;
 }
 
@@ -512,7 +515,7 @@
 	INFO("Initializing Qspi\n");
 
 	if (cad_qspi_idle() == 0) {
-		ERROR("device not idle");
+		ERROR("device not idle\n");
 		return -1;
 	}
 
@@ -587,8 +590,9 @@
 		return -1;
 	}
 
-	cad_qspi_configure_dev_size(S10_QSPI_ADDR_BYTES,
-				S10_QSPI_BYTES_PER_DEV, S10_BYTES_PER_BLOCK);
+	cad_qspi_configure_dev_size(INTEL_QSPI_ADDR_BYTES,
+				INTEL_QSPI_BYTES_PER_DEV,
+				INTEL_BYTES_PER_BLOCK);
 
 	INFO("Flash size: %d Bytes\n", qspi_device_size);
 
@@ -689,13 +693,13 @@
 			((long) ((int *)buffer) & 0x3)  ||
 			(offset & 0x3) ||
 			(size & 0x3)) {
-		ERROR("Invalid read parameter");
+		ERROR("Invalid read parameter\n");
 		return -1;
 	}
 
 	if (CAD_QSPI_INDRD_RD_STAT(mmio_read_32(CAD_QSPI_OFFSET +
 						CAD_QSPI_INDRD))) {
-		ERROR("Read in progress");
+		ERROR("Read in progress\n");
 		return -1;
 	}
 
diff --git a/plat/intel/soc/stratix10/drivers/qspi/cadence_qspi.h b/plat/intel/soc/common/drivers/qspi/cadence_qspi.h
similarity index 95%
rename from plat/intel/soc/stratix10/drivers/qspi/cadence_qspi.h
rename to plat/intel/soc/common/drivers/qspi/cadence_qspi.h
index e419161..4fb2922 100644
--- a/plat/intel/soc/stratix10/drivers/qspi/cadence_qspi.h
+++ b/plat/intel/soc/common/drivers/qspi/cadence_qspi.h
@@ -1,11 +1,12 @@
 /*
  * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2019, Intel Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef __CAD_QSPI_H__
-#define __CAD_QSPI_H__
+#ifndef CAD_QSPI_H
+#define CAD_QSPI_H
 
 #define CAD_QSPI_MICRON_N25Q_SUPPORT		1
 
@@ -146,12 +147,14 @@
 
 #define CAD_QSPI_SUBSECTOR_SIZE			0x1000
 
-#define S10_QSPI_ADDR_BYTES			2
-#define S10_QSPI_BYTES_PER_DEV			256
-#define S10_BYTES_PER_BLOCK			16
+#define INTEL_QSPI_ADDR_BYTES			2
+#define INTEL_QSPI_BYTES_PER_DEV		256
+#define INTEL_BYTES_PER_BLOCK			16
 
 #define QSPI_FAST_READ				0xb
 
+#define QSPI_WRITE				0x2
+
 // QSPI CONFIGURATIONS
 
 #define QSPI_CONFIG_CPOL			1
diff --git a/plat/intel/soc/stratix10/drivers/wdt/watchdog.c b/plat/intel/soc/common/drivers/wdt/watchdog.c
similarity index 87%
rename from plat/intel/soc/stratix10/drivers/wdt/watchdog.c
rename to plat/intel/soc/common/drivers/wdt/watchdog.c
index b4dbe5f..0f89b4f 100644
--- a/plat/intel/soc/stratix10/drivers/wdt/watchdog.c
+++ b/plat/intel/soc/common/drivers/wdt/watchdog.c
@@ -28,10 +28,10 @@
 void watchdog_status(void)
 {
 	if (mmio_read_32(WDT_CR) & 1) {
-		INFO("Watchdog Timer in currently enabled\n");
+		INFO("Watchdog Timer is currently enabled\n");
 		INFO("Current Counter : 0x%x\r\n", mmio_read_32(WDT_CCVR));
 	} else {
-		INFO("Watchdog Timer in currently disabled\n");
+		INFO("Watchdog Timer is currently disabled\n");
 	}
 }
 
@@ -49,10 +49,5 @@
 
 	mmio_write_32(WDT_TORR, (cycles_i << 4) | cycles_i);
 
-	watchdog_enable();
-}
-
-void watchdog_enable(void)
-{
 	mmio_write_32(WDT_CR, WDT_CR_RMOD|WDT_CR_EN);
 }
diff --git a/plat/intel/soc/stratix10/drivers/wdt/watchdog.h b/plat/intel/soc/common/drivers/wdt/watchdog.h
similarity index 90%
rename from plat/intel/soc/stratix10/drivers/wdt/watchdog.h
rename to plat/intel/soc/common/drivers/wdt/watchdog.h
index e920236..2c72463 100644
--- a/plat/intel/soc/stratix10/drivers/wdt/watchdog.h
+++ b/plat/intel/soc/common/drivers/wdt/watchdog.h
@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef __CAD_WATCHDOG_H__
-#define __CAD_WATCHDOG_H__
+#ifndef CAD_WATCHDOG_H
+#define CAD_WATCHDOG_H
 
 #define WDT_BASE			(0xFFD00200)
 #define WDT_REG_SIZE_OFFSET		(0x4)
@@ -32,7 +32,6 @@
 
 
 void watchdog_init(int watchdog_clk);
-void watchdog_enable(void);
 void watchdog_info(void);
 void watchdog_status(void);
 void watchdog_sw_rst(void);
diff --git a/plat/intel/soc/stratix10/bl2_plat_setup.c b/plat/intel/soc/stratix10/bl2_plat_setup.c
index 58e8c02..7830162 100644
--- a/plat/intel/soc/stratix10/bl2_plat_setup.c
+++ b/plat/intel/soc/stratix10/bl2_plat_setup.c
@@ -31,8 +31,8 @@
 #include "s10_pinmux.h"
 #include "aarch64/stratix10_private.h"
 #include "include/s10_mailbox.h"
-#include "drivers/qspi/cadence_qspi.h"
-#include "drivers/wdt/watchdog.h"
+#include "qspi/cadence_qspi.h"
+#include "wdt/watchdog.h"
 
 
 const mmap_region_t plat_stratix10_mmap[] = {
diff --git a/plat/intel/soc/stratix10/platform.mk b/plat/intel/soc/stratix10/platform.mk
index fd91e58..a21280f 100644
--- a/plat/intel/soc/stratix10/platform.mk
+++ b/plat/intel/soc/stratix10/platform.mk
@@ -7,6 +7,7 @@
 PLAT_INCLUDES		:=	\
 			-Iplat/intel/soc/stratix10/			\
 			-Iplat/intel/soc/stratix10/include/		\
+			-Iplat/intel/soc/common/drivers/
 
 PLAT_BL_COMMON_SOURCES	:=	\
 			lib/xlat_tables/xlat_tables_common.c 		\
@@ -46,8 +47,8 @@
 		plat/intel/soc/stratix10/soc/s10_system_manager.c	\
 		common/desc_image_load.c				\
 		plat/intel/soc/stratix10/soc/s10_mailbox.c		\
-		plat/intel/soc/stratix10/drivers/qspi/cadence_qspi.c	\
-		plat/intel/soc/stratix10/drivers/wdt/watchdog.c
+		plat/intel/soc/common/drivers/qspi/cadence_qspi.c	\
+		plat/intel/soc/common/drivers/wdt/watchdog.c
 
 BL31_SOURCES	+=	drivers/arm/cci/cci.c				\
 		lib/cpus/aarch64/cortex_a53.S				\
diff --git a/plat/nvidia/tegra/common/tegra_bl31_setup.c b/plat/nvidia/tegra/common/tegra_bl31_setup.c
index c9beb14..a9d037f 100644
--- a/plat/nvidia/tegra/common/tegra_bl31_setup.c
+++ b/plat/nvidia/tegra/common/tegra_bl31_setup.c
@@ -207,7 +207,7 @@
 	/*
 	 * The previous bootloader passes the base address of the shared memory
 	 * location to store the boot profiler logs. Sanity check the
-	 * address and initilise the profiler library, if it looks ok.
+	 * address and initialise the profiler library, if it looks ok.
 	 */
 	if (plat_params->boot_profiler_shmem_base != 0ULL) {
 
@@ -470,7 +470,7 @@
 	if ((base < TEGRA_DRAM_BASE) || (base >= TEGRA_DRAM_END) ||
 	    (end > TEGRA_DRAM_END)) {
 
-		ERROR("NS address is out-of-bounds!\n");
+		ERROR("NS address 0x%llx is out-of-bounds!\n", base);
 		ret = -EFAULT;
 	}
 
@@ -479,7 +479,7 @@
 	 * to check if the NS DRAM range overlaps the TZDRAM aperture.
 	 */
 	if ((base < (uint64_t)TZDRAM_END) && (end > tegra_bl31_phys_base)) {
-		ERROR("NS address overlaps TZDRAM!\n");
+		ERROR("NS address 0x%llx overlaps TZDRAM!\n", base);
 		ret = -ENOTSUP;
 	}
 
diff --git a/plat/renesas/rcar/platform.mk b/plat/renesas/rcar/platform.mk
index 17fdc0d..dc58e19 100644
--- a/plat/renesas/rcar/platform.mk
+++ b/plat/renesas/rcar/platform.mk
@@ -350,7 +350,7 @@
 
 include drivers/staging/renesas/rcar/ddr/ddr.mk
 include drivers/renesas/rcar/qos/qos.mk
-include drivers/staging/renesas/rcar/pfc/pfc.mk
+include drivers/renesas/rcar/pfc/pfc.mk
 include lib/libfdt/libfdt.mk
 
 PLAT_INCLUDES	:=	-Idrivers/staging/renesas/rcar/ddr	\