marvell: drivers: Add address decoding units drivers
Add address decoding unit drivers for Marvell SoCs.
Address decoding flow and address translation units chart
are located at docs/marvell/misc/mvebu-a8k-addr-map.txt
Change-Id: Id6ce311fa1f4f112df3adfac5d20449f495f71ed
Signed-off-by: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
diff --git a/include/drivers/marvell/addr_map.h b/include/drivers/marvell/addr_map.h
new file mode 100644
index 0000000..6b957a1
--- /dev/null
+++ b/include/drivers/marvell/addr_map.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+
+/* Address map types for Marvell address translation unit drivers */
+
+#ifndef _ADDR_MAP_H_
+#define _ADDR_MAP_H_
+
+#include <stdint.h>
+
+struct addr_map_win {
+ uint64_t base_addr;
+ uint64_t win_size;
+ uint32_t target_id;
+};
+
+#endif /* _ADDR_MAP_H_ */
diff --git a/include/drivers/marvell/amb_adec.h b/include/drivers/marvell/amb_adec.h
new file mode 100644
index 0000000..087864a
--- /dev/null
+++ b/include/drivers/marvell/amb_adec.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+
+/* AXI to M-Bridge decoding unit driver for Marvell Armada 8K and 8K+ SoCs */
+
+#ifndef _AMB_ADEC_H_
+#define _AMB_ADEC_H_
+
+#include <stdint.h>
+
+enum amb_attribute_ids {
+ AMB_SPI0_CS0_ID = 0x1E,
+ AMB_SPI0_CS1_ID = 0x5E,
+ AMB_SPI0_CS2_ID = 0x9E,
+ AMB_SPI0_CS3_ID = 0xDE,
+ AMB_SPI1_CS0_ID = 0x1A,
+ AMB_SPI1_CS1_ID = 0x5A,
+ AMB_SPI1_CS2_ID = 0x9A,
+ AMB_SPI1_CS3_ID = 0xDA,
+ AMB_DEV_CS0_ID = 0x3E,
+ AMB_DEV_CS1_ID = 0x3D,
+ AMB_DEV_CS2_ID = 0x3B,
+ AMB_DEV_CS3_ID = 0x37,
+ AMB_BOOT_CS_ID = 0x2f,
+ AMB_BOOT_ROM_ID = 0x1D,
+};
+
+#define AMB_MAX_WIN_ID 7
+
+int init_amb_adec(uintptr_t base);
+
+#endif /* _AMB_ADEC_H_ */
diff --git a/include/drivers/marvell/ccu.h b/include/drivers/marvell/ccu.h
new file mode 100644
index 0000000..ff30a76
--- /dev/null
+++ b/include/drivers/marvell/ccu.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+
+/* CCU unit device driver for Marvell AP807, AP807 and AP810 SoCs */
+
+#ifndef _CCU_H_
+#define _CCU_H_
+
+#ifndef __ASSEMBLY__
+#include <addr_map.h>
+#endif
+
+/* CCU registers definitions */
+#define CCU_WIN_CR_OFFSET(ap, win) (MVEBU_CCU_BASE(ap) + 0x0 + \
+ (0x10 * win))
+#define CCU_TARGET_ID_OFFSET (8)
+#define CCU_TARGET_ID_MASK (0x7F)
+
+#define CCU_WIN_SCR_OFFSET(ap, win) (MVEBU_CCU_BASE(ap) + 0x4 + \
+ (0x10 * win))
+#define CCU_WIN_ENA_WRITE_SECURE (0x1)
+#define CCU_WIN_ENA_READ_SECURE (0x2)
+
+#define CCU_WIN_ALR_OFFSET(ap, win) (MVEBU_CCU_BASE(ap) + 0x8 + \
+ (0x10 * win))
+#define CCU_WIN_AHR_OFFSET(ap, win) (MVEBU_CCU_BASE(ap) + 0xC + \
+ (0x10 * win))
+
+#define CCU_WIN_GCR_OFFSET(ap) (MVEBU_CCU_BASE(ap) + 0xD0)
+#define CCU_GCR_TARGET_OFFSET (8)
+#define CCU_GCR_TARGET_MASK (0xFF)
+
+#define CCU_SRAM_WIN_CR CCU_WIN_CR_OFFSET(MVEBU_AP0, 1)
+
+#ifndef __ASSEMBLY__
+int init_ccu(int);
+void ccu_win_check(struct addr_map_win *win);
+void ccu_enable_win(int ap_index, struct addr_map_win *win, uint32_t win_id);
+void ccu_temp_win_insert(int ap_index, struct addr_map_win *win, int size);
+void ccu_temp_win_remove(int ap_index, struct addr_map_win *win, int size);
+void ccu_dram_win_config(int ap_index, struct addr_map_win *win);
+void ccu_dram_target_set(int ap_index, uint32_t target);
+void ccu_save_win_all(int ap_id);
+void ccu_restore_win_all(int ap_id);
+#endif
+
+#endif /* _CCU_H_ */
diff --git a/include/drivers/marvell/gwin.h b/include/drivers/marvell/gwin.h
new file mode 100644
index 0000000..5dc9f24
--- /dev/null
+++ b/include/drivers/marvell/gwin.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+
+/* GWIN unit device driver for Marvell AP810 SoC */
+
+#ifndef _GWIN_H_
+#define _GWIN_H_
+
+#include <addr_map.h>
+
+int init_gwin(int ap_index);
+void gwin_temp_win_insert(int ap_index, struct addr_map_win *win, int size);
+void gwin_temp_win_remove(int ap_index, struct addr_map_win *win, int size);
+
+#endif /* _GWIN_H_ */
diff --git a/include/drivers/marvell/io_win.h b/include/drivers/marvell/io_win.h
new file mode 100644
index 0000000..4102a11
--- /dev/null
+++ b/include/drivers/marvell/io_win.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+
+/* IO Window unit device driver for Marvell AP807, AP807 and AP810 SoCs */
+
+#ifndef _IO_WIN_H_
+#define _IO_WIN_H_
+
+#include <addr_map.h>
+
+int init_io_win(int ap_index);
+void iow_temp_win_insert(int ap_index, struct addr_map_win *win, int size);
+void iow_temp_win_remove(int ap_index, struct addr_map_win *win, int size);
+void iow_save_win_all(int ap_id);
+void iow_restore_win_all(int ap_id);
+
+#endif /* _IO_WIN_H_ */
diff --git a/include/drivers/marvell/iob.h b/include/drivers/marvell/iob.h
new file mode 100644
index 0000000..9848c0a
--- /dev/null
+++ b/include/drivers/marvell/iob.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+
+/* IOW unit device driver for Marvell CP110 and CP115 SoCs */
+
+#ifndef _IOB_H_
+#define _IOB_H_
+
+#include <addr_map.h>
+
+enum target_ids_iob {
+ INTERNAL_TID = 0x0,
+ MCI0_TID = 0x1,
+ PEX1_TID = 0x2,
+ PEX2_TID = 0x3,
+ PEX0_TID = 0x4,
+ NAND_TID = 0x5,
+ RUNIT_TID = 0x6,
+ MCI1_TID = 0x7,
+ IOB_MAX_TID
+};
+
+int init_iob(uintptr_t base);
+void iob_cfg_space_update(int ap_idx, int cp_idx,
+ uintptr_t base, uintptr_t new_base);
+
+#endif /* _IOB_H_ */