feat(stm32mp2): generate stm32 file
To be able to boot, STM32MPU platforms require the BL2 binary (together
with its DT) to be preceded with an STM32 header. Add the required
files and macro to properly generate this header.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I675de2c5cb733fe9d9e9baf76a941741a06dfac8
diff --git a/plat/st/stm32mp2/aarch64/stm32mp2.S b/plat/st/stm32mp2/aarch64/stm32mp2.S
new file mode 100644
index 0000000..1866b8b
--- /dev/null
+++ b/plat/st/stm32mp2/aarch64/stm32mp2.S
@@ -0,0 +1,11 @@
+/*
+ * Copyright (c) 2023, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+.section .bl2_image
+.incbin BL2_BIN_PATH
+
+.section .dtb_image
+.incbin DTB_BIN_PATH
diff --git a/plat/st/stm32mp2/aarch64/stm32mp2.ld.S b/plat/st/stm32mp2/aarch64/stm32mp2.ld.S
new file mode 100644
index 0000000..48bf424
--- /dev/null
+++ b/plat/st/stm32mp2/aarch64/stm32mp2.ld.S
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2023, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef STM32MP2_LD_S
+#define STM32MP2_LD_S
+
+#include <lib/xlat_tables/xlat_tables_defs.h>
+#include <platform_def.h>
+
+OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
+OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
+
+ENTRY(__BL2_IMAGE_START__)
+
+MEMORY {
+ HEADER (rw) : ORIGIN = 0x00000000, LENGTH = STM32MP_HEADER_RESERVED_SIZE
+ RAM (rwx) : ORIGIN = STM32MP_BINARY_BASE, LENGTH = STM32MP_BINARY_SIZE
+}
+
+SECTIONS
+{
+ /*
+ * TF mapping must conform to ROM code specification.
+ */
+ .header : {
+ __HEADER_START__ = .;
+ KEEP(*(.header))
+ . = ALIGN(4);
+ __HEADER_END__ = .;
+ } >HEADER
+
+ . = STM32MP_BINARY_BASE;
+ .data . : {
+ . = ALIGN(PAGE_SIZE);
+ __DATA_START__ = .;
+ *(.data*)
+
+ /*
+ * dtb.
+ * The strongest and only alignment contraint is MMU 4K page.
+ * Indeed as images below will be removed, 4K pages will be re-used.
+ */
+ . = ( STM32MP_BL2_DTB_BASE - STM32MP_BINARY_BASE );
+ __DTB_IMAGE_START__ = .;
+ *(.dtb_image*)
+ __DTB_IMAGE_END__ = .;
+
+ /*
+ * bl2.
+ * The strongest and only alignment contraint is MMU 4K page.
+ * Indeed as images below will be removed, 4K pages will be re-used.
+ */
+#if SEPARATE_CODE_AND_RODATA
+ . = ( STM32MP_BL2_RO_BASE - STM32MP_BINARY_BASE );
+#else
+ . = ( STM32MP_BL2_BASE - STM32MP_BINARY_BASE );
+#endif
+ __BL2_IMAGE_START__ = .;
+ *(.bl2_image*)
+ __BL2_IMAGE_END__ = .;
+
+ __DATA_END__ = .;
+ } >RAM
+
+ __TF_END__ = .;
+
+}
+#endif /* STM32MP2_LD_S */
diff --git a/plat/st/stm32mp2/platform.mk b/plat/st/stm32mp2/platform.mk
index ba6ab4b..6ea4638 100644
--- a/plat/st/stm32mp2/platform.mk
+++ b/plat/st/stm32mp2/platform.mk
@@ -26,6 +26,15 @@
# such as metadata (2) and fsbl-m (2) to find all the FIP partitions (default is 2).
PLAT_PARTITION_MAX_ENTRIES := $(shell echo $$(($(STM32_TF_A_COPIES) + 6)))
+# Device tree
+BL2_DTSI := stm32mp25-bl2.dtsi
+FDT_SOURCES := $(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl2.dts,$(DTB_FILE_NAME)))
+
+# Macros and rules to build TF binary
+STM32_TF_STM32 := $(addprefix ${BUILD_PLAT}/tf-a-, $(patsubst %.dtb,%.stm32,$(DTB_FILE_NAME)))
+STM32_LD_FILE := plat/st/stm32mp2/${ARCH}/stm32mp2.ld.S
+STM32_BINARY_MAPPING := plat/st/stm32mp2/${ARCH}/stm32mp2.S
+
# STM32MP2x is based on Cortex-A35, which is Armv8.0, and does not support BTI
# Disable mbranch-protection to avoid adding useless code
TF_CFLAGS += -mbranch-protection=none
diff --git a/plat/st/stm32mp2/stm32mp2_def.h b/plat/st/stm32mp2/stm32mp2_def.h
index f8148b7..66514fc 100644
--- a/plat/st/stm32mp2/stm32mp2_def.h
+++ b/plat/st/stm32mp2/stm32mp2_def.h
@@ -45,6 +45,24 @@
};
#endif
+/* Section used inside TF binaries */
+#define STM32MP_PARAM_LOAD_SIZE U(0x00002400) /* 9 KB for param */
+/* 512 Octets reserved for header */
+#define STM32MP_HEADER_SIZE U(0x00000200)
+#define STM32MP_HEADER_BASE (STM32MP_SEC_SYSRAM_BASE + \
+ STM32MP_PARAM_LOAD_SIZE)
+
+/* round_up(STM32MP_PARAM_LOAD_SIZE + STM32MP_HEADER_SIZE, PAGE_SIZE) */
+#define STM32MP_HEADER_RESERVED_SIZE U(0x3000)
+
+#define STM32MP_BINARY_BASE (STM32MP_SEC_SYSRAM_BASE + \
+ STM32MP_PARAM_LOAD_SIZE + \
+ STM32MP_HEADER_SIZE)
+
+#define STM32MP_BINARY_SIZE (STM32MP_SEC_SYSRAM_SIZE - \
+ (STM32MP_PARAM_LOAD_SIZE + \
+ STM32MP_HEADER_SIZE))
+
#define STM32MP_BL2_SIZE U(0x0002A000) /* 168 KB for BL2 */
#define STM32MP_BL2_BASE (STM32MP_SEC_SYSRAM_BASE + \
@@ -60,6 +78,12 @@
*/
#define MAX_MMAP_REGIONS 6
+/* DTB initialization value */
+#define STM32MP_BL2_DTB_SIZE U(0x00005000) /* 20 KB for DTB */
+
+#define STM32MP_BL2_DTB_BASE (STM32MP_BL2_BASE - \
+ STM32MP_BL2_DTB_SIZE)
+
#define STM32MP_BL33_BASE (STM32MP_DDR_BASE + U(0x04000000))
#define STM32MP_BL33_MAX_SIZE U(0x400000)