diff --git a/plat/intel/soc/agilex/include/agilex_clock_manager.h b/plat/intel/soc/agilex/include/agilex_clock_manager.h
new file mode 100644
index 0000000..c1a7546
--- /dev/null
+++ b/plat/intel/soc/agilex/include/agilex_clock_manager.h
@@ -0,0 +1,128 @@
+/*
+ * Copyright (c) 2019, Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CLOCKMANAGER_H
+#define CLOCKMANAGER_H
+
+#include "agilex_handoff.h"
+
+/* Clock Manager Registers */
+#define CLKMGR_OFFSET				0xffd10000
+
+#define CLKMGR_CTRL				0x0
+#define CLKMGR_STAT				0x4
+#define CLKMGR_INTRCLR				0x14
+
+/* Main PLL Group */
+#define CLKMGR_MAINPLL				0xffd10024
+#define CLKMGR_MAINPLL_EN			0x0
+#define CLKMGR_MAINPLL_BYPASS			0xc
+#define CLKMGR_MAINPLL_MPUCLK			0x18
+#define CLKMGR_MAINPLL_NOCCLK			0x1c
+#define CLKMGR_MAINPLL_NOCDIV			0x20
+#define CLKMGR_MAINPLL_PLLGLOB			0x24
+#define CLKMGR_MAINPLL_FDBCK			0x28
+#define CLKMGR_MAINPLL_MEM			0x2c
+#define CLKMGR_MAINPLL_MEMSTAT			0x30
+#define CLKMGR_MAINPLL_PLLC0			0x34
+#define CLKMGR_MAINPLL_PLLC1			0x38
+#define CLKMGR_MAINPLL_VCOCALIB			0x3c
+#define CLKMGR_MAINPLL_PLLC2			0x40
+#define CLKMGR_MAINPLL_PLLC3			0x44
+#define CLKMGR_MAINPLL_PLLM			0x48
+
+/* Peripheral PLL Group */
+#define CLKMGR_PERPLL				0xffd1007c
+#define CLKMGR_PERPLL_EN			0x0
+#define CLKMGR_PERPLL_BYPASS			0xc
+#define CLKMGR_PERPLL_EMACCTL			0x18
+#define CLKMGR_PERPLL_GPIODIV			0x1c
+#define CLKMGR_PERPLL_PLLGLOB			0x20
+#define CLKMGR_PERPLL_FDBCK			0x24
+#define CLKMGR_PERPLL_MEM			0x28
+#define CLKMGR_PERPLL_MEMSTAT			0x2c
+#define CLKMGR_PERPLL_PLLC0			0x30
+#define CLKMGR_PERPLL_PLLC1			0x34
+#define CLKMGR_PERPLL_VCOCALIB			0x38
+#define CLKMGR_PERPLL_PLLC2			0x3c
+#define CLKMGR_PERPLL_PLLC3			0x40
+#define CLKMGR_PERPLL_PLLM			0x44
+
+/* Altera Group */
+#define CLKMGR_ALTERA				0xffd100d0
+#define CLKMGR_ALTERA_JTAG			0x0
+#define CLKMGR_ALTERA_EMACACTR			0x4
+#define CLKMGR_ALTERA_EMACBCTR			0x8
+#define CLKMGR_ALTERA_EMACPTPCTR		0xc
+#define CLKMGR_ALTERA_GPIODBCTR			0x10
+#define CLKMGR_ALTERA_SDMMCCTR			0x14
+#define CLKMGR_ALTERA_S2FUSER0CTR		0x18
+#define CLKMGR_ALTERA_S2FUSER1CTR		0x1c
+#define CLKMGR_ALTERA_PSIREFCTR			0x20
+#define CLKMGR_ALTERA_EXTCNTRST			0x24
+
+/* Membus */
+#define CLKMGR_MEM_REQ				BIT(24)
+#define CLKMGR_MEM_WR				BIT(25)
+#define CLKMGR_MEM_ERR				BIT(26)
+#define CLKMGR_MEM_WDAT_OFFSET			16
+#define CLKMGR_MEM_ADDR				0x4027
+#define CLKMGR_MEM_WDAT				0x80
+
+/* Clock Manager Macros */
+#define CLKMGR_CTRL_BOOTMODE_SET_MSK		0x00000001
+#define CLKMGR_STAT_BUSY_E_BUSY			0x1
+#define CLKMGR_STAT_BUSY(x)			(((x) & 0x00000001) >> 0)
+#define CLKMGR_STAT_MAINPLLLOCKED(x)		(((x) & 0x00000100) >> 8)
+#define CLKMGR_STAT_PERPLLLOCKED(x)		(((x) & 0x00010000) >> 16)
+#define CLKMGR_INTRCLR_MAINLOCKLOST_SET_MSK	0x00000004
+#define CLKMGR_INTRCLR_PERLOCKLOST_SET_MSK	0x00000008
+
+/* Main PLL Macros */
+#define CLKMGR_MAINPLL_EN_RESET			0x000000ff
+#define CLKMGR_MAINPLL_PLLM_MDIV(x)		((x) & 0x000003ff)
+#define CLKMGR_MAINPLL_PLLGLOB_PD_SET_MSK	0x00000001
+#define CLKMGR_MAINPLL_PLLGLOB_RST_SET_MSK	0x00000002
+
+#define CLKMGR_MAINPLL_PLLGLOB_REFCLKDIV(x)	(((x) & 0x00003f00) >> 8)
+#define CLKMGR_MAINPLL_PLLGLOB_AREFCLKDIV(x)	(((x) & 0x00000f00) >> 8)
+#define CLKMGR_MAINPLL_PLLGLOB_DREFCLKDIV(x)	(((x) & 0x00003000) >> 12)
+
+#define CLKMGR_MAINPLL_PLLGLOB_PSRC(x)		(((x) & 0x00030000) >> 16)
+#define CLKMGR_MAINPLL_PLLGLOB_PSRC_EOSC1	0x0
+#define CLKMGR_MAINPLL_PLLGLOB_PSRC_INTOSC	0x1
+#define CLKMGR_MAINPLL_PLLGLOB_PSRC_F2S		0x2
+#define CLKMGR_MAINPLL_VCOCALIB_HSCNT_SET(x)	(((x) << 0) & 0x000003ff)
+#define CLKMGR_MAINPLL_VCOCALIB_MSCNT_SET(x)	(((x) << 16) & 0x00ff0000)
+
+/* Peripheral PLL Macros */
+#define CLKMGR_PERPLL_EN_RESET			0x00000fff
+#define CLKMGR_PERPLL_PLLM_MDIV(x)		((x) & 0x000003ff)
+#define CLKMGR_PERPLL_GPIODIV_GPIODBCLK_SET(x)	(((x) << 0) & 0x0000ffff)
+#define CLKMGR_PERPLL_PLLGLOB_PD_SET_MSK	0x00000001
+
+#define CLKMGR_PERPLL_PLLGLOB_REFCLKDIV(x)	(((x) & 0x00003f00) >> 8)
+#define CLKMGR_PERPLL_PLLGLOB_AREFCLKDIV(x)	(((x) & 0x00000f00) >> 8)
+#define CLKMGR_PERPLL_PLLGLOB_DREFCLKDIV(x)	(((x) & 0x00003000) >> 12)
+
+#define CLKMGR_PERPLL_PLLGLOB_RST_SET_MSK	0x00000002
+#define CLKMGR_PERPLL_VCOCALIB_HSCNT_SET(x)	(((x) << 0) & 0x000003ff)
+#define CLKMGR_PERPLL_VCOCALIB_MSCNT_SET(x)	(((x) << 16) & 0x00ff0000)
+
+/* Altera Macros */
+#define CLKMGR_ALTERA_EXTCNTRST_RESET		0xff
+
+
+typedef struct {
+	uint32_t  clk_freq_of_eosc1;
+	uint32_t  clk_freq_of_f2h_free;
+	uint32_t  clk_freq_of_cb_intosc_ls;
+} CLOCK_SOURCE_CONFIG;
+
+void config_clkmgr_handoff(handoff *hoff_ptr);
+int get_wdt_clk(handoff *hoff_ptr);
+
+#endif
diff --git a/plat/intel/soc/agilex/include/agilex_handoff.h b/plat/intel/soc/agilex/include/agilex_handoff.h
new file mode 100644
index 0000000..2016406
--- /dev/null
+++ b/plat/intel/soc/agilex/include/agilex_handoff.h
@@ -0,0 +1,96 @@
+/*
+ * Copyright (c) 2019, Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef	HANDOFF_H
+#define	HANDOFF_H
+
+#define HANDOFF_MAGIC_HEADER		0x424f4f54	/* BOOT */
+#define HANDOFF_MAGIC_PINMUX_SEL	0x504d5558	/* PMUX */
+#define HANDOFF_MAGIC_IOCTLR		0x494f4354	/* IOCT */
+#define HANDOFF_MAGIC_FPGA		0x46504741	/* FPGA */
+#define HANDOFF_MAGIC_IODELAY		0x444c4159	/* DLAY */
+#define HANDOFF_MAGIC_CLOCK		0x434c4b53	/* CLKS */
+#define HANDOFF_MAGIC_MISC		0x4d495343	/* MISC */
+
+typedef struct handoff_t {
+	/* header */
+	uint32_t	header_magic;
+	uint32_t	header_device;
+	uint32_t	_pad_0x08_0x10[2];
+
+	/* pinmux configuration - select */
+	uint32_t	pinmux_sel_magic;
+	uint32_t	pinmux_sel_length;
+	uint32_t	_pad_0x18_0x20[2];
+	uint32_t	pinmux_sel_array[96];	/* offset, value */
+
+	/* pinmux configuration - io control */
+	uint32_t	pinmux_io_magic;
+	uint32_t	pinmux_io_length;
+	uint32_t	_pad_0x1a8_0x1b0[2];
+	uint32_t	pinmux_io_array[96];	/* offset, value */
+
+	/* pinmux configuration - use fpga switch */
+	uint32_t	pinmux_fpga_magic;
+	uint32_t	pinmux_fpga_length;
+	uint32_t	_pad_0x338_0x340[2];
+	uint32_t	pinmux_fpga_array[42];	/* offset, value */
+	uint32_t	_pad_0x3e8_0x3f0[2];
+
+	/* pinmux configuration - io delay */
+	uint32_t	pinmux_delay_magic;
+	uint32_t	pinmux_delay_length;
+	uint32_t	_pad_0x3f8_0x400[2];
+	uint32_t	pinmux_iodelay_array[96];	/* offset, value */
+
+	/* clock configuration */
+	uint32_t	clock_magic;
+	uint32_t	clock_length;
+	uint32_t	_pad_0x588_0x590[2];
+	uint32_t	main_pll_mpuclk;
+	uint32_t	main_pll_nocclk;
+	uint32_t	main_pll_nocdiv;
+	uint32_t	main_pll_pllglob;
+	uint32_t	main_pll_fdbck;
+	uint32_t	main_pll_pllc0;
+	uint32_t	main_pll_pllc1;
+	uint32_t	main_pll_pllc2;
+	uint32_t	main_pll_pllc3;
+	uint32_t	main_pll_pllm;
+	uint32_t	per_pll_emacctl;
+	uint32_t	per_pll_gpiodiv;
+	uint32_t	per_pll_pllglob;
+	uint32_t	per_pll_fdbck;
+	uint32_t	per_pll_pllc0;
+	uint32_t	per_pll_pllc1;
+	uint32_t	per_pll_pllc2;
+	uint32_t	per_pll_pllc3;
+	uint32_t	per_pll_pllm;
+	uint32_t	alt_emacactr;
+	uint32_t	alt_emacbctr;
+	uint32_t	alt_emacptpctr;
+	uint32_t	alt_gpiodbctr;
+	uint32_t	alt_sdmmcctr;
+	uint32_t	alt_s2fuser0ctr;
+	uint32_t	alt_s2fuser1ctr;
+	uint32_t	alt_psirefctr;
+	uint32_t	hps_osc_clk_h;
+	uint32_t	fpga_clk_hz;
+	uint32_t	_pad_0x604_0x610[3];
+
+	/* misc configuration */
+	uint32_t	misc_magic;
+	uint32_t	misc_length;
+	uint32_t	_pad_0x618_0x620[2];
+	uint32_t	boot_source;
+} handoff;
+
+int verify_handoff_image(handoff *hoff_ptr, handoff *reverse_hoff_ptr);
+int agilex_get_handoff(handoff *hoff_ptr);
+
+#endif
+
+
diff --git a/plat/intel/soc/agilex/include/agilex_mailbox.h b/plat/intel/soc/agilex/include/agilex_mailbox.h
new file mode 100644
index 0000000..2a21447
--- /dev/null
+++ b/plat/intel/soc/agilex/include/agilex_mailbox.h
@@ -0,0 +1,125 @@
+/*
+ * Copyright (c) 2019, Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef AGX_MBOX_H
+#define AGX_MBOX_H
+
+#define MBOX_OFFSET			0xffa30000
+
+#define MBOX_ATF_CLIENT_ID		0x1
+#define MBOX_JOB_ID			0x1
+
+/* Mailbox interrupt flags and masks */
+#define MBOX_INT_FLAG_COE		0x1
+#define MBOX_INT_FLAG_RIE		0x2
+#define MBOX_INT_FLAG_UAE		0x100
+#define MBOX_COE_BIT(INTERRUPT)		((INTERRUPT) & 0x3)
+#define MBOX_UAE_BIT(INTERRUPT)		(((INTERRUPT) & (1<<8)))
+
+/* Mailbox response and status */
+#define MBOX_RESP_BUFFER_SIZE		16
+#define MBOX_RESP_ERR(BUFFER)		((BUFFER) & 0x00000fff)
+#define MBOX_RESP_LEN(BUFFER)		(((BUFFER) & 0x007ff000) >> 12)
+#define MBOX_RESP_CLIENT_ID(BUFFER)	(((BUFFER) & 0xf0000000) >> 28)
+#define MBOX_RESP_JOB_ID(BUFFER)	(((BUFFER) & 0x0f000000) >> 24)
+#define MBOX_STATUS_UA_MASK		(1<<8)
+
+/* Mailbox command and response */
+#define MBOX_CMD_FREE_OFFSET		0x14
+#define MBOX_CMD_BUFFER_SIZE		32
+#define MBOX_CLIENT_ID_CMD(CLIENT_ID)	((CLIENT_ID) << 28)
+#define MBOX_JOB_ID_CMD(JOB_ID)		(JOB_ID<<24)
+#define MBOX_CMD_LEN_CMD(CMD_LEN)	((CMD_LEN) << 12)
+#define MBOX_INDIRECT			(1 << 11)
+#define MBOX_INSUFFICIENT_BUFFER	-2
+#define MBOX_CIN			0x00
+#define MBOX_ROUT			0x04
+#define MBOX_URG			0x08
+#define MBOX_INT			0x0C
+#define MBOX_COUT			0x20
+#define MBOX_RIN			0x24
+#define MBOX_STATUS			0x2C
+#define MBOX_CMD_BUFFER			0x40
+#define MBOX_RESP_BUFFER		0xC0
+
+#define MBOX_RESP_BUFFER_SIZE		16
+#define MBOX_RESP_OK			0
+#define MBOX_RESP_INVALID_CMD		1
+#define MBOX_RESP_UNKNOWN_BR		2
+#define MBOX_RESP_UNKNOWN		3
+#define MBOX_RESP_NOT_CONFIGURED	256
+
+/* Mailbox SDM doorbell */
+#define MBOX_DOORBELL_TO_SDM		0x400
+#define MBOX_DOORBELL_FROM_SDM		0x480
+
+/* Mailbox QSPI commands */
+#define MBOX_CMD_RESTART		2
+#define MBOX_CMD_QSPI_OPEN		50
+#define MBOX_CMD_QSPI_CLOSE		51
+#define MBOX_CMD_QSPI_DIRECT		59
+#define MBOX_CMD_GET_IDCODE		16
+#define MBOX_CMD_QSPI_SET_CS		52
+
+/* Mailbox REBOOT commands */
+#define MBOX_CMD_REBOOT_HPS		71
+
+/* Generic error handling */
+#define MBOX_TIMEOUT			-2047
+#define MBOX_NO_RESPONSE		-2
+#define MBOX_WRONG_ID			-3
+
+/* Mailbox status */
+#define RECONFIG_STATUS_STATE		0
+#define RECONFIG_STATUS_PIN_STATUS	2
+#define RECONFIG_STATUS_SOFTFUNC_STATUS 3
+#define PIN_STATUS_NSTATUS		(1 << 31)
+#define SOFTFUNC_STATUS_SEU_ERROR	(1 << 3)
+#define SOFTFUNC_STATUS_INIT_DONE	(1 << 1)
+#define SOFTFUNC_STATUS_CONF_DONE	(1 << 0)
+#define MBOX_CFGSTAT_STATE_CONFIG	0x10000000
+
+/* SMC function IDs for SiP Service queries */
+#define SIP_SVC_CALL_COUNT	0x8200ff00
+#define SIP_SVC_UID		0x8200ff01
+#define SIP_SVC_VERSION		0x8200ff03
+
+/* SiP Service Calls version numbers */
+#define SIP_SVC_VERSION_MAJOR	0
+#define SIP_SVC_VERSION_MINOR	1
+
+/* Mailbox reconfiguration commands */
+#define MBOX_RECONFIG		6
+#define MBOX_RECONFIG_DATA	8
+#define MBOX_RECONFIG_STATUS	9
+
+/* Sip get memory */
+#define INTEL_SIP_SMC_FPGA_CONFIG_START			0xC2000001
+#define INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM		0xC2000005
+#define INTEL_SIP_SMC_FPGA_CONFIG_ISDONE		0xC2000004
+#define INTEL_SIP_SMC_FPGA_CONFIG_WRITE			0x42000002
+#define INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE	0xC2000003
+#define INTEL_SIP_SMC_STATUS_OK				0
+#define INTEL_SIP_SMC_STATUS_ERROR			0x4
+#define INTEL_SIP_SMC_STATUS_BUSY			0x1
+#define INTEL_SIP_SMC_STATUS_REJECTED			0x2
+#define INTEL_SIP_SMC_FPGA_CONFIG_ADDR			0x1000
+#define INTEL_SIP_SMC_FPGA_CONFIG_SIZE			16777216
+
+void mailbox_set_int(int interrupt_input);
+int mailbox_init(void);
+void mailbox_set_qspi_close(void);
+void mailbox_set_qspi_open(void);
+void mailbox_set_qspi_direct(void);
+int mailbox_send_cmd(int job_id, unsigned int cmd, uint32_t *args,
+				int len, int urgent, uint32_t *response);
+void mailbox_send_cmd_async(int job_id, unsigned int cmd, uint32_t *args,
+				int len, int urgent);
+int mailbox_read_response(int job_id, uint32_t *response);
+int mailbox_get_qspi_clock(void);
+void mailbox_reset_cold(void);
+
+#endif
diff --git a/plat/intel/soc/agilex/include/agilex_memory_controller.h b/plat/intel/soc/agilex/include/agilex_memory_controller.h
new file mode 100644
index 0000000..c0c94e6
--- /dev/null
+++ b/plat/intel/soc/agilex/include/agilex_memory_controller.h
@@ -0,0 +1,162 @@
+/*
+ * Copyright (c) 2019, Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef AGX_MEMORYCONTROLLER_H
+#define AGX_MEMORYCONTROLLER_H
+
+#define AGX_MPFE_IOHMC_REG_DRAMADDRW			0xf80100a8
+#define AGX_MPFE_IOHMC_CTRLCFG0				0xf8010028
+#define AGX_MPFE_IOHMC_CTRLCFG1				0xf801002c
+#define AGX_MPFE_IOHMC_DRAMADDRW			0xf80100a8
+#define AGX_MPFE_IOHMC_DRAMTIMING0			0xf8010050
+#define AGX_MPFE_IOHMC_CALTIMING0			0xf801007c
+#define AGX_MPFE_IOHMC_CALTIMING1			0xf8010080
+#define AGX_MPFE_IOHMC_CALTIMING2			0xf8010084
+#define AGX_MPFE_IOHMC_CALTIMING3			0xf8010088
+#define AGX_MPFE_IOHMC_CALTIMING4			0xf801008c
+#define AGX_MPFE_IOHMC_CALTIMING9			0xf80100a0
+#define AGX_MPFE_IOHMC_CALTIMING9_ACT_TO_ACT(x) (((x) & 0x000000ff) >> 0)
+#define AGX_MPFE_IOHMC_CTRLCFG1_CFG_ADDR_ORDER(value)	\
+						(((value) & 0x00000060) >> 5)
+
+#define AGX_RSTMGR_BRGMODRST				0xffd1102c
+#define AGX_RSTMGR_BRGMODRST_DDRSCH			0x00000040
+
+#define AGX_MPFE_HMC_ADP_ECCCTRL1			0xf8011100
+#define AGX_MPFE_HMC_ADP_ECCCTRL2			0xf8011104
+#define AGX_MPFE_HMC_ADP_RSTHANDSHAKESTAT		0xf8011218
+#define AGX_MPFE_HMC_ADP_RSTHANDSHAKESTAT_SEQ2CORE	0x000000ff
+#define AGX_MPFE_HMC_ADP_RSTHANDSHAKECTRL		0xf8011214
+
+
+#define AGX_MPFE_IOHMC_REG_CTRLCFG1			0xf801002c
+
+#define AGX_MPFE_IOHMC_REG_NIOSRESERVE0_OFST		0xf8010110
+
+#define IOHMC_DRAMADDRW_COL_ADDR_WIDTH(x)	(((x) & 0x0000001f) >> 0)
+#define IOHMC_DRAMADDRW_ROW_ADDR_WIDTH(x)	(((x) & 0x000003e0) >> 5)
+#define IOHMC_DRAMADDRW_CS_ADDR_WIDTH(x)	(((x) & 0x00070000) >> 16)
+#define IOHMC_DRAMADDRW_BANK_GRP_ADDR_WIDTH(x)	(((x) & 0x0000c000) >> 14)
+#define IOHMC_DRAMADDRW_BANK_ADDR_WIDTH(x)	(((x) & 0x00003c00) >> 10)
+
+#define AGX_MPFE_DDR(x)					(0xf8000000 + x)
+#define AGX_MPFE_HMC_ADP_DDRCALSTAT			0xf801100c
+#define AGX_MPFE_DDR_MAIN_SCHED				0xf8000400
+#define AGX_MPFE_DDR_MAIN_SCHED_DDRCONF			0xf8000408
+#define AGX_MPFE_DDR_MAIN_SCHED_DDRTIMING		0xf800040c
+#define AGX_MPFE_DDR_MAIN_SCHED_DDRCONF_SET_MSK		0x0000001f
+#define AGX_MPFE_DDR_MAIN_SCHED_DDRMODE			0xf8000410
+#define AGX_MPFE_DDR_MAIN_SCHED_DEVTODEV		0xf800043c
+#define AGX_MPFE_DDR_MAIN_SCHED_READLATENCY		0xf8000414
+#define AGX_MPFE_DDR_MAIN_SCHED_ACTIVATE		0xf8000438
+#define AGX_MPFE_DDR_MAIN_SCHED_ACTIVATE_FAWBANK_OFST	10
+#define AGX_MPFE_DDR_MAIN_SCHED_ACTIVATE_FAW_OFST	4
+#define AGX_MPFE_DDR_MAIN_SCHED_ACTIVATE_RRD_OFST	0
+#define AGX_MPFE_DDR_MAIN_SCHED_DDRCONF_SET(x)	(((x) << 0) & 0x0000001f)
+#define AGX_MPFE_DDR_MAIN_SCHED_DEVTODEV_BUSRDTORD_OFST	0
+#define AGX_MPFE_DDR_MAIN_SCHED_DEVTODEV_BUSRDTORD_MSK	(BIT(0) | BIT(1))
+#define AGX_MPFE_DDR_MAIN_SCHED_DEVTODEV_BUSRDTOWR_OFST	2
+#define AGX_MPFE_DDR_MAIN_SCHED_DEVTODEV_BUSRDTOWR_MSK	(BIT(2) | BIT(3))
+#define AGX_MPFE_DDR_MAIN_SCHED_DEVTODEV_BUSWRTORD_OFST	4
+#define AGX_MPFE_DDR_MAIN_SCHED_DEVTODEV_BUSWRTORD_MSK	(BIT(4) | BIT(5))
+
+#define AGX_MPFE_HMC_ADP(x)				(0xf8011000 + (x))
+#define AGX_MPFE_HMC_ADP_HPSINTFCSEL			0xf8011210
+#define AGX_MPFE_HMC_ADP_DDRIOCTRL			0xf8011008
+#define HMC_ADP_DDRIOCTRL				0x8
+#define HMC_ADP_DDRIOCTRL_IO_SIZE(x)		(((x) & 0x00000003) >> 0)
+#define HMC_ADP_DDRIOCTRL_CTRL_BURST_LENGTH(x)	(((x) & 0x00003e00) >> 9)
+#define ADP_DRAMADDRWIDTH				0xe0
+
+#define ACT_TO_ACT_DIFF_BANK(value)		(((value) & 0x00fc0000) >> 18)
+#define ACT_TO_ACT(value)			(((value) & 0x0003f000) >> 12)
+#define ACT_TO_RDWR(value)			(((value) & 0x0000003f) >> 0)
+#define ACT_TO_ACT(value)			(((value) & 0x0003f000) >> 12)
+
+/* timing 2 */
+#define RD_TO_RD_DIFF_CHIP(value)		(((value) & 0x00000fc0) >> 6)
+#define RD_TO_WR_DIFF_CHIP(value)		(((value) & 0x3f000000) >> 24)
+#define RD_TO_WR(value)				(((value) & 0x00fc0000) >> 18)
+#define RD_TO_PCH(value)			(((value) & 0x00000fc0) >> 6)
+
+/* timing 3 */
+#define CALTIMING3_WR_TO_RD_DIFF_CHIP(value)	(((value) & 0x0003f000) >> 12)
+#define CALTIMING3_WR_TO_RD(value)		(((value) & 0x00000fc0) >> 6)
+
+/* timing 4 */
+#define PCH_TO_VALID(value)			(((value) & 0x00000fc0) >> 6)
+
+#define DDRTIMING_BWRATIO_OFST				31
+#define DDRTIMING_WRTORD_OFST				26
+#define DDRTIMING_RDTOWR_OFST				21
+#define DDRTIMING_BURSTLEN_OFST				18
+#define DDRTIMING_WRTOMISS_OFST				12
+#define DDRTIMING_RDTOMISS_OFST				6
+#define DDRTIMING_ACTTOACT_OFST				0
+
+#define ADP_DDRIOCTRL_IO_SIZE(x)			(((x) & 0x3) >> 0)
+
+#define DDRMODE_AUTOPRECHARGE_OFST			1
+#define DDRMODE_BWRATIOEXTENDED_OFST			0
+
+
+#define AGX_MPFE_IOHMC_REG_DRAMTIMING0_CFG_TCL(x)	(((x) & 0x7f) >> 0)
+#define AGX_MPFE_IOHMC_REG_CTRLCFG0_CFG_MEM_TYPE(x)	(((x) & 0x0f) >> 0)
+
+#define AGX_CCU_CPU0_MPRT_DDR				0xf7004400
+#define AGX_CCU_CPU0_MPRT_MEM0				0xf70045c0
+#define AGX_CCU_CPU0_MPRT_MEM1A				0xf70045e0
+#define AGX_CCU_CPU0_MPRT_MEM1B				0xf7004600
+#define AGX_CCU_CPU0_MPRT_MEM1C				0xf7004620
+#define AGX_CCU_CPU0_MPRT_MEM1D				0xf7004640
+#define AGX_CCU_CPU0_MPRT_MEM1E				0xf7004660
+#define AGX_CCU_IOM_MPRT_MEM0				0xf7018560
+#define AGX_CCU_IOM_MPRT_MEM1A				0xf7018580
+#define	AGX_CCU_IOM_MPRT_MEM1B				0xf70185a0
+#define	AGX_CCU_IOM_MPRT_MEM1C				0xf70185c0
+#define	AGX_CCU_IOM_MPRT_MEM1D				0xf70185e0
+#define	AGX_CCU_IOM_MPRT_MEM1E				0xf7018600
+
+#define AGX_NOC_FW_DDR_SCR				0xf8020200
+#define AGX_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMITEXT	0xf802021c
+#define AGX_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT		0xf8020218
+#define AGX_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT	0xf802029c
+#define AGX_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT	0xf8020298
+
+#define AGX_SOC_NOC_FW_DDR_SCR_ENABLE			0xf8020200
+#define AGX_CCU_NOC_DI_SET_MSK				0x10
+
+#define AGX_SYSMGR_CORE_HMC_CLK				0xffd120b4
+#define AGX_SYSMGR_CORE_HMC_CLK_STATUS			0x00000001
+
+#define AGX_MPFE_IOHMC_NIOSRESERVE0_NIOS_RESERVE0(x)	(((x) & 0xffff) >> 0)
+#define AGX_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE_MSK		0x00000003
+#define AGX_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE_OFST		0
+#define AGX_MPFE_HMC_ADP_HPSINTFCSEL_ENABLE		0x001f1f1f
+#define AGX_IOHMC_CTRLCFG1_ENABLE_ECC_OFST		7
+
+#define AGX_MPFE_HMC_ADP_ECCCTRL1_AUTOWB_CNT_RST_SET_MSK	0x00010000
+#define AGX_MPFE_HMC_ADP_ECCCTRL1_CNT_RST_SET_MSK		0x00000100
+#define AGX_MPFE_HMC_ADP_ECCCTRL1_ECC_EN_SET_MSK		0x00000001
+
+#define AGX_MPFE_HMC_ADP_ECCCTRL2_AUTOWB_EN_SET_MSK		0x00000001
+#define AGX_MPFE_HMC_ADP_ECCCTRL2_OVRW_RB_ECC_EN_SET_MSK	0x00010000
+#define AGX_MPFE_HMC_ADP_ECCCTRL2_RMW_EN_SET_MSK		0x00000100
+#define AGX_MPFE_HMC_ADP_DDRCALSTAT_CAL(value)		(((value) & 0x1) >> 0)
+
+
+#define AGX_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE(x)		(((x) & 0x00003) >> 0)
+#define IOHMC_DRAMADDRW_CFG_BANK_ADDR_WIDTH(x)		(((x) & 0x03c00) >> 10)
+#define IOHMC_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH(x)	(((x) & 0x0c000) >> 14)
+#define IOHMC_DRAMADDRW_CFG_COL_ADDR_WIDTH(x)		(((x) & 0x0001f) >> 0)
+#define IOHMC_DRAMADDRW_CFG_CS_ADDR_WIDTH(x)		(((x) & 0x70000) >> 16)
+#define IOHMC_DRAMADDRW_CFG_ROW_ADDR_WIDTH(x)		(((x) & 0x003e0) >> 5)
+
+#define AGX_SDRAM_0_LB_ADDR				0x0
+
+int init_hard_memory_controller(void);
+
+#endif
diff --git a/plat/intel/soc/agilex/include/agilex_noc.h b/plat/intel/soc/agilex/include/agilex_noc.h
new file mode 100644
index 0000000..22db3e2
--- /dev/null
+++ b/plat/intel/soc/agilex/include/agilex_noc.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2019, Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef AGX_NOC_H
+#define AGX_NOC_H
+
+
+#define AXI_AP					(1<<0)
+#define FPGA2SOC				(1<<16)
+#define MPU					(1<<24)
+#define AGX_NOC_PER_SCR_NAND			0xffd21000
+#define AGX_NOC_PER_SCR_NAND_DATA		0xffd21004
+#define AGX_NOC_PER_SCR_USB0			0xffd2100c
+#define AGX_NOC_PER_SCR_USB1			0xffd21010
+#define AGX_NOC_PER_SCR_SPI_M0			0xffd2101c
+#define AGX_NOC_PER_SCR_SPI_M1			0xffd21020
+#define AGX_NOC_PER_SCR_SPI_S0			0xffd21024
+#define AGX_NOC_PER_SCR_SPI_S1			0xffd21028
+#define AGX_NOC_PER_SCR_EMAC0			0xffd2102c
+#define AGX_NOC_PER_SCR_EMAC1			0xffd21030
+#define AGX_NOC_PER_SCR_EMAC2			0xffd21034
+#define AGX_NOC_PER_SCR_SDMMC			0xffd21040
+#define AGX_NOC_PER_SCR_GPIO0			0xffd21044
+#define AGX_NOC_PER_SCR_GPIO1			0xffd21048
+#define AGX_NOC_PER_SCR_I2C0			0xffd21050
+#define AGX_NOC_PER_SCR_I2C1			0xffd21058
+#define AGX_NOC_PER_SCR_I2C2			0xffd2105c
+#define AGX_NOC_PER_SCR_I2C3			0xffd21060
+#define AGX_NOC_PER_SCR_SP_TIMER0		0xffd21064
+#define AGX_NOC_PER_SCR_SP_TIMER1		0xffd21068
+#define AGX_NOC_PER_SCR_UART0			0xffd2106c
+#define AGX_NOC_PER_SCR_UART1			0xffd21070
+
+
+#define AGX_NOC_SYS_SCR_DMA_ECC			0xffd21108
+#define AGX_NOC_SYS_SCR_EMAC0RX_ECC		0xffd2110c
+#define AGX_NOC_SYS_SCR_EMAC0TX_ECC		0xffd21110
+#define AGX_NOC_SYS_SCR_EMAC1RX_ECC		0xffd21114
+#define AGX_NOC_SYS_SCR_EMAC1TX_ECC		0xffd21118
+#define AGX_NOC_SYS_SCR_EMAC2RX_ECC		0xffd2111c
+#define AGX_NOC_SYS_SCR_EMAC2TX_ECC		0xffd21120
+#define AGX_NOC_SYS_SCR_NAND_ECC		0xffd2112c
+#define AGX_NOC_SYS_SCR_NAND_READ_ECC		0xffd21130
+#define AGX_NOC_SYS_SCR_NAND_WRITE_ECC		0xffd21134
+#define AGX_NOC_SYS_SCR_OCRAM_ECC		0xffd21138
+#define AGX_NOC_SYS_SCR_SDMMC_ECC		0xffd21140
+#define AGX_NOC_SYS_SCR_USB0_ECC		0xffd21144
+#define AGX_NOC_SYS_SCR_USB1_ECC		0xffd21148
+#define AGX_NOC_SYS_SCR_CLK_MGR			0xffd2114c
+#define AGX_NOC_SYS_SCR_IO_MGR			0xffd21154
+#define AGX_NOC_SYS_SCR_RST_MGR			0xffd21158
+#define AGX_NOC_SYS_SCR_SYS_MGR			0xffd2115c
+#define AGX_NOC_SYS_SCR_OSC0_TIMER		0xffd21160
+#define AGX_NOC_SYS_SCR_OSC1_TIMER		0xffd21164
+#define AGX_NOC_SYS_SCR_WATCHDOG0		0xffd21168
+#define AGX_NOC_SYS_SCR_WATCHDOG1		0xffd2116c
+#define AGX_NOC_SYS_SCR_WATCHDOG2		0xffd21170
+#define AGX_NOC_SYS_SCR_WATCHDOG3		0xffd21174
+#define AGX_NOC_SYS_SCR_DAP			0xffd21178
+#define AGX_NOC_SYS_SCR_L4_NOC_PROBES		0xffd21190
+#define AGX_NOC_SYS_SCR_L4_NOC_QOS		0xffd21194
+
+#define AGX_CCU_NOC_BRIDGE_CPU0_RAM		0xf7004688
+#define AGX_CCU_NOC_BRIDGE_IOM_RAM		0xf7004688
+
+#endif
diff --git a/plat/intel/soc/agilex/include/agilex_pinmux.h b/plat/intel/soc/agilex/include/agilex_pinmux.h
new file mode 100644
index 0000000..e6a7b34
--- /dev/null
+++ b/plat/intel/soc/agilex/include/agilex_pinmux.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2019, Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef AGX_PINMUX_H
+#define AGX_PINMUX_H
+
+#define AGX_PINMUX_PIN0SEL		0xffd13000
+#define AGX_PINMUX_IO0CTRL		0xffd13130
+#define AGX_PINMUX_PINMUX_EMAC0_USEFPGA	0xffd13300
+#define AGX_PINMUX_IO0_DELAY		0xffd13400
+
+#include "agilex_handoff.h"
+
+void config_pinmux(handoff *handoff);
+
+#endif
+
diff --git a/plat/intel/soc/agilex/include/agilex_private.h b/plat/intel/soc/agilex/include/agilex_private.h
new file mode 100644
index 0000000..5ccbc8c
--- /dev/null
+++ b/plat/intel/soc/agilex/include/agilex_private.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2019, Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef AGX_PRIVATE_H
+#define AGX_PRIVATE_H
+
+#define AGX_MMC_REG_BASE	0xff808000
+
+#define EMMC_DESC_SIZE		(1<<20)
+#define EMMC_INIT_PARAMS(base)			\
+	{	.bus_width = MMC_BUS_WIDTH_4,	\
+		.clk_rate = 50000000,		\
+		.desc_base = (base),		\
+		.desc_size = EMMC_DESC_SIZE,	\
+		.flags = 0,			\
+		.reg_base = AGX_MMC_REG_BASE,	\
+		\
+	}
+
+typedef enum {
+	BOOT_SOURCE_FPGA = 0,
+	BOOT_SOURCE_SDMMC,
+	BOOT_SOURCE_NAND,
+	BOOT_SOURCE_RSVD,
+	BOOT_SOURCE_QSPI,
+} boot_source_type;
+
+void enable_nonsecure_access(void);
+void socfpga_io_setup(int boot_source);
+
+#endif
diff --git a/plat/intel/soc/agilex/include/agilex_reset_manager.h b/plat/intel/soc/agilex/include/agilex_reset_manager.h
new file mode 100644
index 0000000..a1b6297
--- /dev/null
+++ b/plat/intel/soc/agilex/include/agilex_reset_manager.h
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2019, Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef AGX_RESETMANAGER_H
+#define AGX_RESETMANAGER_H
+
+#define AGX_RSTMGR_HDSKEN				0xffd11010
+#define AGX_RSTMGR_PER0MODRST				0xffd11024
+#define AGX_RSTMGR_PER1MODRST				0xffd11028
+#define AGX_RSTMGR_BRGMODRST				0xffd1102c
+
+#define AGX_RSTMGR_PER0MODRST_EMAC0			0x00000001
+#define AGX_RSTMGR_PER0MODRST_EMAC1			0x00000002
+#define AGX_RSTMGR_PER0MODRST_EMAC2			0x00000004
+#define AGX_RSTMGR_PER0MODRST_USB0			0x00000008
+#define AGX_RSTMGR_PER0MODRST_USB1			0x00000010
+#define AGX_RSTMGR_PER0MODRST_NAND			0x00000020
+#define AGX_RSTMGR_PER0MODRST_SDMMC			0x00000080
+#define AGX_RSTMGR_PER0MODRST_EMAC0OCP			0x00000100
+#define AGX_RSTMGR_PER0MODRST_EMAC1OCP			0x00000200
+#define AGX_RSTMGR_PER0MODRST_EMAC2OCP			0x00000400
+#define AGX_RSTMGR_PER0MODRST_USB0OCP			0x00000800
+#define AGX_RSTMGR_PER0MODRST_USB1OCP			0x00001000
+#define AGX_RSTMGR_PER0MODRST_NANDOCP			0x00002000
+#define AGX_RSTMGR_PER0MODRST_SDMMCOCP			0x00008000
+#define AGX_RSTMGR_PER0MODRST_DMA			0x00010000
+#define AGX_RSTMGR_PER0MODRST_SPIM0			0x00020000
+#define AGX_RSTMGR_PER0MODRST_SPIM1			0x00040000
+#define AGX_RSTMGR_PER0MODRST_SPIS0			0x00080000
+#define AGX_RSTMGR_PER0MODRST_SPIS1			0x00100000
+#define AGX_RSTMGR_PER0MODRST_DMAOCP			0x00200000
+#define AGX_RSTMGR_PER0MODRST_EMACPTP			0x00400000
+#define AGX_RSTMGR_PER0MODRST_DMAIF0			0x01000000
+#define AGX_RSTMGR_PER0MODRST_DMAIF1			0x02000000
+#define AGX_RSTMGR_PER0MODRST_DMAIF2			0x04000000
+#define AGX_RSTMGR_PER0MODRST_DMAIF3			0x08000000
+#define AGX_RSTMGR_PER0MODRST_DMAIF4			0x10000000
+#define AGX_RSTMGR_PER0MODRST_DMAIF5			0x20000000
+#define AGX_RSTMGR_PER0MODRST_DMAIF6			0x40000000
+#define AGX_RSTMGR_PER0MODRST_DMAIF7			0x80000000
+
+#define AGX_RSTMGR_PER1MODRST_WATCHDOG0			0x1
+#define AGX_RSTMGR_PER1MODRST_WATCHDOG1			0x2
+#define AGX_RSTMGR_PER1MODRST_WATCHDOG2			0x4
+#define AGX_RSTMGR_PER1MODRST_WATCHDOG3			0x8
+#define AGX_RSTMGR_PER1MODRST_L4SYSTIMER0		0x00000010
+#define AGX_RSTMGR_PER1MODRST_L4SYSTIMER1		0x00000020
+#define AGX_RSTMGR_PER1MODRST_SPTIMER0			0x00000040
+#define AGX_RSTMGR_PER1MODRST_SPTIMER1			0x00000080
+#define AGX_RSTMGR_PER1MODRST_I2C0			0x00000100
+#define AGX_RSTMGR_PER1MODRST_I2C1			0x00000200
+#define AGX_RSTMGR_PER1MODRST_I2C2			0x00000400
+#define AGX_RSTMGR_PER1MODRST_I2C3			0x00000800
+#define AGX_RSTMGR_PER1MODRST_I2C4			0x00001000
+#define AGX_RSTMGR_PER1MODRST_UART0			0x00010000
+#define AGX_RSTMGR_PER1MODRST_UART1			0x00020000
+#define AGX_RSTMGR_PER1MODRST_GPIO0			0x01000000
+#define AGX_RSTMGR_PER1MODRST_GPIO1			0x02000000
+
+#define AGX_RSTMGR_HDSKEN_FPGAHSEN			0x00000004
+#define AGX_RSTMGR_HDSKEN_ETRSTALLEN			0x00000008
+#define AGX_RSTMGR_HDSKEN_L2FLUSHEN			0x00000100
+#define AGX_RSTMGR_HDSKEN_L3NOC_DBG			0x00010000
+#define AGX_RSTMGR_HDSKEN_DEBUG_L3NOC			0x00020000
+#define AGX_RSTMGR_HDSKEN_SDRSELFREFEN			0x00000001
+
+#define AGX_RSTMGR_BRGMODRST_SOC2FPGA			0x1
+#define AGX_RSTMGR_BRGMODRST_LWHPS2FPGA			0x2
+#define AGX_RSTMGR_BRGMODRST_FPGA2SOC			0x4
+#define AGX_RSTMGR_BRGMODRST_MPFE			0x40
+
+void deassert_peripheral_reset(void);
+void config_hps_hs_before_warm_reset(void);
+
+#endif
+
diff --git a/plat/intel/soc/agilex/include/agilex_system_manager.h b/plat/intel/soc/agilex/include/agilex_system_manager.h
new file mode 100644
index 0000000..6ec2084
--- /dev/null
+++ b/plat/intel/soc/agilex/include/agilex_system_manager.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2019, Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef AGX_SYSTEMMANAGER_H
+#define AGX_SYSTEMMANAGER_H
+
+#define AGX_FIREWALL_SOC2FPGA			0xffd21200
+#define AGX_FIREWALL_LWSOC2FPGA			0xffd21300
+
+#define AGX_NOC_FW_L4_PER_SCR_NAND_REGISTER	0xffd21000
+#define AGX_NOC_FW_L4_PER_SCR_NAND_DATA		0xffd21004
+#define AGX_NOC_FW_L4_PER_SCR_USB0_REGISTER	0xffd2100c
+#define AGX_NOC_FW_L4_PER_SCR_USB1_REGISTER	0xffd21010
+#define AGX_NOC_FW_L4_PER_SCR_SPI_MASTER0	0xffd2101c
+#define AGX_NOC_FW_L4_PER_SCR_SPI_MASTER1	0xffd21020
+#define AGX_NOC_FW_L4_PER_SCR_SPI_SLAVE0	0xffd21024
+#define AGX_NOC_FW_L4_PER_SCR_SPI_SLAVE1	0xffd21028
+#define AGX_NOC_FW_L4_PER_SCR_EMAC0		0xffd2102c
+#define AGX_NOC_FW_L4_PER_SCR_EMAC1		0xffd21030
+#define AGX_NOC_FW_L4_PER_SCR_EMAC2		0xffd21034
+#define AGX_NOC_FW_L4_PER_SCR_SDMMC		0xffd21040
+#define AGX_NOC_FW_L4_PER_SCR_GPIO0		0xffd21044
+#define AGX_NOC_FW_L4_PER_SCR_GPIO1		0xffd21048
+#define AGX_NOC_FW_L4_PER_SCR_I2C0		0xffd21050
+#define AGX_NOC_FW_L4_PER_SCR_I2C1		0xffd21054
+#define AGX_NOC_FW_L4_PER_SCR_I2C2		0xffd21058
+#define AGX_NOC_FW_L4_PER_SCR_I2C3		0xffd2105c
+#define AGX_NOC_FW_L4_PER_SCR_I2C4		0xffd21060
+#define AGX_NOC_FW_L4_PER_SCR_SP_TIMER0		0xffd21064
+#define AGX_NOC_FW_L4_PER_SCR_SP_TIMER1		0xffd21068
+#define AGX_NOC_FW_L4_PER_SCR_UART0		0xffd2106c
+#define AGX_NOC_FW_L4_PER_SCR_UART1		0xffd21070
+
+#define AGX_NOC_FW_L4_SYS_SCR_DMA_ECC		0xffd21108
+#define AGX_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC	0xffd2110c
+#define AGX_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC	0xffd21110
+#define AGX_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC	0xffd21114
+#define AGX_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC	0xffd21118
+#define AGX_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC	0xffd2111c
+#define AGX_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC	0xffd21120
+#define AGX_NOC_FW_L4_SYS_SCR_NAND_ECC		0xffd2112c
+#define AGX_NOC_FW_L4_SYS_SCR_NAND_READ_ECC	0xffd21130
+#define AGX_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC	0xffd21134
+#define AGX_NOC_FW_L4_SYS_SCR_OCRAM_ECC		0xffd21138
+#define AGX_NOC_FW_L4_SYS_SCR_SDMMC_ECC		0xffd21140
+#define AGX_NOC_FW_L4_SYS_SCR_USB0_ECC		0xffd21144
+#define AGX_NOC_FW_L4_SYS_SCR_USB1_ECC		0xffd21148
+#define AGX_NOC_FW_L4_SYS_SCR_CLK_MGR		0xffd2114c
+#define AGX_NOC_FW_L4_SYS_SCR_IO_MGR		0xffd21154
+#define AGX_NOC_FW_L4_SYS_SCR_RST_MGR		0xffd21158
+#define AGX_NOC_FW_L4_SYS_SCR_SYS_MGR		0xffd2115c
+#define AGX_NOC_FW_L4_SYS_SCR_OSC0_TIMER	0xffd21160
+#define AGX_NOC_FW_L4_SYS_SCR_OSC1_TIMER	0xffd21164
+#define AGX_NOC_FW_L4_SYS_SCR_WATCHDOG0		0xffd21168
+#define AGX_NOC_FW_L4_SYS_SCR_WATCHDOG1		0xffd2116c
+#define AGX_NOC_FW_L4_SYS_SCR_WATCHDOG2		0xffd21170
+#define AGX_NOC_FW_L4_SYS_SCR_WATCHDOG3		0xffd21174
+#define AGX_NOC_FW_L4_SYS_SCR_DAP		0xffd21178
+#define AGX_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES	0xffd21190
+#define AGX_NOC_FW_L4_SYS_SCR_L4_NOC_QOS	0xffd21194
+
+#define AGX_CCU_NOC_CPU0_RAMSPACE0_0		0xf7004688
+#define AGX_CCU_NOC_IOM_RAMSPACE0_0		0xf7018628
+
+#define DISABLE_BRIDGE_FIREWALL			0x0ffe0101
+#define DISABLE_L4_FIREWALL	(BIT(0) | BIT(16) | BIT(24))
+
+void enable_nonsecure_access(void);
+void enable_ns_bridge_access(void);
+
+#endif
diff --git a/plat/intel/soc/agilex/include/plat_macros.S b/plat/intel/soc/agilex/include/plat_macros.S
new file mode 100644
index 0000000..43db9a2
--- /dev/null
+++ b/plat/intel/soc/agilex/include/plat_macros.S
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2019, Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLAT_MACROS_S
+#define PLAT_MACROS_S
+
+#include <platform_def.h>
+
+	/* ---------------------------------------------
+	 * The below required platform porting macro
+	 * prints out relevant platform registers
+	 * whenever an unhandled exception is taken in
+	 * BL31.
+	 * ---------------------------------------------
+	 */
+	.macro plat_crash_print_regs
+	.endm
+
+#endif /* PLAT_MACROS_S */
diff --git a/plat/intel/soc/agilex/include/platform_def.h b/plat/intel/soc/agilex/include/platform_def.h
new file mode 100644
index 0000000..10f7338
--- /dev/null
+++ b/plat/intel/soc/agilex/include/platform_def.h
@@ -0,0 +1,196 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2019, Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
+
+#include <arch.h>
+#include <common/interrupt_props.h>
+#include <common/tbbr/tbbr_img_def.h>
+#include <plat/common/common_def.h>
+
+
+#define PLAT_CPUID_RELEASE			0xffe1b000
+#define PLAT_AGX_SEC_ENTRY			0xffe1b008
+
+/* Define next boot image name and offset */
+#define PLAT_NS_IMAGE_OFFSET			0x50000
+#define PLAT_HANDOFF_OFFSET			0xFFE3F000
+
+/*******************************************************************************
+ * Platform binary types for linking
+ ******************************************************************************/
+#define PLATFORM_LINKER_FORMAT			"elf64-littleaarch64"
+#define PLATFORM_LINKER_ARCH			aarch64
+
+/* Agilex supports up to 124GB RAM */
+#define PLAT_PHY_ADDR_SPACE_SIZE		(1ULL << 39)
+#define PLAT_VIRT_ADDR_SPACE_SIZE		(1ULL << 39)
+
+
+/*******************************************************************************
+ * Generic platform constants
+ ******************************************************************************/
+#define PLAT_PRIMARY_CPU			0
+#define PLAT_SECONDARY_ENTRY_BASE		0x01f78bf0
+
+/* Size of cacheable stacks */
+#define PLATFORM_STACK_SIZE			0x2000
+
+/* PSCI related constant */
+#define PLAT_NUM_POWER_DOMAINS			5
+#define PLAT_MAX_PWR_LVL			1
+#define PLAT_MAX_RET_STATE			1
+#define PLAT_MAX_OFF_STATE			2
+#define PLATFORM_SYSTEM_COUNT			1
+#define PLATFORM_CLUSTER_COUNT			1
+#define PLATFORM_CLUSTER0_CORE_COUNT		4
+#define PLATFORM_CLUSTER1_CORE_COUNT		0
+#define PLATFORM_CORE_COUNT		(PLATFORM_CLUSTER1_CORE_COUNT + \
+					PLATFORM_CLUSTER0_CORE_COUNT)
+#define PLATFORM_MAX_CPUS_PER_CLUSTER		4
+
+/* Interrupt related constant */
+
+#define INTEL_AGX_IRQ_SEC_PHY_TIMER		29
+
+#define INTEL_AGX_IRQ_SEC_SGI_0			8
+#define INTEL_AGX_IRQ_SEC_SGI_1			9
+#define INTEL_AGX_IRQ_SEC_SGI_2			10
+#define INTEL_AGX_IRQ_SEC_SGI_3			11
+#define INTEL_AGX_IRQ_SEC_SGI_4			12
+#define INTEL_AGX_IRQ_SEC_SGI_5			13
+#define INTEL_AGX_IRQ_SEC_SGI_6			14
+#define INTEL_AGX_IRQ_SEC_SGI_7			15
+
+#define TSP_IRQ_SEC_PHY_TIMER		INTEL_AGX_IRQ_SEC_PHY_TIMER
+#define TSP_SEC_MEM_BASE		BL32_BASE
+#define TSP_SEC_MEM_SIZE		(BL32_LIMIT - BL32_BASE + 1)
+/*******************************************************************************
+ * Platform memory map related constants
+ ******************************************************************************/
+#define DRAM_BASE				(0x0)
+#define DRAM_SIZE				(0x80000000)
+
+#define OCRAM_BASE				(0xFFE00000)
+#define OCRAM_SIZE				(0x00040000)
+
+#define MEM64_BASE				(0x0100000000)
+#define MEM64_SIZE				(0x1F00000000)
+
+#define DEVICE1_BASE				(0x80000000)
+#define DEVICE1_SIZE				(0x60000000)
+
+#define DEVICE2_BASE				(0xF7000000)
+#define DEVICE2_SIZE				(0x08E00000)
+
+#define DEVICE3_BASE				(0xFFFC0000)
+#define DEVICE3_SIZE				(0x00008000)
+
+#define DEVICE4_BASE				(0x2000000000)
+#define DEVICE4_SIZE				(0x0100000000)
+
+/*******************************************************************************
+ * BL31 specific defines.
+ ******************************************************************************/
+/*
+ * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if
+ * present). BL31_BASE is calculated using the current BL3-1 debug size plus a
+ * little space for growth.
+ */
+
+
+#define FIRMWARE_WELCOME_STR		"Booting Trusted Firmware\n"
+
+#define BL1_RO_BASE	(0xffe00000)
+#define BL1_RO_LIMIT	(0xffe0f000)
+#define BL1_RW_BASE	(0xffe10000)
+#define BL1_RW_LIMIT	(0xffe1ffff)
+#define BL1_RW_SIZE	(0x14000)
+
+#define BL2_BASE	(0xffe00000)
+#define BL2_LIMIT	(0xffe1b000)
+
+#define BL31_BASE	(0xffe1c000)
+#define BL31_LIMIT	(0xffe3bfff)
+
+/*******************************************************************************
+ * Platform specific page table and MMU setup constants
+ ******************************************************************************/
+#define MAX_XLAT_TABLES			8
+#define MAX_MMAP_REGIONS		16
+
+/*******************************************************************************
+ * Declarations and constants to access the mailboxes safely. Each mailbox is
+ * aligned on the biggest cache line size in the platform. This is known only
+ * to the platform as it might have a combination of integrated and external
+ * caches. Such alignment ensures that two maiboxes do not sit on the same cache
+ * line at any cache level. They could belong to different cpus/clusters &
+ * get written while being protected by different locks causing corruption of
+ * a valid mailbox address.
+ ******************************************************************************/
+#define CACHE_WRITEBACK_SHIFT			6
+#define CACHE_WRITEBACK_GRANULE		(1 << CACHE_WRITEBACK_SHIFT)
+
+#define PLAT_GIC_BASE			(0xFFFC0000)
+#define PLAT_GICC_BASE			(PLAT_GIC_BASE + 0x2000)
+#define PLAT_GICD_BASE			(PLAT_GIC_BASE + 0x1000)
+#define PLAT_GICR_BASE			0
+
+/*******************************************************************************
+ * UART related constants
+ ******************************************************************************/
+#define PLAT_UART0_BASE		(0xFFC02000)
+#define PLAT_UART1_BASE		(0xFFC02100)
+
+#define CRASH_CONSOLE_BASE	PLAT_UART0_BASE
+
+#define PLAT_BAUDRATE		(115200)
+#define PLAT_UART_CLOCK		(100000000)
+
+/*******************************************************************************
+ * System counter frequency related constants
+ ******************************************************************************/
+#define PLAT_SYS_COUNTER_FREQ_IN_TICKS	(400000000)
+#define PLAT_SYS_COUNTER_FREQ_IN_MHZ	(400)
+
+#define PLAT_INTEL_AGX_GICD_BASE	PLAT_GICD_BASE
+#define PLAT_INTEL_AGX_GICC_BASE	PLAT_GICC_BASE
+
+/*
+ * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
+ * terminology. On a GICv2 system or mode, the lists will be merged and treated
+ * as Group 0 interrupts.
+ */
+#define PLAT_INTEL_AGX_G1S_IRQ_PROPS(grp) \
+	INTR_PROP_DESC(INTEL_AGX_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \
+			grp, GIC_INTR_CFG_LEVEL), \
+	INTR_PROP_DESC(INTEL_AGX_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \
+			GIC_INTR_CFG_EDGE), \
+	INTR_PROP_DESC(INTEL_AGX_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \
+			GIC_INTR_CFG_EDGE), \
+	INTR_PROP_DESC(INTEL_AGX_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \
+			GIC_INTR_CFG_EDGE), \
+	INTR_PROP_DESC(INTEL_AGX_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \
+			GIC_INTR_CFG_EDGE), \
+	INTR_PROP_DESC(INTEL_AGX_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \
+			GIC_INTR_CFG_EDGE), \
+	INTR_PROP_DESC(INTEL_AGX_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \
+			GIC_INTR_CFG_EDGE), \
+	INTR_PROP_DESC(INTEL_AGX_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \
+			GIC_INTR_CFG_EDGE), \
+	INTR_PROP_DESC(INTEL_AGX_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \
+			GIC_INTR_CFG_EDGE)
+
+#define PLAT_INTEL_AGX_G0_IRQ_PROPS(grp)
+
+#define MAX_IO_HANDLES			4
+#define MAX_IO_DEVICES			4
+#define MAX_IO_BLOCK_DEVICES		2
+
+#endif /* PLATFORM_DEF_H */
+
diff --git a/plat/intel/soc/agilex/include/socfpga_private.h b/plat/intel/soc/agilex/include/socfpga_private.h
new file mode 100644
index 0000000..6ab1409
--- /dev/null
+++ b/plat/intel/soc/agilex/include/socfpga_private.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2019, Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLATFORM_PRIVATE_H
+#define PLATFORM_PRIVATE_H
+
+/*******************************************************************************
+ * Function and variable prototypes
+ ******************************************************************************/
+void socfgpa_configure_mmu_el3(unsigned long total_base,
+			unsigned long total_size,
+			unsigned long ro_start,
+			unsigned long ro_limit,
+			unsigned long coh_start,
+			unsigned long coh_limit);
+
+
+void socfpga_configure_mmu_el1(unsigned long total_base,
+			unsigned long total_size,
+			unsigned long ro_start,
+			unsigned long ro_limit,
+			unsigned long coh_start,
+			unsigned long coh_limit);
+
+void socfpga_delay_timer_init(void);
+
+void socfpga_gic_driver_init(void);
+
+uint32_t socfpga_get_spsr_for_bl32_entry(void);
+
+uint32_t socfpga_get_spsr_for_bl33_entry(void);
+
+unsigned long socfpga_get_ns_image_entrypoint(void);
+
+
+#endif /* PLATFORM_PRIVATE_H */