tree f63f0740a57f260550fc9a87c4caa6ff45afc846
parent b4a76766dd81e34b2b5c0eb2822e7e699467c11a
author Xing Zheng <zhengxing@rock-chips.com> 1482237881 +0800
committer Xing Zheng <zhengxing@rock-chips.com> 1487938064 +0800

FIXUP: rockchip: rk3399: fix the incorrect bit during m0_init

We found that the DUT will be hanged if we don't set the bit_1 of the
PMUCRU_GATEDIS_CON0. But, from the TRM, there is weird that the bit_1
is set the clk_center1_gating_dis, not clk_pmum0_gating_dis. Is the
TRM incorrect? We need to check it with the IC team and re-clean the
commit message and explain it tomorrow.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>