feat(tc): add SLC MSC nodes to TC4 DT
These specify the addresses of the MPAM registers in the MCN block. Note
that these are enabled for TC4 FPGA only as the MPAM devices are not
available on FVP.
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>
Change-Id: I105cd21952c2bd4fac5a06c84c0a93217b5e1312
diff --git a/fdts/tc4.dts b/fdts/tc4.dts
index 98cfea1..675c39b 100644
--- a/fdts/tc4.dts
+++ b/fdts/tc4.dts
@@ -104,4 +104,46 @@
compatible = "arm,coresight-pmu";
reg = <0x0 MCN_PMU_ADDR(7) 0x0 0xffc>;
};
+
+#if defined(TARGET_FLAVOUR_FPGA)
+ slc-msc@0 {
+ compatible = "arm,mpam-msc";
+ reg = <0x0 MCN_MPAM_NS_BASE_ADDR(0) 0x0 0x4000>;
+ };
+
+ slc-msc@1 {
+ compatible = "arm,mpam-msc";
+ reg = <0x0 MCN_MPAM_NS_BASE_ADDR(1) 0x0 0x4000>;
+ };
+
+ slc-msc@2 {
+ compatible = "arm,mpam-msc";
+ reg = <0x0 MCN_MPAM_NS_BASE_ADDR(2) 0x0 0x4000>;
+ };
+
+ slc-msc@3 {
+ compatible = "arm,mpam-msc";
+ reg = <0x0 MCN_MPAM_NS_BASE_ADDR(3) 0x0 0x4000>;
+ };
+
+ slc-msc@4 {
+ compatible = "arm,mpam-msc";
+ reg = <0x0 MCN_MPAM_NS_BASE_ADDR(4) 0x0 0x4000>;
+ };
+
+ slc-msc@5 {
+ compatible = "arm,mpam-msc";
+ reg = <0x0 MCN_MPAM_NS_BASE_ADDR(5) 0x0 0x4000>;
+ };
+
+ slc-msc@6 {
+ compatible = "arm,mpam-msc";
+ reg = <0x0 MCN_MPAM_NS_BASE_ADDR(6) 0x0 0x4000>;
+ };
+
+ slc-msc@7 {
+ compatible = "arm,mpam-msc";
+ reg = <0x0 MCN_MPAM_NS_BASE_ADDR(7) 0x0 0x4000>;
+ };
+#endif /* TARGET_FLAVOUR_FPGA */
};